Features
•Single Supply Voltage, Range 3V to 3.6V
•3-volt Only Read and Write Operation
•Software Protected Programming
•Fast Read Access Time – 120 ns
•Low Power Dissipation
– 15 mA Active Current
– 40 µA CMOS Standby Current
•Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 1024 Sectors (128 Bytes/Sector)
– Internal Address and Data Latches for 128 Bytes
•Two 8K Bytes Boot Blocks with Lockout
•Fast Sector Program Cycle Time – 20 ms
•Internal Program Control and Timer
•DATA Polling for End of Program Detection
•Typical Endurance > 10,000 Cycles
•CMOS and TTL Compatible Inputs and Outputs
•Commercial and Industrial Temperature Ranges
1. Description
The AT29LV010A is a 3-volt only in-system Flash programmable and erasable read
only memory (Flash). Its 1 megabit of memory is organized as 131,072 bytes by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 120 ns with power dissipation of just 54 mW over the commercial tem-
perature range. When the device is deselected, the CMOS standby current is less
than 40 µA. The device endurance is such that any sector can typically be written to in
excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29LV010A does not require
high input voltages for programming. Three-volt-only commands determine the opera-
tion of the device. Reading data out of the device is similar to reading from an
EPROM. Reprogramming the AT29LV010A is performed on a sector basis; 128 bytes
of data are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 bytes of data are captured at
microprocessor speed and internally latched, freeing the address and data bus for
other operations. Following the initiation of a program cycle, the device will automati-
cally erase the sector and then program the latched data using an internal control
timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the
end of a program cycle has been detected, a new access for a read or program can
begin.
1-megabit
(128K x 8)
3-volt Only
Flash Memory
AT29LV010A
0520F–FLASH–9/08
Not Recommended
for New Design
Use AT29BV010A
Contact Atmel to discuss
the latest design in trends
and options
2
0520F–FLASH–9/08
AT29LV010A
2. Pin Configurations
2.1 32-lead PLCC Top View
2.2 32-lead TSOP Top View – Type 1
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
NC
VCC
WE
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
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AT29LV010A
3. Block Diagram
4. Device Operation
4.1 Read
The AT29LV010A is accessed like an EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state whenever CE or OE is high. This dual-line con-
trol gives designers flexibility in preventing bus contention.
4.2 Software Data Protection Programming
The AT29LV010A has 1024 individual sectors, each 128 bytes. Using the software data protec-
tion feature, byte loads are used to enter the 128 bytes of a sector to be programmed. The
AT29LV010A can only be programmed or reprogrammed using the software data protection fea-
ture. The device is programmed on a sector basis. If a byte of data within the sector is to be
changed, data for the entire 128-byte sector must be loaded into the device. The data in any
byte that is not loaded during the programming of its sector will be indeterminate. The
AT29LV010A automatically does a sector erase prior to loading the data into the sector. An
erase command is not required.
Software data protection protects the device from inadvertent programming. A series of three
program commands to specific addresses with specific data must be presented to the device
before programming may occur. The same three program commands must begin each program
operation. All software program commands must obey the sector program timing specifications.
Power transitions will not reset the software data protection feature; however, the software fea-
ture will guard against inadvertent program cycles during power transitions.
Any attempt to write to the device without the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however, for the duration of tWC, a read opera-
tion will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed by
applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The
address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE.
The 128 bytes of data must be loaded into each sector. Any byte that is not loaded during the
programming of its sector will be erased to read FFh. Once the bytes of a sector are loaded into
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0520F–FLASH–9/08
AT29LV010A
the device, they are simultaneously programmed during the internal programming period. After
the first data byte has been loaded into the device, successive bytes are entered in the same
manner. Each new byte to be programmed must have its high to low transition on WE (or CE)
within 150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high to low
transition is not detected within 150 µs of the last low-to-high transition, the load period will end
and the internal programming period will start. A7 to A16 specify the sector address. The sector
address must be valid during each high to low transition of WE (or CE). A0 to A6 specify the byte
address within the sector. The bytes may be loaded in any order; sequential loading is not
required. Once a programming operation has been initiated, and for the duration of tWC, a read
operation will effectively be a polling operation.
4.3 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29LV010A in the following
ways: (a) VCC sense – if VCC is below 1.8V (typical), the program function is inhibited; (b) VCC
power on delay – once VCC has reached the VCC sense level, the device will automatically time
out 10 ms (typical) before programming; (c) Program inhibit – holding any one of OE low, CE
high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical)
on the WE or CE inputs will not initiate a program cycle.
4.4 Input Levels
While operating with a 3.3V ± 0.3V power supply, the address inputs and control inputs (OE, CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.
The I/O lines can be driven from 0 to VCC + 0.6V.
4.5 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
In addition, users may wish to use the software product identification mode to identify the part
(i.e. using the device code), and have the system software use the appropriate sector size for
program operations. In this manner, the user can have a common board design for 256K to
4-megabit densities and, with each density’s sector size in a memory map, have the system soft-
ware apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.6 DATA Polling
The AT29LV010A features DATA polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will result in the complement of the loaded
data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and
the next cycle may begin. DATA polling may begin at any time during the program cycle.
4.7 Toggle Bit
In addition to DATA polling the AT29LV010A provides another method for determining the end
of a program or erase cycle. During a program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle.
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AT29LV010A
4.8 Optional Chip Erase Mode
The entire device can be erased by using a 6-byte software code. Please see Software Chip
Erase application note for details.
4.9 Boot Block Programming Lockout
The AT29LV010A has two designated memory blocks that have a programming lockout feature.
This feature prevents programming of data in the designated block once the feature has been
enabled. Each of these blocks consists of 8K bytes; the programming lockout feature can be set
independently for either block. While the lockout feature does not have to be activated, it can be
activated for either or both blocks.
These two 8K memory sections are referred to as boot blocks. Secure code which will bring up a
system can be contained in a boot block. The AT29LV010A blocks are located in the first 8K
bytes of memory and the last 8K bytes of memory. The boot block programming lockout feature
can therefore support systems that boot from the lower addresses of memory or the higher
addresses. Once the programming lockout feature has been activated, the data in that block can
no longer be erased or programmed; data in other memory locations can still be changed
through the regular programming methods. To activate the lockout feature, a series of seven
program commands to specific addresses with specific data must be performed. Please see
Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on either block, the chip erase function will
be disabled.
4.9.1 Boot Block Lockout Detection
A software method is available to determine whether programming of either boot block section is
locked out. See Software Product Identification Entry and Exit sections. When the device is in
the software product identification mode, a read from location 00002H will show if programming
the lower address boot block is locked out while reading location 1FFF2H will do so for the upper
boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the
program lockout feature has been activated and the corresponding block cannot be pro-
grammed. The software product identification exit mode should be used to return to standard
operation.
5. Absolute Maximum Ratings*
Temperature Under Bias............................... -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature.................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on A9 (including NC Pins)
with Respect to Ground ...................................-0.6V to +13.5V
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0520F–FLASH–9/08
AT29LV010A
Notes: 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an
operational mode is started.
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code is 1F. The Device Code is 35.
5. See details under Software Product Identification Entry/Exit.
6. DC and AC Operating Range
AT29LV010A-12 AT29LV010A-15 AT29LV010A-20 AT29LV010A-25
Operating Temperature (Case) Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply(1) 3.3V ± 0.3V 3.3V ± 0.3V 3.3V ± 0.3V 3.3V ± 0.3V
2. Not recommended for New Designs.
7. Operating Modes
Mode CE OE WE Ai I/O
Read VIL VIL VIH Ai DOUT
Program(2) VIL VIH VIL Ai DIN
5V Chip Erase VIL VIH VIL Ai
Standby/Write Inhibit VIH X(1) X X High Z
Program Inhibit X X VIH
Program Inhibit X VIL X
Output Disable X VIH X High Z
Product Identification
Hardware VIL VIL VIH
A1 - A16 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code(4)
A1 - A16 = VIL, A9 = VH,(3) A0 = VIH Device Code(4)
Software(5) A0 = VIL, A1 - A16 =VIL Manufacturer Code(4)
A0 = VIH, A1 - A16 =VIL Device Code(4)
8. DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 1μA
ILO Output Leakage Current VI/O = 0V to VCC 1μA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC
Com. 40 μA
Ind. 50 μA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 1mA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA; VCC = 3.6V 15 mA
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 1.6 mA; VCC = 3.0V 0.45 V
VOH Output High Voltage IOH = -100 μA; VCC = 3.0V 2.4 V
7
0520F–FLASH–9/08
AT29LV010A
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
9. AC Read Characteristics
Symbol Parameter
AT29LV010A-12 AT29LV010A-15 AT29LV010A-20 AT29LV010A-25
UnitsMinMaxMinMaxMin Max Min Max
tACC Address to Output Delay 120 150 200 250 ns
tCE(1) CE to Output Delay 120 150 200 250 ns
tOE(2) OE to Output Delay 0 50 0 70 0100 0120 ns
tDF(3)(4) CE or OE to Output Float 0 30 0 40 050 060 ns
tOH
Output Hold from OE, CE or
Address, whichever occurred
first
000 0 ns
Note: Not recommended for New Designs.
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0520F–FLASH–9/08
AT29LV010A
11. Input Test Waveforms and Measurement Level
12. Output Test Load
Note: 1. These parameters are characterized and not 100% tested.
tR, tF < 5 ns
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT 812pFV
OUT = 0V
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0520F–FLASH–9/08
AT29LV010A
15. AC Byte Load Waveforms(1)(2)
15.1 WE Controlled
15.2 CE Controlled
14. AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 10 ns
tAH Address Hold Time 100 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 200 ns
tDS Data Set-up Time 100 ns
tDH, tOEH Data, OE Hold Time 10 ns
tWPH Write Pulse Width High 200 ns
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0520F–FLASH–9/08
AT29LV010A
17. Software Protected Program Waveform
Notes: 1. OE must be high when WE and CE are both low.
2. A7 through A16 must specify the sector address during each high to low transition of WE (or CE) after the software code has
been entered.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
18. Programming Algorithm(1)
16. Program Cycle Characteristics
Symbol Parameter Min Max Units
tWC Write Cycle Time 20 ms
tAS Address Set-up Time 10 ns
tAH Address Hold Time 100 ns
tDS Data Set-up Time 100 ns
tDH Data Hold Time 10 ns
tWP Write Pulse Width 200 ns
tBLC Byte Load Cycle Time 150 μs
tWPH Write Pulse Width High 200 ns
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA
TO
SECTOR (128 BYTES)
(3)
WRITES ENABLED
ENTER DATA
PROTECT STATE
(2)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data Protect state will be re-activated at end of
program cycle.
3. 128 bytes of data MUST BE loaded.
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0520F–FLASH–9/08
AT29LV010A
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
20. Data Polling Waveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
22. Toggle Bit Waveforms(1)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
19. Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tWR Write Recovery Time 0 ns
21. Toggle Bit Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
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0520F–FLASH–9/08
AT29LV010A
23. Software Product Identification
Entry(1)
24. Software Product Identification
Exit(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A16 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is 35.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
PAUSE 20 mS ENTER PRODUCT
IDENTIFICATION
MODE
(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 20 mS EXIT PRODUCT
IDENTIFICATION
MODE(4)
25. Boot Block Lockout
Feature Enable Algorithm(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
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0520F–FLASH–9/08
AT29LV010A
26. Ordering Information
26.1 Standard Package
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
120
15 0.04 AT29LV010A-12JC
AT29LV010A-12TC
32J
32T
Commercial
(0° to 70°C)
15 0.05 AT29LV010A-12JI
AT29LV010A-12TI
32J
32T
Industrial
(-40° to 85°C)
150
15 0.04 AT29LV010A-15JC
AT29LV010A-15TC
32J
32T
Commercial
(0° to 70°C)
15 0.05 AT29LV010A-15JI
AT29LV010A-15TI
32J
32T
Industrial
(-40° to 85°C)
200
15 0.04 AT29LV010A-20JC
AT29LV010A-20TC
32J
32T
Commercial
(0° to 70°C)
15 0.05 AT29LV010A-20JI
AT29LV010A-20TI
32J
32T
Industrial
(-40° to 85°C)
250
15 0.04 AT29LV010A-25JC
AT29LV010A-25TC
32J
32T
Commercial
(0° to 70°C)
15 0.05 AT29LV010A-25JI
AT29LV010A-25TI
32J
32T
Industrial
(-40° to 85°C)
Note: Not recommended for New Designs.
Package Type
32J 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
32T 32-Lead, Thin Small Outline Package (TSOP)
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AT29LV010A
27. Packaging Information
27.1 32J – PLCC
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B
32J
10/04/01
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
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0520F–FLASH–9/08
AT29LV010A
27.2 32T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP) B
32T
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
0520F–FLASH–9/08
Headquarters International
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Product Contact
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Technical Support
Flash@atmel.com
Sales Contact
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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