Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 TPS54020 Small, 10-A, 4.5-V to 17-V Input, SWIFTTM Synchronous Step-Down Converter With Light-Load Efficiency 1 Features 2 Applications * * * * * 1 * * * * * * * * * * * * * * * * * Integrated 8-m and 6-m MOSFETs Thermally Enhanced 3.5-mm x 3.5-mm HotRodTM Package Peak Current Mode Control Eco-modeTM Pulse Skip for Higher Efficiency Overcurrent Protection for Both MOSFETs Selectable Overcurrent Protection Schemes Selectable Overcurrent Protection Levels Split Power Rail: 1.6 V to 17 V on PVIN 0.6-V Voltage Reference With 1% Accuracy 200-kHz to 1.2-MHz Switching Frequency Synchronizes to External Clock Start-Up Into Prebiased Outputs Overtemperature and Overvoltage Protection -40C to 150C Operating Junction Temperature Range Adjustable Soft-Start and Power Sequencing Power-Good Output Monitor for Undervoltage and Overvoltage SYNC_OUT Function Provides Output Clock Signal 180 Out-of-Phase Supported by WEBENCH(R) Software Tool For SWIFTTM Documentation and WEBENCH, visit http://www.ti.com/swift Power for FPGAs, SoCs, DSPs and Processors Wireless, Data, and Cloud Infrastructure Gaming, DTV, STB, and Smart Grid Systems 3 Description The TPS54020 is a 10-A, 4.5-V to 17-V input SWIFT converter. The innovative 3.5 mm x 3.5 mm HotRod package optimizes high-density step-down designs. The TPS54020 is a full-featured converter. High efficiency is achieved through the innovative integration and packaging of the high-side and lowside MOSFETs. The TPS54020 operates at continuous current mode (CCM) at higher load conditions, and transitions to Eco-mode while skipping pulses to boost the efficiency at light loads. Current limiting on both MOSFETs provides device and system protection. Cycle-by-cycle current limiting in the high-side MOSFET protects for overload situations. Low-side MOSFET zero current detection turns off the low-side MOSFET while operating under light loads. Three selectable current-limit thresholds allow a good fit for various applications. A hiccup or cycle-by-cycle overcurrent protection scheme is also selectable. Thermal shutdown protection disables switching when die temperature exceeds the thermal shutdown trip point and enables switching after the built-in thermal hysteresis and shutdown hiccup time. Device Information(1) PART NUMBER TPS54020 PACKAGE BODY SIZE (NOM) VQFN (15) 3.50 mm x 3.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Application Schematic Efficiency vs. Load Current 96 TPS54020 PWRGD 94 VIN SYNC_OUT 92 EN BOOT PVIN ILIM SS LOUT PH RT/CLK COMP VOUT COUT HICCUP TA = 25C VOUT = 1.8 V fSW = 500 kHz 90 88 86 84 VSENSE RTN Efficiency (%) VPVIN: 1.6 V to 17 V VVIN: 4.5 V to 17 V VIN = 5 V VIN = 12 V VIN = 17 V 82 PGND 80 2 3 4 5 6 7 Load Current (A) 8 9 10 G000 UGD-13037 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 17 9 Application and Implementation ........................ 20 9.1 Application Information............................................ 20 9.2 Typical Application ................................................. 23 10 Power Supply Recommendations ..................... 32 11 Layout................................................................... 32 11.1 Layout Guidelines ................................................. 32 11.2 Layout Example .................................................... 33 12 Device and Documentation Support ................. 35 12.1 12.2 12.3 12.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 35 35 35 35 13 Mechanical, Packaging, and Orderable Information ........................................................... 35 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D * Page Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 Changes from Revision B (February 2013) to Revision C Page * Deleted Note 2 from the Thermal Information table ............................................................................................................... 4 * Added VIN Internal UVLO Threshold .................................................................................................................................... 5 * Added VIN Internal UVLO hysteresis ..................................................................................................................................... 5 * Changed OVERVIEW paragraph "The TPS54020 starts up..." ........................................................................................... 10 Changes from Revision A (September 2012) to Revision B Page * Changed the Input Voltage and Power Input Voltage Pins (VIN and PVIN) section............................................................ 12 * Changed the DETAILED DESCRIPTION section ................................................................................................................ 17 * Changed the DESIGN EXAMPLE section............................................................................................................................ 23 Changes from Original (July 2012) to Revision A * 2 Page Changed the device From: Product Preview To: Production ................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 5 Description (Continued) The SS pin controls the output voltage start-up ramp and allows for selectable soft-start times. Power supply sequencing is also available by configuring the enable (EN) and the open-drain power-good (PWRGD) pins. Two TPS54020 devices may be synchronized 180 out-of-phase by using the SYNC_OUT and CLK pins. 6 Pin Configuration and Functions RUW PACKAGE 15 PINS (TOP VIEW) VIN 1 15 EN HICCUP 2 14 SS ILIM 3 13 VSENSE SYNC_OUT 4 12 COMP PWRGD 5 11 RTN BOOT 6 10 7 8 9 PVIN PH PGND RT/CLK Pin Functions PIN I/O (1) DESCRIPTION NAME NO. BOOT 6 S A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the high-side MOSFET (BOOT UVLO), the PH node is forced low so that the capacitor is refreshed COMP 12 O Error amplifier current output, and input to the output switch current comparator. Connect frequency compensation to this pin. EN 15 I A divider network must be used to implement an under voltage lockout function. To disable switching and reduce quiescent current, this pin must be pulled to ground. HICCUP 2 O Overcurrent protection scheme select pin. ILIM 3 O Current limit threshold select pin. PGND 9 G Power Ground. Return for the Low-side MOSFET. PH 8 O Switch node PVIN 7 I Power input. Supplies the power switches of the power converter. PWRGD 5 O Power good fault pin. Asserts low if output voltage is out of regulation due to thermal shutdown, dropout, overvoltage, EN shutdown or during soft-start. RT/CLK 10 I/O Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device; In CLK mode, the device synchronizes to an external clock. RTN 11 G Return for control circuitry. SS 14 I/O Soft-start pin. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for sequencing. SYNC_OU T 4 O Synchronization output provides a clock signal 180 out-of-phase with the power switch. VIN 1 I Supplies the control circuitry of the power converter. VSENSE 13 I Inverting node of the transconductance (gm) error amplifier (1) I = Input, O = Output, S = Supply, G = Ground Return Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 3 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Input voltage Output voltage MIN MAX VIN, PVIN -0.3 20 EN -0.3 6 BOOT -0.3 27 COMP, HICCUP, ILIM, SS/TR, SYNC_OUT, VSENSE -0.3 3 PWRGD, RT/CLK -0.3 6 BOOT-PH 0 7.5 PH -1 20 PH (10-ns transient) Sink current V V -3 20 -100 100 A PH Current Limit A PH Current Limit PVIN Current Limit RT/CLK Source current UNIT A COMP -200 200 A PWRGD -0.1 5 mA Operating junction temperature, TJ -40 150 C Storage temperature, Tstg -65 150 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Operating Junction Temperature - TJ MIN MAX UNIT -40 150 C Control Input Voltage VIN 4.5 17 V Power Stage Input Voltage PVIN 1.6 17 V 4 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 7.4 Thermal Information TPS54020 THERMAL METRIC (1) RUW UNIT 15 PINS 16.6 (2) JA Junction-to-ambient thermal resistance JC(top) Junction-to-case (top) thermal resistance 28.8 JB Junction-to-board thermal resistance 19.0 JT Junction-to-top characterization parameter 0.7 JB Junction-to-board characterization parameter 18.9 JC(bottom) Junction-to-case (bottom) thermal resistance 0.3 (1) (2) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Applicable only to the EVM in free space with no airflow. 7.5 Electrical Characteristics TJ = -40C to 150C, VIN = 4.5 V to 17 V, PVIN = 4.5 V to 17 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN AND PVIN PINS) PVIN operating input voltage 1.6 17 V VIN operating input voltage 4.5 17 V 4.5 V VIN Internal UVLO Threshold VIN Rising 4 VIN Internal UVLO hysteresis 150 VIN shutdown supply current VEN = 0 V VIN operating - nonswitching supply current VVSENSE = 610 mV mV 2 10 A 600 1000 A 1.22 1.26 V ENABLE AND UVLO (EN PIN) VEN Enable threshold IIN(EN) Input current Hysteresis current Rising Falling 1.10 1.17 V VEN = 1.1 V -1.15 A VEN = 1.3 V -3.3 A VOLTAGE REFERENCE VREF 0 A IOUT 10 A, -40C TA 150C Voltage reference 0.594 0.6 0.606 V MOSFET DRVH DRVL 9.5 18 m BOOT-PH = 6 V (1) 8 14 m VVIN = 12 V 6 11 m Error amplifier input bias current VVIN = 12 V 50 Error amplifier transconductance -2 A < ICOMP < 2 A, VCOMP = 1 V Error amplifier dc gain VVSENSE = 0.6 V Error amplifier source/sink Start switching threshold High-side switch resistance Low-side switch resistance (1) BOOT-PH = 3 V ERROR AMPLIFIER gM gM COMP to ISWITCH transconductance nA 1300 S 3000 V/V VCOMP = 1 V, 100 mV Overdrive 100 A VCOMP 0.27 V 1000 IILIM = NC 20 IILIM = RTN 17 499 k (1%) between ILIM and RTN 13 A/V CURRENT LIMIT High-side switch current limit threshold High-side switch current limit threshold (1) IILIM = NC 13.4 15.1 16.5 IILIM = RTN 11.2 12.75 14 8.3 9.4 10.2 499 k (1%) between ILIM and RTN A A Measured at pins. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 5 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) TJ = -40C to 150C, VIN = 4.5 V to 17 V, PVIN = 4.5 V to 17 V (unless otherwise noted) PARAMETER Low-side switch sourcing current limit CONDITIONS MIN IILIM = NC IILIM = RTN TYP MAX 11 13 15 9 10.5 12 6.5 8 9.5 -200 -800 UNIT A Low-side switch sourcing current limit 499 k (1%) between ILIM and RTN A Low-side switch sinking current limit -ve current denotes current sourced from PH pin Overcurrent protection scheme (HICCUP = RTN) Cyclebycycle Hiccup delay before re-start HICCUP OPEN 16384 Cycles Hiccup wait time HICCUP OPEN 128 Cycles 175 C mA THERMAL SHUTDOWN Thermal shutdown Thermal shutdown hysteresis 10 Thermal shutdown hiccup time C 16384 Cycles TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching frequency RRT/CLK = 250 k (1%) 185 205 230 RRT/CLK = 100 k (1%) 475 500 525 RRT/CLK = 50 k (1%) 890 990 1090 Minimum CLK pulse width 20 RT/CLK high threshold RT/CLK falling edge to PH rising edge delay ns 2 RT/CLK low threshold 0.8 Measure at 500 kHz with RT resistor in series PLL frequency range kHz V V 66 200 ns 1200 kHz SYNC_OUT (SYNC_OUT PIN) Phase with RT/CLK 180 SYNC_OUT low threshold Degree 0.8 SYNC_OUT high threshold 2 V V PH (PH PIN) tON(min) Minimum on-time Measured at 90% to 90% of VIN, IPH = 2 A 112 IPH(LK) PH leakage current VVIN = 17 V, VOUT = 0.6 V, TA = 150C 300 165 ns A BOOT (BOOT PIN) BOOT-PH UVLO 2.1 3 V SOFT-START AND TRACKING (SS/TR PIN) ISS Soft-start charge current SS/TR to VSENSE matching 2.3 2.5 A VSS/TR = 0.4 V 2.1 22 45 mV VVSENSE falling (Fault) 91 POWER GOOD (PWRGD PIN) VSENSE threshold VVSENSE rising (Good) 95 VVSENSE rising (Fault) 108 VVSENSE falling (Good) 104 Output high leakage VVSENSE = VREF, VPWRGD = 5.5 V Output low IPWRGD = 2 mA Minimum input voltage for valid output VPWRGD < 0.5 V at 100 A Minimum soft-start voltage for valid PWRGD 6 Submit Documentation Feedback 3 0.6 %VREF 100 nA 0.3 V 1 V 1.4 V Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 7.6 Typical Characteristics 9.0 Boot - PH = 3V Boot - PH = 6V 14 RDS(on) - On Resistance - m RDS(on) - On Resistance - m 16 12 10 8 6 8.5 Vin = 12V 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4 4.5 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 -50 Figure 1. High-Side MOSFET On-Resistance vs Junction Temperature 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 2. Low-Side MOSFET On-Resistance vs Junction Temperature 0.6030 499.0 fO - Oscillator Frequency - kHz Vref Vref - Voltage Reference - V -25 0.6025 0.6020 0.6015 0.6010 0.6005 498.5 Rt= 100 kohm 498.0 497.5 497.0 496.5 496.0 495.5 0.6000 495.0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 -50 Figure 3. Voltage Reference vs Junction Temperature 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 4. Oscillator Frequency vs Junction Temperature 3.48 3.5 Vin = 12V Vin = 17V Vin = 12V Vin = 4.5V 3.0 EN Pin Hysteresis Current- A Isd - Shutdown Quiescent Current - uA -25 2.5 2.0 1.5 3.46 3.44 3.42 3.40 3.38 1.0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 3.36 -50 Figure 5. Shutdown Quiescent Current vs Junction Temperature -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 6. EN Pin Hysteresis Current vs Junction Temperature, VEN = 1.3 V Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 7 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 1.230 1.55 1.225 1.220 Vin = 12V EN Pin UVLO Threshold- V EN Pin Pull-Up Current - uA 1.50 1.45 1.40 1.35 1.30 1.25 1.215 Rising Falling 1.210 1.205 1.200 1.195 1.190 1.185 1.20 1.180 1.175 1.15 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 -50 150 Vin = 17V Vin = 12V Vin = 4.5V 660 640 620 600 580 560 125 150 2.335 2.330 2.325 2.320 2.315 2.310 2.305 2.300 2.295 540 2.290 520 -50 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 -25 0 25 50 75 100 125 150 150 TJ - Junction Temperature- C Figure 10. Soft-Start Charge Current vs Junction Temperature 110 30 108 28 106 Vss-Vsense 104 26 % of Vref Voff - SS/TR to Vsense Offset - mV 25 50 75 100 TJ - Junction Temperature - C 2.340 680 Figure 9. Nonswitching Operating Current vs vs Junction Temperature 24 22 102 Fault Rising Good Falling Good Rising Fault Falling 100 98 96 20 94 18 92 90 16 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 11. (VSS-VVSENSE) Offset vs Junction Temperature 8 0 Figure 8. EN Pin UVLO Threshold vs Junction Temperature, VVIN = 12 V ISS - Soft Start Charge Current - uA Non-Switching Operating Quiescent Current -A Figure 7. EN Pin Pullup Current vs Junction Temperature, VEN = 1.1 V -25 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 12. Power-Good Threshold vs Junction Temperature Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 Typical Characteristics (continued) 140 16 135 Min ON Time 500K OPEN GND 14 130 Min ON Time (nS) High Side FET Current (A) 15 13 12 11 125 120 115 10 110 9 105 100 8 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 13. High-Side MOSFET Current Limit vs Junction Temperature, VIN = 12 V -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 14. Minimum On-Time vs Temperature 2.090 BOOT-PH Boot-PH UVLO (V) 2.085 2.080 2.075 2.070 2.065 2.060 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 15. BOOT-PH UVLO vs Junction Temperature Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 9 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com 8 Detailed Description 8.1 Overview The TPS54020 is a 17-V, 10-A, synchronous step-down (buck) converter with two integrated N-channel MOSFETs. To improve performance during line and load transients the TPS54020 implements a constant frequency, peak current mode control which also simplifies external frequency compensation. The wide switching frequency range between 200 kHz and 1200 kHz allows for efficiency and size optimization when selecting the output filter components. A resistor to ground on the RT/CLK pin adjusts the switching frequency. The TPS54020 also has an internal phase lock loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. The TPS54020 starts up safely into pre-biased loads. The device implements an internal under voltage lockout (UVLO) feature on the VIN pin with a nominal START voltage of 4 V and a nominal hysteresis of 150mV. If the design requires more hysteresis due to an input source that droops with load, or if different START and STOP thresholds are required, this functionality can be achieved by using the EN pin. The EN pin has a hysteretic internal pull-up current source that can be used to adjust the input voltage UVLO with two external resistors. The total operating current for the TPS54020 is approximately 600uA when not switching and under no load. When the TPS54020 is disabled, the supply current is typically less than 2 A. The integrated MOSFETs allow for high-efficiency power supply designs with continuous output currents up to 10 A. The MOSFETs are sized to optimize efficiency for low to medium duty cycle applications The TPS54020 reduces the external component count by integrating the boot recharge circuit. A capacitor connected between the BOOT and PH pins supplies the bias voltage for the integrated high-side MOSFET. A UVLO circuit from BOOT to PH monitors the boot capacitor voltage. This monitoring ensures that the BOOT voltage is sufficient for proper high-side MOSFET gate drive current by allowing the device to pull the PH pin low to recharge the boot capacitor. The TPS54020 can operate at 100% duty cycle during transient conditions while the boot capacitor voltage is higher than the preset BOOT-PH UVLO threshold which is typically 2.1 V. The output voltage can be stepped down to as low as the 0.6-V voltage reference (VREF). The TPS54020 has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through the VSENSE pin. The PWRGD pin is an open-drain MOSFET which is pulled low when the VSENSE pin voltage is less than 91% or greater than 108% of the reference voltage (VREF) and asserts high when the VSENSE pin voltage is 95% to 104% of VREF. The SS (soft-start) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor or resistor divider should be coupled to the pin for soft-start or critical power supply sequencing requirements. The device has three preset current limit thresholds to fit 10-A, 8-A, and 6-A applications. Table 1 shows ILIM pin setting selections. Table 1. Current Limit Thresholds ILIM to RTN IMPEDANCE (k) CURRENT LIMIT OPTION (A) NC 10 SHORT 8 499 6 The TPS54020 protects from output overvoltage, overload and thermal fault conditions. The TPS54020 minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. When the overvoltage comparator activates, the high-side MOSFET turns off and the device prevents it from turning on until the VSENSE pin voltage is lower than 104% of VREF. The TPS54020 implements both high-side MOSFET overload protection and bi-directional, low-side MOSFET overload protection which helps control the inductor current and avoid current runaway. The device uses hiccup or cycle-by-cycle overcurrent protection features as listed inTable 2. 10 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 Table 2. Overcurrent Protection HICCUP TO RTN IMPEDANCE CURRENT LIMIT OPTION OPEN 16384 Cycle Hiccup SHORT Cycle-Cycle The TPS54020 shuts down if the junction temperature is higher than the thermal shutdown trip point of 175C. Once the junction temperature drops to 10C (typical) below the thermal shutdown trip point, the internal thermal shutdown hiccup timer begins to count. The TPS54020 restarts under the control of the soft-start circuit automatically after the thermal shutdown hiccup time reaches (16384 cycles). The TPS54020 operates in CCM (continuous conduction mode) at load conditions where the inductor current is always positive (towards the load). To boost efficiency at lighter load conditions, the device enters pulse skipping mode and turns OFF the low-side MOSFET when inductor current tries to reverse. For applications that require two converters to be synchronized together, the SYNC_OUT and RT/CLK pins can be used. The two converters can be configured to operate 180 out-of-phase by using the SYNC_OUT signal from one of the devices and applying it to the RT/CLK pin of the other device. 8.2 Functional Block Diagram PWRGD VIN EN Shutdown Ip UV Ih Enable Comparator Thermal Shutdown Logic PVIN UVLO Shutdown Shutdown Enable Threshold OV Boot Charge Current Sense ERROR AMPLIFIER VSENSE BOOT Boot UVLO SS Pulse Skip HS MOSFET Current Comparator Voltage Reference Power Stage & Deadtime Control Logic HICCUP PH Slope Compensation Overload Recovery VIN Maximum Clamp Oscillator with PLL Regulator LS MOSFET Current Limit Current Sense PGND COMP RT/CLK SYNC_OUT ILIM RTN Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 11 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com 8.3 Feature Description 8.3.1 Fixed Frequency PWM Control The device uses adjustable fixed-frequency, peak current mode control. External resistors on the VSENSE pin sense the output voltage. The device compares this sensed voltage to an internal 0.6-V voltage reference by a transconductance error amplifier. The resulting error signal is a current, and this current drives the COMP pin. An internal oscillator initiates the turn ON of the high-side power switch. The device converts the COMP pin voltage into a current reference which is compared to the high-side power switch current. When the power switch current reaches current reference generated by the COMP voltage level, the high-side power switch is turned OFF and the low-side power switch is turned ON until the next clock cycle. At lighter load conditions, the low-side MOSFET turns OFF when the inductor approaches zero, which results in pulse skipping mode. 8.3.2 Input Voltage and Power Input Voltage Pins (VIN and PVIN) The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to the power stage of the device. If tied together, the input voltage for VIN and PVIN can range from 4.5 V to 17 V. If using the VIN separately from PVIN, the VIN pin must be between 4.5 V and 17 V, and the PVIN pin can range from as low as 1.6 V to 17 V. The device provides an internal UVLO function on the VIN pin, but in cases where more hysteresis or different thresholds are required, a voltage divider connected to the EN pin can be used. When using an external divider, it is recommended to design the minimum turn OFF threshold at 4.2 V or greater, and the minimum turn ON threshold at 4.4 V or greater. These minimum thresholds are required to avoid interference between the user-defined UVLO threshold levels and the device internal UVLO. 8.3.3 Voltage Reference (VREF) The voltage reference system produces a precise 1% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. 8.3.4 Adjusting the Output Voltage The output voltage is set by the resistor divider network of RUPPER and RLOWER. It is recommended that the lower divider resistor, RLOWER, maintain a range between 1 k and 3 k. During light-load conditions, this resistor range provides enough load current to exceed the bias leakage current that may be sourced by the PH pin. To change the output voltage of a design, it is necessary to change the value of the resistor RUPPER. Changing the value of RUPPER can change the output voltage between 0.6 V and 5 V. The value of RUPPER for a specific output voltage can be calculated using Equation 1. RUPPER = (VOUT - VREF ) RLOWER VREF (1) The minimum output setpoint voltage cannot be less than the reference voltage of 0.6 V, but it may also be limited by the minimum ON time of the high-side MOSFET. The maximum output voltage can be limited by bootstrap voltage (BOOT-PH voltage). See more details located in the Minimum Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation sections. 8.3.5 Safe Start-up into Prebiased Outputs The device prevents the low-side MOSFET from discharging a pre-biased output. During pre-biased startup, the low-side MOSFET does not turn on until the high-side MOSFET has started switching. The high-side MOSFET does not start switching until the soft-start voltage exceeds the voltage at the VSENSE pin. 8.3.6 Error Amplifier The transconductance error amplifier compares the VSENSE pin voltage to either the SS pin voltage or the internal 0.6 V voltage reference, whichever is lower. The transconductance of the error amplifier is 1300 A/V during normal operation. The frequency compensation network is connected between the COMP pin and ground. 12 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 Feature Description (continued) 8.3.7 Slope Compensation The device adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations when operating conditions demand greater than 50% duty cycle. The available peak inductor current remains constant over the full duty cycle range. 8.3.8 Enable and Adjusting Undervoltage Lockout The EN pin provides electrical on and off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescent state. The EN pin has an internal hysteretic current source, allowing the user to design the ON and OFF threshold voltages with a resistor divider at the EN pin. If an application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin. The EN pin can be configured as shown in Figure 16, Figure 17, and Figure 18. It is recommended to set the UVLO hysteresis to be greater than 500mV in order to avoid repeated chatter during start up or shut down. The EN pin has a small fixed pull-up current iP which sets the current source value before the start-up sequence. The device includes the second current source iH when the threshold voltage has been exceeded. To achieve clean transitions between the OFF and ON states, TI recommendeds that the turn OFF threshold is no less than 4.2 V, and the turn ON threshold is no less than 4.4 V on the VIN pin. The UVLO thresholds can be calculated using Equation 2 and Equation 3. TPS54020 VIN PVIN IH IP R3 EN 1.22 V R5 EN 1.22 V UDG-13036 Figure 16. Adjustable VIN Undervoltage Lockout IH IP R3 EN TPS54020 PVIN IH IP R3 R5 VIN TPS54020 R5 1.22 V UDG-13035 Figure 17. Adjustable PVIN Undervoltage Lockout, PVIN 4.5 V UDG-13034 Figure 18. Adjustable VIN and PVIN Undervoltage Lockout R3, the top UVLO divider resistor is calculated using Equation 2. ae VEN(falling) o / - VSTOP VSTART c c VEN(rising) / e o R3 = ae VEN(falling) o / +I IP c 1 c VEN(rising) / H e o (2) R5, the bottom UVLO divider resistor is calculated in Equation 3. R3 VEN(falling) R5 = VSTOP - VEN(falling) + R3 (IP + IH ) In this example * * * * IH = 3.3 A IP = 1.15 A VENRISING = 1.22 V VENFALLING = 1.17 V (3) Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 13 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Feature Description (continued) 8.3.9 Adjustable Switching Frequency and Synchronization (RT/CLK) The RT/CLK pin can be used to set the switching frequency of the device in two modes. In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1200 kHz. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized to the external clock frequency with an internal PLL. The CLK mode overrides the RT mode. The device detects the proper mode automatically and switches from the RT mode to CLK mode. See Device Functional Modes for more information. 8.3.10 Soft-Start (SS) Sequence The device has two non-inverting inputs to the error amplifier. One input is the 0.6-V reference (VREF) , and the other is the SS pin voltage. The device regulates to the lower of these two voltages. A capacitor on the SS pin to ground implements a soft-start time. The internal pull-up current source of 2.3 A charges the external soft-start capacitor. The calculations for the soft-start time (tSS, 10% to 90%) and soft-start capacitor (CSS) are shown in Equation 4. The voltage reference (VREF) is 0.6 V and the soft-start charge current (Iss) is 2.3 A. I t CSS = SS SS VREF where * * * * CSS is the soft-start capacitance in nF ISS is the soft-start current in A tSS is the soft-start time in ms VREF of the voltage reference in V (4) The device stops switching and enters low-current operation when either the input voltage UVLO is triggered, or the EN pin is pulled below 1.2 V, or if a thermal shutdown event occurs. During the subsequent power up sequence, when the shutdown condition is removed, the device does not start switching until it has discharged the SS pin to ground ensuring proper soft-start behavior. 8.3.11 Power Good (PWRGD) The PWRGD pin is an open drain output. Once the VSENSE pin is between 95% and 104% of the internal voltage reference the PWRGD pin pull-down is deasserted and the pin floats. It is recommended to use a pull-up resistor between the values of 10k and 100k to a voltage source that is 5.5V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5V. The PWRGD pin is pulled low when the VSENSE pin voltage is lower than 91% or greater than 108% of the nominal internal reference voltage. Also, the PWRGD is pulled low if the input UVLO or thermal shutdowns are asserted, or the EN pin is pulled low, or the SS pin voltage is below 1.4 V. 8.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation The device has an integrated bootstrap voltage regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor should be 0.1 F. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1 V. When the voltage between BOOT and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails, 100% duty cycle operation can be achieved as long as (VIN - PVIN) > 4V. 14 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 Feature Description (continued) 8.3.13 Sequencing (SS) Many of the common power supply sequencing methods can be implemented using the SS, EN and PWRGD pins. The sequential method is illustrated in Figure 19 below using two TPS54020 devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supply reaches regulation. Figure 20 shows the method of implementing ratio-metric sequencing by connecting the SS pins of the two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time the pull-up current source must be doubled in Equation 4. TPS54020 TPS54020 TPS54020 PWRGD EN EN SS/TR CSS EN PWRGD SS/TR SS/TR CSS CSS PWRGD UDG-13032 TPS54020 EN SS/TR PWRGD UDG-13031 Figure 19. Sequential Start Up Sequence Figure 20. Ratiometric Start Up Sequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of RS1 and RS2 shown in Figure 21 to the output of the power supply to which to be tracked, or alternately another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the VOUT2 slightly before, after or at the same time as VOUT1. Equation 7 is the voltage difference between VOUT1 and VOUT2 . To design a ratio-metric start up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number in Equation 5 and Equation 6 for V. Equation 7 results in a positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved. The V variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS to VSENSE offset (VSS(offset), 29 mV) in the soft-start circuit and the offset created by the pull-up current source (ISS, 2.3 A) and tracking resistors, the VSS(offset) and ISS are included as variables in the equations. To ensure proper operation of the device, the calculated RS1 value from Equation 5 must be greater than the value calculated in Equation 8. V DV VSS(offset ) RS1 = OUT2 VREF ISS (5) RS2 = VREF RS1 VOUT2 + DV - VREF (6) DV = VOUT1 - VOUT2 RS1 > 2800 VOUT1 - 180 DV (7) (8) Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 15 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Feature Description (continued) TPS54620 BOOT EN PH VOUT1 SS/TR CSS PWRGD TPS54620 EN BOOT RS1 PH VOUT2 SS/TR RS2 PWRGD R4 VSENSE R8 UDG-13030 Figure 21. Ratiometric and Simultaneous Startup Sequence 8.3.14 Output Overvoltage Protection (OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For example, when the load current is abruptly reduced from a high value to a low value, the output voltage response can exceed the OVP trip threshold, especially if the capacitance on the output voltage bus is relatively low value. The OVP feature minimizes the overshoot by comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP threshold the high-side MOSFET is turned OFF, and the low-side MOSFET is turned ON until the OV is discharged. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn ON at the next clock cycle. During an OVP event, the low-side reverse current limit still applies, and the device does not allow current flow into the PH pin. 8.3.15 Overcurrent Protection The device is protected from overcurrent conditions with cycle-by-cycle current limiting on both the high-side MOSFET and the low-side MOSFET. 8.3.15.1 High-side MOSFET Overcurrent Protection The device implements current mode control which uses the COMP pin voltage to control the turn off of the highside MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and the current reference generated by the COMP pin voltage are compared. The high-side switch is turned off when the peak switch current intersects the current reference. High-side overcurrent protection is achieved by clamping the current reference. 16 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 Feature Description (continued) 8.3.15.2 Low-side MOSFET Overcurrent Protection While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side MOSFET current is less than the lowside MOSFET sourcing current limit at the start of a cycle. To boost efficiency in light load conditions, the control circuitry does not allow the low-side MOSFET to sink current from the load. When negative low-side MOSFET current is detected, the low-side MOSFET is turned OFF immediately for the rest of that clock cycle. In this scenario both MOSFETs are off until the start of the next cycle. Additionally, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time which is programmed for 128 switching cycles, the device shuts down and restarts only after the hiccup time of 16384 cycles has elapsed. The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions. 8.3.16 Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds a nominal value of 175C. Once the junction temperature drops below 165C typically, the internal thermal hiccup timer begins to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time of 16384 cycles has elapsed. 8.4 Device Functional Modes 8.4.1 Single-Supply Operation The TPS54020 is designed to operate from either a single input voltage, or split control logic and power stage supplies. To operate the TPS54020 from a single supply voltage, connect the VIN pin to the power stage PVIN strip. 8.4.2 Split Rail Operation The TPS54020 is designed to be able to operate from separate VIN and PVIN voltages. Bias for the control logic is provided by VIN. Power conversion input is provided by PVIN. Note that the minimum recommended VIN voltage is 4.5 V, while the minimum PVIN voltage can be as low as 1.6 V, both have a maximum recommended operating voltage of 17 V. 8.4.3 Continuous Current Mode Operation (CCM) As a synchronous buck converter, the device normally works in CCM (continuous conduction mode) under load conditions where the inductor current is always positive. It is possible for the device to exhibit extended ON or OFF times (longer than 1 clock cycle) during large signal conditions such as a severe load up-transient (extended ON time) or current limit or OV (extended OFF time). 8.4.4 Eco-mode Light-Load Efficiency Operation The TPS54020 operates in pulse skip mode (see Figure 24) at light-load currents to improve efficiency by reducing switching, gate drive and circulating current losses. When the output voltage is in regulation and the peak switch current at the end of any switching cycle remains below the pulse skipping current threshold, the device enters pulse skip mode. This current threshold is the current level corresponding to a nominal COMP voltage of 270 mV. When in pulse skip mode, the device clamps the COMP pin voltage to 270 mV and inhibits the high-side MOSFET. Further decreases in load current cannot drive the COMP pin below this clamp voltage level. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 17 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Device Functional Modes (continued) When the device is not switching while in pulse skip mode, the output voltage tends to decay. As the voltage control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the device enables the high-side MOSFET, and a switching pulse initiates on the next clock cycle. The COMP pin voltage sets the peak switch current. The output voltage re-charges to the regulation set point value, and then the demand for peak switch current will decrease. Eventually the COMP pin voltage once again falls below the pulse skip mode threshold at which time the device again enters pulse skip mode. Bias circuits in the BOOT regulator and high-side MOSFET gate drive both return bias current out from the PH pin. While this current is small and in the range of 150 A (nominal), during very light load conditions, it is possible that the output voltage rises above the desired output voltage setpoint due to this current. If the application design anticipates that system loads could fall below this current level, it is recommended to add a fixed resistor load to the design that dissipates this current. An easy implementation of this fixed load can be achieved with the feedback voltage divider resistors. The recommendation is to use a lower divider resistor value of 2.5 k or lower in this case, and this lower divider resistor should be installed even when the output voltage setpoint is 0.6 V. PH node = 10 V/div PH node = 10 V/div VOUT = 500 mV/div VOUT = 500 mV/div Inductor Current = 2.5 A/div Inductor Current = 2.5 A/div Figure 22. TPS54020 in Continuous Conduction Mode Figure 23. TPS54020 in Discontinuous Conduction Mode PH node = 10 V/div VOUT = 500 mV/div Inductor Current = 2.5 A/div Figure 24. TPS54020 in Pulse Skipping Mode 18 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 Device Functional Modes (continued) 8.4.5 Adjustable Switching Frequency (RT Mode) To determine the RRT resistance for a given switching frequency, use Equation 9, or the curve in Figure 25. In an attempt to reduce the overall solution size, the temptation is to set the switching frequency as high as possible, but the designer should consider the minimum controllable on-time and the tradeoff between fSW and supply efficiency. -0.964356 fSW = 42533.5 (RRT ) where RRT is in k fSW is in kHz (9) Switching Frequency (kHz) * * 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 40 60 80 100 120 140 160 180 200 220 240 260 Timing Resistance (k) G000 Figure 25. Timing Resistance vs. Switching Frequency 8.4.6 Synchronization (CLK mode) An internal phase locked loop (PLL) has been implemented to allow synchronization at frequencies between 200 kHz and 1200 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% and 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 26. Before the external clock is present, the device functions in RT mode and the switching frequency is set by the RRT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode to RT mode because the internal switching frequency decreases to 100 kHz first before returning to the switching frequency set by the RRT resistor. RT/CLK Mode Select TPS54020 RT/CLK RRT UDG-13033 Figure 26. Synchronization to External CLK and Rt Mode Interface Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 19 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Small Signal Model for Loop Response Figure 27 shows an equivalent model for the device control loop which can be modeled in a circuit simulation program to check frequency response and transient responses. The error amplifier is a transconductance amplifier with a gm of 1300 A/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor ROEA (2.38 M) and capacitor COUT(ea) (20.7 pF) model the open loop gain and frequency response of the error amplifier. A low amplitude (between 10 mV and 100 mV AC) voltage source between node a and node b effectively breaks the control loop for the frequency response measurements. Plotting the designators a-c yields the small signal response of the plant, and plotting designators c-b yields the small signal response of the frequency compensation. Plotting designators a-b yields the small signal response of the overall loop. The dynamic loop response can be simulated by replacing the RLOAD with a current source with the appropriate load step amplitude and step rate in a time domain analysis. TPS54020 PH VOUT Power Stage 20 A/V a b R ESR R4 VSENSE COMP R LOAD C OUT c + C10 C OUT(ea) R6 R OUT(ea) 0.6 V gM 1300 mA/V R8 C8 UDG-13038 Figure 27. Small Signal Model for Loop Response 9.1.2 Simple Small Signal Model for Peak Current Mode Control Figure 28 is a small signal model that can be used to understand how to design the frequency compensation network. This is a simplified model that does not include the effects of slope compensation. The device power stage, or Plant, can be approximated by a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 27) is the power stage transconductance (gmps) which is 20 A/V for the TPS54020 (when ILIM is open). The DC gain or amplification of the power stage, ADC, is the product of gmps and the load resistance RL as shown in Equation 11 with resistive loads. As the load current 20 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 Application Information (continued) increases, the DC gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 29. As the load current decreases, the gain increases and the pole frequency reduces, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. VOUT VC RESR gmps RL CO Figure 28. Simplified Small Signal Model for Peak Current Mode Control VOUT Adc VC RESR gmps fp RL CO fz Figure 29. Simplified Frequency Response for Peak Current Mode Control The simplified control-to-output transfer function is shown in Equation 10. ae s o 1+ c / 2p fZ o VOUT e = Adc VC ae s o 1+ c / e 2p fP o (10) The power stage DC gain is shown in Equation 11. Adc = gM(PS ) RLOAD (11) The pole from load is show in Equation 12. 1 fP = COUT RLOAD 2p (12) To calculate the zero from the capacitor ESR use Equation 13. 1 fZ = COUT RESR 2p where Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 21 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Application Information (continued) * * * * * gM(ea) is the transconductance amplifier gain (1300 A/V) gM(ps) is the power stage gain (20 A/V) RLOAD is the load resistance COUT is the output capacitance RESR is the equivalent series resistance of the output capacitor (13) 9.1.3 Small Signal Model for Frequency Compensation The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 30. In Type IIA, one additional high frequency pole, C10, is added to attenuate high frequency noise. In Type III, one additional capacitor, C7, is added to provide a phase boost at the crossover frequency. See Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352) for a complete explanation of Type III compensation. The design guidelines described in the Designing the Device Loop Compensation section are provided for advanced designers who prefer to compensate using the general method. The equations below apply only to designs in which ESR zero is above the bandwidth of the control loop. This is usually true with ceramic output capacitors. VOUT TPS54020 C7 R4 VSENSE COMP Type III + R6 R6 C10 C8 Type IIB C8 VREF R8 gM(ea) COUT(ea) ROUT(ea) Type IIA UDG-13039 Figure 30. Types of Frequency Compensation NOTE The comp-to-switch transconductance gM(ps) is dependent on the current limit level that is selected. If a different current limit option is selected, the compensation needs to be redesigned with the new gM(ps). 9.1.4 Designing the Device Loop Compensation The general design guidelines for device loop compensation are shown in this section. 9.1.4.1 Step One: Determine the Crossover Frequency (fC) To begin, choose 1/10th of the switching frequency, fSW 9.1.4.2 Step Two: Determine a Value for R6. Resistor R6 is calculated in Equation 14. 2p COUT fC VOUT R6 = gM(ea ) VREF gM(ps ) 22 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 Application Information (continued) where * * * * gM(ea) is the transconductance amplifier gain (1300 A/V) gM(ps) is the power stage gain (20 A/V) VREF is the reference voltage (0.6V) (14) 9.1.4.3 Step Three: Calculate the Compensation Zero. Place a compensation zero at the dominant pole found in Equation 12. The zero is achieved by the combination of R6 and C8, which is calculated in Equation 15. RLOAD C C8 = OUT R6 (15) 9.1.4.4 Step Four: Calculate the Compensation Noise Pole. C10 is optional. It can be used to cancel the zero from the ESR (equivalent series resistance) of the output capacitor (COUT). COUT R C10 = ESR R6 (16) 9.1.4.5 Step Five: Calculate the Compensation Phase Boost Zero. Type III compensation can be implemented with the addition of one capacitor, C7. This addition allows for slightly higher loop bandwidths and higher phase margins. If used, C7 is calculated from Equation 17 1 C7 = 2p R4 fC (17) 9.1.5 Fast Transient Considerations In applications where fast transient responses are very important, Type III frequency compensation can be used instead of the traditional Type II frequency compensation. For more information about Type II and Type III frequency compensation circuits, see Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352). 9.2 Typical Application The application schematic shown in Figure 31 meets the requirements shown in Table 3. This circuit is available as the TPS54020EVM-082 evaluation module. The design procedure is given in this section. For more information about Type II and Type III frequency compensation circuits, see Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352). Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 23 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Typical Application (continued) 2 3 0 R1 R2 0 SYNC OUT TP3 TP1 J1 33.1 PVIN + 2 8V to 17V - 1 R3 PVIN PWRGD C1 + 68uF C2 0.1uF C3 22uF VIN C4 22uF TP2 TP4 10k VIN_SEL PVIN 1 C5 PVIN 2 4.7uF 8V to 17V 6 BOOT PWRGD 5 RT_CLK PGND TP5 1.1 uH TP6 IND_744314110 PVIN 7 1 PH 8 RTN COMP VOUT L1 0.1uF PGND 9 J3 2 PH C7 100uF TP7 C8 100uF R6 69.8k TP12 R8 J5 J6 TRACK/SS 2 R7 5.11k 20.0k R12 20.0k C13 0.1uF C11 1 C12 22nF 1 2 R11 13.3k 1.8V @ 10A TP10 TP11 TP14 VOUT - R5 LOOP 49.9 TP9 SYNC_IN 1 + 2 EN 4 EN/UVLO 1 C9 100uF 15 14 13 12 11 10 C10 0.1uF TP8 VSENSE - 2 TPS54020RUW EN 1 4 U1 J4 + 3 SYNC_OUT VIN C6 SS_TR VIN 2 ILIM 3 HICCUP 1 VIN R4 J2 C14 0.1uF R13 3.01k C15 220pF R9 100k R10 2.55k 500kHz AGND TP13 1 NOTES: 1 DO NOT INSTALL 3 HICCUP_SEL CYCLE-CYCLE: INSTALL R1 16384 CYCLES: REMOVE R1 ILIM_SEL 2 9.4A: INSTALL R2 = 500k ohms 4 R6 and R11 yield Von = 7.5V, Voff = 7.1V 12.75A: INSTALL R2 = short 15A: REMOVE R2 Figure 31. Typical Application Circuit 9.2.1 Design Requirements A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we start with the known parameters shown in Table 3. Table 3. Design Example Characteristics PARAMETER CONDITIONS MIN TYP MAX UNIT VOUT Output voltage 1.8 V IOUT Output current 10 A Transient response VIN Input voltage VOUT(ripple) Output voltage ripple fSW 24 VOUT 5 % 5-A load step 8 12 A 17 V 10 mV(P-P) V Start input voltage Rising input voltage 7.5 Stop Input Voltage Falling input voltage 7.1 V 500 kHz Switching Frequency Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 9.2.2 Detailed Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. 9.2.2.1 Operating Frequency The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher switching frequency causes extra switching losses, which reduce the converter's efficiency and thermal performance. In this design, a moderate switching frequency of 500 kHz is selected to achieve both a small solution size and a high efficiency operation. 9.2.2.2 Output Inductor Selection To calculate the value of the output inductor, use Equation 18. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications. VIN(max ) - VOUT VOUT LOUT = IOUT KIND VIN(max ) fSW (18) For this design example, use KIND = 0.3 and the inductor value is calculated to be 1.07H. For this design, a nearest standard value was chosen at 1.0H. For the output filter inductor, it is important that the rms current and saturation current ratings not be exceeded. The rms and peak inductor current are calculated in Equation 19 and Equation 20. IRIPPLE = (V IN(max ) - VOUT L1 ) VOUT VIN(max ) fSW ( ae 1 c VOUT VIN(max ) - VOUT 2 IL(rms ) = (IOUT ) + 12 cc VIN(max ) L1 fSW e IL(peak ) = IOUT (19) )o/ 2 / / o (20) aeI o + c RIPPLE / 2 o e (21) For this design, the rms inductor current is calculated to be 10.04 A and the peak inductor current is 11.6A. The chosen inductor is 1.0 H, with a saturation current rating of 13 A. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. 9.2.2.3 Output Capacitor Selection There are three primary considerations for selecting the value of the output capacitor. The output capacitor affects three criteria: * how the regulator responds to a change in load current or load transient * the output voltage ripple * the amount of capacitance on the output voltage bus The last of these three considerations is important when designing regulators that must operate where the electrical conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these three criteria. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 25 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com 9.2.2.3.1 Response to a Load Transient The desired response to a load transient is the first criteria. The output capacitor needs to supply the load with the required current when not immediately provided by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects the magnitude of voltage deviation during the transient. In order to meet the requirements for control loop stability, this peak current mode regulator requires the addition of compensation components in the design of the error amplifier. While these compensation components provide for a stable control loop, they often also reduce the speed with which the regulator can respond to load transients. The delay in the regulator response to load changes can be two or more clock cycles before the control loop reacts to the change. During that time the difference between the old and the new load current must be supplied (or absorbed) by the output capacitance. The output capacitor impedance must be designed to be able to supply or absorb the delta current while maintaining the output voltage within acceptable limits. Equation 22 calculates the minimum capacitance necessary to limit the voltage deviation based on a delay of 2 switching cycles. 2 DIOUT COUT > fSW DVOUT where * * * IOUT is the change in output current fSW is the switching frequency VOUT is the allowable change in the output voltage (22) For this example, the transient load response is specified as a 5% change in VOUT for a load step of 5 A. For this example, IOUT = 5.0 A and VOUT = 0.05 x 1.8 = 0.09 V. Using these numbers gives a minimum capacitance of 222 F. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. 9.2.2.3.2 Output Voltage Ripple The output voltage ripple is the second criteria. Equation 23 calculates the minimum output capacitance required to meet the output voltage ripple specification. I 1 COUT > RIPPLE 8 fSW VOUT(ripple ) where * * * fSW is the switching frequency VRIPPLE is the maximum allowable output voltage ripple IRIPPLE is the inductor ripple current. (23) In this case, the maximum output voltage ripple is 10 mV. Under this requirement, the minimum output capacitance for ripple (as calculated in Equation 24) yields 80.5 F. Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 3 m, and this is the requirement when the impedance of the output capacitance is dominated by ESR, such as with an electrolytic capacitor. However, because the output voltage ripple is a combination of capacitive ripple and resistive ripple, the ESR must be much lower than this result when the capacitance is purely ceramic. This is because the lower capacitance values obtained with ceramic capacitors will result in a larger capacitive ripple component of the total ripple. VOUT(ripple ) RESR = IRIPPLE (24) Additional capacitance de-ratings for aging, temperature and DC bias should be factored in, which increases the minimum required capacitance value. For this design example, three 100 F, 6.3 V, X5R, ceramic capacitors with 2 m each of ESR were selected. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (root mean square) value of the maximum ripple current. Equation 25 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields 929 mA. 26 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 IC(rms ) = ( VOUT VIN(max ) - VOUT ) 12 VIN(max ) L1 fSW (25) 9.2.2.3.3 Bus Capacitance The amount of bus capacitance is the third criteria. This requirement is optional. However, extra output bus capacitance should be considered in systems where the electrical environment is unpredictable, or not fully defined, or can be subject to severe events such as hot plug events or even electrostatic discharge (ESD) events. During a hot plug event, when a discharged load capacitor is plugged into the output of the regulator, the instantaneous current demand required to charge this load capacitance will be far too rapid to be supplied by the control loop. Often the peak charging current can be multiple times higher than the current limit of the regulator. Additional output capacitance will help maintain the bus voltage within acceptable limits. For hot plug events, the amount of required bus capacitance can be calculated if the load capacitance is known, based on the concept of conservation of charge. An ESD event, or even non-direct lightning surges at the primary circuit level can cause glitches at this converter system level. A glitch of sufficient amplitude to falsely trip OVP or UVLO can cause several clock cycles of disturbance. In such cases it is beneficial to design in more bus capacitance than is required by the simpler load transient and ripple requirements. The amount of extra bus capacitance can be calculated based on maintaining the output voltage within acceptable limits during the disturbance. This capacitance can be as much as required to fully support the load for the duration of the interrupted converter operation. 9.2.2.4 Input Capacitor Selection The TPS54020 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 F of effective capacitance on the PVIN input voltage pins and another 4.7 F on the VIN input voltage pin. In some applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple to the device during full load. The input ripple current can be calculated using Equation 26. ICIN(rms ) = IOUT ( VIN(min ) - VOUT VOUT VIN(min ) VIN(min ) ) (26) The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. For this example, two 22-F, 25-V ceramic capacitors and one 68-F, 25 V electrolytic capacitor in parallel have been selected for the PVIN voltage rail. For the VIN voltage rail, one 4.7F 25V ceramic capacitor was selected. The VIN and PVIN inputs are normally tied together so the TPS54020 may operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example values, IOUT(max) = 10 A, CIN = 48.7 F, fSW = 500 kHz, yields an input voltage ripple of 103 mV and a RMS input ripple current of 4.18 Arms. Because an electrolytic capacitor typically features a much higher ESR, it was not included in this calculation. The input capacitor ripple voltage is calculated in Equation 27. DVIN = IOUT(max ) 0.25 CIN fSW (27) Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 27 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com 9.2.2.5 Soft-Start Capacitor Selection The soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The extra current required to charge the output capacitors could cause the TPS54020 to reach the current limit. The soft start current surge from the input may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft-start capacitor value can be calculated using Equation 28. For the example circuit, the soft-start time is not critical because the output capacitor value is only 300 F which does not require much current to charge to 1.8 V. The example circuit has the soft-start time set to an arbitrary value of 30 ms which requires a 100 nF capacitor. In this case, ISS is 2.3 A and VREF is 0.6 V. I t CSS = SS SS VREF where * * * * CSS is the soft-start capacitance in nF ISS is the soft-start current in A tSS is the soft-start time in ms VREF of the voltage reference in V (28) 9.2.2.6 Bootstrap Capacitor Selection A ceramic capacitor with a value of 0.1-F must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have voltage rating of 10 V or higher. 9.2.2.7 Undervoltage Lockout Set Point It is recommended that an external divider be connected to the EN pin for clean transitions from OFF to ON and ON to OFF. The Undervoltage Lock Out (UVLO) can be designed using the external voltage divider network of R6 and R11. R6 is connected between VIN and the EN pin of the TPS54020 and R11 is connected between EN and GND. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 7.5 V (UVLO start or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 7.1 V (UVLO stop or disable). Equation 2 and Equation 3 above can be used to calculate the values for the upper and lower resistor values. For the UVLO voltages specified the nearest standard resistor value for R6 is 69.8 k and for R11 is 13.3 k. 9.2.2.8 Output Voltage Feedback Resistor Selection The resistor divider network R7 and R10 is used to set the output voltage. For the example design, R10 was set to 2.55 k. This yields a value of 5.11 k for R7. These relatively low values are used so as to provide some minimum DC load current that is higher than the PH pin bias leakage current. 9.2.2.8.1 Minimum Output Voltage Due to internal design limitations of the TPS54020, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.6 V. However, the output voltage may also be limited to values greater than 0.6 V by the minimum controllable on time. The minimum output voltage in this case is given by Equation 29 ( ( )) ( VOUT(min ) = tON(min ) fSW (max ) VIN(max ) + IOUT(min ) RDS2(min ) - RDS1(min ) - IOUT(min ) RLOAD - RDS2(min ) ) where * * * * * 28 VOUT(min) is the minimum achievable output voltage tON(min) is the minimum controllable on-time (135 nsec max) fSW(max) is the maximum switching frequency including tolerance VIN(max) is the maximum input voltage IOUT(min) is the minimum load current Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 * * * RDS1(min) is the minimum high-side MOSFET on resistance (36 m to 32 m typical) RDS2(min) is the minimum low-side MOSFET on resistance (19 m typical) RLOAD is the series resistance of output inductor (29) 9.2.2.9 Compensation Component Selection There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54020. Because the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use the PSPICE model for a more accurate design. First, the modulator pole, fP(mod), and the esr zero, fZ(mod) must be calculated using Equation 30 and Equation 31. For the output capacitance, use a derated value of 225 F. As a quick estimate, an fC value between 3 and 5 times the double pole frequency of the output filter is chosen. In this case an fC of 35 kHz was selected. fP(mod) is 3.93 kHz and fZ(mod) is 10.6 MHz. IOUT fP(mod) = 2 p VOUT COUT (30) fZ(mod) = 1 2 p RESR COUT (31) Now the compensation components can be calculated. First calculate the value for C12 which sets the gain of the compensated network at low frequencies far below fC. Because the desired fC is 35 kHz, and the expected gain curve is a single pole roll off, then two decades below fC (which is 350 Hz), the gain should be +40 dB. Following this logic, the plant gain at DC is calculated in Equation 32. ae aeV oo A Vdc = 20 log c gM(ea ) 2.38M gM(ps ) c OUT / / = 80.94 dB c / e IOUT o o e (32) This implies that at 350 Hz, the compensation pole capacitor C12 should reduce the gain by (80.94-40) = 40.94 dB, or result in a gain of -40.94 dB. (See Equation 33) ae ZC o 20 log c / = -40.94 dB e 2.38M o (33) ZC = 2.38Meg 10 ae -40.94 o c 20 / e o = 21.367kW (at 350 Hz ) (34) 1 1 C= = = 21.28nF 2p fSW ZC 2p 350 21.367 where * fSW is in kHz The closest standard value is 22 nF. (35) From Equation 30, the required compensation zero resulting from R13 should be placed at fP(mod) of 3.93 kHz. 1 fZ(comp ) = 2p R13 C12 (36) 1 1 R13 = = = 1.84 2p fZ(comp ) C12 2p 3.93 22 where * * * fZ(comp) is in kHz C12 is in nF R13 is in k (37) This value was adjusted after actual Bode measurements to 3.01 k. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 29 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R13 and C12. The pole frequency can be placed at the ESR zero frequency of the output capacitor as given by Equation 13. Use Equation 38 to calculate the required capacitor value for C10. COUT R 666 225 F = = 49 pF C10 = ESR R13 3.01 k (38) This value was adjusted upwards to 220pF to reduce jitter. 9.2.3 Application Curves VOUT = 100 mV/div AC coupled VIN = 5 V/div IOUT = 2 A/div IOUT = 2.5 A/div VOUT = 500 mV/div Load step = 2.5 A to 7.5A Slew rate = 625 mA/s Timebase = 200 s/div Timebase = 5 ms/div Figure 33. Start-Up With VIN Figure 32. Load Transient VIN = 5 V/div VIN = 5 V/div PH = 10 V/div IOUT = 2 A/div VOUT = 500 mV/div VOUT = 500 mV/div EN = 2 V/div EN = 2 V/div, Timebase = 5 ms/div Timebase = 5 ms/div Figure 34. Start-Up With EN Figure 35. Start-Up With Prebias PH = 5 V/div PH = 5 V/div VIN = 200 mV/div AC coupled VOUT = 20 mV/div AC coupled Timebase = 1 s/div Timebase = 1 s/div Figure 36. Output Voltage Ripple With Full Load 30 Figure 37. Input Voltage Ripple With Full Load Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 40 Gain (dB) 30 150 1.840 120 1.835 90 1.830 20 60 10 30 0 0 -10 -30 Magnitude [B/A] Phase [B-A] Zero -20 -30 100 1000 10000 Frequency (Hz) 100000 Output Voltage (V) VOUT = 1.8 V VIN = 12 V RLOAD = 5 A Phase () 50 1.825 1.820 1.815 IOUT = 0.1 A IOUT = 1 A IOUT = 5 A IOUT = 10 A 1.810 -60 1.805 -90 1000000 1.800 5 6 1.830 Efficiency (%) Output Voltage (V) 1.835 1.825 1.820 1.815 VIN = 5 V VIN = 12 V VIN = 17 V 1.800 0 1 2 3 9 TJ = 25C fSW = 500 kHz VOUT =1.8 V 4 5 6 7 Output Current (A) 8 9 10 11 12 13 Input Voltage (V) 14 15 16 17 G000 Figure 39. Line Regulation 1.840 1.805 8 G000 Figure 38. Closed-Loop Bode Response 1.810 7 TJ = 25C fSW = 500 kHz VOUT =1.8 V 10 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 VIN = 5 V VIN = 12 V VIN = 17 V TA = 25C VOUT = 1.8 V fSW = 500 kHz 0 G000 Figure 40. Load Regulation 1 2 3 4 5 6 7 Output Current (A) 8 9 10 G000 Figure 41. Efficiency Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 31 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com 10 Power Supply Recommendations The TPS54020 operates from a controller bias voltage supply between 4.5 V and 17 V, and a power stage input voltage between 1.6 V and 17 V. The TPS54020 is designed to support either split-rail or single-supply operation, and may be operated from separate PVIN and VIN voltages. Proper bypassing of input supplies and internal regulators is also critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in the Layout and Pin Configuration and Functions sections. 11 Layout 11.1 Layout Guidelines Layout is a critical portion of good power supply design. See Figure 42 for a PCB layout example. The top layer contains the main power traces for PVIN, VIN, VOUT and VPHASE. Also on the top layer are connections for several analog pins of the TPS54020 and a large area filled with PGND. The two internal layers are the same and contain mostly power planes, including PGND, Vout, PVIN and VPHASE. The bottom layer contains the remainder of the analog circuit connections, plus power planes similar to the internal layers. The top-side power and ground planes are connected to the bottom and internal power and ground planes with multiple vias placed around the board including several vias directly under the TPS54020 device to provide a thermal path from the top-side power planes to the other layer power planes. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supply performance. To help eliminate these noise problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quiet analog ground trace rather than the power ground trace of the PVIn bypass capacitor. Because the PH connection is the switching node, the output inductor should be located close to the PH pin, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The small signal components should be grounded to the analog ground path as shown. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal trace lengths. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline. Land pattern and stencil information is provided in the data sheet addendum. The dimension and outline information is for the standard RUW package. 32 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 11.2 Layout Example Figure 42. TPS54020EVM-082 Top Side Copper Figure 43. TPS54020EVM-082 Top Side Component Placement Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 33 TPS54020 SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 www.ti.com Layout Example (continued) Figure 44. TPS54020EVM-082 Bottom Side Component Placement 34 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 TPS54020 www.ti.com SLVSB10D - JULY 2012 - REVISED DECEMBER 2014 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352) 12.2 Trademarks HotRod, Eco-mode, SWIFT are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: TPS54020 35 PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS54020RUWR ACTIVE VQFN-HR RUW 15 3000 Pb-Free (RoHS Exempt) CU NIPDAU Level-1-260C-UNLIM -40 to 150 54020 TPS54020RUWT ACTIVE VQFN-HR RUW 15 250 Pb-Free (RoHS Exempt) CU NIPDAU Level-1-260C-UNLIM -40 to 150 54020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54020RUWT Package Package Pins Type Drawing VQFNHR RUW 15 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 12.4 Pack Materials-Page 1 3.75 B0 (mm) K0 (mm) P1 (mm) 3.75 1.15 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54020RUWT VQFN-HR RUW 15 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2017, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: TPS54020RUWT TPS54020RUWR