Standard Products
UT54ACS164/UT54ACTS164
8-Bit Shift Registers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
AND-gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Direct clear
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS164 - SMD 5962-96556
UT54ACTS164 - SMD 5962-96557
DESCRIPTION
The UT54ACS164 and the UT54ACTS16 4 are 8-b it shift reg-
isters which feature AND-gated serial inputs and an asynchro-
nous clear. The gated serial inputs (A and B) permit complete
control over incoming data. A low at either input inhibits entry
of new data and resets the first flip-flop to the low level at the
next clock pulse. A high-level at both serial inputs sets the first
flip-flop to the high level at the next clock pulse. Data at the
serial inputs may be changed while the clock is high or low,
providing the minimum setup time requirements are met. Clock-
ing occurs on the low-to-high-level transition of the clock input.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
Notes:
1. QA0, QB0, QH0 = th e level of QA, QB or QH, respectively , before the indicated
steady-state input conditions were established.
2. QAn and QGn = the level of QA or QG before the most recent ↑ transition of
the clock; indicates a one-bit shift.
PINOUTS
14-Pin DIP
Top View
14-Lead Flatpa ck
Top View
LOGIC SYMBOL
INPUTS OUTPUTS
CLR CLK A B QAQB ... QH
L X X X L L L
H L X X QA0 QB0 QH0
H↑H H H QAn QGn
H↑L X L QAn QGn
H↑X L L QAn QGn
1
2
3
4
5
7
6
14
13
12
11
10
8
9
A
B
QA
QB
QC
QD
VSS
VDD
QH
QG
QF
QE
CLR
CLK
1
2
3
4
5
7
6
14
13
12
11
10
8
9
VDD
QH
QG
QF
QE
CLR
CLK
A
B
QA
QB
QC
QD
VSS
(9)
CLR (8)
CLK R
1D
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
(1)
A(2)
B(3) QA
SRG8
&
(4) QB
(5) QC
(6) QD
(10) QE
(11) QF
(12) QG
(13) QH
C1/