EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 1 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
Access Times of 15, 17, 20, 25, 35, 45, 55ns
Data Retention Function (LPA version)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 512Kx8
Commercial, Industrial and Military Temperature Rang es
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
Single +5V (±10%) Supply Operation
The EDI88512CA is a 4 megabit Monolithic CMOS Stat ic RAM.
The 32 pin DIP pinout adheres to the JEDEC evo lu tion ary stan dard
for the four megabit device. All 32 pin packages are pin for pin
up grades for the single chip enable 128K x 8, the EDI88128CS.
Pins 1 and 30 be come the higher order addresses.
The 36 pin revolutionary pinout also adheres to the JEDEC
stan dard for the four megabit device. The cen ter pin power and
ground pins help to reduce noise in high performance systems.
The 36 pin pinout also allows the user an upgrade path to the
future 2Mx8.
A Low Power version with Data Retention (EDI88512LPA) is
also available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
*This product is subject to change without notice.
PIN DESCRIPTION
I/O0-7 Data Inputs/Outputs
A0-18 Address Inputs
WE# Write Enables
CS# Chip Selects
OE# Output Enable
VCC Power (+5V ±10%)
VSS Ground
NC Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
A
0-18
I/O
0-7
WE#
CS#
OE#
FIGURE 1 – PIN CONFIGURATION
36 PIN
TOP VIEW
NC
A18
A17
A16
A15
OE#
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
36 pin
Revolutionary
A0
A1
A2
A3
A4
CS#
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
32 PIN
TOP VIEW
32 pin
Evolutionary
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 2 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter Value Unit
Voltage on any pin relative to Vss -0.5 to 7.0 V
Operating Temperature TA (Ambient)
Commercial 0 TA +70 °C
Industrial -40 TA +85 °C
Military -55 TA +125 °C
Storage Temperature, Plastic -65 TA +150 °C
Power Dissipation 1.5 W
Output Current 20 mA
Junction Temperature, TJ175 °C
NOTE:
Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and func tion al operation of the device at these or any other
conditions greater than those in di cat ed in the operational sections of this spec i fi ca tion is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
OE# CS# WE# Mode Output Power
X H X Standby High Z Icc2, Icc3
H L H Output Deselect High Z Icc1
L L H Read Data Out Icc1
X L L Write Data In Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Voltage VSS 000V
Input High Voltage VIH 2.2 — VCC + 0.3 V
Input Low Voltage VIL -0.3 — +0.8 V
CAPACITANCE
(TA = +25°C)
Parameter Symbol Condition Max Unit
Address Lines CIVIN = Vcc or Vss, f = 1.0MHz 12 pF
Data Lines COVOUT = Vcc or Vss, f = 1.0MHz 14 pF
These parameters are sampled, not 100% tested.
Input Pulse Levels VSS to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Levels 1.5V
Output Load Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
30pF
480Ω
Vcc
Q
Figure 1 Figure 2
255Ω 5pF
480Ω
Vcc
Q
255Ω
AC TEST CONDITIONS
DC CHARACTERISTICS
(VCC = 5V, TA = -55°C to +125°C)
Parameter Symbol Conditions Min Max Units
Input Leakage Current ILI VIN = 0V to VCC -10 10 μA
Output Leakage Current ILO VI/O = 0V to VCC -10 10 μA
Operating Power Supply Current ICC1WE#, CS# = VIL, II/O = 0mA, Min Cycle (17ns) — 250 mA
(20 -55ns) — 225 mA
Standby (TTL) Power Supply Current ICC2CS# VIH, VIN VIL, VIN VIH —60mA
Full Standby Power Supply Current ICC3CS# VCC -0.2V
VIN Vcc -0.2V or VIN 0.2V
CA — 25 mA
LPA — 20 mA
Output Low Voltage VOL IOL = 6.0mA — 0.4 V
Output High Voltage VOH IOH = -4.0mA 2.4 — V
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 3 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS – READ CYCLE
(VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C)
Parameter
Symbol 15ns 17ns 20ns 25ns 35ns 45ns 55ns
UnitsJEDEC Alt. Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle Time tAVAV tRC 15 17 20 25 35 45 55 ns
Address Access Time tAVQV tAA 15 17 20 25 35 45 55 ns
Chip Enable Access Time tELQV tACS 15 17 20 25 35 45 55 ns
Chip Enable to Output in Low Z (1) tELQX tCLZ 2333333ns
Chip Disable to Output in High Z (1) tEHQZ tCHZ 070708010015020020ns
Output Hold from Address Change tAVQX tOH 0000000ns
Output Enable to Output Valid tGLQV tOE 8 8 10 12 15 25 30 ns
Output Enable to Output in Low Z (1) tGLQX tOLZ 0000000ns
Output Disable to Output in High Z(1) tGHQZ tOHZ 070708010015020020ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(VCC = 5.0V, VSS = 0V, -55°C≤ TA ≤ +125°C)
Parameter
Symbol 15ns 17ns 20ns 25ns 35ns 45ns 55ns
UnitsJEDEC Alt. Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 15 17 20 25 35 45 55 ns
Chip Enable to End of Write tELWH
tELEH
tCW
tCW
13
13
14
14
15
15
17
17
25
25
30
30
50
50
ns
ns
Address Setup Time tAVWL
tAVEL
tAS
tAS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
Address Valid to End of Write tAVWH
tAVEH
tAW
tAW
13
13
14
14
15
15
17
17
25
25
30
30
50
50
ns
ns
Write Pulse Width tWLWH
tWLEH
tWP
tWP
13
13
14
14
15
15
17
17
25
25
30
30
45
45
ns
ns
Write Recovery Time tWHAX
tEHAX
tWR
tWR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
Data Hold Time tWHDX
tEHDX
tDH
tDH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1) tWLQZ tWHZ 080808010025030030ns
Data to Write Time tDVWH
tDVEH
tDW
tDW
8
8
8
8
10
10
12
12
20
20
25
25
40
30
ns
ns
Output Active from End of Write (1) tWHQX tWLZ 0000000ns
1. This parameter is guaranteed by design but not tested.
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 4 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
A
DDRESS
DATA I/O
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
tAVQX
tAVQV
tAVAV
DATA 2
ADDRESS 1 ADDRESS 2
DATA 1
ADDRESS
DATA OUT
READ CYCLE 2 (WE# HIGH)
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tAVAV
tEHQZ
tGHQZ
OE#
CS#
FIGURE 2 – TIMING WAVEFORM – READ CYCLE
WRITE CYCLE 2, CS# CONTROLLED
tAVEH
tELEH
tEHAX
tWLEH
tDVEH tEHDX
tAVAV
DATA VALID
HIGH Z
DATA OUT
tAVEL
ADDRESS
DATA IN
WE#
CS#
FIGURE 4 – WRITE CYCLE – CS# CONTROLLED
FIGURE 3 – WRITE CYCLE – WE# CONTROLLED
ADDRESS
DATA IN
WRITE CYCLE 1, WE# CONTROLLED
tAVWH
tELWH
tWHAX
tWLWH
tDVWH
tWLQZ tWHQX
tAVWL
tWHDX
tAVAV
DATA VALID
HIGH Z
WE#
CS#
DATA OUT
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 5 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY)
(-55°C ≤ TA ≤ +125°C)
Characteristic
Low Power Version only Sym Conditions Min Typ Max Units
Data Retention Voltage
Data Retention Quiescent Current
VCC
ICCDR
VCC = 2.0V
CS# VCC -0.2V
2
–
–
–
–
2
V
mA
Chip Disable to Data Retention Time
Operation Recovery Time
tCDR
TR
VIN VCC -0.2V
or VIN 0.2V
0
tAVAV
–
–
–
–
ns
ns
FIGURE 5 – DATA RETENTION – CS# CONTROLLED
DATA RETENTION MODE
CS# = VCC -0.2V
VCC
CS#
tCDR
VCC
4.5V 4.5V
tR
DATA RETENTION, CS# CONTROLLED
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 6 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
Pin 1 Indicator
0.020
0.016
0.200
0.125
0.100
TYP
15 x 0.100 = 1.500
0.155
0.115
1.616
1.584
0.061
0.017
0.600
NOM
0.060
0.040
0.620
0.600
PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP, SMD 5962-95600XXMXA
ALL DIMENSIONS ARE IN INCHES
PACKAGE 326: 32 LEAD SIDEBRAZED CERAMIC DIP
Pin 1 Indicator
0.020
0.016
0.200
0.125
0.100
TYP
15 x 0.100 = 1.500
0.155
0.115
0.420
0.400
1.616
1.584
0.061
0.017
0.400
NOM
1
1
ALL DIMENSIONS ARE IN INCHES
PACKAGE 140: 32 LEAD CERAMIC SOJ, SMD 5962-95600XXMUA
0.050
TYP
0.444
0.430
0.840
0.820
0.155
0.106
0.379
0.010
0.006
0.019
0.015
ALL DIMENSIONS ARE IN INCHES
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 7 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
PACKAGE 316: 36 PIN CERAMIC FLATPACK, SMD 5962-95600XXMTA
Pin 1
0.019
0.015
0.040
0.030
0.395
0.385
0.125
0.100
0.050
TYP
0.515
0.505
0.045
0.020
0.007
0.003
0.920 ± 0.010
0.370
0.250
1.00 REF
ALL DIMENSIONS ARE IN INCHES
PACKAGE 321: 32 PIN THINPACK™ FLATPACK, SMD 5962-95600XXMYA
0.050
TYP 0.016 ± 0.008
0.118
MAX.
0.020
0.030
0.008
0.005
0.427
0.429
0.838
MAX
0.567
0.559
ALL DIMENSIONS ARE IN INCHES
+0.002
0.006 -0.001
0.838 MAX.
0.016
± 0.008
0.300
± 0.010
0.423
± 0.004 0.024 REF.
0.050 ± 0.002
TYP.
0.112 MAX.
PACKAGE 344: 32 PIN CERAMIC FLATPACK, SMD 5962-95600XXM9A
ALL DIMENSIONS ARE IN INCHES
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 8 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
PACKAGE 327: 36 LEAD CERAMIC SOJ, SMD 5962-95600XXMMA
0.050
TYP
0.44
4
0.43
4
0.920
0.940
0.155
0.106
0.379
0.010
0.006
0.019
0.015
PACKAGE 502: 36 LEAD CERAMIC LCC
0.080
0.100
0.054
0.066
0.022
0.028
0.910
0.930
0.840
0.860
0.445
0.460
0.050
BSC
0.100
TYP
0.115
0.135
0.009 TYP
36 1
ALL DIMENSIONS ARE IN INCHES
ALL DIMENSIONS ARE IN INCHES
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 9 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
MICROSEMI CORPORATION:
SRAM:
ORGANIZATION, 512Kx8:
TECHNOLOGY:
CA = CMOS Standard Power
LPA = Low Power
ACCESS TIME (ns):
PACKAGE TYPE:
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)
K = 36 lead Ceramic LCC (Package 502)
N = 32 lead Ceramic SOJ (Package 140)
T = 32 lead Sidebrazed DIP, 400 mil (Package 326)
B32 = 32 pin Ceramic Thinpack™ Flatpack (Package 321)
F32 = 32 pin Ceramic Flatpack (Package 344)
F36 = 36 pin Ceramic Flatpack (Package 316)
N36 = 36 lead Ceramic SOJ (Package 327)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M = Military Screened -55°C ≤ TA ≤ +125°C
I = Industrial -40°C ≤ TA ≤ +85°C
C = Commercial 0°C ≤ TA ≤ +70°C
EDI 8 8 512 CA X X X
EDI88512CA
February 2012 © 2012 Microsemi Corporation. All rights reserved. 10 Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Rev. 14
Microsemi Corporation reserves the right to change products or specifi cations without notice.
Document Title
512Kx8 Monolithic SRAM, SMD 5962-95600
Revision History
Rev # History Release Date Status
Rev 13 Changes (Pg. 1-10)
13.1 Change document layout from White Electronic Designs to Microsemi
13.2 Add document Revision History page
February 2011 Final
Rev 14 Change2 (Pg. 2)
14.1 Change units on Input/Output Leakage to 10μA verses 10A
August 2012 Final
