© Semiconductor Components Industries, LLC, 2007
November, 2007 - Rev. 3
1Publication Order Number:
NCP1351/D
NCP1351
Variable Off Time PWM
Controller
The NCP1351 is a current-mode controller targeting low power
off-line flyback Switched Mode Power Supplies (SMPS) where cost
is of utmost importance. Based on a fixed peak current technique
(quasi-fixed TON), the controller decreases its switching frequency as
the load becomes lighter. As a result, a power supply using the
NCP1351 naturally offers excellent no-load power consumption,
while optimizing the efficiency in other loading conditions. When the
frequency decreases, the peak current is gradually reduced down to
approximately 30% of the maximum peak current to prevent
transformer mechanical resonance. The risk of acoustic noise is thus
greatly diminished while keeping good standby power performance.
An externally adjustable timer permanently monitors the feedback
activity and protects the supply in presence of a short-circuit or an
overload. Once the timer elapses, NCP1351 stops switching and stays
latched for version A, and tries to restart for version B.
Versions C and D include a dual overcurrent protection trip point,
allowing the implementation of the controller in peak-power
requirements applications such as printers and so on. When the fault is
acknowledged, C version latches-off whereas D version
auto-recovers.
The internal structure features an optimized arrangement which
allows one of the lowest available startup current, a fundamental
parameter when designing low standby power supplies.
The negative current sensing technique minimizes the impact of the
switching noise on the controller operation and offers the user to select
the maximum peak voltage across his current sense resistor. Its power
dissipation can thus be application optimized.
Finally, the bulk input ripple ensures a natural frequency smearing
which smooths the EMI signature.
Features
•Quasi-fixed TON, Variable TOFF Current Mode Control
•Extremely Low Current Consumption at Startup
•Peak Current Compression Reduces Transformer Noise
•Primary or Secondary Side Regulation
•Dedicated Latch Input for OTP, OVP
•Programmable Current Sense Resistor Peak Voltage
•Natural Frequency Dithering for Improved EMI Signature
•Easy External Over Power Protection (OPP)
•Undervoltage Lockout
•Very Low Standby Power via Off-time Expansion
•SOIC-8 Package
•Standard Overcurrent Protection, Latched or
Auto-Recovery, A & B Versions
•Dual Trip Point Overcurrent Protection, Latched or
Auto-Recovery, C & D Versions
•These are Pb-Free Devices
Typical Applications
•Auxiliary Power Supply
•Printer, Game Stations, Low-Cost Adapters
•Off-line Battery Charger
SOIC-8
D SUFFIX
CASE 751
1
8
MARKING DIAGRAMS
PIN CONNECTIONS
1
FB 8TIMER
2
Ct
3
CS
4
GND
7LATCH
6VCC
5DRV
(Top View)
1351x
ALYW
G
1
8
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1
8
PDIP-8
P SUFFIX
CASE 626
NCP1351x
AWL
YYWWG
1
x = A, B, C, or D Options
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
ORDERING INFORMATION
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Figure 1. Typical Application Circuit
1 8
2
3
4
7
6
5
85-265VAC
+
+
*OPP
NCP1351
+
LATCH
GND
VOUT
*Optional
PIN FUNCTION DESCRIPTION
Pin N°Pin Name Function Pin Description
1 FB Feedback Input Injecting Current in this Pin Reduces Frequency
2 Ct Oscillator Frequency A capacitor sets the maximum switching frequency at no feedback current
3 CS Current Sense Input Senses the Primary Current
4 GND – –
5 DRV Driver Output Driving Pulses to the Power MOSFET
6 VCC Supply Input Supplies the controller up to 28 V
7 Latch Latchoff Input A positive voltage above VLATCH fully latches off the controller
8 Timer Fault Timer Capacitor Sets the time duration before fault validation
OVERCURRENT PROTECTION ON NCP1351 VERSIONS:
NCP1351 Auto-recovery Latched Dual level
A x
B x
C x x
D x x
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INTERNAL CIRCUIT ARCHITECTURE
Figure 2. A Version (Latched Short-Circuit Protection)
FB
TIMER
Ct
CS
GND
LATCH
VCC
DRV
-
+
-
+
-
+
-
+
-
+
UVLO Reset
Fault = Low
S
R
1 s
Pulse
VCC
Mngt
S
R
VDD
VDD
+
+
+
+
+
VDD
Clamp
UVLO Reset
VZENER
VCCSTOP
1 = OK
0 = not OK
VLATCH
ITIMER
20 s Filter
20 s Filter
IP Flag
ICt
Q
Q
Q
Q
4V Reset
45k
VOFFset
VDD
ICS-dif*
ICS-dif*
ICS-min*
Vth *(ICS-diff = ICS-max -ICS-min)
VTIMER
VFault
VDD
40 
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FB
TIMER
Ct
CS
GND
LATCH
VCC
DRV
-
+
-
+
-
+
-
+
-
+
UVLO Reset
Fault = Low
S
R
1 s
Pulse
VCC
Mngt
S
R
VDD
VDD
+
+
+
+
+
VDD
Clamp
UVLO Reset
VZENER
VCCSTOP
1 = OK
0 = not OK
VLATCH
ITIMER
20 s Filter
IP Flag
ICt
Q
Q
Q
Q
4V Reset
45k
VOFFset
VDD
ICS-dif*
ICS-dif*
ICS-min*
Vth *(ICS-diff = ICS-max -ICS-min)
Figure 3. B Version (Auto-recovery Short-Circuit Protection)
S
R
Q
Q
VITIMER
VFault
VDD
40 
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Figure 4. C Version (Latched Short-Circuit Protection)
FB
TIMER
Ct
CS
GND
LATCH
VCC
DRV
-
+
-
+
-
+
-
+
-
+
UVLO Reset
Fault = Low
S
R
1 s
Pulse
VCC
Mngt
S
R
VDD
VDD
+
+
+
+
+
VDD
Clamp
UVLO Reset
VZENER
VCCSTOP
1 = OK
0 = not OK
VLATCH
ITIMER
20 s Filter
20 s Filter
IP Flag
ICt
Q
Q
Q
Q
4V Reset
45k
VOFFset
VDD
ICS-dif*
ICS-dif*
ICS-min*
Vth *(ICS-diff = ICS-max -ICS-min)
VTIMER
VFault
VDD
D
CLK
Q
40 
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-
+
+
FB
TIMER
Ct
CS
GND
LATCH
VCC
DRV
-
+
-
+
-
+
-
+
UVLO Reset
Fault = Low
S
R
1 s
Pulse
VCC
Mngt
S
R
VDD
VDD
+
+
+
+
VDD
Clamp
UVLO Reset
VZENER
VCCSTOP
1 = OK
0 = not OK
VLATCH
ITIMER
20 s Filter
IP Flag
ICt
Q
Q
Q
Q
4V Reset
45k
VOFFset
VDD
ICS-dif*
ICS-dif*
ICS-min*
Vth *(ICS-diff = ICS-max -ICS-min)
Figure 5. D Version (Auto-recovery Short-Circuit Protection)
S
R
Q
Q
VITIMER
VFault
VDD
D
CLK
Q
40 
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MAXIMUM RATINGS
Symbol Rating Value Unit
VSUPPLY Maximum Supply on VCC Pin 6 -0.3 to 28 V
ISUPPLY Maximum Current in VCC Pin 6 20 mA
VDRV Maximum Voltage on DRV Pin 5 -0.3 to 20 V
IDRV Maximum Current in DRV Pin 5 $400 mA
VMAX Supply Voltage on all pins, except Pin 6 (VCC), Pin 5 (DRV) -0.3 to 10 V
IMAX Maximum Current in all Pins Except Pin 6 (VCC) and Pin 5 (DRV) $10 mA
IFBmax Maximum Injected Current in Pin 1 (FB) 0.5 mA
RGmin Minimum Resistive Load on DRV Pin 33 k
RJA Thermal Resistance Junction-to-Air PDIP-8
SOIC-8
142
176
°C/W
TJMAX Maximum Junction Temperature 150 °C
Storage Temperature Range -60 to +150 °C
ESD Capability, Human Body Model V per Mil-STD-883, Method 3015 2 kV
ESD Capability, Machine Model 200 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
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Electrical Characteristics (For typical values TJ = 25°C, for Min/Max Values TJ = -25°C to +125°C, Max TJ = 150°C, VCC = 12 V
unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCCON VCC Increasing Level at Which Driving Pulses are Authorized 6 15 18 22 V
VCCSTOP VCC Decreasing Level at Which Driving Pulses are Stopped 6 8.3 8.9 9.5 V
VCCHYST Hysteresis VCCON - VCCSTOP 6 6 - - V
VZENER Clamped VCC When Latched Off 6 - 6 - V
ICC1 Startup Current 6 - - 10 A
ICC2 Internal IC Consumption with IFB = 50 A, FSW = 65 kHz and CL = 0 6 - 1.0 1.8 mA
ICC3 Internal IC Consumption with IFB = 50 A, FSW = 65 kHz and CL = 1 nF 6 - 1.6 2.5 mA
ICC4 Internal IC Consumption in Auto-Recovery Latch-off Phase 6 - 600 - A
ICCLATCH Current Flowing into VCC pin that Keeps the Controller Latched 6 20 - - A
CURRENT SENSE
ICSmin Minimum Source Current (IFB = 90 A) TJ = 0°C to +125°C3 61 70 75 A
ICSmin Minimum Source Current (IFB = 90 A) TJ = -25°C to +125°C3 58 70 75 A
ICSmax Maximum Source Current (IFB = 50 A) TJ = 0°C to +125°C3 251 270 289 A
ICSmax Maximum Source Current (IFB = 50 A) TJ = -25°C to +125°C3 242 270 289 A
VTH Current Sense Comparator Threshold Voltage 3 10 20 35 mV
tdelay Propagation Time Delay (CS Falling Edge to Gate Output) 3 - 160 300 ns
TIMING CAPACITOR
VOFFSET Minimum Voltage on CT Capacitor, IFB = 30 A2 475 510 565 mV
VCTMAX Voltage on CT Capacitor at IFB = 150 A2 5 - - V
ICT Source Current (Ct Pin Grounded) TJ = 25°C
TJ = -25°C to +125°C
2 9.8
9.3
10.8
10.8
11.8
11.9
A
VCTMIN Minimum Voltage on CT
, Discharge Switch Activated 2 - - 20 mV
TDISCH CT Capacitor Discharge Time (Activated at DRV Turn-on) 2 1 s
VFAULT CT Capacitor Level at Which Fault Timer Starts A and B Versions
C and D Version
2 0.4
-
0.5
0.96
0.6
-
V
KFAULT Factor Linking VOFFSET and VFAULT (Note 1) C and D Version - 1.67 1.86 2.05
FEEDBACK SECTION
VFB FB Pin Voltage for an Injected Current of 200 A1 - 0.7 - V
IFAULT FB Current Under Which a Fault is Detected A and B Versions
C and D Versions
1 -
-
40
51
-
-
A
IFBcomp FB Current at Which CS Compression Starts 1 - 60 - A
IFBred FB Current at Which CS Compression is Finished 1 - 80 - A
DRIVE OUTPUT
TrOutput Voltage Rise-time @ CL = 1 nF, 10 - 90% of Output Signal 5 - 90 - ns
TfOutput Voltage Fall-time @ CL = 1 nF, 10 - 90% of Output Signal 5 - 100 - ns
ROH Source Resistance 5 - 80 -
ROL Sink Resistance 5 - 30 -
VDRVlow DRV Pin Level at VCC Close to VCCSTOP with a 33 k Resistor to GND 5 8.0 - - V
VDRVhigh DRV Pin Level at VCC = 28 V with 33 k Resistor to GND 5 15 17 20 V
Protection
ITIMER Timing Capacitor Charging Current 8 10 11.5 13 A
VTIMER Fault Voltage on Pin 8 8 4.5 5 5.5 V
TTIMER Fault Timer Duration, CTIMER = 100 nF - - 42 - ms
VLATCH Latching Voltage 7 4.5 5 5.5 V
1. Guaranteed by design.
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The NCP1351 implements a fixed peak current mode
technique whose regulation scheme implements a variable
switching frequency. As shown on the typical application
diagram, the controller is designed to operate with a
minimum number of external components. It incorporates
the following features:
•Frequency Foldback: Since the switching period
increases when power demand decreases, the switching
frequency naturally diminishes in light load conditions.
This helps to minimize switching losses and offers
good standby power performance.
•Very Low Startup Current: The patented internal
supply block is specially designed to offer a very low
current consumption during startup. It allows the use of
a very high value external startup resistor, greatly
reducing dissipation, improving efficiency and
minimizing standby power consumption.
•Natural Frequency Dithering: The quasi-fixed tON
mode of operation improves the EMI signature since
the switching frequency varies with the natural bulk
ripple voltage.
•Peak Current Compression: As the load becomes
lighter, the frequency decreases and can enter the
audible range. To avoid exciting transformer
mechanical resonances, hence generating acoustic
noise, the NCP1351 includes a patented technique,
which reduces the peak current as power goes down. As
such, inexpensive transformer can be used without
having noise problems.
•Negative Primary Current Sensing: By sensing the
total current, this technique does not modify the
MOSFET driving voltage (VGS) while switching.
Furthermore, the programming resistor, together with
the pin capacitance, forms a residual noise filter which
blanks spurious spikes.
•Programmable Primary Current Sense: It offers a
second peak current adjustment variable, which
improves the design flexibility.
•Extended VCC Range: By accepting VCC levels up to
28 V, the device offers added flexibility in presence of
loosely coupled transformers. The gate drive is safely
clamped below 20 V to avoid stressing the driven
MOSFET.
•Easy OPP: Connecting a resistor from the CS pin to
the auxiliary winding allows easy bulk voltage
compensation.
•Secondary or Primary Regulation: The feedback
loop arrangement allows simple secondary or primary
side regulation without significant additional external
components.
•Latch Input: If voltage on Pin 7 is externally brought
above 5 V, the controller permanently latches off and
stays latched until the user cycles VCC down, below 4
V typically.
•Fault Timer: In presence of badly coupled transformer,
it can be quite difficult to detect an overload or a
short-circuit on the primary side. When the feedback
current disappears, a current source charges a capacitor
connected to Pin 8. When the voltage on this pin
reaches a certain level, all pulses are shut off and the
VCC voltage is pulled down below the VCC(min) level.
This protection is latched on the A version (the
controller must be shut down and restart to resume
normal operation), and auto-recovery on Version B (if
the fault goes away, the controller automatically
resumes operation).
•Dual Trip Point: in some applications, such as printer
power supplies, it is necessary to let the power supply
deliver more power on a transient event. If the event
lasts longer than what the fault timer authorizes, then
the NCP1351 either latches-off (C Version) or enters an
auto-recovery mode (D Version). The level at which
the timer starts is internally set to 55% of the maximum
power capability.
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APPLICATION INFORMATION
The Negative Sensing Technique
Standard current-mode controllers use the positive
sensing technique as portrayed by Figure 6. In this
technique, the controller detects a positive voltage drop
across the sense resistor, representative of the flowing
current. Unfortunately, this solution suffers from the
following drawbacks:
1. Difficulties to precisely adjust the peak current. If
1 V is the maximum sense level, you must
combine low valued resistors to reach the exact
limit you need.
2. The voltage developed across the sense resistor
subtracts from the gate voltage. If your VCC(min)
is 7 V, then the actual gate voltage at the end of the
on time, assuming a full load condition, is 7 V –
1 V = 6 V.
3. The current in the sense resistor also includes the
Ciss current at turn-on. This narrow spike often
disturbs the controller and requires adequate
treatment through a LEB circuitry for instance.
Figure 7 represents the negative current sense technique.
In this simplified example, the source directly connects to
the controller ground. Hence, if VCC is 8 V, the effective
gate-source voltage is very close to 8 V: no sense resistor
drop. How does the controller detect a negative excursion?
In lack of primary current, the voltage on the CS pin reaches
Roffset x ICS. Let us assume that these elements lead to have
1 V on this pin. Now, when the power MOSFET activates,
the current flows via the sense resistor and develop a
negative voltage by respect to the controller ground. The
voltage seen on the CS is nothing else than a positive voltage
(Roffset x ICS) plus the voltage across the sense resistor which
is negative. Thus, the CS pin voltage goes low as the primary
current increases. When the result reaches the threshold
voltage (around 20 mV), the comparator toggles and resets
the main latch. Figure 3 details how the voltage moves on the
CS pin on a 1351 demoboard, whereas Figure 9 zooms on
the sense resistor voltage captured by respect to the
controller ground.
The choice of these two elements is simple. Suppose you
want to develop 1 V across the sense resistor. You would
select the offset resistor via the following formula:
Roffset +1
ICS +1
270+3.7k(eq. 1)
If you need a peak current of 2 A, then, simply apply the
ohm law to obtain the sense resistor value:
Rsense +1
Ipeak_max +1
2+0.5(eq. 2)
Due to the circuit flexibility, suppose you only have access
to a 0.33 resistor. In that case, the peak current will exceed
the 2 A limit. Why not changing the offset resistor value
then? To obtain 2 A from the 0.33 resistor, you should
develop:
The offset resistor is thus derived by:
Vsense +RsenseIpeak_max +0.33 2+660mV
(eq. 3)
Roffset +0.66
ICS +0.66
270+2.44k(eq. 4)
If reducing the sense resistor is of good practice to
improve the efficiency, we recommend to adopt sense values
between 0.5 V and 1 V. Reducing the voltage below these
levels will degrade the noise immunity.
Figure 6. Positive Current-Sense Technique
CBulk
+
+
-
ILp
ILp
ILp
Reset
Peak
Setpoint
Vgs ILp
Vsense
LP
DRV
CS
Rsense
GND
Figure 7. A Simplified Circuit of the Negative Sense
Implementation
CBulk
+
+
-
ILp
ILp
Reset
Vsense
Vth
ILp
VDD
LP
DRV
CS
Roffset
GND
Voffset +
ICS
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Figure 8. The Voltage on the Current Sense Pin Figure 9. The Voltage Across the Sense
Resistor
Current Sense Pin
Current Sense Resistor
Below are a few recommendations concerning the wiring
and the PCB layout:
•A small 22 pF capacitor can be placed between the CS
pin and the controller ground. Place it as close as
possible to the controller.
•Do not place the offset resistor in the vicinity of the
sense element, but put it close to the controller as well.
•Regulation by frequency
•The power a flyback converter can deliver relates to the
energy stored in the primary inductance Lp and obeys
the following formulae:
Pout_DCM +1
2L
PIpeak2FSW(eq. 5)
Pout_CCM +12LP(Ipeak2*Ivalley2)FSW(eq. 6)
Where:
(eta) is the converter efficiency
Ipeak is the peak inductor current reached at the on time
termination
Ivalley represents the current at the end of the off time. It
equals zero in DCM.
FSW is the operating frequency.
Thus, to control the delivered power, we can either play on
the peak current setpoint (classical peak current mode
control) or adjust the switching frequency by keeping the
peak current constant. We have chosen the second scheme
in this NCP1351 for simplicity and ease of implementation.
Thus, once the peak current has been selected, the feedback
loop automatically reacts to satisfy Equations 5 and 6. The
external capacitor that you connect between pin 2 and
ground (again, place it close to the controller pins) sets the
maximum frequency you authorize the converter to operate
up to. Normalized values for this timing capacitor are
270 pF (65 kHz) and 180 pF (100 kHz). Of course, different
combinations can be tried to design at higher or lower
frequencies. Please note that changing the capacitor value
does not affect the operating frequency at nominal line and
load conditions. Again, the operating frequency is selected
by the feedback loop to cope with Equations 5 and 6
definitions.
The feedback current controls the frequency by changing
the timing capacitor end of charge voltage, as illustrated by
Figure 10.
The timing capacitor ending voltage can be precisely
computed using the following formula:
VCt+45k(IFB *40u) )500m (eq. 7)
Where IFB represents the injected current inside the FB
pin (pin 1). The 40u term corresponds to a 40  offset
current purposely placed to force a minimum current
injection when the loop is closed. This allows the controller
to detect a short-circuit condition as the feedback current
drops to zero in that condition.
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Figure 10. The Current Injected into the Feedback Loop Adjusts the Switching Frequency
ICt = 10 A
Controlled by the
FB Current
VCt
Maximum Frequency
Minimum Frequency
Pout
Decreases
Pout
Increases
Figure 11. In Light Load Conditions, the
Oscillator Further Delays the Restart Time
Figure 12. Ct Voltage Swing at a Moderate
Loading
Ct Voltage
Ct Voltage
In light load conditions, the frequency can go down to a
few hundred Hz without any problem. The internal circuitry
naturally blocks the oscillator and softly shifts the restart
time as shown on Figure 11 scope shot.
Delays The Restart Time
In lack of feedback current, for instance during a startup
sequence or a short circuit, the oscillator frequency is pushed
to the limit set by the timing capacitor. In this case, the lower
threshold imposed to the timing capacitor is blocked to
500 mV (parameter Vfault). This is the maximum power the
converter can deliver. To the opposite, as you inject current
via the optocoupler in the feedback pin, the off time expands
and the power delivery reduces. The maximum threshold
level in standby conditions is set to 6 V.
Over Power Protection
As any universal-mains operated converters, the output
power slightly increases at high line compared to what the
power supply can deliver at low line. This discrepancy
relates to the propagation delay from the point where the
peak is detected to the MOSFET gate effective pulldown. It
naturally includes the controller reaction time, but also the
driver capability to pull the gate down. If the MOSFET Qg
is too large, then this parameter will greatly affect your
overpower parameter. Sometimes, the small PNP can help
and we recommend it if you use a large Qg MOSFET:
Figure 13. A Low-Cost PNP Improves the Drive
Capability at Turn-off
D1
1N4148
Q1
2N2907
DRV
GND
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Over power protection can be done without power
dissipation penalty by arranging components around the
auxiliary as suggested by Figure 14. On this schematic, the
diode anode swings negative during the on time. This
negative level directly depends on the input voltage and
offsets the current sense pin via the ROPP resistor. A small
integration is necessary to reduce the OPP action in light load
conditions. However, depending on the compensation level,
the standby power can be affected. Again, the resistor ROPP
should be placed as close as possible to the CS pin. The
22 pF can help to circumvent any picked-up noise and D2
prevents the positive loading of the 270 pF capacitor during
the flyback swing. We have put a typical 100 k O
PP
resistor but a tweak is required depending on your
application.
Figure 14. The OPP is Relatively Easy to Implement and It Does not Waste Power
CBulk
+
C3
270p
R1
150k
Rsense
DRV
ILp
VCC
LP
DRV
CS
Roffset D2
1N4148
C4
22p +
ROPP
100k
CVCC Laux
Daux
Suppose you would need to reduce the peak current by
15% in high-line conditions. The turn-ratio between the
auxiliary winding and the primary winding is Naux. Assume
its value is 0.15. Thus, the voltage on Daux cathode swings
negative during the on time to a level of:
Vaux_peak +-Vin_maxNaux +-375 0.15 +-56V
(eq. 8)
If we selected a 3.7 k resistor for Roffset, then the
maximum sense voltage being developed is:
Vsense +3.7k 270+1V (eq. 9)
The small RC network made of R1 and C3, purposely limits
the voltage excursion on D2 anode. Assume the primary
inductance value gives an on time of 3 s at high-line. The
voltage across C3 thus swings down to:
VC3+tonVaux_peak
R1C3+-3 56
150k 270p +-4.2V (eq.
10)
Typically, we measured around –4 V on our 50 W prototype.
By calculation, we want to decrease the peak current by
15%. Compared to the internal 270 A source, we need to
derive:
Ioffset +-0.15 270+-40.5A(eq. 11)
Thus, from the –4 V excursion, the ROPP resistor is
derived by:
ROPP +4
40.5+98k(eq. 12)
After experimental measurements, the resistor was
normalized down to 100 k.
Feedback
Unlike other controllers, the feedback in the NCP1351
works in current rather than voltage. Figure 15 details the
internal circuitry of this particular section. The optocoupler
injects a current into the FB pin in relationship with the
input/output conditions.
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Figure 15. The Feedback Section Inside the NCP1351
C1
100n
+
-
Reset
VCC
RFB
45k
VCC
DFB
Voffset
500mV
+
IFB
IFB
IFB
FB
ICt
10
Ct
R1
2.5k
Ct
270p
Clock
Idiff
CS
Roffset
3.9k
Idiff = ICSmax - ICSmin
f(IFB)
Idiff
ICSmin
VCC
C3
22pF
to Rsense
The FB pin can actually be seen as a diode, forward biased
by the optocoupler current. The feedback current, IFB on
Figure 15, enter an internal 45 k resistor which develops
a voltage. This voltage becomes the variable threshold point
for the capacitor charge, as indicated by Figure 10. Thus, in
lack of feedback current (start-up or short-circuit), there is
no voltage across the 45 k and the series offset of 500 mV
clamps the capacitor swing. If a 270 pF capacitor is used, the
maximum switching frequency is 65 kHz.
Folding the frequency back at a rather high peak current
can obviously generate audible noise. For this reason, the
NCP1351 uses a patented current compression technique
which reduces the peak current in lighter load conditions. By
design, the peak current changes from 100% of its full load
value, to 30% of this value in light load conditions. This is
the block placed on the lower left corner of Figure 15. In full
load conditions, the feedback current is weak and all the
current flowing through the external offset resistor is:
ICS +ICS_min )Idif +ICS_max *ICS_min )ICS_min
(eq. 13)
+ICS
_
max
As the load goes lighter, the feedback current increases and
starts to steal current away from the generators. Equation 12
can thus be updated by:
ICS +ICS_max *kIFB (eq. 14)
Equation 13 testifies for the current reduction on the offset
generator, k represents an internal coefficient. When the
feedback current equals Idif, the offset becomes:
ICS +ICS_min (eq. 15)
NCP1351
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15
At this point, the current is fully compressed and remains
frozen. To further decrease the transmitted power, the
frequency does not have other choice than going down.
Figure 16. The NCP1351 Peak Current Compression
Scheme
60 A80 A
270 A
70 A
40 A
FAULT
(A, B versions)
FB Current
CS Current
Looking to the data-sheet specifications, the maximum
peak current is set to 270 A whereas the compressed
current goes down to 70 A. The NCP1351 can thus be
considered as a multi operating mode circuit:
•Real fixed peak current / variable frequency mode for
FB current below 60 A.
•Then maximum peak current decreases to ICS,min over a
narrow linear range of IFB (to avoid instability created
by a discrete jump from ICS,max to ICS,min), between
60 A and 80 A.
•Then if IFB keeps on increasing, in a real fixed peak
current/variable frequency mode with reduced peak
current
For biasing purposes and noise immunity improvements,
we recommend to wire a pulldown resistor and a capacitor
in parallel from the FB pin to the controller ground
(Figure 17). Please keep these elements as close as possible
to the circuit. The pulldown resistor increases the
optocoupler current but also plays a role in standby. We
found that a 2.5 k resistor was giving a good tradeoff
between optocoupler operating current (internal pole
position) and standby power.
Figure 17. The Recommended Feedback
Arrangement Around the FB Pin
C1
100nF
VCC
FB
R1
2.5k
Fault detection
The fault detection circuitry permanently observes the FB
current, as shown on Figure 19. When the feedback current
decreases below 40 A, an external capacitor is charged by
a 11.7 A source. As the voltage rises, a comparator detects
when it reaches 5 V typical. Upon detection, there can be
two different scenarios:
1. A version: the circuit immediately latches-off and
remains latched until the voltage on the current
into the VCC pin drops below a few A. The latch
is made via an internal SCR circuit who holds
VCC to around 6 V when fired. As long as the
current flowing through this latch is above a few
A, the circuit remains locked-out. When the user
unplugs the converter, the VCC current falls down
and resets the latch.
2. B version: the circuit stops its output pulses and
the auxiliary VCC decreases via the controller own
consumption (≈600 A). When it touches the
VCC(min) point, the circuit re-starts and attempts to
crank the power supply. If it fails again, an hiccup
mode takes place (Figure 18).
3. C version: this version includes the dual Over
Current Protection (OCP) level. When the
switching frequency imposed by the feedback loop
reaches around 50% of the maximum value set by
the Ct capacitor, the timer starts to count down. If
the fault disappears, the timer is reset. When the
fault is finally confirmed, the controller latches off
as the A version.
4. D version: this version includes the dual Over
Current Protection (OCP) level. When the
switching frequency imposed by the feedback loop
reaches around 50% of the maximum value set by
the Ct capacitor, the timer starts to count down. If
the fault disappears, the timer is reset. When the
fault is finally confirmed, the controller enters
auto-recovery mode, as with the B version.
Figure 18. Hiccup Occurs with the B Version Only,
the A Version Being Latched
VCC
Vdrv
The duty-burst in fault is around 7% in this particular
case.
NCP1351
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16
Figure 19. The Internal Fault Management Differs Depending on the Considered Version
-
+
-
+
C1
100n
VCC
IFB
Ctimer
100nF
VCC
R1
2.5k
+
+
+
Vtimer
5
Itimer
10
20s
Filter
Pon
Reset
DFB
IFB
IFB
Timer Laux
CVCC
ICC
VCC Daux
IFB < 40 A ? = Low
Else = High
DRV Pulses
VCC ==
VCC(min)
? Reset
Q
Q
S
to DRV
Stage
Auto-Recovery - B Version
-
+
-
+
C1
100n
VCC
IFB
Ctimer
100nF
VCC
R1
2.5k
+
+
+
Vtimer
5
Itimer
1020s
Filter
Pon
Reset
DFB
IFB
IFB
Timer Laux
CVCC
ICC
VCC Daux
IFB < 40 A ? = Low
Else = High
SCR Delatches When
ISCR < ICClatch (Few A)
Latched - A Version
6V
FB
FB
R
Knowing both the ending voltage and the charge current,
we can easily calculate the timer capacitor value for a given
delay. Suppose we need 40 ms. In that case, the capacitor is
simply:
Ctimer +ItimerT
Vtimer +11.7 40m
5+94nF (eq. 16)
Select a 100 nF value.
To let the designer understand the behavior behind the
four different options (A, B, C and D), we have graphed
important signals during a fault condition. In versions A and
B, an internal error flag is raised as soon the controller hits
the maximum operating frequency. At this moment, the
external timer capacitor charge begins. If the fault persists,
the timer capacitor hits the fault level and the circuit is either
latched (A) or enters auto-recovery burst mode (B). If the
fault disappears, the timer capacitor is simply reset to 0 V by
an internal switch.
On version C and D, the error flag is asserted as soon as
the current feedback imposes a switching frequency roughly
equal to half of the maximum limit. For instance, should the
designer select a 100 kHz maximum switching frequency,
then the error flag would raise and start the timer for an
operating frequency above ≈ 50 kHz. Below 50 kHz, the
timer pin remains grounded. If we consider a DCM
operation at full load, as the inductor peak current is kept
constant, these 50 kHz correspond to 50% of the maximum
delivered power. If the load stays between 50% and 100% of
its nominal value, the timer continues to charge until it
reaches the final level. In that case, the circuit latches off (C)
or enters auto-recovery (D). This behavior is particularly
well suited for applications where the converter delivers a
moderate average power but is subjected to sudden peak
loading conditions. For instance, a power supply is designed
to permanently deliver 20 W but is sized to deliver 80 W in
peak conditions. During these 80 W power excursions, the
timer will react but will not shut down the power supply. On
the contrary, if a short-circuit appends or if the transient
overload lasts too long, the timer will immediately start to
further shutdown the controller in order to protect both the
application and downstream load.
NCP1351
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17
Depending on the design conditions (DCM or CCM), the
error flag assertion will correspond to either 50% of the
maximum power (full load DCM design) or a value above
this number if the converter operates in CCM at full load and
remains in CCM at half the switching frequency.
The figures below details circuits operation for the various
controller options.
VccON
Vccstop
Vcc
IFB
Vtimer
40 μA
fault
Vtimer
DRV
Vzener
FB reacts ok
startup
User
reset
ICC < 20 μA
ok
ICC1
ICC1
Pulldown
SCR action
Latched
state
fault
FB reacts ok
startup
A version, latched
User
reset
ICC < 20 μA
ok
ICC1
ICC1
Pulldown
SCR action
Latched
state
Figure 20. The A Version Latches-off in Presence of a Fault
VccON
Vccstop
Vcc
IFB
Vtimer
40 μA
fault
Vtimer
DRV
Vzener
FB reacts ok
startup
Auto-recovery
Pulses
stopped
Fault
still present
ICC4 ICC1
ICC1
VccON
Vccstop
Vcc
IFB
Vtimer
40 μA
fault
Vtimer
DRV
Vzener
FB reacts ok
startup
B version, auto-recovery
Auto-recovery
Pulses
stopped
Fault
still present
ICC4 ICC1
ICC1
Figure 21. The B Version Enters an Auto-Recovery Burst Mode in Presence of a Fault
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VccON
Vccstop
Vcc
Pout
Vtimer
overload
Vtimer
DRV
Vzener
startup
51 μA
IFB
100% Pout
50% Pout
overload
Pout>50% Pout>50%
User
reset
ICC < 20 μA
Latched
state
ICC1
Pulldown
SCR action
VccON
Vccstop
Vcc
Pout
Vtimer
overload
Vtimer
DRV
Vzener
startup
C version, latched dual OCP level
μA
IFB
100% Pout
50% Pout
overload
Pout>50% Pout>50%
User
reset
ICC < 20 μA
Latched
state
ICC1
Pulldown
SCR action
Figure 22. The C Version Latches if the Power Excursion Exceeds 50% of the Maximum Power Too Long
(DCM Full Load Operation)
VccON
Vccstop
Vcc
Pout
Vtimer
overload
Vtimer
DRV
Vzener
startup
D version, auto-recovery dual OCP level
51 μA
IFB
100% Pout
50% Pout
overload
Pout>50% Pout>50%
Pulses
stopped
ICC1
ICC4
VccON
Vccstop
Vcc
Pout
Vtimer
overload
Vtimer
DRV
Vzener
startup
μA
IFB
100% Pout
50% Pout
overload
Pout>50% Pout>50%
Pulses
stopped
ICC1
ICC4
Figure 23. The D Version Enters Auto-Recovery Burst Mode if the Power Excursion Exceeds 50% of the
Maximum Power (DCM Full Load Operation)
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Latch Input
The NCP1351 features a patented circuitry which
prevents the FB input to be of low impedance before the VCC
reaches the VCCON level. As such, the circuit can work in
a primary regulation scheme. Capitalizing on this typical
option, Figure 24 shows how to insert a zener diode in series
with the optocoupler emitter pin. In that way, the current
biases the zener diode and offers a nice reference voltage,
appearing at the loop closure (e.g. when the output reaches
the target). Yes, you can use this reference voltage to supply
a NTC and form a cheap OTP protection.
Figure 24. The Latch Input Offers Everything Needed
to Implement an OTP Circuit. Another Zener Can
Help combining an OVP Circuit if Necessary
C2
100n
VCC
R1
2.5k C1
100nF
LatchFB
C3
100nF
5V
OVP
D2
Rpulldown
Figure 25. You can either directly observe the VCC level or add a small RC filter to reduce the leakage inductance
contribution. The best is to directly sense the output voltage and reacts if it runs away, as offered on the right
side.
C4
100n
R4
2.2k
C5
1n
VCC
Latch
C3
100nF
Laux
ROVP
D2
1N4937
Rpulldown
CVCC
20F
VCC
Latch
C3
100nF
C1
100nF
Aux
Sec
U1A
D4
OUT
CVCC
22F
U1B
++
Design Example, a 19 V / 3 A
A Universal Mains Power Supply Designing a
Switch-Mode Power Supply using the NCP1351 does not
differ from a fixed frequency design. What changes,
however, is the regulation method via frequency variations.
In other words, all the calculations must be carried at the
lowest line input where the frequency will hit the maximum
value set by the Ct capacitor. Let us follow the steps:
Vin min = 100 Vdc (bulk valley in low-line conditions)
Vin max = 375 Vdc
Vout = 19 V
Iout = 3 A
Operating mode is CCM
= 0.8
Fsw = 65 kHz
1. Turn Ratio. This is the first parameter to consider.
The MOSFET BVdss actually dictates the amount
of reflected voltage you need. If we consider a
600 V MOSFET and a 15% derating factor, we
must limit the maximum drain voltage to:
Vds_max +600 0.85 +510V (eq. 17)
Knowing a maximum bulk voltage of 375 V, the clamp
voltage must be set to:
Vclamp +510 *375 +135V (eq. 18)
Based on the above level, we decide to adopt a headroom
between the reflected voltage and the clamp level of 50 V. If
this headroom is too small, a high dissipation will occur on
the RDC clamp network and efficiency will suffer. A
leakage inductance of around 1% of the magnetizing value
should give good results with this choice (kc = 1.6). The turn
ratio between primary and secondary is simply:
ǒVout )VfǓ
N+Vclamp
kc
(eq. 19)
Solving for N gives:
N+Ns
Np+kCǒVout )VfǓ
Vclamp +1.6 (19 )0.8)
135 (eq. 20)
+0.234
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Let us round it to 0.25 or 1/N = 4
Figure 26. Primary Inductance Current Evolution
in CCM
DTSW
IL
TSW
Ipeak
Ivalley
Ivalley
Iavg
I1
t
2. Calculate the maximum operating duty-cycle for
this flyback converter operated in CCM:
dmax +VoutńN
VoutńN)Vin_min +19 4
19 4)100 +0.43
(eq. 21)
In this equation, the CCM duty-cycle does not exceed
50%. The design should thus be free of subharmonic
oscillations in steady-state conditions. If necessary,
negative ramp compensation is however feasible by the
auxiliary winding.
3. To obtain the primary inductance, we can use the
following equation which expresses the inductance
in relationship to a coefficient k. This coefficient
actually dictates the depth of the CCM operation.
If it goes to 2, then we are in DCM.
L+(Vin_mindmax)2
FSWKPin
(eq. 22)
where K = IL/II and defines the amount of ripple we want
in CCM (see Figure 26).
•Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
•Large K: approaching BCM where the RMS losses are
the worse, but smaller inductance, leading to a better
leakage inductance.
From Equation 17, a K factor of 0.8 (40% ripple) ensures a
good operation over universal mains. It leads to an
inductance of:
L+(100 43)2
65k 0.8 72 +493H(eq. 23)
+1.34Apeak-to-peak
(eq. 24)
IL+Vin_mindmax
LFSW +100 0.43
493u 65k
The peak current can be evaluated to be:
Iin_avg +Pout
Vin_min +19 3
0.8 100 +712mA (eq. 25)
Ipeak +Iavg
d)IL
2+0.712
0.43 )1.34
2+2.33A (eq. 26)
On Figure 26, I1 can also be calculated:
II+Ipeak *IL
2+2.33 *1.34
2+1.65A (eq. 27)
The valley current is also found to be:
Ivalley +Ipeak *IL+2.33 *1.34 +1.0A (eq. 28)
4. Based on the above numbers, we can now evaluate
the RMS current circulating in the MOSFET and
the sense resistor:
Id_rms +IId
Ǹ1)1
3ǒIL
2I1Ǔ2
Ǹ
(eq. 29)
+1.65 0.65 1)1
3ǒ1.34
2 1.65Ǔ2
Ǹ
+1.1A
5. The current peaks to 2.33 A. Selecting a 1 V drop
across the sense resistor, we can compute its value:
Rsense +1
Ipeak +1
2.5 +0.4(eq. 30)
To generate 1 V, the offset resistor will be 3.7 k, as already
explained. Using Equation 29, the power dissipated in the
sense element reaches:
Psense +RsenseId_rms2+0.4 1.12+484mW
(eq. 31)
6. To switch at 65 kHz, the Ct capacitor connected to
pin 2 will be selected to 180 pF.
7. As the load changes, the operating frequency will
automatically adjust to satisfy either equation 5
(high power, CCM) or equation 6 in lighter load
conditions (DCM).
Figure 27 portrays a possible application schematic
implementing what we discussed in the above lines.
NCP1351
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Figure 27. The 19 V Adapter Featuring the Elements Calculated Above
T1
R15
3.7k
C8
270pF
U1A
U1B
+
C15
22p
+
C2
10n
400V
R13
47k
C10
0.1
R1
2.2k
C9
100n
R5
2.5k
C4
100n
+ + +
U2
OVP
Option
D6
1N4148
R16
10
R6
0.4
C3
4.7
25V
C1
100nF
R7
1M
R3
47k
D3
1N4937
D2
MUR
160
R4
22
R2
1M
+C12
100F
400V
HV-Bulk
NCP1351B
1
2
3
4
8
7
6
5
25V
R18
47k C17
100
6A/600V
M1
LP = 500H
NP:NS = 1:0.25
NP:Naux = 0.18
D5
MBR20200 L2
2.2
VOUT 19V/3A
C5b
1.2mF
25V
C5a
1.2mF
25V
C13
2.2nF
Type = Y1
C7
220F
25V
GND
R14
2.2k
R8
1k
R12
4k
R10
62k
R9
10k
GND
C6
100n
IC2
TL431
On this circuit, the VCC capacitor is split in two parts, a
low value capacitor (4.7 F) and a bigger one (100 F). The
4.7 F capacitor ensures a low startup time, whereas the
second capacitor keeps the VCC alive in standby mode
(where the switching frequency can be low). Due to D6, it
does not hamper startup time.
Application Results
We assembled a board with component values close to
what is described on Figure 27. Here are the obtained
results:
Pin @ no-load = 152 mW, Vin = 230 Vac
Pin @ no-load = 164 mW, Vin = 100 Vac
The efficiency stays flat to above 80%, and keeps good
even at low output levels. It clearly shows the benefit of the
variable frequency implemented in the NCP1351. Figure 28. Efficiency Measured at Various Operating
Points
72
74
76
78
80
82
84
86
88
0 0.5 1 1.5 2 2.5 3 3.5
EFFICIENCY (%)
Iout (A)
Vin = 230 Vac
Vin = 100 Vac
NCP1351
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22
Another benefit of the variable frequency lies in the low
ripple operation at no-load. This is what confirms
Figure 29.
Finally, the power supply was tested for its transient
response, from 100 mA to 3 A, high and low line, with a
slew-rate of 1 A/s (Figure 31). Results appear in
Figures 31 and 32 and confirm the stability of the board.
Figure 29. No-Load Output Ripple
(Vin = 230 Vac)
Figure 30. Same Conditions,
Pout = 5 W
Vds
200 V/div
Vout
1.0 mV/div
Vds
200 V/div
Vout
1.0 mV/div
Figure 31. Transient Step, Low Line Figure 32. Transient Step, High Line
Vout
50 mV/div
Vout
50 mV/div
NCP1351
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23
CHARACTERIZATION CURVES
16
17
18
19
20
Figure 33. VCCON Level versus Junction
Temperature
TEMPERATURE (°C)
VCCON (V)
-25 0 25 50 75 100 125
8.7
8.8
8.9
9
9.1
-25 0 25 50 75 100 125
TEMPERATURE (°C)
VCCmin (V)
Figure 34. VCCmin Level versus Junction
Temperature
65
66.5
68
69.5
71
ICSmin (A)
Figure 35. ICSmin versus Junction
Temperature
-25 0 25 50 75 100 125
TEMPERATURE (°C)
254
258
262
266
270
274
TEMPERATURE (°C)
ICSmax (A)
-25 0 25 50 75 100 12
5
Figure 36. ICSmax versus Junction
Temperature
509
511
513
515
517
VOFFset (mV)
-25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 37. Oscillator Offset Voltage versus
Junction Temperature
10.2
10.4
10.6
10.8
11
ICT (A)
-25 0 25 50 75 100 12
5
TEMPERATURE (°C)
Figure 38. Timing Capacitor Charge-Current
Variation versus Junction Temperature
NCP1351
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24
522
525
528
531
534
Figure 39. Fault Voltage Variations versus
Junction Temperature (A and B Versions)
VFAULT (mV)
-25 0 25 50 75 100 125
TEMPERATURE (°C)
930
940
950
960
970
980
990
-25 0 25 50 75 100 12
5
Figure 40. Fault Voltage Variations versus
Junction Temperature (C and D Versions)
TEMPERATURE (°C)
VFAULT (mV)
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
2.05
-25 0 25 50 75 100 125
KFAULT
TEMPERATURE (°C)
Figure 41. KFAULT Variations versus Junction
Temperature
49.5
50
50.5
51
51.5
52
52.5
53
-25 0 25 50 75 100 12
TEMPERATURE (°C)
IFAULT
Figure 42. IFAULT Current Variation versus
Junction Temperature (Versions C and D)
Figure 43. Latch Level Evolution versus Junction Temperature
4.7
4.8
4.9
5
5.1
5.2
-25 0 25 50 75 100 125
VLATCH (V)
TEMPERATURE (°C)
NCP1351
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ORDERING INFORMATION
Device Package Type Shipping†
NCP1351ADR2G SOIC-8
(Pb-Free)
2500 / Tape & Reel
NCP1351BDR2G SOIC-8
(Pb-Free)
2500 / Tape & Reel
NCP1351CDR2G SOIC-8
(Pb-Free)
2500 / Tape & Reel
NCP1351DDR2G SOIC-8
(Pb-Free)
2500 / Tape & Reel
NCP1351APG PDIP-8
(Pb-Free)
50 Units / Rail
NCP1351BPG PDIP-8
(Pb-Free)
50 Units / Rail
NCP1351CPG PDIP-8
(Pb-Free)
50 Units / Rail
NCP1351DPG PDIP-8
(Pb-Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1351
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26
PACKAGE DIMENSIONS
SOIC-8
D SUFFIX
CASE 751-07
ISSUE AH
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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PACKAGE DIMENSIONS
PDIP-8
P SUFFIX
CASE 626-05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 -A-
-B-
-T-
SEATING
PLANE
H
J
G
DK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040
__
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