ADM4850–ADM4857
Rev. A | Page 4 of 16
ADM4850/ADM4854 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 115 kbps
Propagation Delay tPLH, tPHL 600 2500 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
Skew tSKEW 70 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
Rise/Fall Time tR, tF 600 2400 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
Enable Time 2000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850
Disable Time 2000 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4850
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850
RECEIVER
Propagation Delay tPLH, tPH 400 1000 ns CL = 15 pF, Figure 8
Differential Skew tSKEW 255 ns CL = 15 pF, Figure 8
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
Time to Shut Down 50 330 3000 ns ADM48501
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 500 kbps
Propagation Delay tPLH, tPHL 250 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
Skew tSKEW 40 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
Rise/Fall Time tR, tF 200 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
Enable Time 1000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851
Disable Time 1000 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4851
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851
RECEIVER
Propagation Delay tPLH, tPHL 400 1000 ns CL = 15 pF, Figure 8
Differential Skew tSKEW 250 ns CL = 15 pF, Figure 8
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4851
Disable Time 20 50 ns RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851
Enable Time from Shutdown 4000 ns RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851
Time to Shut Down 50 330 3000 ns ADM48511
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.