SP5301CN-L - Sipex Corporation - Datasheet.Directory

SP5301

Universal Serial Bus Transceiver

The SP5301 is a half-duplex Universal Serial Bus (USB) differential transceiver that interfaces

with the USB Serial Interface Engine (SIE). The SP5301 is designed to allow 3.3V or 5.0V

standard and programmable logic to interface with the physical layer of the Universal Bus. The

USB protocol can support multiple connections for up to 127 physical devices composed of

many diverse functions. It is capable of transmitting and receiving serial data at both full speed

(12Mbps) and low speed (1.5Mbps) data rates. Implementation of the Serial Interface Engine

along with the USB transceiver allow the designer to make flexible USB compatible devices

with widely available logic components. The SP5301 is specifically geared towards low-cost

USB solutions for the PC peripheral market.

■ Utilizes digital inputs and outputs to

transmit and receive USB cable data

■ Supports 12Mbps "Full Speed" and

1.5Mbps "Low Speed" serial data

transmission

■ Compatible with the VHDL "Serial

Interface Engine" from USB developer's

conference

■ Hysteresis on VP and VM Function

■ Ease of use for PC peripheral expansion

■ Protocol flexibility for mixed-mode

isochronous data transfers and

asynchronous messaging

■ Available in 14 pin 0.15" SOIC package

■ Rail to Rail receiver common mode input

range, 20mV typical receiver sensitivity

■ Low Power; 20 nA in SUSPEND mode

■ Enhanced version of the PDIUSBP11

DESCRIPTION

GND

411

RERR

RCV

SUSPND SPEED

RSEO

D-

D+

VPO

VMO

D+

D-

SUSPND

RCV VP VM

SPEED

VMO

VPO

RERR RSE0

Receiver

Logic

RE RE

NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp current ratings are observed.

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at

these ratings or any other above those indicated in the operation sections

of the specifications below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect reliability and

cause permanent damage to the device.

VCC.....................................................................-0.5V to +6.5V

IGND, ICC (DC VCC or GND current)............................+100mA

Input Current and Voltages:

IIK (DC input diode current at VI < 0)......................-50mA

VI (DC input voltage, Note 1)......................-0.5 to +6.5V

VI/O (DC input voltage range, I/O).........-0.5V toVC C 0.5V

Output Currents and Voltages:

IOK (DC output diode current where

VO > VCC or VO < 0)...........................................+50mA

VO (DC output voltage),

Note 1.........................................-0.5V to (VCC + 0.5V)

IO (DC output source or sink current for

VP/VM/RCV/RERR/RSEO pins,VO = 0 to VCC)..+15mA

IO (DC output source or sink current for

D+/D- pins, VO = 0 to VCC.................................+50mA

Storage Temperature.................................-65°C to +150 °C

Ptot (Power dissipation per package)......................1000mW

Figure 1. Block Diagram

OE SUSPND RCV RERR RSEO VP/VM D+/D- Comments

0 0 0 0 0 0 Active Driving

0 1 0 0 0 0 Active Driving

1 0 Active Active Active Active HI-Z Receiving

1 1 0 Active Active Active HI-Z Low Power State

Function Table

D+

D-

SUSPND

RCV VP VM

SPEED

VMO

VPO

RERR RSE0

Receiver

Logic

RE RE

SPECIFICATIONS

NOTE 2: All signals except D+ and D-.

NOTE 3: See "Load D+ and D-" diagram for testing details.

NOTE 4: This value includes a 22Ω external resistor.

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +3.6V with Tamb = 0°C to +70°C.

Typical values apply at VCC = +3.3V and Tamb = 25°C.

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3.10.2

SPECIFICATIONS (continued)

Unless otherwise noted, the following specifications apply for GND = 0V, VCC = 3.3V, tR = tF = 3.0ns, with Tamb = 0°C to +70°C.

Typical values apply at Tamb = 25°C.

NOTE 5: Delay defined from Midpoint of input to Midpoint of output, with other input static (High or Low).

DESCRIPTION

The SP5301 is a half-duplex Universal Serial

Bus (USB) differential transceiver that interfaces

with the VHDL Serial Interface Engine (SIE)

from the USB developer's conference. The

SP5301 is designed to allow digital logic to

communicate with the physical layer of the

Universal Bus.

The USB is a cable bus that supports data

exchange between a host computer and a wide

range of peripherals. Attached peripherals share

USB bandwidth through a host scheduled token

based protocol. The USB allows peripherals to be

attached, configured, used, and detached while

the host and other peripherals are in operation.

This is referred to as dynamic, or hot, attachment

and removal. USB attributes include lower costs,

hot plug-and-play with dynamic attach-detach

capabilities, ease of design and use, multiple

peripherals, guaranteed latency, and guaranteed

bandwidth.

The USB is specified to be an industry standard

extension to the PC architecture with a focus on

Computer Telephony Integration (CTI),

consumer, and productivity applications. The

architecture of the USB protocol can ease the

expansion of PC peripherals, provide a low-cost

solution that supports tranfer rates up to 12Mbps,

and can fully support real-time data for voice,

audio, and compressed video.

The USB protocol can provide protocol flexibility

for mixed-mode isochronous data transfers and

asynchrounous messaging. Guaranteed bandwidth

and low latencies are appropriate for many

telephony and audio applications. A 12Mbps bus

covers the mid-speed and low-speed data ranges.

Typically, mid-speed data types are isochronous

and low-speed data comes from interactive

devices. Isochronous communication can only

be used by full speed devices.

THEORY OF OPERATION

The USB protocol can support multiple

connections for up to 127 physical devices

composed of many diverse functions. This makes

the SP5301 an ideal solution for multidrop

applications. This lower protocol overhead

results in high bus utilization. An isochronous

workload may utilize the entire USB bus

bandwidth. The USB protocol reflects a robust

capability of dynamic insertion and removal of

devices identified in user perceived real-time.

This PC plug and play quality preserves the

marketable synergy with the PC industry, being

a simple protocol to implement and integrate

into existing operating systems.

The SP5301 contains a differential driver

and a differential receiver in a half-duplex

configuration. The driver is enabled by the OE

pin. If OE is asserted LOW, the driver is active

and the D- and D+ pins drive USB signals. The

differential receiver is also controlled by the OE

pin. If OE is HIGH, while SUSPEND is LOW,

the receiver is active and the driver is in tri-state.

In this receive mode, the D- and D+ pins are now

receiving USB signals.

The typical driver output voltage swing for

D- and D+ of the SP5301 will be less than +0.3V

for the LOW state and greater than +2.8V for the

HIGH state.

The SP5301 is a USB differential interface with

very high receiver input sensitivity. This makes

data virtually immune to noise on the USB

pipeline. The +90mV minimum receiver input

sensitivity of the SP5301 ensures recovery of

even severely attenuated signals.

The SP5301 incorporates a receive error circuit.

This error circuit outputs CMOS signals on the

receive error pin (RERR) and the receive single

ended zero pin (RSE0) under specific conditions

from the USB bus. When OE is asserted LOW, it

enables the USB driver to transmit data on the D+

and D- output pins. The receive error circuit is

disabled in this condition and both RERR and

RSE0 are forced low. The receive error circuit is

activated in receive mode when OE is HIGH. The

receive error circuit will signal an error state

when both D+ and D- are HIGH by forcing RERR

HIGH. The receiver error circuit will signal a single

ended zero when both D+ and D- are LOW by

forcing RSE0 HIGH. A single ended zero is a

valid state and is used to signal an end of packet

(EOP) in signal transmission. (CAUTION: Since

both RERR and RSE0 are CMOS outputs, care

must be taken to ensure that RERR and RSE0

are NOT connected to VCC or GND.)

The SP5301 has a suspend input pin (SUSPND)

which enables a low power state while the USB

bus is inactive. When SUSPND is asserted HIGH

or SP5301 is in transmit mode (OE is LOW), the

receive data pin (RCV) will be forced LOW.

The SP5301 can transmit and receive serial data

at both full speed, 12Mbps, and at low speed,

1.5Mbps, data rates. At full speed, the active

supply current of the SP5301 is 6mA. In the

suspend state, the supply current is typically

20nA.

Full speed USB applications include ISDN,

PBX, POTS, sampled analog devices, audio,

printers, and telephony designs. Low speed USB

applications include locator devices, keyboards,

mouse, tablets, light pens, stylus, game

peripherals, virtual reality peripherals, and

monitor configurations. The USB protocol

provides full support for the real-time data

for voice, audio, and compressed video. The

SP5301 is specifically geared towards low-cost

USB solutions for the PC peripheral markets

Waveforms 1 and 2 below show device behavior

in transmit mode, at both low and full speed,

with the D+/D- pins driving the load specified

in figure 9.

Waveform 1. D+/D- Transmit Mode, low speed Waveform 2. D+/D- Transmit Mode, full speed

[]

Ch1 500mV Ch2 500mV M 250nS Ch1 1.68 V

[]

Ch1 500mV Ch2 500mV M 20.0nS Ch1 1.68 V

PIN ASSIGNMENTS

Pin 1 — RERR — Receive Error. This CMOS

level output pin is forced HIGH when

both D+ and D- are HIGH to signal an

error state. CAUTION: Since RERR is a

CMOS output, care must be taken to

ensure that RERR is NOT connected to

VCC or GND.

Pin 2 — OE — Output Enable Not. When

asserted LOW, this input pin enables the

driver to transmit data on the bus. When

HIGH, the receiver is active and the driver

outputs are in tri-state.

Pin 3 — RCV — Receive data. This is a

CMOS level output pin from D+ and D-,

typically connected to the inputs of the

USB Serial Interface Engine (SIE).

Pin 4, 5 — VP, VM — Gated version of D+

and D-. Used to detect single ended zero

(SEO), error conditions, and interconnect

speed. These pins have CMOS level

outputs.

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GND

411

RERR

RCV

SUSPND SPEED

RSEO

D-

D+

VPO

VMO

Pin 6 — SUSPND — Suspend. This input pin

provides a low power state for the SP5301

while the USB bus is inactive. While the

SUSPND pin is asserted HIGH, it will

drive RCV pin LOW.

Pin 7 — GND — Ground.

Pin 8 — RSEO — Receive Single Ended Zero.

This CMOS level output pin is forced

HIGH when both D+ and D- are LOW to

signal the end of packet (EOP) in signal

transmission. CAUTION: Since RSEO

is a CMOS output, care must be taken to

ensure that RSEO is NOT connected to

VCC or GND.

Pin 9 — SPEED — Speed. Edge rate control.

This input pin determines edge rates, where

a logic HIGH designates edge rates for

"full speed" and logic LOW designates

edge rates for "low speed."

Pin 10, 11 — D-, D+ — Data-, Data+. These

differential data bus I/O pins conform to

the Universal Serial Bus standard.

Pin 12, 13 — VPO, VMO — These are the

PINOUT

logic inputs to the differential driver,

typically connected to the outputs of the

Serial Interface Engine (SIE).

Pin 14 — VCC — +3.0V to +3.6V power supply.

Figure 4. D+/D to RCV Figure 5. OE to D+/D-

Figure 2. D+/D- to VP/VM or VPO/VMO to D+/D- Figure 3. Rise and Fall Times

2.7V

INPUT

GND

VOH

OUTPUTVOL

tPLH

50%

tPHL

50%

50% 50%

RISE

90% 90%

10%

FALL

10%

D+

D-

PLH

PHL

2.0V

1.0V

50% 50%

2.7V

OE OV

VOH

VOL

D+/D-

1.5V 1.5V

tPZH

tPZL

tPHZ

tPLZ

50% 50%

AC WAVEFORMS

NOTE: VX = VOL + 0.3V, VY = VOH - 0.3V, VCC > +3.0V, VOL and VOH are the typical output voltage drops that occur

with the output load.

Figure 6. Setup for Speed Figure 7. Load for VM, VP, RERR, RSEO and RCV

Figure 8. Load for Enable and Disable Times Figure 9. Load for D+/D-

2.7V

GND

2.7V

GND

SPEED

D+/D-

50% 50%

D.U.T. 25pF

Test Point

AC WAVEFORMS (continued)

NOTE: VX = VOL + 0.3V, VY = VOH - 0.3V, VCC > +3.0V, VOL and VOH are the typical output voltage drops that occur

with the output load.

D.U.T.

50pF

22Ω500Ω

Test Point

V = 0V for tPZH and tPHZ

V = VCC for tPZL and tPLZ

D.U.T.

15KΩC

22Ω

Test Point SW1

1.5KΩ

= 50pF, Full Speed

= 350pF, Low Speed

TEST SW1

D-/LS Close

D+/LS Open

D-/FS Open

D+/FS Close

Figure 10. Receiver Delay VS. Common Mode Voltage

(with peak to peak overdrive voltage as a parameter) Figure 11. Transmitter Rise and Fall Time VS.

Capacitive Load (full speed)

Figure 12. D+/D- to RERR Delay Figure 13. D+/D- to RSEO Delay

AC WAVEFORMS (continued)

NOTE: VX = VOL + 0.3V, VY = VOH - 0.3V, VCC > +3.0V, VOL and VOH are the typical output voltage drops that occur

with the output load.

60V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V

Delay (ns)

Common Mode (Volts)

50mV

100mV

200mV

500mV

XXXXX

5.5

4.5

3.5

310 20 30 40 50

tR/tF (nS)

Load (pF)

tR/tF

D+

D- t

PLH

2.0V

1.0V

50%

RERR

D+

D- t

PLH

2.0V

1.0V

50%

RSEO

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

(NARROW)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) 8–PIN

h x 45°

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249

0.014/0.019

(0.35/0.49)

0.189/0.197

(4.80/5.00)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

14–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249)

0.013/0.020

(0.330/0.508)

0.337/0.344

(8.552/8.748)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

16–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249)

0.013/0.020

(0.330/0.508)

0.386/0.394

(9.802/10.000)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

P ACKAGE: PLASTIC THIN SMALL

OUTLINE

(TSSOP)

DIMENSIONS

in inches (mm)

Minimum/Maximum 14–PIN

- /0.43

(- /1.10)

0.002/0.006

(0.05/0.15)

0.007/0.012

(0.19/0.30)

0.193/0.201

(4.90/5.10)

0.169/0.177

(4.30/4.50)

0.026 BSC

(0.65 BSC)

0.126 BSC

(3.20 BSC)

0.020/0.030

(0.50/0.75)

0°/8°

ORDERING INFORMATION

Model Temperature Range Package Types

SP5301CN.......................................................0°C to +70°C.....................................................14-Pin NSOIC

SP5301CY.......................................................0°C to +70°C.....................................................14-Pin TSSOP

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Sipex Corporation

Headquarters and

Sales Office

22 Linnell Circle

Billerica, MA 01821

TEL: (978) 667-8700

FAX: (978) 670-9001

e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600