LTC1960
1
1960fb
TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual Battery Charger/
Selector with SPI Interface
The LTC
®
1960 is a highly integrated battery charger and
selector intended for portable products using dual smart
batteries. A serial SPI interface allows an external microcon-
troller to control and monitor status of both batteries.
A proprietary PowerPath architecture supports simulta-
neous charging or discharging of both batteries. Typical
battery run times are extended by 10%, while charging
times are reduced by up to 50%. The LTC1960 automati-
cally switches between power sources in less than 10µs
to prevent power interruption upon battery or wall adapter
removal.
The synchronous buck battery charger delivers 95% effi-
ciency with only 0.5V dropout voltage, and prevents audible
noise in all operating modes. Patented input current limit-
ing with 5% accuracy charges batteries in the shortest
possible time without overloading the wall adapter.
The LTC1960’s 5mm × 7mm 38-pin QFN and 36-pin nar-
row SSOP packages allow implementation of a complete
SBS-compliant dual battery system while consuming
minimum PCB area.
LTC1960 Dual Battery/Selector System Architecture
APPLICATIONS
n Complete Dual-Battery Charger/Selector System
n Serial SPI Interface Allows External µC Control and
Monitoring
n Simultaneous Dual-Battery Discharge Extends Run
Time by Typically 10%
n Simultaneous Dual-Battery Charging Reduces
Charging Time by Up to 50%
n Automatic PowerPath™ Switching in <10µs
Prevents Power Interruption
n Circuit Breaker Protects Against Overcurrent Faults
n 5% Accurate Adapter Current Limit Maximizes
Charging Rate
n 95% Efficient Synchronous Buck Charger
n Charger Has Low 0.5V Dropout Voltage
n No Audible Noise Generation, Even with Ceramic
Capacitors
n 11-Bit VDAC Delivers 0.8% Voltage Accuracy
n 10-Bit IDAC Delivers 5% Current Accuracy
n VIN Up to 32V; VBATT Up to 28V
n Available in 5mm × 7mm 38-Pin QFN and 36-Pin
Narrow SSOP Packages
n Portable Computers
n Portable Instruments
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No RSENSE and PowerPath are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
5481178, 5723970, 6304066, 6580258.
Dual vs Sequential Charging
LTC1960 MICROCONTROLLER
DC
IN
4
SYSTEM POWER
SMBus
1960 TA01
BAT2 BAT1
SPI
TIME (MINUTES)
BATTERY CURRENT (mA)
3500
3000
2500
2000
1500
1000
500
0
3500
3000
2500
2000
1500
1000
500
0
1960 TA01b
050 100 150 200 250 300
BAT1
CURRENT
BAT2
CURRENT
SEQUENTIAL
DUAL
BAT1
CURRENT
100
MINUTES
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)
REQUESTED CURRENT = 3A
REQUESTED VOLTAGE = 12.3V
MAX CHARGER CURRENT = 4.1A
BAT2
CURRENT
LTC1960
2
1960fb
ABSOLUTE MAXIMUM RATINGS
Voltage from DCIN, SCP, SCN, CLP, VPLUS,
SW to GND ................................................. –0.3V to 32V
Voltage from SCH1, SCH2 to GND ............. –0.3V to 28V
Voltage from BOOST to GND ......................–0.3V to 41V
PGND with Respect to GND ...................................±0.3V
CSP, CSN, BAT1, BAT2 to GND ...................... –5V to 28V
LOPWR, DCDIV to GND ............................. –0.3V to 10V
SSB, SCK, MOSI, MISO to GND ................... –0.3V to 7V
(Note 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
36
25
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VPLUS
BAT2
BAT1
SCN
SCP
GDCO
GDCI
GB1O
GB1I
GB2O
GB2I
LOPWR
VSET
ITH
ISET
GND
DCDIV
SSB
SCH2
GCH2
GCH1
SCH1
TGATE
BOOST
SW
DCIN
VCC
BGATE
PGND
COMP1
CLP
CSP
CSN
MOSI
MISO
SCK
TJMAX = 125°C, θJA = 70°C/W
13 14 15 16
TOP VIEW
39
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1VSET
ITH
ISET
GND
DCDIV
SSB
SCK
MISO
MOSI
GND
CSN
CSP
SCP
SCN
BAT1
BAT2
VPLUS
GND
SCH2
GCH2
GCH1
SCH1
TGATE
BOOST
LOPWR
GB2I
GB2O
GB1I
GB1O
GDCI
GDCO
CLP
COMP1
PGND
BGATE
VCC
DCIN
SW
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
THE EXPOSED PAD (PIN 39) IS GND. MUST BE SOLDERED TO THE PCB
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1960CG#PBF LTC1960CG#TRPBF LTC1960CG 36-Lead Plastic SSOP 0°C to 70°C
LTC1960CUHF#PBF LTC1960CUHF#TRPBF 1960 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
COMP1 to GND ............................................ –0.3V to 5V
Operating Ambient Temperature
Range (Note 7) ............................................ 0°C to 70°C
Operating Junction Temperature ............ –40°C to 125°C
Storage Temperature.............................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
SSOP Only ........................................................ 300°C
LTC1960
3
1960fb
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply and Reference
DCIN Operating Range DCIN Selected 6 28 V
ICH DCIN Operating Current Not Charging (DCIN Selected)
Charging (DCIN Selected)
1
1.3
1.5
2
mA
mA
Battery Operating Voltage Range Battery Selected, PowerPath Function (Note 2) 6 28 V
Battery Drain Current Battery Selected, Not Charging, VDCIN = 0V 175 µA
VFDC
VFB1
VFB2
VFSCN
VPLUS Diodes Forward Voltage:
DCIN to VPLUS
BAT1 to VPLUS
BAT2 to VPLUS
SCN to VPLUS
IVCC = 10mA
IVCC = 0mA
IVCC = 0mA
IVCC = 0mA
0.8
0.7
0.7
0.7
V
V
V
V
UVLO Undervoltage Lockout Threshold VPLUS Ramping Down, Measured at VPLUS
to GND
l3 3.5 3.9 V
UVHYS UV Lockout Hysteresis VPLUS Rising, Measured at VPLUS to GND 60 mV
VVCC VCC Regulator Output Voltage 5 5.2 5.4 V
VLDR VCC Load Regulation IVCC = 0mA to 10mA 0.2 1 %
Switching Regulator
VTOL Overall Voltage Accuracy 5V ≤ VOUT < 25V, (Note 3)
l
–0.8
–1
0.8
1
%
%
ITOL Overall Current Accuracy IDAC Value = 3FFHEX
VCSP , VCSN = 12V
l
–5
–6
5
6
%
%
fOSC Regulator Switching Frequency 255 300 345 kHz
fDO Regulator Switching Frequency in Low
Dropout Mode
Duty Cycle ≥ 99% 20 25 kHz
DCMAX Regulator Maximum Duty Cycle 99 99.5 %
IMAX Maximum Current Sense Threshold VITH = 2.2V 140 155 190 mV
ISNS CA1 Input Bias Current VCSP = VCSN > 5V 150 µA
CMSL CAI Input Common Mode Low 0 V
CMSH CAI Input Common Mode High VDCIN–0.2 V
VCL1 CL1 Turn-On Threshold 95 100 105 mV
TG tr
TG tf
TGATE Transition Time:
TGATE Rise Time
TGATE Fall Time
CLOAD = 3300pF, 10% to 90%
CLOAD = 3300pF, 10% to 90%
50
50
90
90
ns
ns
BG tr
BG tf
BGATE Transition Time:
BGATE Rise Time
BGATE Fall Time
CLOAD = 3300pF, 10% to 90%
CLOAD = 3300pF, 10% to 90%
50
40
90
80
ns
ns
Trip Points
VTR DCDIV/LOPWR Threshold VDCDIV or VLOPWR Falling l1.166 1.19 1.215 V
VTHYS DCDIV/LOPWR Hysteresis Voltage VDCDIV or VLOPWR Rising 30 mV
IBVT DCDIV/LOPWR Input Bias Current VDCDIV or VLOPWR = 1.19V 20 200 nA
VTSC Short-Circuit Comparator Threshold VSCP – VSCN, VCC ≥ 5V l90 100 115 mV
VFTO Fast PowerPath Turn-Off Threshold VDCDIV Rising from VCC 6 7 7.9 V
VOVSD Overvoltage Shutdown Threshold as a Percent
of Programmed Charger Voltage
VSET Rising from 0.8V Until TGATE and
BGATE Stop Switching
107 %
The l denotes the specifications which apply over the full operating
temperature range (Note 7), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, unless otherwise noted.
LTC1960
4
1960fb
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DACs
IRES IDAC Resolution Guaranteed Monotonic Above IMAX/16 10 bits
tIP
tILOW
IDAC Pulse Period:
Normal Mode
Low Current Mode
6
10
50
15
µs
ms
VRES VDAC Resolution Guaranteed Monotonic (5V < VBAT < 25V) 11 bits
VSTEP VDAC Granularity 16 mV
VOFF VDAC Offset (Note 6) 0.8 V
tVP VDAC Pulse Period 7 11 16.5 µs
Charge MUX Switches
tONC GCH1/GCH2 Turn-On Time VGCHX – VSCHX > 3V, CLOAD = 3nF 5 10 ms
tONC GCH1/GCH2 Turn-Off Time VGCHX – VSCHX < 1V, from Time of VCSN <
VBATX – 30mV, CLOAD = 3nF
3 7 µs
VCON CH Gate Clamp Voltage
GCH1
GCH2
ILOAD = 1µA
VGCH1 – VSCH1
VGCH2 – VSCH2
5
5
5.8
5.8
7
7
V
V
VCOFF CH Gate Off Voltage
GCH1
GCH2
ILOAD = 10µA
VGCH1 – VSCH1
VGCH2 – VSCH2
–0.8
–0.8
–0.4
–0.4
0
0
V
V
VTOC CH Switch Reverse Turn-Off Voltage VCSN – VBATX, 5V ≤ VBATX ≤ 28V l5 20 40 mV
VFC CH Switch Forward Regulation Voltage VBATX – VCSN, 5V ≤ VBATX ≤ 28V l15 35 60 mV
IOC(SRC)
IOC(SNK)
GCH1/GCH2 Active Regulation:
Max Source Current
Max Sink Current
VGCHX – VSCHX = 1.5V
–2
2
µA
µA
VCHMIN BATX Voltage Below Which Charging Is Inhibited (Note 8) 3.5 4.7 V
PowerPath Switches
tD LY Blanking Period After UVLO Trip Switches Held Off 250 ms
tPPB Blanking Period After LOPWR Trip Switches in 3-Diode Mode 1 sec
tONPO GB1O/GB2O/GDCO Turn-On Time VGS < –3V, from Time of Battery/DC
Removal, or LOPWR Indication
l5 10 µs
tOFFPO GB1O/GB2O/GDCO Turn-Off Time VGS > –1V, from Time of Battery/DC
Removal, or LOPWR Indication
l3 7 µs
VPONO Output Gate Clamp Voltage
GB1O
GB2O
GDCO
ILOAD = 1µA
Highest (VBAT1 or VSCP) – VGB1O
Highest (VBAT2 or VSCP) – VGB2O
Highest (VDCIN or VSCP) – VGDCO
4.75
4.75
4.75
6.25
6.25
6.25
7
7
7
V
V
V
VPOFFO Output Gate Off Voltage
GB1O
GB2O
GDCO
ILOAD = –25µA
Highest (VBAT1 or VSCP) – VGB1O
Highest (VBAT2 or VSCP) – VGB2O
Highest (VDCIN or VSCP) – VGDCO
0.18
0.18
0.18
0.25
0.25
0.25
V
V
V
VTOP PowerPath Switch Reverse Turn-Off Voltage VSCP – VBATX or VSCP – VDCIN
6V ≤ VSCP ≤ 28V
l5 20 60 mV
VFP PowerPath Switch Forward Regulation Voltage VBATX – VSCP or VDCIN – VSCP
6V ≤ VSCP ≤ 28V
l0 25 50 mV
IOP(SRC)
IOP(SNK)
GDCI/GB1I/GB2I Active Regulation
Source Current
Sink Current
(Note 4)
–4
75
µA
µA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range (Note 7), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, unless otherwise noted.
LTC1960
5
1960fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. Battery voltage must be adequate to drive gates of PowerPath
P-channel FET switches. This does not affect charging voltage of the
battery, which can be zero volts.
Note 3. See Test Circuit.
Note 4. DCIN, BAT1, BAT2 are held at 12V and GDCI, GB1I, GB2I are
forced to 10.5V. SCP is set at 12.0V to measure source current at GDCI,
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tONPI Gate B1I/B2I/DCI Turn-On Time VGS < –3V, CLOAD = 3nF (Note 5) 300 µs
tOFFPI Gate B1I/B2I/DCI Turn-Off Time VGS > –1V, CLOAD = 3nF (Note 5) 10 µs
VPONI Input Gate Clamp Voltage
GB1I
GB2I
GDCI
ILOAD = 1µA
Highest (VBAT1 or VSCP) – VGB1I
Highest (VBAT2 or VSCP) – VGB2I
Highest (VDCIN or VSCP) – VGDCI
4.75
4.75
4.75
6.7
6.7
6.7
7.5
7.5
7.5
V
V
V
VPOFFI Input Gate Off Voltage
GB1I
GB2I
GDCI
ILOAD = 25µA
Highest (VBAT1 or VSCP) – VGB1I
Highest (VBAT2 or VSCP) – VGB2I
Highest (VDCIN or VSCP) – VGDCI
0.18
0.18
0.18
0.25
0.25
0.25
V
V
V
Logic I/O
IIH/IIL SSB/SCK/MOSI Input High/Low Current l–1 1 µA
VIL SSB/MOSI/SCK Input Low Voltage l0.8 V
VIH SSB/MOSI/SCK Input High Voltage l2 V
VOL MISO Output Low Voltage IOL = 1.3mA l0.4 V
IOFF MISO Output Off-State Leakage Current VMISO = 5V l2 µA
SPI Timing (See Timing Diagram)
TWD Watch Dog Timer l1.2 2.5 4.5 sec
tSSH SSB High Time 680 ns
tCYC SCK Period CLOAD = 200pF RPULLUP = 4.7k on MISO l2 µs
tSH SCK High Time 680 ns
tSL SCK Low Time 680 ns
tLD Enable Lead Time 200 ns
tLG Enable Lag Time 200 ns
tsu Input Data Set-Up Time l100 ns
tHInput Data Hold Time l100 ns
tAAccess Time (From Hi-Z to Data Active on MISO) l125 ns
tdis Disable Time (Hold Time to Hi-Z State on MISO) l125 ns
tVOutput Data Valid CL = 200pF, RPULLUP = 4.7k on MISO l580 ns
tHO Output Data Hold l0 ns
tIr SCK/MOSI/SSB Rise Time 0.8V to 2V 250 ns
tIf SCK/MOSI/SSB Fall Time 2V to 0.8V 250 ns
tOf MISO Fall Time 2V to 0.4V, CL = 200pF l400 ns
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range (Note 7), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, unless otherwise noted.
GB1I and GB2I. SCP is set at 11.9V to measure sink current at GDCI, GB1I
and GB2I.
Note 5. Extrapolated from testing with CL = 50pF.
Note 6. VDAC offset is equal to the reference voltage, since
VOUT = VREF(16mV • VDAC(VALUE)/2047 + 1)
Note 7. The LTC1960C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet specified
performance at –40°C and 85°C, but is not tested at these extended
temperature limits.
Note 8. Does not apply to low current mode. Refer to “The Current DAC
Block” in the Operation section.
LTC1960
6
1960fb
TYPICAL PERFORMANCE CHARACTERISTICS
Charger Efficiency Charger Start-Up Charger Load Dump
Charger Load Regulation Charging Current Accuracy
IDAC Low Current Mode
vs Normal Mode
Battery Drain Current
(BAT1 Selected) PowerPath Switching
PowerPath Autonomous
Switching
BAT1 VOLTAGE (V)
6
BAT1 CURRENT (µA)
30
1960 G01
12 18 24
250
240
230
220
210
200
190
180
170
160
150
TA = 25°C
TIME (µs)
16
15
14
13
12
11
10
9
8
7
6
LOAD VOLTAGE (V)
1960 G02
–50 –40 –30 –10 010 20 30 40 50
–20
CLOAD = 20µF
ILOAD = 0.8A
TA = 25°C
LOPWR
THRESHOLD
TIME (SEC)
–1
LOAD VOLTAGE (V)
012 3
1960 G03
4
16
15
14
13
12
11
10
9
8
7
65
BAT1
REMOVED
NOTE: LIGHT LOAD TO
EXAGGERATE SWITCHING EVENT
IOUT (A)
0
0
EFFICIENCY (%)
10
30
40
50
100
70
0.025 0.10
1960 G04
20
80
90
60
0.50 2.5 4.0
TIME (SEC)
–0.05
CHARGER OUTPUT (V)
0.05 0.15 0.20 0.40
1960 G05
0 0.10 0.25 0.30 0.35
12
10
8
6
4
2
0
TIME (ms)
–4 –2
BAT1 VOLTAGE (V)
14
12
10
8
6
4
2
0
1960 G06
42 10 12 14 16
06 8
VIN = 20V
VDAC = 12.29V
IDAC = 3000mA
LOAD CURRENT = 1A
TA = 25°C
BAT1
OUTPUT
LOAD
CONNECTED
LOAD
DISCONNECTED
CHARGE CURRENT (mA)
0
BAT1 VOLTAGE (V)
4000
1960 G07
1000 2000 3000
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
VIN = 20V
VDAC = 12.288V
IDAC = 4000mA
TA = 25°C
IDAC VALUE
0 200
OUTPUT CURRENT ERROR (mA)
400 800600 1000 1200
1960 G08
120
100
80
60
40
20
0
–20
–40
VDCIN = 20V
VBAT1 = 12V
RSNS = 0.025Ω
TA = 25°C
PROGRAMMED CURRENT (mA)
0
CHARGING CURRENT (mA)
500
450
400
350
300
250
200
150
100
50
0160 320 400
1960 G09
80 240 480 560
LOW CURRENT
MODE
NORMAL
MODE
VIN = 20V
VBAT1 = 12V
RSNS = 0.025Ω
TA = 25°C
LTC1960
7
1960fb
VDAC VALUE
250 450
OUTPUT VOLTAGE ERROR (mV)
650 1050850 1250 1450
1960 G10
100
75
50
25
0
–25
–50
–75
–100
DCIN = 24V
TA = 25°C
ILOAD = 100mA
TIME (MINUTES)
BATTERY CURRENT (mA)
3500
3000
2500
2000
1500
1000
500
0
3500
3000
2500
2000
1500
1000
500
0
1960 G11
050 100 150 200 250 300
BAT1
CURRENT
BAT2
CURRENT
SEQUENTIAL
DUAL
BAT1
CURRENT
100
MINUTES
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)
REQUESTED CURRENT = 3A
REQUESTED VOLTAGE = 12.3V
MAX CHARGER CURRENT = 4.1A
BAT2
CURRENT
BAT2
VOLTAGE
BAT2
CURRENT
BAT1
CURRENT
BAT1
VOLTAGE
BAT1 INITIAL CAPACITY = 0%
BAT2 INITIAL CAPACITY = 90%
PROGRAMMED CHARGER CURRENT = 3A
PROGRAMMED CHARGER VOLTAGE = 16.8V
TIME (MINUTES)
0
BATTERY VOLTAGE (V)
120
1960 G12
40 80 160
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5 20 60 100 140
BATTERY CURRENT (mA)
3500
3000
2500
2000
1500
1000
500
0
TIME (MINUTES)
0
BATTERY VOLTAGE (V)
120
12.0
11.0
10.0
9.0
8.0
12.0
11.0
10.0
9.0
8.0
1960 G13
20 180
40 60 80 100 140 160
BAT1
VOLTAGE
BAT1
VOLTAGE
DUAL
SEQUENTIAL
BAT2
VOLTAGE
BAT2
VOLTAGE
BATTERY TYPE: 10.8V Li-Ion(MOLTECH NI2020)
LOAD CURRENT = 3A
11
MINUTES
TIME (MINUTES)
0120
20 40 60 80 100 140
BATTERY VOLTAGE (V)
15
14
13
12
11
10
15
14
13
12
11
10
1960 G14
BAT2
VOLTAGE
BAT2
VOLTAGE
BAT1
VOLTAGE
BAT1
VOLTAGE
BATTERY TYPE: 12V NIMH (MOLTECH NJ1020)
LOAD: 33W
16
MINUTES
DUAL
SEQUENTIAL
TYPICAL PERFORMANCE CHARACTERISTICS
Dual vs Sequential Discharge Dual vs Sequential Discharge
Voltage Accuracy Dual vs Sequential Charging
Dual Charging Batteries with
Different Charge State
LTC1960
8
1960fb
PIN FUNCTIONS
Input Power Related
SCN (Pin 4/Pin 30): PowerPath Current Sensing Negative
Input. This pin should be connected directly to the “bottom”
(output side) of the sense resistor, RSC, in series with the
three PowerPath switch pairs, for detecting short-circuit
current events. Also powers LTC1960 internal circuitry
when all other sources are absent.
SCP (Pin 5/Pin 31): PowerPath Current Sensing Positive
Input. This pin should be connected directly to the “top”
(switch side) of the sense resistor, RSC, in series with the
three PowerPath switch pairs, for detecting short-circuit
current events.
GDCO (Pin 6/Pin 32): DCIN Output Switch Gate Drive.
Together with GDCI, this pin drives the gate of the P-channel
switch in series with the DCIN input switch.
GDCI (Pin 7/Pin 33): DCIN Input Switch Gate Drive.
Together with GDCO, this pin drives the gate of the
P-channel switch connected to the DCIN input.
GB1O (Pin 8/Pin 34): BAT1 Output Switch Gate Drive.
Together with GB1I, this pin drives the gate of the P-channel
switch in series with the BAT1 input switch.
GB1I (Pin 9/Pin 35): BAT1 Input Switch Gate Drive.
Together with GB1O, this pin drives the gate of the P-channel
switch connected to the BAT1 input.
GB2O (Pin 10/Pin 36): BAT2 Output Switch Gate Drive.
Together with GB2I, this pin drives the gate of the P-channel
switch in series with the BAT2 input switch.
GB2I (Pin 11/Pin 37): BAT2 Input Switch Gate Drive.
Together with GB2O, this pin drives the gate of the P-channel
switch connected to the BAT2 input.
CLP (Pin 24/Pin 13): The Positive Input to the Supply
Current Limiting Amplifier CL1. The threshold is set at
100mV above the voltage at the DCIN pin. When used
to limit supply current, a filter is needed to filter out the
switching noise.
Battery Charging Related
VSET (Pin 13/Pin 1): The Tap Point of a Programmable
Resistor Divider Which Provides Battery Voltage Feedback
to the Charger. A capacitor from CSN to VSET and from
VSET to GND provide necessary compensation and filtering
for the voltage loop.
ITH (Pin 14/Pin 2): The Control Signal of the Inner Loop of
the Current Mode PWM. Higher ITH voltage corresponds to
higher charging current in normal operation. A capacitor
of at least 0.1µF to GND filters out PWM ripple. Typical
full-scale output current is 30µA. Nominal voltage range
for this pin is 0V to 2.4V.
ISET (Pin 15/Pin 3): A capacitor from ISET to ground is
required to filter higher frequency components from the
delta-sigma IDAC.
CSN (Pin 22/Pin 11): Current Amplifier CA1 Input. Con-
nect this to the common output of the charger MUX
switches.
CSP (Pin 23/Pin 12): Current Amplifier CA1 Input. This
pin and the CSN pin measure the voltage across the
sense resistor, RSNS, to provide the instantaneous cur-
rent signals required for both peak and average current
mode operation.
COMP1 (Pin 25/Pin 14): The Compensation Node for the
Amplifier CL1. A capacitor is required from this pin to GND
if input current amplifier CL1 is used. At input adapter
current limit, this node rises to 1V. By forcing COMP1 low,
amplifier CL1 will be defeated (no adapter current limit).
COMP1 can source 10µA.
BGATE (Pin 27/Pin 16): Drives the bottom external MOSFET
of the battery charger buck converter.
SW (Pin 30/Pin 19): PWM switch node connected to source
of the top external MOSFET switch. Used as reference for
top gate driver.
BOOST (Pin 31/Pin 20): Supply to Topside Floating Driver.
The bootstrap capacitor is returned to this pin. Voltage
swing at this pin is from a diode drop below VCC to (DCIN
+ VCC).
(G/UHF)
LTC1960
9
1960fb
TGATE (Pin 32/Pin 21): Drives the top external MOSFET
of the battery charger buck converter.
SCH1 (Pin 33/Pin 22), SCH2 (Pin 36/Pin 25): Charger
MUX N-Channel Switch Source Returns. These two pins
are connected to the sources of the back-to-back switch
pairs, Q3/Q4 and Q9/Q10 (see Typical Application on back
page of data sheet), respectively. A small pull-down cur-
rent source returns these nodes to 0V when the switches
are turned off.
GCH1 (Pin 34/Pin 23), GCH2 (Pin 35/Pin 24): Charger
MUX N-Channel Switch Gate Drives. These two pins drive
the gates of the back-to-back switch pairs, Q3/Q4 and Q9/
Q10, between the charger output and the two batteries.
External Power Supply Pins
VPLUS (Pin 1/Pin 27): Supply. The VPLUS pin is connected
via four internal diodes to the DCIN, SCN, BAT1, and BAT2
pins. Bypass this pin with a 1µF to 2µF capacitor.
BAT1 (Pin 3/Pin 29), BAT2 (Pin 2/Pin 28): These two
pins are the inputs from the two batteries for power to
the LTC1960 and to provide voltage feedback to the bat-
tery charger.
LOPWR (Pin 12/Pin 38): LOPWR Comparator Input from
SCN External Resistor Divider to GND. If the voltage at
LOPWR is lower than the LOPWR comparator threshold,
then system power has failed and power is autonomously
switched to a higher voltage source, if available. See
PowerPath section of LTC1960 operation.
DCDIV (Pin 17/Pin 5): External DC Source Comparator
Input from DCIN External Resistor Divider to GND. If the
voltage at DCDIV is above the DCDIV comparator thresh-
old, then the DC bit is set and the wall adapter power is
considered to be adequate to charge the batteries. If DCDIV
rises more than 1.8V above VCC, then all of the PowerPath
switches are latched off until all power is removed.
A capacitor from DCDIV to GND is recommended to prevent
noise-induced false emergency turn-off conditions from
being detected. Refer to “Fast PowerPath Turn-Off” in the
Operation section and the Typical Application on the back
page of this data sheet.
DCIN (Pin 29/Pin 18): Supply. External DC power source.
A 1µF bypass capacitor should be connected to this pin as
close as possible. No series resistance is allowed, since
the adapter current limit comparator input is also this pin.
Internal Power Supply Pins
GND (Pin 16/Pin 4, Pin 10, Pin 26, Pin 39): Ground for
Low Power Circuitry.
PGND (Pin 26/Pin 15): High Current Ground Return for
BGATE Driver.
VCC (Pin 28/Pin 17): Internal Regulator Output. Bypass
this output with at least a 2µF to 4.7µF capacitor. Do not
use this regulator output to supply more than 1mA to
external circuitry.
Digital Interface Pins
SSB (Pin 18/Pin 6): SPI Slave Select Input. Active low.
TTL levels. This signal is low when clocking data to/from
the LTC1960.
SCK (Pin 19/Pin 7): Serial SPI Clock. TTL levels.
MISO (Pin 20/Pin 8): SPI Master-In-Slave-Out Output,
Open Drain. Serial data is transmitted from the LTC1960,
when SSB is low, on the falling edge of SCK. TTL levels.
A 4.7k pull-up resistor is recommended.
MOSI (Pin 21/Pin 9): SPI Master-Out-Slave-In Input. Serial
data is transmitted to the LTC1960, when SSB is low, on
the rising edge of SCK. TTL levels.
GND (Exposed Pad Pin 39, UHF Package Only): Ground.
Must be soldered to the PCB ground for rated thermal
performance.
PIN FUNCTIONS
(G/UHF)
LTC1960
10
1960fb
BLOCK DIAGRAM
SPI
INTERFACE
11-BIT ∆Σ
VOLTAGE DAC
10-BIT ∆Σ
CURRENT DAC
SELECTOR
CONTROLLER
CHARGE
+
–
+
–
+
–
+
–
–
–
–
–
–
1.19V
100Ω
100mV
SWB1
DRIVER
CHARGE
PUMP
SWB2
DRIVER
SWDC
DRIVER
CSN
+
–
ON
+
–
ON
DCIN
GCH1
SCH2
GCH2
SCH1
TGATE
PGND
BGATE
SW
BAT1
GND
VCC
DCIN
DCIN
VSET
VPLUS
BAT2
VCC
REGULATOR
OSCILLATOR
LOW DROP
DETECT TON
+
BOOST
BGATE
VCC
PWM
LOGIC
CHGMON
400k
0.86V
0.8V
+
+
+
+
Q
S
R
CHARGE
100mV
CLP
+
CHGMON
0.75V
40mV
+
–
÷15
SCN
GB1I GB1O GB2I GB2O GDCI GDCO
SHORT CIRCUIT
AC_PRESENT
SCP
SCN
DCDIV
LOPWR
MOSI
MISO
SCK
SSB
CSP
CSN
ISET
CA1
3k
3k
0.8V
BUFFERED ITH
gm = 1.4m
Ω
gm = 0.4m
Ω
CLAMP
IREV
ICMP
ITH
COMP1
EA
0V
11
1960 BD
CSP-CSN
3kΩ
gm = 1.4m
Ω
24
26
27
30
32
31
13
29
16
28
1
2
3
36
35
33
34
9 8 11 10 7 6
25 14
5
4
17
12
21
20
19
18
15
23
22
CL1
CA2
–
–
+
(LTC1960CG Pin Numbers Shown)
LTC1960
11
1960fb
TEST CIRCUIT
–
+
–
+
VREF
VSW
ITH
BAT1 BAT2
CHGMON
VSET
0.5V
EA
1960 TC01
SSB
SCK
MOSI
MISO
tCYC
tdis
tSSH
tLD
tSH
tsu
tH
tAtVtHO
tSL
tLG
SLAVE
BIT 7 OUT
SLAVE
BIT 0 OUT
BIT 0BIT 7
1960 TD01
TIMING DIAGRAM
SPI Timing Diagram
LTC1960
12
1960fb
OPERATION
OVERVIEW
The LTC1960 is composed of a battery charger controller,
charge MUX controller, PowerPath controller, SPI inter-
face, a 10-bit current DAC (IDAC) and 11-bit voltage DAC
(VDAC). When coupled with a low cost microprocessor, it
forms a complete battery charger/selector system for two
batteries. The battery charger is programmed for voltage
and current, and the charging battery is selected via the
SPI interface. Charging can be accomplished only if the
voltage at DCDIV indicates that sufficient voltage is avail-
able from the input power source, usually an AC adapter.
The charge MUX, which selects the battery to be charged,
is capable of charging both batteries simultaneously by
selecting both batteries for charging. The charge MUX
switch drivers are configured to allow charger current to
share between the two batteries and to prevent current
from flowing in a reverse direction in the switch. The
amount of current that each battery receives will depend
upon the relative capacity of each battery and the battery
voltage. This can result in significantly shorter charging
times (up to 50% for Li-Ion batteries) than sequential
charging of each battery. In order to continue charging,
the CHARGE_BAT information must be updated more
frequently than the internal watchdog timer.
The PowerPath controller selects which of the pairs of
PFET switches, input and output, will provide power to
the system load. The selection is accomplished over
the SPI interface. If the system voltage drops below the
threshold set by the LOPWR resistor divider, then all of
the output side PFETs are turned on quickly and power
is taken from the highest voltage source available at the
DCIN, BAT1 or BAT2 inputs. The input side PFETs act as
diodes in this mode and power is taken from the source
with the highest voltage. The input side PowerPath switch
driver that is delivering power then closes its input switch
to reduce the power dissipation in the PFET bulk diode. In
effect, this system provides diode -like behavior from the
FET switches, without the attendant high power dissipa-
tion from diodes. The microprocessor is informed of this
3-diode mode status when it polls the PowerPath status
register via the SPI interface. The microprocessor can then
assess which power source is capable of providing power,
and program the PowerPath switches accordingly. Since
high speed PowerPath switching at LOPWR trip points
is handled autonomously, there is no need for real-time
microprocessor resources to accomplish this task.
Simultaneous discharge of both batteries is accomplished
by simply programming both batteries for discharge into
the system load. The switch drivers prevent reverse current
flow in the switches and automatically discharge both bat-
teries into the load, sharing current according to the relative
capacity of the batteries. Simultaneous dual discharge can
increase battery operating time by approximately 10%
by reducing losses in the switches and reducing internal
losses associated with high discharge rates.
SPI Interface
The SPI interface is used to write to the internal PowerPath
registers, the charger control registers, the current DAC,
and the voltage DAC. The SPI is also able to read internal
status registers. There are two types of SPI write com-
mands. The first write command is a 1-byte command used
to load PowerPath and charger control bits. The second
write command is a 2-byte command used to load the
DACs. The SPI read command is a 2-byte command. In
order to ensure the integrity of the SPI communication,
the last bit received by the SPI is echoed back over the
MISO output after the next falling SCK. The data format
is set up so that the master has the option of aborting a
write if the returned MISO bit is not as expected.
(Refer to Block Diagram and Typical Application)
LTC1960
13
1960fb
SSB
SCK
MOSI
MISO
1960 F01
BYTE 1 BYTE 2
Figure 1. SPI Write to VDAC of Data = b101_0101_0101
OPERATION
1-Byte SPI Write Format:
bit 7........byte 1..........bit 0
MOSI D0 D1 D2 X A0 A1 A2 0
MISO X D0 D1 D2 X A0 A1 A2
Charger Write Address: A[2:0] = b111
Charger Write Data: D2 = X
D1 = CHARGE_BAT2
D0 = CHARGE_BAT1
PowerPath Write Address: A[2:0] = b110
PowerPath Write Data: D2 = POWER_BY_DC
D1 = POWER_BY_BAT2
D0 = POWER_BY_BAT1
2-Byte SPI Write Format:
bit 7........byte 1..........bit 0 bit 7..........byte 2............bit 0
MOSI D0 D1 D2 D3 D4 D5 D6 1 D7 D8 D9 D10 A0 A1 A2 0
MISO X D0 D1 D2 D3 D4 D5 D6 1 D7 D8 D9 D10 A0 A1 A2
IDAC Write Address: A[2:0] = b000
IDAC Data Bits D9-D0: IDAC value data (MSB-LSB)
IDAC Data Bit D10 : Normal mode = 0, low current mode = 1 (Dual battery charging is disabled)
VDAC Write Address: A[2:0] = b001
VDAC Data Bits D10-D0: VDAC value (MSB-LSB)
Subsequent SPI communication is inhibited until after the addressed DAC is finished loading. It is recommended that
the master transmit all zeros until MISO goes low. This handshaking procedure is illustrated in Figure 1.
LTC1960
14
1960fb
SSB
SCK
MOSI
MISO
1960 F02
BYTE 1 BYTE 2
Figure 2. SPI Read of FA = 0, LP = 0, DC = 1, PF = 0, and CH = 1
OPERATION
2-Byte SPI Read Format:
bit 7........byte 1.......bit 0 bit 7........byte 2............bit 0
MOSI 0 0 0 0 A0 A1 A2 0 0 0 0 0 A0 A1 A2 1
MISO X 0 0 0 0 A0 A1 A2 X FA LP DC PF CH X X
Status Address: A[2:0] = b010
Status Read Data: LP = LOW_POWER (Low power comparator output)
DC = DCDIV (DCDIV comparator output)
PF = POWER_FAIL (Set if selected power supply failed to hold up system power after
three tries)
CH = CHARGING (One or more batteries are being charged)
FA = FAULT. This bit is set for any of the following conditions:
1) The LTC1960 is still in power-on reset.
2) The LTC1960 has detected a short circuit and has shut down power and charging.
3) The system has asserted a fast off using DCDIV.
Note: All other values of A[2:0] are reserved and must not be used.
A status read is illustrated in Figure 2.
LTC1960
15
1960fb
Battery Charger Controller
The LTC1960 charger controller uses a constant off-time,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
main current comparator ICMP resets the SR latch. While
the top MOSFET is off, the bottom MOSFET is turned on
until either the inductor current reverses, as indicated by
current comparator IREV, or the beginning of the next
cycle. The oscillator uses the equation:
tOFF =1
fOSC
•(VDCIN
−
VCSN)
VDCIN
to set the bottom MOSFET on time. The peak inductor
current at which ICMP resets the SR latch is controlled
by the voltage on ITH. ITH is in turn controlled by several
loops, depending upon the situation at hand. The average
current control loop converts the voltage between CSP and
CSN to a representative current. Error amp CA2 compares
this current against the desired current requested by the
IDAC at the ISET pin and adjusts ITH until the IDAC value
is satisfied. The BAT1/BAT2 MUX provides the selected
battery voltage at CHGMON, which is divided down to the
VSET pin by the VDAC resistor divider and is used by error
amp EA to decrease ITH if the VSET voltage is above the 0.8V
reference. The amplifier CL1 monitors and limits the input
current, normally from the AC adapter, to a preset level
(100mV/RCL). At input current limit, CL1 will decrease the
ITH voltage and thus reduce battery charging current.
An overvoltage comparator, 0V, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned
off until the overvoltage condition is cleared. This feature
is useful for batteries which “load dump” themselves by
opening their protection switch to perform functions such
as calibration or pulse mode charging.
Charging is inhibited for battery voltages below the mini-
mum charging threshold, VCHMIN. Charging is not inhibited
when the low current mode of the IDAC is selected.
The top MOSFET driver is powered from a floating boot-
strap capacitor CB. This capacitor is normally recharged
from VCC through an external diode when the top MOSFET
is turned off. A 2µF to 4.7µF capacitor across VCC to GND
is required to provide a low dynamic impedance to charge
the boost capacitor. It is also required for stability and
power-on reset purposes.
As VIN decreases towards the selected battery voltage,
the converter will attempt to turn on the top MOSFET
continuously (“dropout’’). A dropout timer detects this
condition and forces the top MOSFET to turn off, and the
bottom MOSFET on, for about 200ns at 40µs intervals to
recharge the bootstrap capacitor.
Charge MUX Switches
The equivalent circuit of a charge MUX switch driver is
shown in Figure 3. If the charger controller is not enabled,
the charge MUX drivers will drive the gate and source of
the series-connected MOSFETs to a low voltage and the
switch is off. When the charger controller is on, the charge
MUX driver will keep the MOSFETs off until the voltage at
CSN rises at least 35mV above the battery voltage. GCH1
is then driven with an error amplifier EAC until the volt-
age between BAT1 and CSN satisfies the error amplifier
or until GCH1 is clamped by the internal Zener diode.
The time required to close the switch could be quite long
(many ms) due to the small currents output by the error
amp and depending upon the size of the MOSFET switch.
If the voltage at CSN decreases below VBAT1 – 20mV, a
comparator CC quickly turns off the MOSFETs to prevent
reverse current from flowing in the switches. In essence,
this system performs as a low forward voltage diode.
Operation is identical for BAT2.
Figure 3. Charge MUX Switch Driver Equivalent Circuit
OPERATION
–
+
+
–
GCH1
SCH1
Q4
Q3
TO
BATTERY
1
FROM
CHARGER
BAT1
CSN 35mV
20mV
OFF
DCIN + 10V
(CHARGE PUMPED)
10k
1960 F03
EAC
CC
LTC1960
16
1960fb
Dual Charging
Note that the charge MUX switch drivers will operate
together to allow both batteries to be charged simultane-
ously. If both charge MUX switch drivers are enabled,
only the battery with the lowest voltage will be charged
until its voltage rises to equal the higher voltage battery.
The charge current will then share between the batteries
according to the capacity of each battery.
If both batteries are selected for charging, only batteries
with voltages above VCHMIN are allowed to charge. Dual
charging is not allowed when the low current mode of
the IDAC is selected. If dual charging is enabled when
the IDAC enters low current mode, then only BAT1 will
be charged.
Charger Start-Up
When the charger controller is enabled by the SPI Interface
block, the charger output CSN will ramp from 0V until it
exceeds the selected battery voltage. The clamp error amp
is used to prevent the charger output from exceeding the
selected battery voltage by more than 0.7V during the
start-up transient while the charge MUX switches, have
yet to close. Once the charge MUX switches have closed,
the clamp releases ITH to allow control by another loop.
PowerPath Controller
The PowerPath switches are turned on and off via the SPI
interface, in any combination. The external P-MOSFETs
are usually connected as an input switch and an output
switch. The output switch PFET is connected in series with
the input PFET and the positive side of the short-circuit
sensing resistor, RSC. The input switch is connected in
series between the power source and the output PFET.
The PowerPath switch driver equivalent circuit is shown
in Figure 4. The output PFET is driven high and low by the
output side driver controlling pin GXXO, the PFET is either
on or off. The gate of the input PFET is driven by an error
amplifier which monitors the voltage between the input
power source (BAT1 in this case) and SCP. If the switch
is turned off, the two outputs are driven to the higher of
the two voltages present across the input/output terminals
of the switch. When the switch is instructed to turn on,
the output side driver immediately drives the gate of the
output PFET approximately 6V below the highest of the
voltages present at the input/output. When the output
PFET turns on, the voltage at SCP will be pulled up to a
diode drop below the source voltage by the bulk diode of
the input PFET. If the source voltage is more than 25mV
above SCP, EAP will drive the gate of the input PFET low
until the input PFET turns on and reduces the voltage
across the input/output to the EAP set point, or until the
Zener clamp engages to limit the voltage applied to the
input PFET. If the source voltage drops more than 20mV
below SCP, then comparator CP turns on SWP to quickly
prevent large reverse current in the switch. This operation
mimics a diode with a low forward voltage drop.
Figure 4. PowerPath Driver Equivalent Circuit
OPERATION
–
+
+
–
GB1I
GB1O
Q8
Q7
FROM
BATTERY
1
BAT1
SCP
25mV
20mV OFF
OFF
1960 F04
EAP
CP
SWP
TO
LOAD
CL
RSC
Autonomous PowerPath Switching
The LOPWR comparator monitors the voltage at the
load through the resistor divider from pin SCN. If any
POWER_BY bit is set and the LOPWR comparator trips,
then all of the switches are turned on (3-diode mode) by
the PowerPath controller to ensure that the system is
powered from the source with the highest voltage. The
PowerPath controller waits approximately 1 second, to
allow power to stabilize, and then reverts to the previous
PowerPath switch configuration. A power-fail counter is
incremented to indicate that a failure has occurred. If the
power-fail counter equals a value of 3, then the PowerPath
controller sets the switches to 3-diode mode and the PF
LTC1960
17
1960fb
bit is set in the status register. This is a three-strikes-and-
you’re-out process which is intended to debounce the
PowerPath PF indicator. The power-fail counter is reset
by a PowerPath SPI write.
Short-Circuit Protection
Short-circuit protection operates in both a current mode
and a voltage mode. If the voltage between SCP and SCN
exceeds the short-circuit comparator threshold VTSC for
more than 15ms, then all of the PowerPath switches are
turned off and the FAULT bit (FA) is set. Similarly, if the
voltage at SCN falls below 3V for more than 15ms, then
all of the PowerPath switches are turned off and the FA bit
is set. The FA bit is reset by removing all power sources
and allowing the voltage at VPLUS to fall below the UVLO
threshold. If the FA bit is set, charging is disabled until
VPLUS exceeds the UVLO threshold and charging is re-
quested via the SPI interface.
When a hard short-circuit occurs, it might pull all of the
power sources down to near 0V potentials. The capacitors
on VCC and VPLUS must be large enough to keep the circuit
operating correctly during the 15ms short-circuit event.
The charger will stop within a few microseconds leaving
a small current which must be provided by the capacitor
on VPLUS. The recommended minimum values (1µF on
VPLUS and 2µF on VCC, including tolerances) should keep
the LTC1960 operating above the UVLO trip voltage long
enough to perform the short-circuit function when the
input voltages are greater than 8V. Increasing the capaci-
tor across VCC to 4.7µF will allow operation down to the
recommended 6V minimum.
Fast PowerPath Turn-Off
All of the PowerPath switches can be forced off by set-
ting the DCDIV pin to a voltage between 8V and 10V. This
will have the same effect as a short-circuit event. The PF
status bit will also be set. DCDIV must be less than 5V
and VPLUS must decrease below the UVLO threshold to
re-enable the PowerPath switches.
Power-Up Strategy
All three PowerPath switches are turned on after VPLUS
exceeds the UVLO threshold for more than 250ms. This
delay is to prevent oscillation from a turn-on transient
near the UVLO threshold.
The Voltage DAC Block
The voltage DAC (VDAC) is a delta-sigma modulator
which controls the effective value of an internal resistor,
RVSET = 7.2k, used to program the maximum charger
voltage. Figure 5 is a simplified diagram of the VDAC
operation. The charger monitor MUX is connected to the
appropriate battery indicated by the CHARGE_BATx bit.
The delta-sigma modulator and switch SWV convert the
VDAC value, received via SPI communication, to a vari-
able resistance equal to (11/8)RVSET/(VDAC(VALUE)/2047).
In regulation, VSET is servo driven to the 0.8V reference
voltage, VREF .
Therefore, programmed voltage is:
VBATx = (8/11) VREF 405.3k/7.2k • (VDAC(VALUE)/2047)
+ VREF = 32,752mV • (VDAC(VALUE)/2047) + 0.8V
Note that the reference voltage must be subtracted from
the VDAC value in order to obtain the correct output volt-
age. This value is VREF /16mV = 50 (32HEX).
Capacitors CB1 and CB2 are used to average the voltage
present at the VSET pin as well as provide a zero in the
voltage loop to help stability and transient response time
to voltage variations. See the Applications Information
section.
OPERATION
Figure 5. Voltage DAC Operation
–
+
BAT2
BAT1
CB1
CB2
CSN
1960 F05
EA
VREF
VSET
RVSET
7.2k
RVF
405.3k
∆Σ
MODULATOR
SWV 11
TO
ITH
DAC
VALUE
(11 BITS)
CHGMON
LTC1960
18
1960fb
The Current DAC Block
The current DAC is a delta-sigma modulator which controls
the effective value of an internal resistor, RSET = 18.77k,
used to program the maximum charger current. Figure 6 is
a simplified diagram of the DAC operation. The delta-sigma
modulator and switch convert the IDAC value, received
via SPI communication, to a variable resistance equal to
1.25RSET/(IDAC(VALUE)/1023). In regulation, ISET is servo
driven to the 0.8V reference voltage, VREF , and the cur-
rent from RSET is matched against a current derived from
the voltage between pins CSP and CSN. This current is
(VCSP – VCSN)/3k.
Therefore, programmed current is:
IAVG =VREF •3k
(1.25RSNS RSET )
•IDAC(VALUE)
1023
When the low current mode bit (D10) is set to 1, the current
DAC enters a different mode of operation. The current DAC
output is pulse-width modulated with a high frequency clock
having a duty cycle value of 1/8. Therefore, the maximum
output current provided by the charger is IMAX/8. The
delta-sigma output gates this low duty cycle signal on
and off. The delta-sigma shift registers are then clocked
at a slower rate, about 40ms/bit, so that the charger has
time to settle to the IMAX/8 value. The resulting average
charging current is equal to 1/8 of the current programmed
in normal mode. Dual battery charging is disabled in low
current mode. If both batteries are selected for charging,
then only BAT1 will charge.
OPERATION
Figure 6. Current DAC Operation
Figure 7. Charging Current Waveform in Low Current Mode
–
+
1960 F06
VREF
ISET
RSET
18.77k
∆Σ
MODULATOR
10
TO
ITH
DAC
VALUE
(10 BITS)
CSET
(VCSP – VCSN)
3kΩ
(FROM CA1 AMPLIFIER)
AVERAGE CHARGER CURRENT
IMAX/8
0
~40ms
1960 F07
LTC1960
19
1960fb
Figure 8. Adapter Current Limiting
it is actual physical capacity rating at the time of charge.
Capacity rating will change with age and use and hence
the current sharing ratios can change over time.
In dual charge mode, the charger uses feedback from the
BAT2 input to determine charger output voltage. When
charging batteries with significantly different initial states of
charge (i.e., one almost full, the other almost depleted), the
full battery will get a much lower current. This will cause a
voltage difference across the charge MUX switches, which
may cause the BAT1 voltage to exceed the programmed
voltage. Using MOSFETs in the charge MUX with lower
RDS(ON) will alleviate this problem.
Adapter Limiting
An important feature of the LTC1960 is the ability to auto-
matically adjust charging current to a level which avoids
overloading the wall adapter. This allows the product to
operate at the same time that batteries are being charged
without complex load management algorithms. Addition-
ally, batteries will automatically be charged at the maximum
possible rate of which the adapter is capable.
This feature is created by sensing total adapter output cur-
rent and adjusting charging current downward if a preset
adapter current limit is exceeded. True analog control is
used, with closed loop feedback ensuring that adapter
load current remains within limits. Amplifier CL1 in Figure
8 senses the voltage across RCL, connected between the
CLP and DCIN pins. When this voltage exceeds 100mV,
the amplifier will override programmed charging current
to limit adapter current to 100mV/RCL. A lowpass filter
formed by 5kΩ and 0.1µF is required to eliminate switch-
ing noise. If the current limit is not used, CLP should be
connected to DCIN.
100mV
–
+
5kΩ
CLP
DCIN
11960 F08
0.1µF
+
RCL*
CIN
VIN
CL1
AC ADAPTER
INPUT
*RCL = 100mV
ADAPTER CURRENT LIMIT
+
APPLICATIONS INFORMATION
Automatic Current Sharing
In a dual parallel charge configuration, the LTC1960 does
not actually control the current flowing into each individual
battery. The capacity, or amp-hour rating, of each battery
determines how the charger current is shared. This auto-
matic steering of current is what allows both batteries to
reach their full capacity points at the same time. In other
words, given all other things equal, charge termination
will happen simultaneously.
A battery can be modeled as a huge capacitor and hence
governed by the same laws.
I = C • (dV/dT), where:
I = The current flowing through the capacitor
C = Capacity rating of battery (using amp-hour value
instead of capacitance)
dV = Change in voltage
dt = Change in time
The equivalent model of a set or parallel batteries is a
set of parallel capacitors. Since they are in parallel, the
change in voltage over change in time is the same for both
batteries 1 and 2.
dV
dtBAT1
=dV
dtBAT2
From here we can simplify.
IBAT1/CBAT1 = dV/dt = IBAT2/CBAT2
IBAT2 = IBAT1 CBAT2/CBAT1
At this point you can see that the current divides as the
ratio of the two batteries capacity ratings. The sum of the
current into both batteries is the same as the current being
supply by the charger. This is independent of the mode of
the charger (CC or CV).
ICHRG = IBAT1 + IBAT2
From here we solve for the actual current for each battery.
IBAT2 = ICHRG CBAT2/(CBAT1 + CBAT2)
IBAT1 = ICHRG CBAT1/(CBAT1 + CBAT2)
Please note that the actual observed current sharing will
vary from manufactures claimed capacity ratings since
LTC1960
20
1960fb
Watchdog Timer
Charging will begin when either CHARGE_BAT1 or
CHARGE_BAT2 bits are set in the charger register (ad-
dress: 111). Charging will stop if the charger register is
not updated prior to the expiration of the watchdog timer.
Simply repeating the same data transmission to the charger
register at a rate higher than once per second will ensure
that charging will continue uninterrupted.
Extending System to More Than Two Batteries
The LTC1960 can be extended to manage systems with more
than three sources of power. Contact Linear Technology
Applications Engineering for more information.
Charging Depleted Batteries
Some batteries contain internal protection switches that
disconnect a load if the battery voltage falls below what
is considered a reasonable minimum. In this case, the
charger may not start because the voltage at the battery
terminal is less than 5V. The low current mode of the IDAC
must be used in this case to condition the battery. In low
current mode, there is no minimum voltage requirement
(but dual charging is not allowed). Usually, the battery will
detect that it is being charged and then close its protec-
tion switch, which will allow the IDAC to switch to normal
mode. Smart batteries require that charging current not
exceed 100mA until valid charging voltage and charging
current parameters are transmitted via the SMBus. The
low current IDAC mode is ideal for this purpose.
Starting Charge with Dissimilar Batteries in Dual
Charge Mode
When charging batteries of different charger termination
voltages, the charger should be started using the follow-
ing procedure:
Step 1. Select only the lowest termination voltage bat-
tery for charging, and set the charger to its charging
parameters.
Step 2. When the battery current is flowing into that bat-
tery, change to dual charging mode (without stopping the
charger) and set the appropriate charging parameters for
this dual charger condition.
If this procedure is not followed, and BAT2 is significantly
higher voltage than BAT1, the charger could refuse to
charge either battery.
Charge Termination Issues
Batteries with constant-current charging and voltage-based
charger termination might experience problems with re-
ductions of charger current caused by adapter limiting. It
is recommended that input limiting feature be defeated in
such cases. Consult the battery manufacturer for informa-
tion on how your battery terminates charging.
Setting Output Current Limit
The full-scale output current setting of the IDAC will produce
VMAX = 102.3mV between CSP and CSN. To set the full-
scale current of the DAC simply divide VMAX by RSNS.
This is expressed by the following equation:
RSNS = 0.1023/IMAX
Table 1. Recommended RSNS Resistor Values
IMAX (A) RSNS (Ω) 1% RSNS (W)
1.023 0.100 0.25
2.046 0.050 0.25
4.092 0.025 0.5
8.184 0.012 1
Use resistors with low ESL.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value
on ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases with
higher frequency and increases with higher VIN.
∆IL=1
f
( )
L
( )
VOUT 1−VOUT
VIN
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). In no case should
APPLICATIONS INFORMATION
LTC1960
21
1960fb
∆IL exceed 0.6(IMAX) due to limits imposed by IREV and
CA1. Remember the maximum ∆IL occurs at the maxi-
mum input voltage. In practice, 10µH is the lowest value
recommended for use.
Charger Switching Power MOSFET and Diode
Selection
Two external power MOSFETs must be selected for use with
the LTC1960 charger: An N-channel MOSFET for the top
(main) switch and an N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak gate drive levels are set by the VCC volt-
age. This voltage is typically 5.2V. Consequently, logic-level
threshold MOSFETs must be used. Pay close attention to
the BVDSS specification for the MOSFETs as well; many of
the logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance RDS(ON), reverse transfer capacitance CRSS,
input voltage and maximum output current. The LTC1960
charger is always operating in continuous mode so the duty
cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle = VOUT/VIN
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN
The MOSFET power dissipations at maximum output
current are given by:
PMAIN = VOUT/VIN(IMAX)2(1 +
d
∆
T
)RDS(ON) + k(VIN)2
(IMAX)(CRSS)(f)
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 +
d
∆
T
) RDS(ON)
Where
d
∆
T
is the temperature dependency of RDS(ON) and
k is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CRSS actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage or during a short-circuit when the duty cycle in this
switch is nearly 100%. The term (1 +
d
∆
T
) is generally
given for a MOSFET in the form of a normalized RDS(ON)
vs Temperature curve, but
d
= 0.005/°C can be used as
an approximation for low voltage MOSFETs. CRSS is usu-
ally specified in the MOSFET characteristics. The constant
k = 1.7 can be used to estimate the contributions of the
two terms in the main switch dissipation equation.
If the LTC1960 charger is to operate in low dropout mode
or with a high duty cycle greater than 85%, then the top-
side N-channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.
The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency. A 1A Schottky is generally a good
size for 4A regulators due to the relatively small average
current. Larger diodes can result in additional transition
losses due to their larger junction capacitance. The diode
may be omitted if the efficiency loss can be tolerated.
Calculating IC Power Dissipation
The power dissipation of the LTC1960 is dependent upon the
gate charge of QTG and QBG (refer to Typical Application).
The gate charge is determined from the manufacturer’s
data sheet and is dependent upon both the gate voltage
swing and the drain voltage swing of the FET.
PD = (VDCIN – VVCC) • [fOSC(QTG + QBG) + IVCC]
+ VDCIN • IDCIN
Example: VVCC = 5.2V, VDCIN = 19V, fOSC = 345kHz,
QG2 = QG3 = 15nC, IVCC = 0mA.
PD = 165mW
APPLICATIONS INFORMATION
LTC1960
22
1960fb
VSET/ISET Capacitors
Capacitor C7 is used to filter the delta-sigma modulation
frequency components to a level which is essentially DC.
Acceptable voltage ripple at ISET is about 10mVP-P . Since
the period of the delta-sigma switch closure, T∆∑, is about
10µs and the internal IDAC resistor, RSET, is 18.77k, the
ripple voltage can be approximated by:
∆VISET =VREF •T∆ ∑
RSET •C7
Then the equation to extract C7 is:
C7 =VREF •T∆ ∑
∆VISET •RSET
= 0.8/0.01/18.77k(10µs) @ 0.043µF
In order to prevent overshoot during start-up transients,
the time constant associated with C7 must be shorter than
the time constant of C5 at the ITH pin. If C7 is increased
to improve ripple rejection, then C5 should be increased
proportionally and charger response time to average cur-
rent variation will degrade.
Capacitor CB1 and CB2 are used to filter the VDAC delta-
sigma modulation frequency components to a level which
is essentially DC. CB2 is the primary filter capacitor and
CB1 is used to provide a zero in the response to cancel
the pole associated with CB2. Acceptable voltage ripple
at VSET is about 10mVP-P . Since the period of the delta-
sigma switch closure, T∆∑, is about 11µs and the internal
VDAC resistor, RVSET , is 7.2kΩ, the ripple voltage can be
approximated by:
∆VVSET =VREF •T∆ ∑
RVSET CB1 || CB2
( )
Then the equation to extract CB1 || CB2 is:
CB1 || CB2 =VREF •T∆ ∑
RVSET∆VVSET
CB2 should be 10× to 20× CB1 to divide the ripple voltage
present at the charger output. Therefore CB1 = 0.01µF and
CB2 = 0.1µF are good starting values. In order to prevent
overshoot during start-up transients the time constant as-
sociated with CB2 must be shorter than the time constant
of C5 at the ITH pin. If CB2 is increased to improve ripple
rejection, then C5 should be increased proportionally and
charger response time to voltage variation will degrade.
Input and Output Capacitors
In the 4A Lithium Battery Charger (Typical Application
section), the input capacitor (CIN) is assumed to absorb all
input switching ripple current in the converter, so it must
have adequate ripple current rating. Worst-case RMS ripple
current will be equal to one-half of output charging current.
Actual capacitance value is not critical. Solid tantalum,
low ESR capacitors have a high ripple current rating in a
relatively small surface mount package,
but caution must
be used when tantalum capacitors are used for input or
output bypass.
High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
battery is connected to the charger. Solid tantalum capaci-
tors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of “surge robust” low ESR tantalums are rated for high
surge conditions such as battery to ground.
The relatively high ESR of an aluminum electrolytic for
C15, located at the AC adapter input terminal, is helpful
in reducing ringing during the hot-plug event.
Highest possible voltage rating on the capacitor will
minimize problems. Consult with the manufacturer before
use. Alternatives include new high capacity ceramic (at
least 20µF) from Tokin, United Chemi-Con/Marcon, et al.
Other alternative capacitors include OSCON capacitors
from Sanyo.
The output capacitor (COUT) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
IRMS =
0.29(VBAT) 1−VBAT
VDCIN
(L1)(f)
For example:
VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and f = 300kHz,
IRMS = 0.41A.
APPLICATIONS INFORMATION
LTC1960
23
1960fb
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
may be added to increase battery impedance at the 300kHz
switching frequency. Switching ripple current splits be-
tween the battery and the output capacitor depending on
the ESR of the output capacitor and the battery impedance.
If the ESR of COUT is 0.2Ω and the battery impedance is
raised to 4Ω with a bead or inductor, only 5% of the cur-
rent ripple will flow in the battery.
PowerPath and Charge MUX MOSFET Selection
Three pairs of P-channel MOSFETs must be used with
the wall adapter and the two battery discharge paths. Two
pairs of N-channel MOSFETs must be used with the battery
charge path. The nominal gate drive levels are set by the
clamp drive voltage of their respective control circuitry.
This voltage is typically 6.25V. Consequently, logic-level
threshold MOSFETs must be used. Pay close attention to
the BVDSS specification for the MOSFETs as well; many of
the logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), input voltage and maximum out-
put current. For the N-channel charge path, the maximum
current is the maximum programmed current to be used.
For the P-channel discharge path maximum current typi-
cally occurs at end of life of the battery when using only
one battery. The upper limit of RDS(ON) value is a function of
the
actual
power dissipation capability of a given MOSFET
package that must take into account the PCB layout. As a
starting point, without knowing what the PCB dissipation
capability would be, derate the package power rating by
a factor of two.
RDS(ON)MAX =PMOSFET
2 IMAX
( )
2
If you are using a dual MOSFET package with both MOS-
FETs in series, you must cut the package power rating in
half again and recalculate.
RDS(ON)MAX =PMOSFETDUAL
4 IMAX
( )
2
If you use identical MOSFETs for both battery paths, voltage
drops will track over a wide current range. The LTC1960
linear 25mV CV drop regulation will not occur until the
current has dropped below:
ILINEARMAX =25mV
2RDS(ON)MAX
However, if you try to use the above equation to determine
RDS(ON) to force linear mode at full current, the MOSFET
RDS(ON) value becomes unreasonably low for MOSFETs
available at this time. The need for the LTC1960 voltage
drop regulation only comes into play for parallel battery
configurations that terminate charge or discharge using
voltage. At first this seems to be a problem, but there are
several factors helping out:
1. When batteries are in parallel current sharing, the current
flow through any one battery is less than if it is running
standalone.
2. Most batteries that charge in constant-voltage mode,
such as Li-Ion, charge terminate at a current value of
C/10 or less which is well within the linear operation
range of the MOSFETs.
3. Voltage tracking for the discharge process does not
need such precise voltage tracking values.
The LTC1960 has two transient conditions that force the
discharge path P-channel MOSFETs to have two additional
parameters to consider. The parameters are gate charge
QGATE and single pulse power capability.
When the LTC1960 senses a LOW_POWER event, all
the P-channel MOSFETs are turned on simultaneously
to allow voltage recovery due to a loss of a given power
source. However, there is a delay in the time it takes to
turn on all the MOSFETs. Slow MOSFETs will require more
bulk capacitance to hold up all the system’s power sup-
ply function during the transition and fast MOSFET will
require less bulk capacitance. The transition speed of a
MOSFET to an on or off state is a direct function of the
MOSFET gate charge.
t=QGATE
IDRIVE
APPLICATIONS INFORMATION
LTC1960
24
1960fb
IDRIVE is the fixed drive current into the gate from the
LTC1960 and “t” is the time it takes to move that charge
to a new state and change the MOSFET conduction mode.
Hence, time is directly related to QGATE. Since QGATE
goes up with MOSFETs of lower RDS(ON), choosing such
MOSFETs has a counterproductive increase in gate charge
making the MOSFET slower. Please note that the LTC1960
recovery time specification only refers to the time it takes
for the voltage to recover to the level just prior to the
LOW_POWER event as opposed to full voltage.
The single pulse current rating of the MOSFET is important
when a short-circuit takes place. The MOSFET must survive
a 15ms overload. MOSFETs of lower RDS(ON) or MOSFETs
that use more powerful thermal packages will have a high
power surge rating. Using too small of a pulse rating will
allow the MOSFET to blow to the open-circuit condition
instantly like a fuse. Typically there is no outward sign of
failure because it happens so fast. Please measure the
surge current for all discharge power paths under worse
case conditions and consult the MOSFET data sheet for
the limitations. Voltage sources with the highest voltage
and the most bulk capacitance are often the biggest risk.
Specifically the MOSFETs in the wall adapter path with wall
adapters of high voltage, large bulk capacitance and low
resistance DC cables between the adapter and device are
the most common failures. Remember to
only
use the
real
wall adapter with a production DC power cord when per-
forming the wall adapter path test. The use of a laboratory
power supply is unrealistic for this test and will force you
to over specify the MOSFET ratings. A battery pack usu-
ally has enough series resistance to limit the peak current
or are too low in voltage to create enough instantaneous
power to damage their respective PowerPath MOSFETs.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
time is kept as short as possible. To prevent magnetic
and electrical field radiation and high frequency resonant
problems, proper layout of the components connected to
the IC is essential.
1. Keep the highest frequency loop path as small and
tight as possible. This includes the bypass capacitors,
with the higher frequency capacitors being closer to
the noise source than the lower frequency capacitors.
The highest frequency switching loop has the highest
layout priority. For best results, avoid using vias in this
loop and keep the entire high frequency loop on a single
external PCB layer. If you must, use multiple vias to keep
the impedance down (see Figure 9).
APPLICATIONS INFORMATION
Figure 10. Kelvin Sensing of Charging Current
Figure 9. High Speed Switching Path
1960 F09
VBAT
L1
VIN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
CIN COUT
D1
CSP
1960 F10
DIRECTION OF CHARGING CURRENT
RSNS
CSN
2. Run long power traces in parallel. Best results are
achieved if you run each trace on separate PCB layer one
on top of the other for maximum capacitance coupling
and common mode noise rejection.
3. If possible, use a ground plane under the switcher
circuitry to minimize capacitive interplane noise cou-
pling.
4. Keep signal or analog ground separate. Tie this analog
ground back to the power supply at the output ground
using a single point connection.
5. For best current programming accuracy provide a Kelvin
connection from RSENSE to CSP and CSN. See Figure 10
as an example.
LTC1960
25
1960fb
PACKAGE DESCRIPTION
G36 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678910 11 12 14 15 16 17 1813
12.50 – 13.10*
(.492 – .516)
2526 22 21 20 19232427282930313233343536
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
LTC1960
26
1960fb
5.00 ± 0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF
5.15 ± 0.10
7.00 ± 0.10
0.75 ± 0.05
R = 0.125
TYP
R = 0.10
TYP
0.25 ± 0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ± 0.10
0.40 ±0.10
0.70 ± 0.05
0.50 BSC
5.5 REF
3.00 REF 3.15 ± 0.05
4.10 ± 0.05
5.50 ± 0.05 5.15 ± 0.05
6.10 ± 0.05
7.50 ± 0.05
0.25 ± 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
PACKAGE DESCRIPTION
LTC1960
27
1960fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
B 04/11 Updated Absolute Maximum Ratings section
Added Note 8
Updated Pin Functions
Updated equation in “The Current DAC Block” section
Updated equation in “Calculating IC Power Dissipation” section
Updated Typical Application
2
5
8, 9
18
21
28
(Revision history begins at Rev B)
LTC1960
28
1960fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
LT 0411 REV B • PRINTED IN USA
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24
29
3
2
20
19
21
18
17
25
35
36
34
33
13
28
16
CB1
0.01µF
CB2
0.1µF
C3
0.01µF
R6
100Ω
R7
49.9k
1%
R5
1k
1%
R4
14k
1%
C5
0.15µF
CL
20µF
25V
C7
0.1µF
R9
3.3k
1%
D2
1
7
6
9
8
11
10
5
4
12
22
23
14
15
30
31
32
27
26
C4
0.1µF
QBG
QTG
L1
10µH
4A
RSNS
0.025Ω
1%
CIN
20µF
25V
COUT
20µF 25V
CLP
DCIN
BAT1
BAT2
MISO
SCK
MOSI
SSB
DCDIV
COMP1
GCH2
SCH2
GCH1
SCH1
VSET
VCC
GND
LTC1960
VPLUS
GDCI
GDCO
GB1I
GB1O
GB2I
GB2O
SCP
SCN
LOPWR
CSN
CSP
ITH
ISET
SW
BOOST
TGATE
BGATE
PGND
R1
5.1k
1%
R2
649k
1%
R3
100k
1%
RCL
0.03
RSC
0.02Ω
SSB
BAT2
BAT1
VIN
SCK
MOSI
MISO
C1
0.1µF
C2
1µF
Q1
Q2
Q6
Q5
Q7
Q8
Q4
Q3
1960 TA02
LOAD
Q9
Q10
C9
100pF
C6
1µF
Q1, Q2, Q5, Q6, Q7, Q8: Si4925DY
Q3, Q4, Q9, Q10, QTG, QBG: FDS6912A
D1: MBR130T3
D2: CMDSH-3 TYPE
D3, D4: BAT54A TYPE
PowerPath MUX
CHARGE MUX
VDD
4.7k
D1
100Ω
C8
0.1µF
R11
1k
BAT2 BAT1
D4
D3
C6
2µF
Dual Battery Selector and 4A Charger
(LTC1960CG Pin Numbers Shown)
