www.lansdale.com
ML13156
Wideband FM IF System
Page 1 of 21 Issue A
Legacy Device: Motorola MC13156
The ML13156 is a wideband FM IF subsystem targeted at high per-
formance data and analog applications. The ML13156 has an onboard
grounded collector VCO transistor that may be used with a fundamen-
tal or overtone crystal in single channel operation or with a PLL in
multichannel operation. The mixer is useful to 500 MHz and may be
used in a balanced–differential, or single–ended configuration. The IF
amplifier is split to accommodate two low cost cascaded filters. RSSI
output is derived by summing the output of both IF sections. A preci-
sion data shaper has a hold function to preset the shaper for fast recov-
ery of new data.
Applications for the ML13156 include CT–2, wideband data links
and other radio systems utilizing GMSK, FSK, or FM modulation.
• 2.0 to 6.0 Vdc Operation
• Typical Sensitivity at 200 MHz of 2.0 µV for 12 dB SINAD
• RSSI Dynamic Range Typically 80 dB
• High Performance Data Shaper for Enhanced CT–2 Operation
• Internal 330 Ωand 1.4 kΩTerminations for 10.7 Mhz and 455 kHz
Filters
• Split IF for Improved Filtering and Extended RSSI Range
• 3rd Order Intercept (Input) of –25 dBm (Input Matched)
• Operating Temperature Range – TA= –40 to +85°C
SO 24W = -6P
PLASTIC PACKAGE
CASE 751E
(SO-24L)
24
1
QFP 32 = -8P
PLASTIC QFP PACKAGE
CASE 873
32
1
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
SO 24W MC13156DW ML13156-6P
QFP 32 MC13156FB ML13156-8P
LANSDALEPACKAGE
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN CONNECTIONS
Function
RF Input 1
RF Input 2
Mixer Output
VCC1
IF Amp Input
IF Amp Decoupling 1
IF Amp Decoupling 2
VCC Connect (N/C Internal)
IF Amp Output
VCC2
Limiter IF Input
Limiter Decoupling 1
Limiter Decoupling 2
VCC Connect (N/C Internal)
Quad Coil
Demodulator Output
Data Slicer Input
VCC Connect (N/C Internal)
Data Slicer Ground
Data Slicer Output
Data Slicer Hold
VEE2
RSSI Output/Carrier Detect In
Carrier Detect Output
VEE1 and Substrate
LO Emitter
LO Base
VCC Connect (N/C Internal)
1
2
3
4
5
6
7
–
8
9
10
11
12
–
13
14
15
–
16
17
18
19
20
21
22
23
24
–
31
32
1
2
3
4
5
6
7
8
9
10
11
12, 13, 14
15
16
17
18
19
20
21
22
23
24
25
26
27
28, 29, 30
SO–24L QFP
11
Simplified Block Diagram
18192022 1314151617212324
1210987654321
LIM
DEC 2
LIM
DEC 1
LIM
In
VCC2
IF
Out
IF
DEC 2
IF
DEC 1
IF
In
VCC1
Mix
Out
RF
In 2
RF
In 1
Quad
Coil
Demod
DS
In
DS
Gnd
Data
Out
DS
Hold
VEE2
RSSI
CAR
Det
VEE1
LO
Emit
LO
In
Bias
5.0
pF
Data
Slicer
LIM Amp
IF Amp
Bias
Mixer
NOTE: Pin Numbers shown for SOIC package only. Refer to Pin Assignments Table.
This device contains 197 active transistors.
ML13156
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS
Rating Pin Symbol Value Unit
Power Supply Voltage 16, 19, 22 VEE(max) –6.5 Vdc
Junction Temperature – TJ(max) 150 °C
Storage Temperature Range – Tstg –65 to +150 °C
NOTES: 1. Devices should not be operated at or outside these values. The "Recommended Operating
Conditions" table provides for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Rating Pin Symbol Value Unit
Power Supply Voltage @ TA = 25°C4, 9 VCC 0 (Ground) Vdc
–40°C ≤ TA ≤ +85°C16, 19, 22 VEE –2.0 to –6.0
Input Frequency 1, 2 fin 500 MHz
Ambient Temperature Range – TA–40 to +85 °C
Input Signal Level 1, 2 Vin 200 mVrms
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC1 = VCC2 = 0, no input signal.)
Characteristic Pin Symbol Min Typ Max Unit
Total Drain Current (See Figure 2) 19, 22 ITo ta l mA
VEE = –2.0 Vdc – 4.8 –
VEE = –3.0 Vdc 3.0 5.0 8.0
VEE = –5.0 Vdc – 5.2 –
VEE = –6.0 Vdc – 5.4 –
Drain Current, I22 (See Figure 3) 22 I22 mA
VEE = –2.0 Vdc – 3.0 –
VEE = –3.0 Vdc – 3.1 –
VEE = –5.0 Vdc – 3.3 –
VEE = –6.0 Vdc – 3.4 –
Drain Current, I19 (See Figure 3) 19 I19 mA
VEE = –2.0 Vdc – 1.8 –
VEE = –3.0 Vdc – 1.9 –
VEE = –5.0 Vdc – 1.9 –
VEE = –6.0 Vdc – 2.0 –
DATA SLICER (Input Voltage Referenced to VEE = –3.0 Vdc, no input signal; See Figure 15.)
Input Threshold Voltage (High Vin) 15 V15 1.0 1.1 1.2 Vdc
Output Current (Low Vin) 17 I17 – 1.7 – mA
Data Slicer Enabled (No Hold)
V15 > 1.1 Vdc
V18 = 0 Vdc
AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VEE = –3.0 Vdc, fRF = 130 MHz, fLO = 140.7 MHz, Figure 1 test
circuit, unless otherwise specified.)
Characteristic Pin Symbol Min Typ Max Unit
12 dB SINAD Sensitivity (See Figures 17, 23) 1, 14 – – –100 – dBm
fin = 144.45 MHz; fmod = 1.0 kHz; fdev = ±75 kHz
MIXER
Conversion Gain 1, 3 – – 22 – dB
Pin = –37 dBm (Figure 4)
Mixer Input Impedance 1, 2 Rp– 1.0 – kΩ
Single–Ended (Table 1) Cp– 4.0 – pF
Mixer Output Impedance 3 – – 330 – Ω
IF AMPLIFIER SECTION
IF RSSI Slope (Figure 6) 20 – 0.2 0.4 0.6 µA/dB
IF Gain (Figure 5) 5, 8 – – 39 – dB
Input Impedance 5 – – 1.4 – kΩ
Output Impedance 8 – – 290 – Ω
www.lansdale.comPage 2 of 21 Issue A
LANSDALE Semiconductor, Inc.
ML13156
AC ELECTRICAL CHARACTERISTICS (continued) (TA = 25°C, VEE = –3.0 Vdc, fRF = 130 MHz, fLO = 140.7 MHz, Figure 1 test
circuit, unless otherwise specified.)
Characteristic UnitMaxTypMinSymbolPin
LIMITING AMPLIFIER SECTION
Limiter RSSI Slope (Figure 7) 20 – 0.2 0.4 0.6 µA/dB
Limiter Gain – – – 55 – dB
Input Impedance 10 – – 1.4 – kΩ
CARRIER DETECT
Output Current – Carrier Detect (High Vin) 21 – – 0 – µA
Output Current – Carrier Detect (Low Vin) 21 – – 3.0 – mA
Input Threshold Voltage – Carrier Detect 20 – 0.9 1.2 1.4 Vdc
Input Voltage Referenced to VEE = –3.0 Vdc
Figure 1. Test Circuit
11
20
22
17
24
12
10
9
8
7
6
3
Bias
5.0 p
Data
Slicer
LIM Amp
IF Amp
Bias
23
21
1
2
5
Mixer
VEE
Mixer
Output
RF Input
130MHz
330
1.0 n
200
1:4
TR 1
(1)
IF Input
IF Output
4
Limiter
Input
50
330
50
1.0 n
VCC
VCC
1.0 n
1.0 n
1.0 n
13
14
15
16 1.0 n
1.0 n
1.0 n
1.0 n
50
100 k
100 k
1.0 n100 n
1.0
µ
100 n
1.0
µ
1.0
µ
H
100 n
150 p
(3)
Local
Oscillator
Input
140.7MHz
200m Vrms
Carrier
Detect
Data Slicer
Hold
VEE
A
A
A
A
A
VEE
VEE
Data Output
19
ML13156
RSSI
Output
+
NOTES: 1. TR 1 Coilcraft 1:4 impedance transformer.
2. VCC is DC Ground.
3. 1.5 µH variable shielded inductor:
Toko Part # 292SNS–T1373 or Equivalent.
SMA
V
+
18
www.lansdale.comPage 3 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
Pin, INPUT SIGNAL LEVEL (dBm)
–70
30
–65
40
4.0
–50
20.0
–90
25.0
1.0
6.5
LIMITER AMPLIFIER RSSI OUTPUT CURRENT ( A)
µ
IF AMPLIFIER GAIN (dB)
Pin, IF INPUT SIGNAL LEVEL (dBm)
I19 DRAIN CURRENTS (mA)
VEE, SUPPLY VOLTAGE (–Vdc)
IF AMPLIFIER RSSI CURRENT ( A)
µ
Pin, IF INPUT SIGNAL LEVEL (dBm)
MIXER GAIN (dB)
Pin, RF INPUT SIGNAL LEVEL (dBm)
Figure 2. Total Drain Current versus Supply
Voltage and Temperature Figure 3. Drain Currents versus Supply Voltage
Figure 4. Mixer Gain versus Input Signal Level
Figure 5. IF Amplifier Gain versus Input
Signal Level and Ambient Temperature
ITOTAL
TOTAL DRAIN CURRENT,
Figure 6. IF Amplifier RSSI Output Current versus
Input Signal Level and Ambient Temperature
VEE, SUPPLY VOLTAGE (–Vdc)
Figure 7. Limiter Amplifier RSSI Output Current
versus Input Signal Level and Temperature
6.0
5.5
5.0
4.5
4.0
3.5 2.0 3.0 4.0 5.0 6.0 7.0
55°C
25°C
–10°C
–40°C
(mA)
3.6
3.2
2.8
2.4
2.0
1.6
I22
1.0 2.0 3.0 4.0 5.0 6.0 7.0
I22
,
TA = 25°C
22.5
20.0
17.5
15.0
12.5
10.0 –80 –70 –60 –50 –40 –30 –20 –10
38
36
34
32
30
28
26 –60 –55 –50 –45 –40 –35 –30
17.5
15.0
12.5
10.0
7.5
5.0
2.5
0–40 –30 –20 –10 0 10
5.0
0–60 –50 –40 –30 –20 –10 0 10
25
20
15
10
TA = 85°C
VEE = –5.0 Vdc
f = 10.7 MHz
TA = 25°C
I19
–10°C
–40°C
55°C
25°C
–10°C
–40°C
85°C
TA = 25° to 85°C
–40°C
VEE = –5.0 Vdc
f = 10.7 MHz –10°C
VEE = – 5.0 Vdc
f = 10.7 MHz
TA = 25° to 85°C
www.lansdale.comPage 4 of 21 Issue A
LANSDALE Semiconductor, Inc.
ML13156
VCC1
L
Obase
O
emitter
VEE1
VCC2
IMdec1
IMdec2
LIM in
VEE2
4
24
23
22
9
11
12
10
19
1.0 k 1.0 k
12
RFin2
RFin1
330
3
Mix
Output 5
7
6
IF
dec1
IF
dec2
IFin
1.4 k
32 k
32 k
290
8
IF
out
400
µ
20
RSSI
Out
21
Carrier
Detect
Output
28
µ
17
16
18
64 k64 k
64 k
DS
Output
DSGnd
DSHold
DS in
15
16 k
Demod
14
13
Quad coil
5.0 p
Local Oscillator Mixer IF Amplifier RSSI Carrier Detect
Linear Amplifier Quadrature Detector
Data Slicer
Figure 8.
Figure 8. ML13156-6P Internal Circuit Schematic
www.lansdale.comPage 5 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
GENERAL
The ML13156 is a low power single conversion wideband FM
receiver incorporating a split IF. This device can be used as a single
conversion receiver or as the backend in digital FM systems such as
CT–2 and wide band data links with data rates up to 500 kbaud. It
contains a mixer, oscillator, signal strength meter drive, IF amplifi-
er, limiting IF, quadrature detector and a data slicer with a hold
function (refer to Figure 8, Simplified Internal Circuit Schematic).
CURRENT REGULATION
Temperature compensating voltage independent current regula-
tors are used throughout.
MIXER
The mixer is a double–balanced four quadrant multiplier and is
designed to work up to 500 MHz. It can be used in differential
or in single–ended mode by connecting the other input to the
positive supply rail.
Figure 4 shows the mixer gain and saturated output response as
a function of input signal drive. The circuit used to measure this
is shown in Figure 1. The linear gain of the mixer is approxi-
mately 22 dB. Figure 9 shows the mixer gain versus the IF out-
put frequency with the local oscillator of 150 MHz at 100
mVms LO drive level. The RF frequency is swept. The sensitivi-
ty of the IF output of the mixer is shown in Figure 10 for an RF
input drive of 10 mVrms at 140 MHz and IF at 10 MHz.
The single–ended parallel equivalent input impedance of the
mixer is Rp ~ 1.0 kΩand Cp ~ 4.0 pF (see Table 1 for details).
The buffered output of the mixer is internally loaded resulting in
an output impedance of 330 Ω.
LOCAL OSCILLATOR
The on–chip transistor operates with crystal and LC resonant
elements up to 220 MHz. Series resonant, overtone crystals are
used to achieve excellent local oscillator stability. 3rd overtone
crystals are used through about 65 to 70 MHz. Operation from
70 MHz up to 180 MHz is feasible using the on–chip transistor
with a 5th or 7th overtone crystal. To enhance operation using
an overtone crystal, the internal transistor’s bias is increased by
adding an external resistor from Pin 23 to VEE. –10 dBm of
local oscillator drive is needed to adequately drive the mixer
(Figure 10).
The oscillator configurations specified above, and two others
using an external transistor, are described in the application sec-
tion:
1) A 133 MHz oscillator multiplier using a 3rd overtone
crystal, and
2) A 307.8 to 309.3 MHz manually tuned, varactor
controlled local oscillator.
RSSI
The Received Signal Strength Indicator (RSSI) output is a cur-
rent proportional to the log of the received signal amplitude. The
RSSI current output is derived by summing the currents for the
IF and limiting amplifier stages. An external resistor at Pin 20
sets the voltage range or swing of the RSSI output voltage.
Linearity of the RSSI is optimized by using external ceramic or
crystal bandpass filters which have and insertion loss of 8.0 dB.
The RSSI circuit is designed to provide 70+ dB of dynamic
range with temperature compensation (see Figures 6 and 7
which show RSSI responses of the IF and Limiter amplifiers).
Variation in the RSSI output current with supply voltage is 5 ma
total delta (see Figure 11).
CARRIER DETECT
When the meter current flowing through the meter load resist-
ance reaches 1.2 Vdc above ground, the comparator flips, caus-
ing the carrier detect output to go high. Hysteresis can be
accomplished by adding a very large resistor for positive feed-
back between the output and the input of the comparator.
IF AMPLIFIER
The first IF amplifier section is composed of three differential
stages with the second and third stages contributing to the RSSI.
This section has internal dc feedback and external input decou-
pling for improved symmetry and stability. The total gain of the
IF amplifier block is approximately 39 dB at 10.7 MHz. Figure
5 shows the gain and saturated output response of the IF ampli-
fier over temperature, while Figure 12 shows the IF amplifier
gain as a function of the IF frequency.
The fixed internal input impedance is 1.4kΩ. It is designed for
application where a 455 kHz ceramic filter is used and no exter-
nal output matching is necessary since the filter requires a 1.4
kΩsource and load impedance.
For 10.7 Mhz ceramic filter applications, an external 430 Ω
resistor must be added in parallel to provide the equivalent load
impedance of 330 Ωthat is required by the filter; however, no
external matching is necessary at the input since the mixer out-
put matches the 330 Ωsource impedance of the filter. For 455
kHz applications, an external 1.1 kΩresistor must be added in
series with the mixer output to obtain the required matching
impedance of 1.4 kΩof the filter input resistance. Overall RSSI
linearity is dependent on having total midband attenuation of 12
dB (6.0 dB insertion loss plus 6.0 dB impedance matching loss)
for the filter. The output of the IF amplifier is buffered and the
impedance is 290 Ω.
LIMITER
The limiter section is similar to the IF amplifier section except
that four stages are used with the last three contributing to the
RSSI. The fixed internal input impedance is 1.4 kΩ. The total
gain of the limiting amplifier sections is approximately 55 dB.
This IF limiting amplifier section internally drives the quadra-
ture detector section.
CIRCUIT DESCRIPTION
www.lansdale.comPage 6 of 21 Issue A
LANSDALE Semiconductor, Inc.
ML13156
0.1
60
–5.0
1.0
40
0.1
20
IF AMPLIFIER GAIN (dB)
f, FREQUENCY (MHz)
MIXER IF OUTPUT LEVEL (dBm)
LO DRIVE (dBm)
VEE, SUPPLY VOLTAGE (–Vdc)
Figure 9. Mixer Gain versus IF Frequency
Figure 10. Mixer IF Output Level versus
Local Oscillator Input Level
MIXER GAIN (dB)
Figure 11. RSSI Output Current versus
Supply Voltage and RF Input Signal Level
fIF, IF FREQUENCY (MHz)
Figure 12. IF Amplifier Gain versus IF Frequency
15
10
5.0
0
–5.0 1.0 10 100
–10
–15
–20
–25
–30
–35
VEE = –3.0 Vdc
TA = 25°C
–50 –40 –30 –20 –10 0 10
35
30
25
20
15
10
2.0 3.0 4.0 5.0 6.0 7.0
50
40
30
20
10
01.0 10 100
–40
–45
fRF = 140 MHz; fLO = 150 MHz
RF Input Level = –27 dBm
(10 mVrms)
Rin = 50
Ω
; RO = 330
Ω
–20 dBm
–40 dBm
–60 dBm
–100 dBm
5.0
0
RSSI OUTPUT CURRENT ( A)
µ
I20 ,
Vin = 100
µ
V
Rin = 50
Ω
RO = 330
Ω
BW(3.0 dB) = 26.8 MHz
TA = 25°C
–80 dBm
1.0
400
Figure 13. Recovered Audio Output Voltage
versus Supply Voltage
VEE, SUPPLY VOLTAGE (–Vdc)
fmod = 1.0 kHz
fdev =
±
75 kHz
fRF = 140 MHz
RF Input Level = 1.0 mVrms
TA = 25°C
300
200
100
02.0 3.0 4.0 5.0 6.0 7.0
RECOVERED AUDIO OUTPUT (mVrms)V14 ,
Vin =
VEE = –3.0 Vdc
Vin = 1.0 mVrms (–47 dBm)
RO = 330
Ω
Rin = 50
Ω
BW(3.0 dB) = 21.7 MHz
fIF = fLO – fRF
fLO = 150 MHz
VLO = 100 mVrms
TA = 25°C
www.lansdale.comPage 7 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
QUADRATURE DETECTOR
The quadrature detector is a doubly balanced four quadrant
multiplier with an internal 5.0 pF quadrature capacitor to cou-
ple the IF signal to the external parallel RLC resonant circuit
that provides the 90 degree phase shift and drives the quadra-
ture detector. A single pin (Pin 13) provides for the external
LC parallel resonant network and the internal connection to
the quadrature detector.
The bandwidth of the detector allows for recovery of relative-
ly high data rate modulation. The recovered signal is convert-
ed from differential to single ended through a push–pull
NPN/PNP output stage. Variation in recovered audio output
voltage with supply voltage is very small (see Figure 13). The
output drive capability is approximately ±9.0 µA for a fre-
quency deviation of ±75 kHz and 1.0 kHz modulating fre-
quency (see Application Circuit)
DATA SLICER
The data slicer input (Pin 15) is self centering around 1.1 V
with clamping occurring at 1.1 ± 0.5 Vbe Vdc. It is designed
to square up the data signal. Figure 14 shows a detailed
schematic of the data slicer.
The Voltage Regulator sets up to 1.1 Vdc on the base of Q12,
the Differential Input Amplifier. There is a potential of 1.0
Vbe on the base–collector of transistor diode Q11 and 2.0
Vbe on the base–collector of Q10. This sets up a 1.5 Vbe
(~1.1 Vdc) on the node between the 36 kΩresistors which is
connected to the base of Q12. The differential output of the
data slicer Q12 and Q13 is converted to a single–ended out-
put by the Driver Circuit. Additional circuitry, not shown in
Figure 14, tends to keep the data slicer input centered at 1.1
Vdc as input signal levels vary.
The Input Diode Clamp Circuit provides the clamping at 1.0
Vbe (0.75 Vdc) and 2.0 Vbe (1.45 Vdc). Transistor diodes Q7
and Q8 are on , thus, providing a 2.0 Vbe potential at the base
of Q1. Also, the voltage regulator circuit provides a potential
of 2.0 Vbe on the base of Q3 and 1.0 Vbe on the emitter of
Q3 and Q2. When the data slicer input (Pin 15) is pulled up,
Q1 turns off; Q2 turns on, thereby clamping the input at 2.0
Vbe. On the other hand, when Pin 15 is pulled down, Q1
turns on; Q2 turns off, thereby clamping the input at 1.0 Vbe.
The recovered data signal from the quadrature detector is ac
coupled to the data slicer via an input coupling capacitor. The
size of the capacitor and the nature of the data signal deter-
mine how faithfully the data slicer shapes up the recovered
signal. The time constant is short for large peak to peak volt-
age swings or when there is a change in dc level at the detec-
tor output. For small signal or for continuous bits of the same
polarity which drift close to the threshold voltage, the time
constant is longer. When centered there is no input current
allowed, which is to say, that the input looks high in imped-
ance.
Another unique feature of the data slicer is that it responds to
various logic levels applied to the Data Slicer Hold Control
pin (Pin 18). Figure 15 illustrates how the input and output
currents under “no hold” condition relate to the input voltage.
Figure 16 shows how the input current and input voltage
relate to the both the “no hold” and “hold” condition.
The Hold control (Pin 18) does three separate tasks:
1) With Pin 18 at 1.0 Vbe or greater, the output is shut off
(sets high). Q19 turns on which shunts the base drive
from Q20, thereby turning the output off.
2) With Pin 18 at 2.0 Vbe or greater, internal clamping diodes
are open circuited and the comparator input is shut off and
effectively open circuited. This is accomplished by turning
off the current source to emitters of the input differential
amplifier, thus, the input differential amplifier is shut off.
3) When the input is shut off, it allows the input capacitor to
hold its charge during transmit to improve recovery at the
beginning of the next receive period. When it is turned on,
it allows for very fast charging of the input capacitor for
quick recovery of new tuning or data average. The above
features are very desirable in a TDD digital FM system.
www.lansdale.comPage 8 of 21 Issue A
LANSDALE Semiconductor, Inc.
ML13156
Figure 14. Data Slicer Circuit
64 k
9
15
19
18
16
17
VCC
VEE 64 k
64 k
16 k16 k
32 k
36 k
36 k
8.0 k8.0 k
Q10
Q8
Q17
Q18
Q19
Q16
Q20
Q12 Q13
Q4 Q9 Q11
Q2
Q1
Q3
Q5 Q7
Q6
Q14 Q15
DS Gnd
DS Hold
Data Out
DS In
Input Diode
Clamp Circuit
(Q1 to Q9)
Voltage
Regulator
(Q10, Q11)
Differential
Input Amplifier
(Q12, Q13)
Driver and
Output Circuit
(Q14, Q20)
150
0.6
0.5
V15, INPUT VOLTAGE (Vdc)
Figure 15. Data Slicer Input/Output Currents
versus Input Voltage
V15, INPUT VOLTAGE (Vdc)
Figure 16. Data Slicer Input Current
versus Input Voltage
VEE = –3.0 Vdc
V18 = 0 Vdc
(No Hold)
0.3
0.1
–0.1
–0.3
–0.5 0.8 1.0 1.2
100
50
0
–50
–100
VEE = –3.0 Vdc
–1.0 –0.5 0 0.5 1.0 1.5 2.0
No Hold
V18 = 0 Vdc
1.4 1.6 1.8
2.5
1.5
0.5
–0.5
–1.5
–2.5
Output Current
(I17)
INPUT CURRENT (mA)I15 ,
OUTPUT CURRENT (mA)I17 ,
µ
Hold
V18 ≥1
INPUT CURRENT ( A)I15 ,
2.5 3.0
No Hold
Hold
Input Current
(I15)
Legacy Applications Information
www.lansdale.comPage 9 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
Figure 17. MC13156DW Application Circuit
1.5
µ
150 p
(3)
NOTES: 1. 0.1 µH Variable Shielded Inductor: Coilcraft part # M1283–A or equivalent.
2. 10.7 MHz Ceramic Filter: Toko part # SK107M5–A0–10X or Murata Erie part # SFE10.7MHY–A.
3. 1.5 µH Variable Shielded Inductor: Toko part # 292SNS–T1373.
4. 3rd Overtone, Series Resonant, 25 PPM Crystal at 44.585 MHz.
5. 0.814 µH Variable Shielded Inductor: Coilcraft part # 143–18J12S.
6. 0.146 µH Variable Inductor: Coilcraft part # 146–04J08.
Data Slicer
Hold
430
+
+
Data
Output
RSSI
Output
Carrier
Detect
133.755 MHz
Osc/Tripler
50 p7.5 p
144.455 MHz
RF Input
VCC
VCC
1.0
µ
430
47 k
470
5.6 k
15 k
100 p
1.0
µ
0.146
µ
(6)
SMA
(2) 10.7 MHz
Ceramic
Filter
(2) 10.7 MHz
Ceramic
Filter
10 n
10 n
10 n
10 n
10 n
(1)
0.1
µ
100 k
10 k
100 k
68 p
43 p
10 n
100 k
10 n
10 n
10 k
100 n
180 p
MMBR5179
(4) 3rd O.T.
XTAL
1.0 k
(5) 0.82
µ
11
20
22
17
24
12
10
9
8
7
6
3
Bias
5.0 p
Data
Slicer
LIM Amp
IF Amp
Bias
23
21
1
5
Mixer
VEE
4VCC
VCC
14
15
16
VEE
VEE
19
ML13156
18
2
13
Legacy Applications Information
www.lansdale.comPage 10 of 21 Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
www.lansdale.comPage 11 of 21 Issue A
LANSDALE Semiconductor, Inc.
ML13156
Table 1. Mixer Input Impedance Data
(Single–ended configuration, VCC = 3.0 Vdc, local oscillator drive = 100 mVrms)
Frequency
(MHz)
Series Equivalent
Complex Impedance
(R + jX)
(Ω)
Parallel
Resistance
Rp
(Ω)
Parallel
Capacitance
Cp
(pF)
90 190 – j380 950 4.7
100 160 – j360 970 4.4
110 130 – j340 1020 4.2
120 110 – j320 1040 4.2
130 97 – j300 1030 4.0
140 82 – j280 1040 4.0
150 71 – j270 1100 4.0
160 59 – j260 1200 3.9
170 52 – j240 1160 3.9
180 44 – j230 1250 3.8
190 38 – j220 1300 3.8
COMPONENT SELECTION
The evaluation PC board is designed to accommodate specific
components, while also being versatile enough to use components
from various manufacturers and coil types. Figures 18 and 19 show
the placement for the components specified in the application cir-
cuit (Figure 17). The application circuit schematic specifies particu-
lar components that were used to achieve the results shown in the
typical curves and tables but equivalent components should give
similar results.
INPUT MATCHING NETWORKS.COMPONENTS
The input matching circuit shown in the application circuit
schematic is passive high pass network which offers effective image
rejection when the local oscillator is below the RF input frequency.
Silver mica capacitors are used for their high Q and tight tolerance.
The PC board is not dedicated to any particular input matching net-
work topology; space is provided for the designer to breadboard as
desired.
Alternate matching networks using 4:1 surface mount transformers
or BALUNs provide satisfactory performance. The 12 dB SINAD
sensitivity using the above matching networks is typically –100
dBm for fmod = 1.0 kHz and fdev = ±75 kHz at fIN = 144.45
MHz and fOSC = 133.75 MHz (see Figure 23).
It is desirable to use a SAW filter before the mixer to provide addi-
tional selectivity and adjacent channel rejection and improved sen-
sitivity. The SAW filter should be designed to interface with the
mixer input impedance of approximately 1.0 kΩ. Table 1 displays
the series equivalent single–ended mixer input impedance.
LOCAL OSCILLATORS
VHF APPLICATIONS – The local oscillator circuit shown in the
application schematic utilizes a third overtone crystal and an RF
transistor. Selecting a transistor having good phase noise perform-
ance is important; a mandatory criteria is for the device to have
good linearity of beta over several decades of collector current. In
other words, if the low current beta is suppressed, it will not offer
good 1/f noise performance. A third overtone series resonant crystal
having at least 25 ppm tolerance over the operating temperature is
recommended. The local oscillator is an impedance inversion third
overtone Colpitts network and harmonic generator. In this circuit a
560 to 1.0 kΩresistor shunts the crystal to ensure that it operates in
its overtone mode; thus, a blocking capacitor is needed to eliminate
the dc path to ground. The resulting parallel LC network should
“free–run” near the crystal frequency if a short to ground is placed
across the crystal. To provide sufficient output loading at the collec-
tor, a high Q variable inductor is used that is tuned to self resonate
at the 3rd harmonic of the overtone crystal frequency.
The on–chip grounded collector transistor may be used for HF and
VHF local oscillator with higher order overtone crystals. Figure 18
shows a 5th overtone oscillator at 93.3 MHz and Figure 19 shows a
7th overtone oscillator at 148.3 MHz. Both circuits use a Butler
overtone oscillator configuration. The amplifier is an emitter fol-
lower. The crystal is driven from the emitter and is coupled to the
high impedance base through a capacitive tap network. Operation at
the desired overtone frequency is ensured by the parallel resonant
circuit formed by the variable inductor and the tap transistor and
PC board. The variable inductor specified in the schematic could be
replaced with a high tolerance, high Q ceramic or air wound sur-
face mount component. if the other component have good toler-
ance. A variable inductor provides an adjustment for gain and fre-
quency of the resonant tank ensuring lock up and start up of the
crystal oscillator. The overtone crystal is chosen with ESR of typi-
cally 80 Ωand 120 Ωmaximum; if the resistive loss in the crystal
is too high, the performance of the oscillator may be impacted by
lower gain margins.
Legacy Applications Information
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LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
www.lansdale.comPage 13 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
Figure 18. MC13156DW Application Circuit
fRF = 104 MHz; fLO = 93.30 MHz
5th Overtone Crystal Oscillator
NOTES: 1. 0.1 µH Variable Shielded Inductor: Coilcraft part # M1283–A or equivalent.
2. Capacitors are Silver Mica.
3. 5th Overtone, Series Resonant, 25 PPM Crystal at 93.300 MHz.
4. 0.135 µH Variable Shielded Inductor: Coilcraft part # 146–05J08S or equivalent.
5th OT
XTAL
+
To Filter
120 p
(2)
10 p
RF Input
1.0
µ
SMA
10 n
(1)
0.1
µ
27 p
30 p
4.7 k
(4)
0.135
µ
H
22
24
3
23
1
Mixer
VEE
2
VCC
10 n
1.0
µ
H
33
104 MHz
3.0 p (3)
A series LC network to ground (which is VCC) is comprised of the
inductance of the base lead of the on–chip transistor and PC board
traces and tap capacitors. Parasitic oscillations often occur in the
200 to 800 MHz range. A small resistor is placed in series with the
base (Pin 24) to cancel the negative resistance associated with this
undesired mode of oscillation. Since the base input impedance is so
large a small resistor in the range of 27 to 68 Ωhas very little effect
on the desired Butler mode of oscillation.
The crystal parallel capacitance, Co, provides a feedback path that
is low enough in reactance at frequencies of 5th overtone or higher
to cause trouble. Cohas little effect near resonance because of the
low impedance of the crystal motional arm (Rm–Lm–Cm). As the
tunable inductor which forms the resonant tank with the tap capaci-
tors is tuned off the crystal resonant frequency, it may be difficult
to tell if the oscillation is under crystal control. Frequency jumps
may occur as the inductor is tuned. In order to eliminate this behav-
ior an inductor (Lo) is placed in parallel with the crystal. Lois cho-
sen to resonant with the crystal parallel capacitance (Co) at the
desired operation frequency. The inductor provides a feedback path
at frequencies well below resonance; however, the parallel tank net-
work of the tap capacitors and tunable inductor prevent oscillation
at these frequencies.
UHF APPLICATION
Figure 20 shows a 318.5 to 320 MHz receiver which drives the
mixer with an external varactor controlled (307.8 to 309.3 MHz)
LC oscillator using an MPS901 (RF low power transistor in a
TO–92 plastic package; also MMBR901 is available in a SOT–23
surface mount package). With the 50 kΩ10 turn potentiomenter
this oscillator is tunable over a range of approximately 1.5 MHz.
The MMBV909L is a low voltage varactor suitable for UHF appli-
cations; it is a dual back–to–back varactor in a SOT–23 package.
The input matching network uses a 1:4 impedance matching trans-
former (Recommended sources are Mini–Circuits and Coilcraft).
Using the same IF ceramic filters and quadrature detector circuit as
specified in the applications circuit in Figure 17, the 12 dB SINAD
performance is –95 dBm for a fmod = 1.0 kHz sinusoidal wave-
form and fdev ±40 kHz.
This circuit is breadboarded using the evaluation PC bard shown in
Figures 32 and 33. The RF ground is VCC and path lengths are
minimized. High quality surface mount components were used
except where specified. The absolute values of the components
used will vary with layout placement and component parasitics.
RSSI RESPONSE
Figure 24 shows the full RSSI response in the application circuit.
The 10.7 MHz, 110 kHz wide bandpass ceramic filters (recom-
mended sources are TOKO part # SK107M5–AO–10X or Murata
Erie SFE10.7MHY–A) provide the correct band pass insertion loss
to linearize the curve between the limiter and IF portions of RSSI.
Figure 23 shows that limiting occurs at an input of –100 dBm. As
shown in Figure 24, the RSSI output linear from –100 dBm to –30
dBm.
The RSSI rise and fall times for various RF input signal levels and
R20 values are measures at Pin 20 without 10 nF filter capacitor. A
10 kHz square wave pulses the RF input signal on and off. Figure
25 shows that the rise and fall times are short enough to recover
greater than 10 kHz ASK data; with a wider IF band pass filters
data rates up to 50 kHz may be achieved. The circuit used is the
application circuit in Figure 17 with no RSSI output filter capacitor.
Legacy Applications Information
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LANSDALE Semiconductor, Inc.
ML13156
Figure 19. MC13156DW Application Circuit
fRF = 159 MHz; fLO = 148.30 MHz
7th Overtone Crystal Oscillator
NOTES: 1. 0.08 µH Variable Shielded Inductor: Toko part # 292SNS–T1365Z or equivalent.
2. Capacitors are Silver Mica.
3. 7th Overtone, Series Resonant, 25 PPM Crystal at 148.300 MHz.
4. 76 nH Variable Shielded Inductor: Coilcraft part # 150≠03J08S or equivalent.
7th OT
XTAL
To IF Filter
50 p
(2)
5.0 p
RF Input
SMA
10 n
(1)
0.08
µ
H
27 p
47 p
4.7 k
(4)
76 nH
22
24
3
23
1
Mixer
VEE
2
VCC
10 n
0.22
µ
H
33
Figure 20. MC13156DW Varactor Controlled LC Oscillator
NOTES: 1. 1:4 Impedance Transformer: Mini±Circuits.
2. 50 k Potentiometer, 10 turns.
3. Spring Coil; Coilcraft A05T.
4. Dual Varactor in SOT–23 Package.
5. All other components are surface mount components.
6. Ferrite beads through loop of 24 AWG wire.
12 k
307.8–309.3 MHz
LC Varactor
Controlled Oscillator
MPS901
4.7 k
1.0 n
318.5 to
320 MHz
SMA
1.8 k
22
24
3
23
1
Mixer
VEE
2
20 p
24 p
VCC = 3.3 Vdc (Reg)
+
1.0
µ
RF Input
(1)
1:4 Transformer
24 p
6.8 p
VVCO
(2)
50 k 47 k
(4)
MMBV909L
470
+
1.0
µ
0.1
µ
1.0 M
159 MHz
(6)
(3)
18.5 nH
(3)
Legacy Applications Information
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ML13156
LANSDALE Semiconductor, Inc.
Figure 21. MC13156DW Application Circuit at 45 MHz
NOTES: 1. 0.33 µH Variable Shielded Inductor: Coilcraft part # 7M3–331 or equivalent.
2. 455 kHz Ceramic Filter: Murata Erie part # SFG455A3.
3. 455 kHz Quadrature Tank: Toko part # 7MC8128Z.
4. 3rd Overtone, Series Resonant, 25 PPM Crystal at 44.540 MHz.
5. 0.416 µH Variable Shielded Inductor: Coilcraft part # 143–10J12S.
6. 1.8 µH Molded Inductor.
680
µ
H
180 p
(3)
Data Slicer
Hold
+
+
Data
Output
RSSI
Output
Carrier
Detect
1.2 k
33 p
45 Hz
RF Input
VCC
VCC = 2.0 to 5.0 Vdc
1.0
µ
47 k
56 p
10 n
1.0
µ
SMA
(2) 455 kHz
Ceramic
Filter
(2) 455 kHz
Ceramic
Filter
0.1
µ
10 n
(1)
0.33
µ
H
100 k
27 k
100 k
100 k
10 n
10 n
10 k
100 n
(4) 3rd OT
XTAL
470 k
1.8
µ
H
11
20
22
17
24
12
10
9
8
7
6
3
Bias
5.0 p
Data
Slicer
LIM Amp
IF Amp
Bias 21
1
5
Mixer
VEE
4VCC
VCC
14
15
16
VEE
VEE
19
18
2
13
0.1
µ
180 p
1.2 k
0.1
µ
0.1
µ
1.0 n
Audio To
C–Message
Filter and
Amp.
39 p 10 k
23
10 n
44.545
MHz
(5) 0.416
µ
H
(6)
45 MHZ NARROWBAND RECEIVER
The above application examples utilize a 10.7 MHz IF. In this sec-
tion a narrowband receiver with a 455 kHz IF will be described.
Figure 21 shows a full schematic of a 45 MHz reciever that uses a
3rd overtone crystal with the on–chip oscillator transistor. The
oscillator configuration is similar to the one used in Figure 17; it is
called an impedance inversion Colpitts. A 44.545 Mhz 3rd over-
tone, series resonant crystal is used to achieve an IF frequency at
455 kHz. The ceramic IF filters selected are Murata Erie part #
SFG455A3. 1.2 kΩchip resistors are used in series with the filters
to achieve the terminating resistance of 1.4 kΩto the filter. The IF
decoupling is very important; 0.1 µF chip capacitors are used at
Pins 6, 7, 11 and 12. The quadrature detector tank circuit uses a
455 kHz quadrature tank from Toko.
The 12 dB SINAD performance is –109 dBm for a fmod = 1.0 kHz
and a fdev = ±4.0 kHz. The RSSI dynamic range is approximately
80 db of linear range (see Figure 22).
RECEIVER DESIGN CONSIDERATIONS
The curves of signal levels at various portions of the application
receiver with respect to RF input level are shown in Figure 26. This
information helps determine the network topology and gain blocks
required ahead of the MC13156 to achieve the desired sensitivity
and dynamic range of the receiver system. In the application circuit
the input third order intercept (IP3) performance of the system is
approximately –25 dBm (see Figure 27).
Legacy Applications Information
www.lansdale.comPage 16 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
–100
10
S + N, N (dB)
RF INPUT SIGNAL (dBm)
VCC = 5.0 Vdc
fdev =
±
75 kHz
fmod = 1.0 kHz
fin = 144.45 MHz
(See Figure 17)
0
–10
–20
–30
–40
–90 –80 –70
–50 –60 –50 –40 –30 –20
–110
S+N
N
tr@ 22 k
tf @ 22 k
tr@ 47 k
tf @ 47 k
tr@ 100 k
tf@ 100 k
–120
1.8
RSSI OUTPUT VOLTAGE (Vdc)
Figure 22. RSSI Output Voltage
versus Input Signal Level
SIGNAL INPUT LEVEL (dBm)
1.6
1.4
1.2
1.0
0.8
–100 –80
0.4 –60 –40 20
1.4
RSSI OUTPUT VOLTAGE (Vdc)
SIGNAL INPUT LEVEL (dBm)
Figure 23. S + N/N versus RF Input Signal Level
1.2
1.0
0.8
0.6
0.4
0.2
–120 –100 –80 –60 –40 –20 0
VCC = 5.0 Vdc
fc = 144.455 MHz
fLO = 133.755 MHz
Low Loss 10.7 MHz
Ceramic Filter
(See Figure 17)
fRF = 45.00 MHz
VCC = 2.0 Vdc
12 dB SINAD @ –109 dBm
(0.8
µ
Vrms)
(See Figure 21)
35
t , ,
Figure 24. RSSI Output Voltage
versus Input Signal Level
RF INPUT SIGNAL LEVEL (dBm)
30
25
20
15
10
0–20
0–40 –60 –80
0.6
–20 0
5.0
rf
µ
Figure 25. RSSI Output Rise and Fall Times
versus RF Input Signal Level
RSSI RISE AND FALL TIMES ( s)t
–100
10
–100
0
MIXER IF OUTPUT LEVEL (dBm)
RF INPUT POWER (dBm)RF INPUT SIGNAL LEVEL (dBm)
Figure 26. Signal Levels versus
RF Input Signal Level
Figure 27. 1.0 dB Compression Pt. and Input
Third Order Intercept Pt. versus Input Power
–10
–20
–30
–40
–50
–60
–90 –80 –70 –60 –50 –40
0
–10
–20
–30
–40
–50
–80 –60 –40
IF Output
Limiter Input
–70
POWER (dBm)
–30
LO Level = –2.0 dBm
(See Figure 17)
–60
–70 –20 0
1.0 dB Comp. Pt.
= –37 dBm
VCC = 5.0 Vdc
fRF1 = 144.4 MHz
fRF2 = 144.5 MHz
fLO = 133.75 MHz
PLO = –2.0 dBm
(See Figure 17)
IP3 = –25 dBm
Legacy Applications Information
www.lansdale.comPage 17 of 21 Issue A
DESCRIPTION
The test setup shown in Figure 29 is configured so that the function
generator supplies a 100 kHz clock source to the bit error rate
tester. This device generates and receives a repeating data pattern
and drives a 5 pole baseband data filter. The filter effectively
reduces harmonic content of the base band data which is used to
modulate the RF generator which is running at 144.45 MHz.
Following processing of the signal by the receiver (ML13156), the
recovered baseband sinewave (data) is AC coupled to the data
slicer. The data slicer is essentially an auto–threshold comparator
which tracks the zero crossing of the incoming sinewave and pro-
vides logic level data at its output. Data errors associated with the
recovered data are collected by the bit error rate receiver and dis-
played.
Bit error rate versus RF signal input level and IF filter bandwidth
are shown in Figure 28. The bit error rate data was taken under the
following test conditions:
• Data rate = 100kbps
• Filter cutoff frequency set to 39% of the data rate or 39 kHz.
• Filter type is a 5 pole equal–ripple with 0.5° phase error.
• VCC = 4.0 Vdc
• Frequency deviation = ±32 kHz.
EVALUATION PC BOARD
The evaluation PCB is very versatile and is intended to be used
across the entire useful frequency range of this device. The center
section of the board provides an area for attaching all SMT compo-
nents to the component ground side (see Figures 32 and 33).
Additionally, the peripheral area surrounding the RF core provides
pads to add supporting and interface circuitry as a particular appli-
cation dictates
ML13156
LANSDALE Semiconductor, Inc.
BER TESTING AND PERORMANCE
–90
Figure 28. Bit Error Rate versus RF
Input Signal Level and IF Bandpass Filter
RF INPUT SIGNAL LEVEL (dBm)
–85 –80 –75 –70
BER, BIT ERROR RATE
10 –1
10 –5
10 –7
10 –3
IF Filter BW
110 kHz
IF Filter BW
230 kHz
VCC = 4.0 Vdc
Data Pattern = 2E09 Prbs NRZ
Baseband Filter fc = 50 kHz
fdev =
±
32 kHz
www.lansdale.comPage 18 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
Figure 29. Bit Error Rate Test Setup
Function Generator
Clock
Out
Gen
Clock
Input
Rcr
Clock
Input
Rcr
Data
Input
Generator
Output
Bit Error Rate Tester RF Generator
Modulation
Input
RF
Output
5 Pole
Bandpass
Filter
MC13156
UUT
Data Slicer
Output
Mixer
Input
Wavetek Model No. 164 HP3780A or Equivalent HP8640B
Legacy Applications Information
www.lansdale.comPage 19 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
(ML13156-8P)
PLASTIC QFP PACKAGE
CASE 873–01
ISSUE A
OUTLINE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
U
B
L
DETAIL A
L
–A–
32
25
24
16
17
18
9
V
S
A–B
M
0.20 (0.008) D
S
C
S
A–B
M
0.20 (0.008) D
S
H
A–B0.05 (0.002)
S
A–B
M
0.20 (0.008) D
S
C
A–B0.05 (0.002)
S
A–B
M
0.20 (0.008) D
S
H
–D–
A
S
–B–
–C–
SEATING
PLANE
–H–
DATUM
PLANE
M
G
DETAIL C
M
H
CE
0.01 (0.004)
–H–
DATUM
PLANE
T
DETAIL C
R
KQ
X
DETAIL A
B
B
P
–A–, –B–, –D–
S
A–B
M
0.20 (0.008) D
S
C
J
F
N
D
SECTION B–B
BASE
METAL
VIEW ROTATED 90 CLOCKWISE
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A6.95 0.274 0.280
B6.95 7.10 0.274 0.280
C1.40 1.60 0.055 0.063
D0.273 0.373 0.010 0.015
E1.30 1.50 0.051 0.059
F0.273 ––– 0.010 –––
G0.80 BSC 0.031 BSC
H––– 0.20 ––– 0.008
J0.119 0.197 0.005 0.008
K0.33 0.57 0.013 0.022
L5.6 REF 0.220 REF
M6° 8° 6° 8°
N0.119 0.135 0.005 0.005
P0.40 BSC 0.016 BSC
Q5° 10° 5° 10°
R0.15 0.25 0.006 0.010
S8.85 9.15 0.348 0.360
T0.15 0.25 0.006 0.010
U5° 11° 5° 11°
V8.85 9.15 0.348 0.360
X1.00 REF 0.039 REF
7.10
www.lansdale.comPage 20 of 21 Issue A
ML13156
LANSDALE Semiconductor, Inc.
(ML13156-6P)
PLASTIC PACKAGE
CASE 751E–04
(SO–24L)
ISSUE E
OUTLINE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P12X
D24X
12
1324
1
M
0.010 (0.25) B
M
S
A
M
0.010 (0.25) B
S
T
–T–
G
22X
SEATING
PLANE
K
C
RX 45°
M
F
J
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A15.25 15.54 0.601 0.612
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.41 0.90 0.016 0.035
G1.27 BSC 0.050 BSC
J0.23 0.32 0.009 0.013
K0.13 0.29 0.005 0.011
M0° 8° 0° 8°
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
www.lansdale.comPage 21 of 21 Issue A
