TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Available in 5-V, 4.85-V, 3.3-V, 3.0-V, and
2.5-V Fixed-Output and Adjustable Versions
D
Dropout Voltage <85 mV Max at
IO = 100 mA (TPS7250)
D
Low Quiescent Current, Independent of
Load, 180 µA Typ
D
8-Pin SOIC and 8-Pin TSSOP Package
D
Output Regulated to ±2% Over Full
Operating Range for Fixed-Output Versions
D
Extremely Low Sleep-State Current,
0.5 µA Max
D
Power-Good (PG) Status Output
description
The TPS72xx family of low-dropout (LDO) voltage
regulators offers the benefits of low-dropout
voltage, micropower operation, and miniaturized
packaging. These regulators feature extremely
low dropout voltages and quiescent currents
compared to conventional LDO regulators.
Offered in small-outline integrated-circuit (SOIC)
packages and 8-terminal thin shrink small-outline
(TSSOP), the TPS72xx series devices are ideal
for cost-sensitive designs and for designs where
board space is at a premium.
A combination of new circuit design and process
innovation has enabled the usual pnp pass
transistor to be replaced by a PMOS device.
Because the PMOS pass element behaves as a
low-value resistor , the dropout voltage is very low
– maximum of 85 mV at 100 mA of load current
(TPS7250) – and is directly proportional to the
load current (see Figure 1). Since the PMOS pass
element is a voltage-driven device, the quiescent current is very low (300 µA maximum) and is stable over the
entire range of output load current (0 mA to 250 mA). Intended for use in portable systems such as laptops and
cellular phones, the low-dropout voltage and micropower operation result in a significant increase in system
battery operating life.
The TPS72xx also features a logic-enabled sleep mode to shut down the regulator , reducing quiescent current
to 0.5 µA maximum at TJ = 25°C. Other features include a power-good function that reports low output voltage
and may be used to implement a power-on reset or a low-battery indicator.
The TPS72xx is offered in 2.5-V, 3-V , 3.3-V, 4.85-V , and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for adjustable version).
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
SENSE†/FB‡
RESET/PG
GND
EN
OUT
OUT
IN
IN
D, P, OR PW PACKAGE
(TOP VIEW)
†SENSE – Fixed voltage options only
(TPS7225, TPS7230, TPS7233, TPS7248,
and TPS7250)
‡FB – Adjustable version only (TPS7201)
Figure 1. Typical Dropout Voltage Versus
Output Current
200
00 50 100 150
– Dropout Voltage – mV
400
200 250
100
300
VDO
IO – Output Current – mA
TPS7233
TPS7248
TPS7250
TA = 25°C
TPS7230
TPS7225
500
600
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
TJ
OUTPUT VOLTAGE
(V) PACKAGED DEVICES CHIP FORM
T
JMIN TYP MAX SMALL OUTLINE
(D) PDIP
(P) TSSOP
(PW) (Y)
4.9 5 5.1 TPS7250QD TPS7250QP TPS7250QPWR TPS7250Y
4.75 4.85 4.95 TPS7248QD TPS7248QP TPS7248QPWR TPS7248Y
3.23 3.3 3.37 TPS7233QD TPS7233QP TPS7233QPWR TPS7233Y
–55°C to 150°C2.94 3 3.06 TPS7230QD TPS7230QP TPS7230QPWR TPS7230Y
2.45 2.5 2.55 TPS7225QD TPS7225QP TPS7225QPWR TPS7225Y
Adjustable
1.2 V to 9.75 V TPS7201QD TPS7201QP TPS7201QPWR TPS7201Y
The D package is available taped and reeled. Add R suffix to device type (e.g., TPS7250QDR). The PW package is only available left-end
taped and reeled. The TPS7201Q is programmable using an external resistor divider (see application information). The chip form is tested
at 25°C.
‡TPS7225Q, TPS7230Q, TPS7233Q, TPS7248Q, TPS7250Q (fixed-voltage
options)
NOTE A: Capacitor selection is nontrivial. See application information section
for details.
SENSE
PG
OUT
OUT
6
5
4
IN
IN
EN
GND
3
2
1
7
8
VI
0.1 µF
PG
CSR = 1 Ω
VO
10 µF
+
TPS72xx‡
CO
(see Note A)
250 kΩ
Figure 2. Typical Application Configuration
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS72xx chip information
These chips, when properly assembled, display characteristics similar to the TPS72xxQ. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
(6)
(4)
(3)
(7)
(2)
(1)
GND
FB
ĕ
OUT
PG
IN
EN TPS72xx
57
69
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
(6)
(7)
(2)
(5) (4)
(3)
(1)
BONDING PAD ASSIGNMENTS SENSE
Ĕ
(5)
NOTE A. For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to the SENSE-pin
connection discussion in the application
information section of this data sheet.
7654
1
23†Fixed-voltage options only (TPS7225, TPS7230,
TPS7233, TPS7248, and TPS7250)
‡Adjustable version only (TPS7201)
functional block diagram
_
+
Vref = 1.188 V
OUT
SENSE/FB
EN
IN
GND
R1
R2
PG
_
+
TPS7201
TPS7225
TPS7230
TPS7233
TPS7248
TPS7250
DEVICE UNITR1 R2
0
257
357
420
726
756
∞
233
233
233
233
233
Ω
kΩ
kΩ
kΩ
kΩ
kΩ
RESISTOR DIVIDER OPTIONS
§Switch positions are shown with EN low (active).
For most applications, SENSE should be externally connected to OUT as close as possible to the device.
For other implementations, refer to the SENSE-pin connection discussion in application information section.
NOTE A: Resistors are nominal values only.
1.12 V
§§§
MOS transistors
Bilpolar transistors
Diodes
Capacitors
Resistors
COMPONENT COUNT
108
41
4
15
75
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Ĕ
Input voltage range
ĕ
, VI, PG, SENSE, EN –0.3 V to 11 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Tables 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
‡All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Note 1 and Figure 3)
PACKAGE
T
A
≤ 25°CDERATING FACTOR T
A
= 70°C T
A
= 85°C T
A
= 125°C
PACKAGE
A
POWER RATING ABOVE TA = 25°C
A
POWER RATING
A
POWER RATING
A
POWER RATING
D
P
725 mW
1175 mW
5.8 mW/°C
8 74 mW/
°
C
464 mW
782 mW
377 mW
650 mW
145 mW
301 mW
P
PW
1175
mW
525 mW
8
.
74
mW/°C
4.2 mW/°C
782
mW
336 mW
650
mW
273 mW
301
mW
105 mW
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Note 1 and Figure 4)
PACKAGE
T
C
≤ 25°CDERATING FACTOR T
C
= 70°C T
C
= 85°C T
C
= 125°C
PACKAGE
C
POWER RATING ABOVE TC = 25°C
C
POWER RATING
C
POWER RATING
C
POWER RATING
D
P
2063 mW
2738 mW
16.5 mW/°C
20 49 mW/
°
C
1320 mW
1816 mW
1073 mW
1508 mW
413 mW
689 mW
P
PW
2738
mW
2900 mW
20
.
49
mW/°C
23.2 mW/°C
1816
mW
1856 mW
1508
mW
1508 mW
689
mW
580 mW
NOTE 1: Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute
maximum of 150°C. For guidelines on maintaining junction temperature within the recommended operating range,
see application information section.
Figure 3
600
400
200
025 50 75 100
800
1000
1200
125 150
1100
900
700
500
300
100
– Maximum Continuous Dissipation – mW
MAXIMUM CONTINUOUS DISSIPATION
vs
FREE-AIR TEMPERATURE
PD
TA – Free-Air Temperature – °C
D Package
RθJA = 172°C/W
PW Package
RθJA = 238°C/W
P Package
RθJA = 114.4°C/W
Figure 4
– Maximum Continuous Dissipation – mW
MAXIMUM CONTINUOUS DISSIPATION
vs
CASE TEMPERATURE
PD
TC – Case Temperature – °C
1500
1000
500
025 50 75 100
2000
2500
3000
125 150
D Package
RθJC = 60.6°C/W
PW Package
RθJC = 43.1°C/W
P Package
RθJC = 48.8°C/W
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
†
TPS7201Q 3 10
†
TPS7225Q 3.65 10
In
p
ut voltage VI†
TPS7230Q 3.96 10
V
Inp
u
t
v
oltage
,
V
I
†
TPS7233Q 3.98 10
V
TPS7248Q 5.24 10
TPS7250Q 5.41 10
High-level input voltage at EN, VIH 2 V
Low-level input voltage at EN, VIL 0.5 V
Output current, IO0 250 mA
Operating virtual junction temperature, TJ–40 125 °C
†Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the
maximum specified load range. Since dropout voltage is a function of output current,
the usable range can be extended for lighter loads
. To
calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:
VI(min)
+
VO(max)
)
VDO(max load)
Because the TPS7201 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for
calculating VDO from rDS(on) is given in Note 3 under the TPS7201 electrical characteristics table. The minimum value of 3 V is the absolute
lower limit for the recommended input-voltage range for the TPS7201.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, IO = 10 mA, EN = 0 V , CO = 4.7 µF (CSR† = 1 Ω), SENSE/FB shorted to OUT
(unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS72xxQ
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
Ground current (active mode)
EN ≤ 0.5 V
,
V
I
= V
O
+ 1 V
,
25°C 180 225
Gro
u
nd
c
u
rrent
(acti
v
e
mode)
EN
≤
0.5
V,
0 mA ≤ IO ≤ 250 mA
VI
VO
+
1
V,
–40°C to 125°C 325 µ
In
p
ut current (standby mode)
EN V
3V≤V≤10 V
25°C 0.5
Inp
u
t
c
u
rrent
(standb
y
mode)
EN
=
V
I,
3
V
≤
V
I
≤
10
V
–40°C to 125°C 1 µ
Out
p
ut current limit threshold
VO=0V
VI=10V
25°C 0.6 1
O
u
tp
u
t
c
u
rrent
limit
threshold
V
O =
0
V
V
I =
10
V
–40°C to 125°C 1.5
Pass-element leakage current in
EN VI
3V≤VI≤10 V
25°C 0.5
g
standby mode
EN
=
V
I,
3
V
≤
V
I
≤
10
V
–40°C to 125°C 1 µ
PG leakage current
VPG =10V
Normal o
p
eration
25°C 0.5
PG
l
ea
k
age curren
t
V
PG =
10
V
,
Normal
operation
–40°C to 125°C 0.5 µ
Output voltage temperature coefficient –40°C to 125°C 31 75 ppm/°C
Thermal shutdown junction temperature 165 °C
EN logic high (standby mode)
3 V ≤ VI ≤ 6 V
40
°
Cto125
°
C
2
EN
l
og
i
c
hi
g
h
(
s
t
an
db
y mo
d
e
)
6 V ≤ VI ≤ 10 V –
40°C
to
125°C
2.7
EN logic low (active mode)
3V≤VI≤10 V
25°C 0.5
EN
l
og
i
c
l
ow
(
ac
ti
ve mo
d
e
)
3
V
≤
V
I
≤
10
V
–40°C to 125°C 0.5
EN hysteresis voltage 25°C 50 mV
EN input current
0V≤VI≤10 V
25°C –0.5 0.5
EN
i
npu
t
curren
t
0
V
≤
V
I
≤
10
V
–40°C to 125°C –0.5 0.5 µ
Minimum VIfor active
p
ass element
25°C 1.9 2.5
Minim
u
m
V
I
for
acti
v
e
pass
element
–40°C to 125°C 2.5
Minimum VIfor valid PG
IPG = 300 µA
25°C 1.1 1.5
Minim
u
m
V
I
for
v
alid
PG
I
PG =
300
µ
A
–40°C to 125°C 1.9
†CSR(compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor , any
series resistance added externally, and PWB trace resistance to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7201Q electrical characteristics, IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), FB
shorted to OUT at device leads (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7201Q
UNIT
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
UNIT
Reference voltage (measured VI = 3.5 V, IO = 10 mA 25°C 1.188 V
g(
at FB with OUT connected to
FB) 3 V ≤ VI ≤ 10 V,
See Note 2 5 mA ≤ IO ≤ 250 mA, –40°C to 125°C 1.152 1.224 V
Reference voltage
temperature coefficient –40°C to 125°C 31 75 ppm/°C
VI = 2.4 V,§50 µA ≤ IO ≤ 100 mA 25°C 2.1
VI = 2.4 V,§100 mA ≤ IO ≤ 200 mA 25°C 2.9
Pass-element series
VI=29V
50 µA≤IO≤250 mA
25°C 1.6 2.7
Ω
resistance (see Note 3)
V
I =
2
.
9
V
,
50
µ
A
≤
I
O
≤
250
mA
–40°C to 125°C 4.5
Ω
VI = 3.9 V, 50 µA ≤ IO ≤ 250 mA 25°C 1
VI = 5.9 V, 50 µA ≤ IO ≤ 250 mA 25°C 0.8
In
p
ut regulation
V
I
= 3 V to 10 V, 50
µ
A ≤ I
O
≤ 250 mA, 25°C 23
mV
Inp
u
t
reg
u
lation
I,
See Note 2
µO,
–40°C to 125°C 36
mV
I
O
= 5 mA to 250 mA, 3 V ≤ V
I
≤ 10 V, 25°C 15 25
Out
p
ut regulation
O,
See Note 2
I,
–40°C to 125°C 36
mV
O
u
tp
u
t
reg
u
lation
I
O
= 50 µA to 250 mA, 3 V ≤ V
I
≤ 10 V, 25°C 17 27
mV
Oµ,
See Note 2
I,
–40°C to 125°C 43
IO=50µA
25°C 49 60
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 32
dB
Ripple
rejection
f
=
120
H
zI
O
= 250 mA, 25°C 45 50
dB
O,
See Note 2 –40°C to 125°C 30
Output noise spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF 25°C 235
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR†=1Ω
CO = 10 µF 25°C 190 µVrms
CSR†
=
1
Ω
CO = 100 µF 25°C 125
PG trip-threshold voltageVFB voltage decreasing from above VPG –40°C to 125°C0.95 ×
VFB(nom) V
PG hysteresis voltageMeasured at VFB 25°C 12 mV
PG out
p
ut low voltage
IPG = 400 µA
VI= 2 13 V
25°C 0.1 0.4
V
PG
ou
t
pu
t
l
ow vo
lt
age
I
PG =
400
µ
A
,
V
I =
2
.
13
V
–40°C to 125°C 0.4
V
FB in
p
ut current
25°C–10 0.1 10
nA
FB
inp
u
t
c
u
rrent
–40°C to 125°C–20 20
nA
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§This voltage is not recommended.
Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 2. When VI < 2.9 V and IO > 100 mA simultaneously , pass element rDS(on) increases (see Figure 10) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
3. To calculate dropout voltage, use equation:
VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figures 10 and 11.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7225Q electrical characteristics, IO = 10 mA, VI = 3.5 V , EN = 0 V , CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7225Q
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
Out
p
ut voltage
VI = 3.5 V, IO = 10 mA 25°C 2.5
O
u
tp
u
t
v
oltage
3.5 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 2.45 2.55
Dropout voltage
IO= 250 mA
VI= 2 97 V
25°C 560 850 mV
D
ropou
t
vo
lt
age
I
O =
250
mA
,
V
I =
2
.
97
V
–40°C to 125°C 1.1 V
Pass element series resistance
(2.97 V – V
O
)/I
O
, V
I
= 2.97 V, 25°C 2.24 3.4
Pass
-
element
series
resistance
(O)O,
IO = 250 mA
I,
–40°C to 125°C 3.84
In
p
ut regulation
VI=35Vto10V
50 µA≤IO≤250 mA
25°C 9 27
Inp
u
t
reg
u
lation
V
I =
3
.
5
V
to
10
V
,
50
µ
A
≤
I
O
≤
250
mA
–40°C to 125°C 33
IO=5mAto250mA
35V≤VI≤10 V
25°C 28 36
Out
p
ut regulation
I
O =
5
mA
to
250
mA
,
3
.
5
V
≤
V
I
≤
10
V
–40°C to 125°C 60
O
u
tp
u
t
reg
u
lation
IO=50µA to 250 mA
35V≤VI≤10 V
25°C 24 41
I
O =
50
µ
A
to
250
mA
,
3
.
5
V
≤
V
I
≤
10
V
–40°C to 125°C 73
IO=50µA
25°C 47 58
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 45
Ripple
rejection
f
=
120
H
z
IO= 250 mA
25°C 40 46
I
O =
250
mA
–40°C to 125°C 38
Output noise spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF25°C 248
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR
†=
1Ω
CO = 10 µF25°C 200 µVrms
CSR†
=
1
Ω
CO = 100 µF25°C 130
PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C0.95 ×
VO(nom) V
PG hysteresis voltage 25°C 50 mV
PG out
p
ut low voltage
IPG =12mA
VI= 2 13 V
25°C 0.3 0.44
PG
output
low
voltage
I
PG =
1
.
2
mA
,
V
I =
2
.
13
V
–40°C to 125°C 0.5
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7230Q electrical characteristics, IO = 10 mA, VI = 4 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7230Q
UNIT
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
UNIT
Out
p
ut voltage
VI = 4 V, IO = 10 mA 25°C 3
V
O
u
tp
u
t
v
oltage
4 V ≤VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 2.94 3.06
V
IO= 100 mA
VI= 2 97 V
25°C 145 185
Dropout voltage
I
O =
100
mA
,
V
I =
2
.
97
V
–40°C to 125°C 270
mV
D
ropou
t
vo
lt
age
IO= 250 mA
VI= 2 97 V
25°C 390 502
mV
I
O =
250
mA
,
V
I =
2
.
97
V
–40°C to 125°C 900
Pass element series resistance
(2.97 V – V
O
)/I
O
, V
I
= 2.97 V, 25°C 1.56 2.01
Ω
Pass
-
element
series
resistance
(O)O,
IO = 250 mA
I,
–40°C to 125°C 3.6
Ω
In
p
ut regulation
VI=4Vto10V
50 µA≤IO≤250 mA
25°C 9 27
mV
Inp
u
t
reg
u
lation
V
I =
4
V
to
10
V
,
50
µ
A
≤
I
O
≤
250
mA
–40°C to 125°C 33
mV
IO=5mAto250mA
4V≤VI≤10 V
25°C 34 45
Out
p
ut regulation
I
O =
5
mA
to
250
mA
,
4
V
≤
V
I
≤
10
V
–40°C to 125°C 74
mV
O
u
tp
u
t
reg
u
lation
IO=50µA to 250 mA
4V≤VI≤10 V
25°C 42 60
mV
I
O =
50
µ
A
to
250
mA
,
4
V
≤
V
I
≤
10
V
–40°C to 125°C 98
IO=50µA
25°C 45 56
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 44
dB
Ripple
rejection
f
=
120
H
z
IO= 250 mA
25°C 40 45
dB
I
O =
250
mA
–40°C to 125°C 38
Output noise spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF25°C 256
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR
†=
1Ω
CO = 10 µF25°C 206 µVrms
CSR†
=
1
Ω
CO = 100 µF25°C 132
PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C0.95 ×
VO(nom) V
PG hysteresis voltage 25°C 50 mV
PG out
p
ut low voltage
IPG =12mA
VI= 2 55 V
25°C 0.25 0.44
V
PG
output
low
voltage
I
PG =
1
.
2
mA
,
V
I =
2
.
55
V
–40°C to 125°C 0.44
V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7233Q electrical characteristics, IO = 10 mA, VI = 4.3 V , EN = 0 V , CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7233Q
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
Out
p
ut voltage
VI = 4.3 V, IO = 10 mA 25°C 3.3
O
u
tp
u
t
v
oltage
4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 3.23 3.37
IO=10mA
VI= 3 23 V
25°C 14 20
I
O =
10
mA
,
V
I =
3
.
23
V
–40°C to 125°C 30
Dropout voltage
IO= 100 mA
VI= 3 23 V
25°C 140 180
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
3
.
23
V
–40°C to 125°C 232
IO= 250 mA
VI= 3 23 V
25°C 360 460
I
O =
250
mA
,
V
I =
3
.
23
V
–40°C to 125°C 610
Pass element series resistance
(3.23 V – V
O
)/I
O
, V
I
= 3.23 V, 25°C 1.5 1.84
Pass
-
element
series
resistance
(O)O,
IO = 250 mA
I,
–40°C to 125°C 2.5
In
p
ut regulation
VI=43Vto10V
50 µA≤IO≤250 mA
25°C 8 25
Inp
u
t
reg
u
lation
V
I =
4
.
3
V
to
10
V
,
50
µ
A
≤
I
O
≤
250
mA
–40°C to 125°C 33
IO=5mAto250mA
43V≤VI≤10 V
25°C 32 42
Out
p
ut regulation
I
O =
5
mA
to
250
mA
,
4
.
3
V
≤
V
I
≤
10
V
–40°C to 125°C 71
O
u
tp
u
t
reg
u
lation
IO=50µA to 250 mA
43V≤VI≤10 V
25°C 41 55
I
O =
50
µ
A
to
250
mA
,
4
.
3
V
≤
V
I
≤
10
V
–40°C to 125°C 98
IO=50µA
25°C 40 52
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 38
Ripple
rejection
f
=
120
H
z
IO= 250 mA
25°C 35 44
I
O =
250
mA
–40°C to 125°C 33
Output noise spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF25°C 265
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR
†=
1Ω
CO = 10 µF25°C 212 µVrms
CSR†
=
1
Ω
CO = 100 µF25°C 135
PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C0.95 ×
VO(nom) V
PG hysteresis voltage 25°C 32 mV
PG out
p
ut low voltage
IPG =12mA
VI=28V
25°C 0.22 0.4
PG
output
low
voltage
I
PG =
1
.
2
mA
,
V
I =
2
.
8
V
–40°C to 125°C 0.4
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7248Q electrical characteristics, IO = 10 mA, VI = 5.85 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7248Q
UNIT
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
UNIT
Out
p
ut voltage
VI = 5.85 V, IO = 10 mA 25°C 4.85
V
O
u
tp
u
t
v
oltage
5.85 V ≤VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 4.75 4.95
V
IO=10mA
VI= 4 75 V
25°C 10 19
I
O =
10
mA
,
V
I =
4
.
75
V
–40°C to 125°C 30
Dropout voltage
IO= 100 mA
VI= 4 75 V
25°C 90 100
mV
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
4
.
75
V
–40°C to 125°C 150
mV
IO= 250 mA
VI= 4 75 V
25°C 216 250
I
O =
250
mA
,
V
I =
4
.
75
V
–40°C to 125°C 285
Pass element series resistance
(4.75 V – V
O
)/I
O
, V
I
= 4.75 V, 25°C 0.8 1
Ω
Pass
-
element
series
resistance
(O)O,
IO = 250 mA
I,
–40°C to 125°C 1.4
Ω
In
p
ut regulation
VI=585Vto10V
50 µA≤IO≤250 mA
25°C 34
mV
Inp
u
t
reg
u
lation
V
I =
5
.
85
V
to
10
V
,
50
µ
A
≤
I
O
≤
250
mA
–40°C to 125°C 50
mV
IO=5mAto250mA
585V≤VI≤10 V
25°C 43 55
Out
p
ut regulation
I
O =
5
mA
to
250
mA
,
5
.
85
V
≤
V
I
≤
10
V
–40°C to 125°C 95
mV
O
u
tp
u
t
reg
u
lation
IO=50µA to 250 mA
585V≤VI≤10 V
25°C 55 75
mV
I
O =
50
µ
A
to
250
mA
,
5
.
85
V
≤
V
I
≤
10
V
–40°C to 125°C 135
IO=50µA
25°C 42 53
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 36
dB
Ripple
rejection
f
=
120
H
z
IO= 250 mA
25°C 36 46
dB
I
O =
250
mA
–40°C to 125°C 34
Output noise spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF25°C 370
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR
†=
1Ω
CO = 10 µF25°C 290 µVrms
CSR†
=
1
Ω
CO = 100 µF25°C 168
PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C0.95 ×
VO(nom) V
PG hysteresis voltage 25°C 50 mV
PG out
p
ut low voltage
IPG =12mA
VI= 4 12 V
25°C 0.2 0.4
V
PG
output
low
voltage
I
PG =
1
.
2
mA
,
V
I =
4
.
12
V
–40°C to 125°C 0.4
V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7250Q electrical characteristics, IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7250Q
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
Out
p
ut voltage
VI = 6 V, IO = 10 mA 25°C 5
O
u
tp
u
t
v
oltage
6 V ≤VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 4.9 5.1
IO=10mA
VI= 4 88 V
25°C 8 12
I
O =
10
mA
,
V
I =
4
.
88
V
–40°C to 125°C 30
Dropout voltage
IO= 100 mA
VI= 4 88 V
25°C 76 85
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
4
.
88
V
–40°C to 125°C 136
IO= 250 mA
VI= 4 88 V
25°C 190 206
I
O =
250
mA
,
V
I =
4
.
88
V
–40°C to 125°C 312
Pass element series resistance
(4.88 V – V
O
)/I
O
, V
I
= 4.88 V, 25°C 0.76 0.825
Pass
-
element
series
resistance
(O)O,
IO = 250 mA
I,
–40°C to 125°C 1.25
In
p
ut regulation
VI=6Vto10V
50 µA≤IO≤250 mA
25°C 28
Inp
u
t
reg
u
lation
V
I =
6
V
to
10
V
,
50
µ
A
≤
I
O
≤
250
mA
–40°C to 125°C 35
IO=5mAto250mA
6V≤VI≤10 V
25°C 46 61
Out
p
ut regulation
I
O =
5
mA
to
250
mA
,
6
V
≤
V
I
≤
10
V
–40°C to 125°C 100
O
u
tp
u
t
reg
u
lation
IO=50µA to 250 mA
6V≤VI≤10 V
25°C 59 79
I
O =
50
µ
A
to
250
mA
,
6
V
≤
V
I
≤
10
V
–40°C to 125°C 150
IO=50µA
25°C 41 52
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 37
Ripple
rejection
f
=
120
H
z
IO= 250 mA
25°C 36 46
I
O =
250
mA
–40°C to 125°C 32
Output noise spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF25°C 390
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR
†=
1Ω
CO = 10 µF25°C 300 µVrms
CSR†
=
1
Ω
CO = 100 µF25°C 175
PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C0.95 ×
VO(nom) V
PG hysteresis voltage 25°C 50 mV
PG out
p
ut low voltage
IPG =12mA
VI= 4 25 V
25°C 0.19 0.4
PG
output
low
voltage
I
PG =
1
.
2
mA
,
V
I =
4
.
25
V
–40°C to 125°C 0.4
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally , and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE/FB
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TPS72xxY
UNIT
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
UNIT
Ground current (active mode) EN ≤ 0.5 V,
0 mA ≤ IO ≤ 250 mA VI = VO + 1 V, 180 µA
Output current limit threshold VO = 0 V, VI = 10 V 0.6 A
Thermal shutdown junction temperature 165 °C
EN hysteresis voltage 50 mV
Minimum VI for active pass element 1.9 V
Minimum VI for valid PG IPG = 300 µA 1.1 V
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, FB shorted to
OUT at device leads (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TPS7201Y
UNIT
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
UNIT
Reference voltage (measured at FB with OUT
connected to FB) VI = 3.5 V, IO = 10 mA 1.188 V
VI = 2.4 V,§50 µA ≤ IO ≤ 100 mA 2.1
VI = 2.4 V,§100 mA ≤ IO ≤ 200 mA 2.9
Pass-element series resistance (see Note 3) VI = 2.9 V, 50 µA ≤ IO ≤ 250 mA 1.6 Ω
VI = 3.9 V, 50 µA ≤ IO ≤ 250 mA 1
VI = 5.9 V, 50 µA ≤ IO ≤ 250 mA 0.8
Out
p
ut regulation
3 V ≤ VI ≤ 10 V,
See Note 2 IO = 5 mA to 250 mA, 15
mV
O
u
tp
u
t
reg
u
lation
3 V ≤ VI ≤ 10 V,
See Note 2 IO = 50 µA to 250 mA, 17
mV
VI=35V
IO = 50 µA 60
Ripple rejection
V
I =
3
.
5
V
,
f = 120 Hz IO = 250 mA,
See Note 2 50 dB
Output noise spectral density VI = 3.5 V, f = 120 Hz 2µV/√Hz
VI
=
3.5 V,
CO = 4.7 µF 235
Output noise voltage
VI
=
3
.
5
V
,
10 Hz ≤ f ≤ 100 kHz,
†
CO = 10 µF 190 µVrms
CSR† = 1 ΩCO = 100 µF 125
PG hysteresis voltageVI = 3.5 V, Measured at VFB 12 mV
PG output low voltageVI = 2.13 V, IPG = 400 µA 0.1 V
FB input current VI = 3.5 V 0.1 nA
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§This voltage is not recommended.
Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 2 When VI < 2.9 V and IO > 100 mA simultaneously , pass element rDS(on) increases (see Figure 10) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
3 To calculate dropout voltage, use equation:
VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figures 10 and 11.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, FB shorted to
OUT at device leads (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TPS7225Y
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
Output voltage VI = 3.5 V, IO = 10 mA 2.5 V
Dropout voltage VI = 2.97 V, IO = 250 mA 560 mV
Pass-element series resistance (2.97 V – VO)/IO,
IO = 250 mA VI = 2.97 V, 2.24 Ω
Input regulation VI = 3.5 V to 10 V, 50 µA ≤ IO ≤ 250 mA 9 mV
Out
p
ut regulation
3.5 V ≤ VI ≤ 10 V IO = 5 mA to 250 mA 28
O
u
tp
u
t
reg
u
lation
3.5 V ≤ VI ≤ 10 V IO = 50 µA to 250 mA 24
Ri
pp
le rejection
V
I
= 3.5 V, IO = 50 µA 58
Ripple
rejection
I,
f = 120 Hz IO = 250 mA 46
Output noise spectral density VI = 3.5 V, f = 120 Hz 2µV/√Hz
VI
=
3.5 V,
CO = 4.7 µF248
Output noise voltage
VI
=
3
.
5
V
,
10 Hz ≤ f ≤ 100 kHz,
CSR†
CO = 10 µF200 µVrms
CSR
†
= 1 ΩCO = 100 µF130
PG hysteresis voltage VI = 3.5 V 50 mV
PG output low voltage VI = 2.13 V IPG = 1.2 mA 0.3 V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TPS7230Y
UNIT
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
UNIT
Output voltage VI = 4 V, IO = 10 mA 3 V
Dropout voltage
VI = 2.97 V, IO = 100 mA 145
mV
D
ropou
t
vo
lt
age VI = 2.97 V, IO = 250 mA 390
mV
Pass-element series resistance (2.97 V – VO)/IO,
IO = 250 mA VI = 2.97 V, 1.56 Ω
Input regulation VI = 4 V to 10 V, 50 µA ≤ IO ≤ 250 mA 9 mV
Out
p
ut regulation
4 V ≤ VI ≤ 10 V IO = 5 mA to 250 mA 34
mV
O
u
tp
u
t
reg
u
lation
4 V ≤ VI ≤ 10 V IO = 50 µA to 250 mA 41
mV
Ri
pp
le rejection
V
I
= 4 V, IO = 50 µA 56
dB
Ripple
rejection
I,
f = 120 Hz IO = 250 mA 45
dB
Output noise spectral density VI = 4 V, f = 120 Hz 2µV/√Hz
VI
=
4V,
CO = 4.7 µF256
Output noise voltage
VI
=
4
V
,
10 Hz ≤ f ≤ 100 kHz,
CSR†
CO = 10 µF206 µVrms
CSR
†
= 1 ΩCO = 100 µF132
PG hysteresis voltage VI = 4 V 50 mV
PG output low voltage VI = 2.55 V IPG = 1.2 mA 0.25 V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
PARAMETER
TEST CONDITIONS‡
TPS7233Y
UNIT
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
UNIT
Output voltage VI = 4.3 V, IO = 10 mA 3.3 V
VI = 3.23 V, IO = 10 mA 14
Dropout voltage VI = 3.23 V, IO = 100 mA 140 mV
VI = 3.23 V, IO = 250 mA 360
Pass-element series resistance (3.23 V – VO)/IO,
IO = 250 mA VI = 3.23 V, 1.5 Ω
Input regulation VI = 4.3 V to 10 V, 50 µA ≤ IO ≤ 250 mA 8 mV
Out
p
ut regulation
4.3 V ≤ VI ≤ 10 V, IO = 5 mA to 250 mA 32
mV
O
u
tp
u
t
reg
u
lation
4.3 V ≤ VI ≤ 10 V, IO = 50 µA to 250 mA 41
mV
Ri
pp
le rejection
V
I
= 4.3 V, IO = 50 µA 52
dB
Ripple
rejection
I,
f = 120 Hz IO = 250 mA 44
dB
Output noise spectral density VI = 4.3 V, f = 120 Hz 2µV/√Hz
VI
=
4.3 V,
CO = 4.7 µF265
Output noise voltage
VI
=
4
.
3
V
,
10 Hz ≤ f ≤ 100 kHz,
CSR†
CO = 10 µF212 µVrms
CSR
†
= 1 ΩCO = 100 µF135
PG hysteresis voltage VI = 4.3 V 32 mV
PG output low voltage VI = 2.8 V, IPG = 1.2 mA 0.22 V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS‡
TPS7248Y
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
Output voltage VI = 5.85 V, IO = 10 mA 4.85 V
VI = 4.75 V, IO = 10 mA 10
Dropout voltage VI = 4.75 V, IO = 100 mA 90 mV
VI = 4.75 V, IO = 250 mA 216
Pass-element series resistance (4.75 V – VO)/IO,
IO = 250 mA VI = 4.75 V, 0.8 Ω
Out
p
ut regulation
5.85 V ≤ VI ≤ 10 V IO = 5 mA to 250 mA 43
O
u
tp
u
t
reg
u
lation
5.85 V ≤ VI ≤ 10 V IO = 50 µA to 250 mA 55
Ri
pp
le rejection
V
I
= 5.85 V, IO = 50 µA 53
Ripple
rejection
I,
f = 120 Hz IO = 250 mA 46
Output noise spectral density VI = 5.85 V, f = 120 Hz 2µV/√Hz
VI
=
5.85 V,
CO = 4.7 µF370
Output noise voltage
VI
=
5
.
85
V
,
10 Hz ≤ f ≤ 100 kHz,
CSR†
CO = 10 µF290 µVrms
CSR
†
= 1 ΩCO = 100 µF168
PG hysteresis voltage VI = 5.85 V 50 mV
PG output low voltage VI = 4.12 V IPG = 1.2 mA 0.2 V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
PARAMETER
TEST CONDITIONS‡
TPS7250Y
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
Output voltage VI = 6 V, IO = 10 mA 5 V
VI = 4.88 V IO = 10 mA 8
Dropout voltage VI = 4.88 V IO = 100 mA 76 mV
VI = 4.88 V, IO = 250 mA 190
Pass-element series resistance (4.88 V – VO)/IO,
IO = 250 mA VI = 4.88 V, 0.76 Ω
Input regulation VI = 6 V to 10 V, 50 µA ≤ IO ≤ 250 mA mV
Out
p
ut regulation
6 V ≤ VI ≤ 10 V, IO = 5 mA to 250 mA 46
O
u
tp
u
t
reg
u
lation
6 V ≤ VI ≤ 10 V, IO = 50 µA to 250 mA 59
Ri
pp
le rejection
V
I
= 6 V, IO = 50 µA 52
Ripple
rejection
I,
f = 120 Hz IO = 250 mA 46
Output noise spectral density VI = 6 V, f = 120 Hz 2µV/√Hz
VI
=
6V,
CO = 4.7 µF390
Output noise voltage
VI
=
6
V
,
10 Hz ≤ f ≤ 100 kHz,
CSR†
CO = 10 µF300 µVrms
CSR
†
= 1 ΩCO = 100 µF175
PG hysteresis voltage VI = 6 V 50 mV
PG output low voltage VI = 4.25 V, IPG = 1.2 mA 0.19 V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally , and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IQ
Quiescent current
vs Output current 5
I
Q
Q
u
iescent
c
u
rrent
vs Input voltage 6
∆IQ†Change in quiescent current vs Free-air temperature 7
VDO Dropout voltage vs Output current 8
∆VDO Change in dropout voltage vs Free-air temperature 9
VDO Dropout voltage (TPS7201 only) vs Output current 10
rDS(on) Pass-element series resistance vs Input voltage 11
∆VOChange in output voltage vs Free-air temperature 12
VOOutput voltage vs Input voltage 13
Line regulation
(TPS7201, TPS7233, TPS7248, TPS7250) 14
Load regulation
(TPS7225, TPS7233, TPS7248, TPS7250) 15
VO(PG) Power-good (PG) voltage vs Output voltage 16
rDS(on)PG Power-good (PG) on-resistance vs Input voltage 17
VIMinimum input voltage for valid PG vs Free-air temperature 18
Output voltage response from enable (EN) 19
Load transient response (TPS7201/TPS7233) 20
Load transient response (TPS7248/TPS7250) 21
Line transient response (TPS7201) 22
Line transient response (TPS7233) 23
Line transient response (TPS7248/TPS7250) 24
Ripple rejection vs Frequency 25
Output Spectral Noise Density vs Frequency 26
vs Output current (CO = 4.7 µF) 27
Com
p
ensation series resistance (CSR)
vs Added ceramic capacitance (CO = 4.7 µF) 28
Compensation
series
resistance
(CSR)
vs Output current (CO = 10 µF) 29
vs Added ceramic capacitance (CO = 10 µF) 30
†This symbol is not currently listed within EIA or JEDEC standards for semiconductor symbology.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
190
180
160
1500 50 100 150
– Quiescent Current –
200
220
QUIESCENT CURRENT
vs
OUTPUT CURRENT
230
200 250
170
210
IQ Aµ
IO – Output Current – mA
TA = 25°CTPS7248 VI = 10 V
TPS7233 VI = 10 V
TPS7250 VI = 10 V
TPS7248 VI = 5.85 V
TPS7250 VI = 6.0 V
TPS7233 VI = 4.3 V
Figure 6
100
50
00123456
150
200
QUIESCENT CURRENT
vs
INPUT VOLTAGE
250
78910
– Quiescent Current –
IQ Aµ
VI – Input Voltage – V
TA 25°C
IO = 250 mA TPS7248
TPS7233
TPS7250
TPS7201 With
VO Programmed to 2.5 V
Figure 7
10
0
– Change in Quiescent Current –
30
20
40
CHANGE IN QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
50
∆IQAµ
–10
–20
–30
– 40
– 40 – 20 0 20 40 60 80 100 120 140
TA – Free-Air Temperature – °C
IO = 10 mA
VI = VO + 1 V
Figure 8
200
00 50 100 150
– Dropout Voltage – mV
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
400
200 250
100
300
VDO
IO – Output Current – mA
TPS7233
TPS7248
TPS7250
TA = 25°C
TPS7230
TPS7225
500
600
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
0.01
0
0.03
0.02
0.04
CHANGE IN DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.05
– Change in Dropout Voltage – V∆VDO
TA – Free-Air Temperature – °C
–0.01
–0.02
–0.03
–0.04
–40 –20 0 20 40 60 80 100 120 140
TPS7233
TPS7248/TPS7250
TPS7230
Figure 10
0 50 100 150 200 250
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
– Dropout Voltage – VVDO
IO – Output Current – mA
TPS7201
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
VI = 2.9 V
VI = 2.4 V†
VI = 2.6 V†
VI = 3.2 V
VI = 3.9 V
VI = 5.9 V
VI = 9.65 V
†This voltage is not recommended.
Figure 11
3
2
1
0234567
– Pass Element Series Resistance –
4
5
PASS ELEMENT SERIES RESISTANCE
vs
INPUT VOLTAGE
6
8910
rDS(on) Ω
VI – Input Voltage – V
TA = 25°C
VFB = 1.12 V
IO = 250 mA
IO = 100 mA
Figure 12
CHANGE IN OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
– Change in Output Voltage – mV∆VO
TA – Free-Air Temperature – °C
15
10
5
0
–5
–10
–15
–20
–25
–40 –20 0 20 40 60 80 100 120 140
IO = 10 mA
VI = VO + 1 V
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
3
2
1
00123456
– Output Voltage – V
4
4.5
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
5.5
78910
5
3.5
2.5
1.5
0.5
VO
VI – Input Voltage – V
TPS7250
TPS7248
TPS7233
TA = 25°C
IO = 250 mA
TPS7201 With
VO Programmed to 2.5 V
∆
Figure 14
4 4.5 5 6 6.5 7 7.5
LINE REGULATION
8 8.5 9.5 105.5 9
25
20
15
10
5
0
–5
–10
–15
–20
–25
TPS7250
TPS7233
TPS7248
TA = 25°C
IO = 250 mA
– Change in Output Voltage – mV∆VO
VI – Input Voltage – V
TPS7201 With
VO Programmed to 2.5 V
Figure 15
0 50 100 150 200 250
50
40
30
20
10
0
–10
–20
–30
–40
–50
IO – Output Current – mA
TA = 25°C
– Change in Output Voltage – mV∆VO
TPS7233
TPS7250
TPS7248
TPS7225
LOAD REGULATION
Figure 16
POWER-GOOD (PG) VOLTAGE
vs
OUTPUT VOLTAGE†
GND
092 93 94 95
– Power-Good (PG) Voltage – V
6
96 98
TA = 25°C
PG Pulled Up to VI With 5 kΩ Resistor
VO – Output Voltage – %
ÁÁ
ÁÁ
VO(PG)
97
VI
†VO as a percent of VOnom.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 17
10
1
0
100
1 1.5 2 2.5 3 3.5 4
– Power-Good (PG) On-Resistance – k
POWER-GOOD (PG) ON-RESISTANCE
vs
INPUT VOLTAGE
4.5 5
rDS(on) Ω
VI – Input Voltage – V
TA = 25°C
Figure 18
1.125
1.095
– Minimum Input Voltage for Valid PG
1.115
1.11
1.12
MINIMUM INPUT VOLTAGE FOR VALID PG
vs
FREE-AIR TEMPERATURE
1.3
–40 –20 0 20 40 60 80 100 120 140
ÁÁ
VI
1.105
TA – Free-Air Temperature – °C
1.1
– Output Voltage – V
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
0 50 100 150
5
0
– EN Voltage – V
VO
VO nom
VI(EN)
t – Time – µs
(Values V ary With
Selection of Device)
10
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
Figure 19
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
TPS7201 (WITH VO PROGRAMMED T O 2.5 V), TPS7233
LOAD TRANSIENT RESPONSE
200
100
0
–100
–200
– Output Current – mA
105
55
5
IO
t – Time – µs
0 100 200 300 400 500
TA = 25°C
VI = 6 V
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– Change in Output Voltage – mV∆VO
Figure 20
LOAD TRANSIENT RESPONSE
200
100
0
–100
–200
105
55
5
TPS7248/TPS7250
t – Time – µs
0 100 200 300 400 500
TA = 25°C
VI = 6 V
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– Change in Output Voltage – mV∆VO
– Output Current – mA
IO
Figure 21
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
LINE TRANSIENT RESPONSE
100
50
0
–50
–100
6.5
6.25
6
TPS7201 WITH VO PROGRAMMED T O 2.5 V
t – Time – µs
0 100 200 300 400
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– Change in Output Voltage – mV∆VO
– Input Voltage – V
VI
Figure 22
LINE TRANSIENT RESPONSE
200
100
0
–50
–100
– Input Voltage – V
6.5
6.25
6
VI
TPS7233
t – Time – µs
5.75
0 100 200 300 400 500
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– Change in Output Voltage – mV∆VO
Figure 23
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
LINE TRANSIENT RESPONSE
100
50
0
–50
–100
– Input Voltage – V
6.5
6.25
6
VI
TPS7248/TPS7250
t – Time – µs
0 100 200 300 400 500
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– Change in Output Voltage – mV∆VO
Figure 24
Figure 25
30
10
0
Ripple Rejection – dB
40
50
f – Frequency – Hz
RIPPLE REJECTION
vs
FREQUENCY
60
20
10 100 1 K 10 K 100 K 1 M 10 M
TA = 25°C
No Input
Capacitance Added
VI = VO + 1 V
IO = 100 mA
CO = 4.7 µF (CSR = 1 Ω)
TPS7233
TPS7201 With
VO Programmed
to 2.5 V
TPS7248/
TPS7250
Figure 26
10 100 1 k 10 k 100 k
CO = 10 µF (CSR = 1 Ω)
CO = 4.7 µF (CSR = 1 Ω)
CO = 100 µF (CSR = 1 Ω)
f – Frequency – Hz
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
1
0.1
0.01
TA = 25°C
No Input Capacitance Added
VI = VO + 1 V
Output Spectral Noise Density – V/ Hzµ
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 27
0.1
0.010 50 100 150 200 250
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
OUTPUT CURRENT
10
100
IO – Output Current – mA
CSR – Compensation Series Resistance – Ω
Region of Instability
1
TA = 25°C
VI = VO + 1 V
CO = 4.7 µF
No Added Ceramic Capacitance
No Input Capacitance Added
Region of Instability
Figure 28
0.1
0.010 0.1 0.2 0.3 0.4 0.5
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
ADDED CERAMIC CAPACITANCE
10
100
Added Ceramic Capacitance – µF
0.6 0.7 0.8 0.9 1
1
TA = 25°C
VI = VO + 1 V
IO = 250 mA
CO = 4.7 µF
No Input Capacitor Added
Region of Instability
Region of
Instability
CSR – Compensation Series Resistance – Ω
Figure 29
0.1
0.010 50 100 150 200 250
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
OUTPUT CURRENT
10
100
IO – Output Current – mA
1
Region of Instability
TA = 25°C
VI = VO + 1 V
CO = 10 µF
No Added Ceramic Capacitance
No Input Capacitor Added
Region of Instability
CSR – Compensation Series Resistance – Ω
Figure 30
0.1
0.010 0.1 0.2 0.3 0.4 0.5
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
ADDED CERAMIC CAPACITANCE
10
100
Added Ceramic Capacitance – µF
1
0.6 0.7 0.8 0.9 1
Region of Instability
TA = 25°C
VI = VO + 1 V
IO = 250 mA
CO = 10 µF
No Input Capacitor Added
Region of
Instability
CSR – Compensation Series Resistance – Ω
†CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The design of the TPS72xx family of low-dropout (LDO) regulators is based on the higher-current TPS71xx
family . These new families of regulators have been optimized for use in battery-operated equipment and feature
extremely low dropout voltages, low supply currents that remain constant over the full-output-current range of
the device, and an enable input to reduce supply currents to less than 0.5 µA when the regulator is turned off.
device operation
The TPS72xx uses a PMOS pass element to dramatically reduce both dropout voltage and supply current over
more conventional PNP-pass-element LDO designs. The PMOS transistor is a voltage-controlled device that,
unlike a PNP transistor, does not require increased drive current as output current increases. Supply current
in the TPS72xx is essentially constant from no-load to maximum.
Current limiting and thermal protection prevent damage by excessive output current and/or power dissipation.
The device switches into a constant-current mode at approximately 1 A; further load increases reduce the output
voltage instead of increasing the output current. The thermal protection shuts the regulator off if the junction
temperature rises above 165°C. Recovery is automatic when the junction temperature drops approximately 5°C
below the high temperature trip point. The PMOS pass element includes a back diode that safely conducts
reverse current when the input voltage level drops below the output voltage level.
A logic high on the enable input, EN, shuts off the output and reduces the supply current to less than 0.5 µA.
EN should be grounded in applications where the shutdown feature is not used.
Power good (PG) is an open-drain output signal used to indicate output-voltage status. A comparator circuit
continuously monitors the output voltage. When the output drops to approximately 95% of its nominal regulated
value, the comparator turns on and pulls PG low.
T ransient loads or line pulses can also cause activation of PG if proper care is not taken in selecting the input
and output capacitors. Load transients that are faster than 5 µs can cause a signal on PG if high-ESR output
capacitors (greater than approximately 7 Ω) are used. A 1-µs transient causes a PG signal when using an output
capacitor with greater than 3.5 Ω of ESR. It is interesting to note that the output-voltage spike during the transient
can drop well below the reset threshold and still not trip if the transient duration is short. A 1-µs transient must
drop at least 500 mV below the threshold before tripping the PG circuit. A 2-µs transient trips PG at just 400 mV
below the threshold. Lower-ESR output capacitors help by reducing the drop in output voltage during a transient
and should be used when fast transients are expected.
A typical application circuit is shown in Figure 31.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
C1
0.1 µF
NOTE A: TPS7225, TPS7230, TPS7233, TPS7248, TPS7250
(fixed-voltage options).
SENSE
PG
OUT
OUT
6
5
4
IN
IN
EN
GND
3
2
1
7
8
VIPG
CSR = 1 Ω
VO
10 µF
+
TPS72xx
(see Note A)
250 kΩ
Figure 31. Typical Application Circuit
external capacitor requirements
Although not required, a 0.047-µF to 0.1-µF ceramic bypass input capacitor, connected between IN and GND
and located close to the TPS72xx, is recommended to improve transient response and noise rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
An output capacitor is required to stabilize the internal feedback loop. For most applications, a 10-µF to 15-µF
solid-tantalum capacitor with a 0.5-Ω resistor (see capacitor selection table) in series is sufficient. The maximum
capacitor ESR should be limited to 1.3 Ω to allow for ESR doubling at cold temperatures. Figure 32 shows the
transient response of a 5-mA to 85-mA load using a 10-µF output capacitor with a total ESR of 1.7 Ω.
A 4.7-µF solid-tantalum capacitor in series with a 1-Ω resistor may also be used (see Figures 27 and 28)
provided the ESR of the capacitor does not exceed 1 Ω at room temperature and 2 Ω over the full operating
temperature range.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
2→
1→
Ch 2
VO
IO = 5 mA
Ch1 50 mV 50 mA 100 µs/div
VI = VO + 1 V
IO = 85 mA
Figure 32. Load Transient Response (CSR total = 1.7 Ω), TPS7248Q
A partial listing of surface-mount capacitors usable with the TPS72xx family is provided below . This information
(along with the stability graphs, Figures 27 through 30) is included to assist the designer in selecting suitable
capacitors.
CAPACIT OR SELECTION
PART NO. MFR. VALUE MAX ESR†SIZE (H × L × W)†
592D156X0020R2T Sprague 15 µF, 20 V 1.1 1.2 × 7.2 × 6
595D156X0025C2T Sprague 15 µF, 25 V 1 2.5 × 7.1 × 3.2
595D106X0025C2T Sprague 10 µF, 25 V 1.2 2.5 × 7.1 × 3.2
695D106X0035G2T Sprague 10 µF, 35 V 1.3 2.5 × 7.6 × 2.5
†Size is in mm. ESR is maximum resistance in ohms at 100 kHz and TA = 25°C. Listings are sorted by height.
sense-pin connection
SENSE must be connected to OUT for proper operation of the regulator. Normally this connection should be
as short as possible; however, remote sense may be implemented in critical applications when proper care of
the circuit path is exercised. SENSE internally connects to a high-impedance wide-bandwidth amplifier through
a resistor-divider network, and any noise pickup on the PCB trace will feed through to the regulator output.
SENSE must be routed to minimize noise pickup. Filtering SENSE using an RC network is not recommended
because of the possibility of inducing regulator instability.
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output voltage programming
The output voltage of the TPS7201 adjustable regulator is programmed using an external resistor divider as
shown in Figure 33. The output voltage is calculated using:
VO
+
Vref
@ǒ
1
)
R1
R2
Ǔ
(1)
Where:
Vref = 1.188 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 169 kΩ to set the divider current at 7 µA and then calculate R1 using:
R1
+ǒ
VO
Vref
*
1
Ǔ@
R2 (2)
VO
VIPG
OUT
FB
R2
GND
EN
IN
<0.4 V
>2.7 V
TPS7201
Power-Good Indicator
0.1 µF250 kΩ
OUTPUT
VOLTAGE
(V) R1 R2
2.5
3.3
3.6
4
5
6.4
191
309
348
402
549
750
169
169
169
169
169
169
OUTPUT VOLTAGE
PROGRAMMING GUIDE
DIVIDER RESISTANCE
(kΩ)†
†1% values shown.
10 µF
CSR = 1 Ω
IN
5
6
4
2
8
7
1
3
+
OUT
R1
Figure 33. TPS7201 Adjustable LDO Regulator Programming
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
allowable to avoid damaging the device is 150°C. These restrictions limit the power dissipation that the regulator
can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate
the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal
to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
PD(max)
+
TJmax
*
TA
R
q
JA
Where:
TJmax is the maximum allowable junction temperature, i.e.,150°C absolute maximum and 125°C
recommended operating temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 172°C/W for the 8-terminal
SOIC and 238°C/W for the 8-terminal TSSOP.
TA is the ambient temperature.
The regulator dissipation is calculated using:
PD
+ǒ
VI
*
VO
Ǔ@
IO
Power dissipation resulting from quiescent current is negligible.
regulator protection
The TPS72xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be
appropriate.
The TPS72xx also features internal current limiting and thermal protection. During normal operation, the
TPS72xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator
operation resumes.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Feb-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS7201QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7201QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7201QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7201QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7201QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7201QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7201QPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7201QPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7201QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI Add to cart
TPS7201QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7201QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7225QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7225QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7225QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7225QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7225QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7225QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7225QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7225QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
PACKAGE OPTION ADDENDUM
www.ti.com 17-Feb-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS7230QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7230QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7230QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7230QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7230QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7230QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7233QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7233QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7233QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7233QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7233QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7233QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7233QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI Add to cart
TPS7233QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7233QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7248QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7248QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7248QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7248QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7248QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7248QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
PACKAGE OPTION ADDENDUM
www.ti.com 17-Feb-2011
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS7248QPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7248QPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7248QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI Add to cart
TPS7250QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7250QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7250QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7250QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7250QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7250QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Add to cart
TPS7250QPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7250QPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7250QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI Add to cart
TPS7250QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
TPS7250QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Feb-2011
Addendum-Page 4
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS7201QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7201QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS7225QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7225QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS7230QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS7233QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7233QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS7248QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7250QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7250QPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7201QDR SOIC D 8 2500 367.0 367.0 35.0
TPS7201QPWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS7225QDR SOIC D 8 2500 367.0 367.0 35.0
TPS7225QPWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS7230QPWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS7233QDR SOIC D 8 2500 367.0 367.0 35.0
TPS7233QPWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS7248QDR SOIC D 8 2500 367.0 367.0 35.0
TPS7250QDR SOIC D 8 2500 367.0 367.0 35.0
TPS7250QPWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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