High Voltage, Quad-Channel 12-Bit Voltage Output DAC AD5504 FEATURES GENERAL DESCRIPTION Quad-channel high voltage DAC 12-bit resolution Pin selectable 30 V or 60 V output range Integrated precision reference Low power serial interface with readback capability Integrated temperature sensor alarm function Power-on reset Simultaneous updating via LDAC Wide operating temperature: -40C to +105C The AD5504 is a quad-channel, 12-bit, serial input, digital-toanalog converter with on-chip high voltage output amplifiers and an integrated precision reference. The DAC output voltage ranges are programmable via the range select pin (R_SEL). If R_SEL is held high, the DAC output ranges are 0 V to 30 V. If R_SEL is held low, the DAC output ranges are 0 V to 60 V. The on-chip output amplifiers allow an output swing within the range of AGND + 0.5 V to VDD - 0.5 V. The AD5504 has a high speed serial interface, which is compatible with SPI(R)-, QSPITM-, MICROWIRETM-, and DSP-interface standards and can handle clock speeds of up to 16.667 MHz. APPLICATIONS Programmable voltage sources High voltage LED drivers Receiver bias in optical communications FUNCTIONAL BLOCK DIAGRAM CLR R_SEL VLOGIC VDD LDAC REFERENCE 122.36k SDI 12 SDO SCLK INPUT REGISTER A DAC REGISTER A DACA 12 1713k - VOUTA + 1713k INPUT CONTROL LOGIC 122.36k INPUT REGISTER B SYNC DAC REGISTER B DAC B 12 ALARM - VOUTB + 1713k POWER-ON RESET 122.36k INPUT REGISTER C DAC REGISTER C DAC C 12 - VOUTC + 1713k 122.36k INPUT REGISTER D DAC REGISTER D DAC D 12 - VOUTD + TEMPERATURE SENSOR DGND AGND 07994-001 POWER-DOWN CONTROL LOGIC AD5504 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009-2010 Analog Devices, Inc. All rights reserved. AD5504 TABLE OF CONTENTS Features .............................................................................................. 1 Power-Down Mode .................................................................... 14 Applications ....................................................................................... 1 DAC Channel Architecture....................................................... 14 General Description ......................................................................... 1 Selecting the Output Range ...................................................... 14 Functional Block Diagram .............................................................. 1 CLR Function.............................................................................. 14 Revision History ............................................................................... 2 LDAC Function .......................................................................... 14 Specifications..................................................................................... 4 Temperature Sensor ................................................................... 15 AC Characteristics........................................................................ 5 Power Dissipation....................................................................... 15 Timing Characteristics ................................................................ 6 Power Supply Sequencing ......................................................... 15 Absolute Maximum Ratings............................................................ 8 Serial Interface ................................................................................ 16 Thermal Resistance ...................................................................... 8 Write Mode ................................................................................. 16 ESD Caution .................................................................................. 8 Read Mode .................................................................................. 16 Pin Configuration and Function Descriptions ............................. 9 Writing to the Control Register ................................................ 16 Typical Performance Characteristics ........................................... 10 Interfacing Examples ................................................................. 18 Terminology .................................................................................... 12 Outline Dimensions ....................................................................... 19 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 19 Power-Up State ........................................................................... 14 REVISION HISTORY 10/10--Rev. 0 to Rev. A Changes to Figure 3 and Figure 4 ................................................... 7 7/09--Revision 0: Initial Version Rev. A | Page 2 of 20 AD5504 The serial interface offers the user the capability of both writing to, and reading from, most of the internal registers. To reduce power consumption at power up, only the digital section of the AD5504 is powered up initially. This gives the user the ability to program the DAC registers to the required value while typically only consuming 30 A of supply current. The AD5504 incorporates power-on reset circuitry that ensures the DAC registers power up in a known condition and remain there until a valid write to the device has taken place. The analog section is powered up by issuing a power-up command via the SPI interface. The AD5504 provides software-selectable output loads while in the power-down mode. The AD5504 has an on-chip temperature sensor. When the temperature on the die exceeds 110C, the ALARM pin (an active low CMOS output pin) flags an alarm and the AD5504 enters a temperature power-down mode disconnecting the output amplifier thus removing the short-circuit condition. The AD5504 remains in power-down mode until a software power-up command is executed. The AD5504 is available in a compact 16-lead TSSOP. The AD5504 is guaranteed to operate over the extended temperature range of -40C to +105C. Table 1. Related Device Part No. AD5501 Rev. A | Page 3 of 20 Description High Voltage, 12-Bit Voltage Output DAC AD5504 SPECIFICATIONS VDD = 10 V to 62 V; VLOGIC = 2.3 V to 5.5 V; RL = 60 k; CL = 200 pF; -40C < TA < +105C, unless otherwise noted. Table 2. Parameter ACCURACY 2 Resolution Differential Nonlinearity Integral Nonlinearity 60 V Mode 30 V Mode VOUTX Temperature Coefficient 3, 4, 5 Zero-Scale Error Zero-Scale Error Drift4 Offset Error 6 Offset Error Drift4 Full-Scale Error Full-Scale Error Drift4 Gain Error Gain Temperature Coefficient4 DC Crosstalk4 Due to Single Channel Full-Scale Output Change Due to Powering Down (Per Channel) OUTPUT CHARACTERISTICS Output Voltage Range 7 Short-Circuit Current4, 8 Capacitive Load Stability4 RL = 60 k to Load Current4 DC Output Impedance4 DC Output Leakage4 DIGITAL INPUTS Input Logic High Input Logic Low Input Current Input Capacitance4 DIGITAL OUTPUTS Output High Voltage Output Low Voltage Three-State Leakage Current SDI, SDO, SCLK, LDAC, CLR, R_SEL ALARM Output Capacitance4 POWER SUPPLIES VDD VLOGIC Quiescent Supply Current (IQUIESCENT) Logic Supply Current (ILOGIC) DC PSRR4 60 V Mode Symbol Min DNL INL Typ 1 Max Unit -1 1 Bits LSB -2 -3 +2 +3 12 10 LSB LSB ppm/C mV V/C mV V/C mV mV/C V/C % of FSR ppm of FSR/C 3 mV 60 V mode RL = 60 k to AGND or VDD 60 V mode 4 mV 60 V mode 50 VZSE 100 60 VOE -80 +120 60 VFSE -325 +275 1 350 -0.6 +0.6 AGND + 0.5 VDD - 0.5 2 1 +1 VOH VOL 60 V mode -40C to +25C; 60 V mode +25C to +105C; 60 V mode On any single channel 1 V to 4 V step 3 10 VLOGIC = 4.5 V to 5.5 V VLOGIC = 2.3 V to 3.6 V VLOGIC = 2.3 V to 5.5 V 5 V V V A pF V V ISOURCE = 200 A ISINK = 200 A 2.0 1.8 VIL IIL IIC V mA VDD = 62 V VDD = 62 V DAC code = half scale DAC code = 0 60 V mode nF mA A -1 VIH Test Conditions/Comments 0.8 1 VLOGIC - 0.4 V DGND + 0.4 V -1 -10 +1 +10 A A pF 2 62 5.5 3 V V mA 0.4 2 A 5 10 2.3 68 dB Rev. A | Page 4 of 20 On any single channel Static conditions; DAC outputs = midscale VIH = VLOGIC; VIL = DGND DAC output = full-scale AD5504 Parameter 30 V Mode POWER-DOWN MODE Supply Current Software Power-Down Mode Junction Temperature8 Symbol Min 76 Typ 1 Max Unit dB 30 50 130 A C Test Conditions/Comments IDD_PWD TJ TJ = TA + PTOTAL x JA 1 Typical specifications represent average readings at 25C, VDD = 62 V and VLOGIC = 5 V. Valid in output voltage range of (VDD - 0.5 V) to (AGND + 0.5 V). Outputs are unloaded. Includes linearity, offset, and gain drift. 4 Guaranteed by design and characterization. Not production tested. 5 VOUTX refers to VOUTA, VOUTB, VOUTC, or VOUTD. 6 DAC code = 32 for 60 V mode; DAC code = 64 for 30 V mode. 7 The DAC architecture gives a fixed linear voltage output range of 0 V to 30 V if R_SEL is held high and 0 V to 60 V if R_SEL is held low. As the output voltage range is limited by output amplifier compliance, VDD should be set to at least 0.5 V higher than the maximum output voltage to ensure compliance. 8 If the die temperature exceeds 110C, the AD5504 enters a temperature power-down mode putting the DAC outputs into a high impedance state thereby removing the short-circuit condition. Overheating caused by long term short-circuit condition(s) is detected by an integrated thermal sensor. After power-down, the AD5504 stays powered down until a software power-up command is executed. 2 3 AC CHARACTERISTICS VDD = 10 V to 62 V; VLOGIC = 2.3 V to 5.5 V; RL = 60 k; CL = 200 pF; -40C < TA < +105C, unless otherwise noted. Table 3. Parameter 1, 2 AC CHARACTERISTICS Output Voltage Settling Time 60 V Mode 30 V Mode Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Peak-to-Peak Noise 1 2 3 Min Typ Max Unit 45 25 0.65 300 170 40 5 600 600 140 4 55 35 s s V/s nV-s mV nV-s nV-s nV-s nV-s V p-p mV p-p Test Conditions/Comments 3 1/4 to 3/4 scale settling to 1 LSB, RL = 60 k 1 LSB change around major carry in 60 V mode 60 V mode 0.1 Hz to 10 Hz; DAC code = 0x800 0.1 Hz to 10 kHz; DAC code = 0x800 Guaranteed by design and characterization; not production tested. See the Terminology section. Temperature range is -40C to + 105C, typical at 25C. Rev. A | Page 5 of 20 AD5504 TIMING CHARACTERISTICS VDD = 30 V, VLOGIC = 2.3 V to 5.5 V and -40C < TA < +105C; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 3 t163 t17 4 t18 5 t19 Limit 1 60 10 10 30 15 5 0 20 20 50 15 100 20 110 55 25 50 50 5 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ s typ ns min ns max ns min s max s max s typ Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time LDAC pulse width low SCLK falling edge to LDAC rising edge CLR pulse width low CLR pulse activation time ALARM clear time SCLK cycle time in read mode SCLK rising edge to SDO valid SCLK to SDO data hold time Power-on reset time (this is not shown in the timing diagrams) Power-on time (this is not shown in the timing diagrams) ALARM clear to output amplifier turn on (this is not shown in the timing diagrams) 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 16.667 MHz. 3 Under load conditions shown in Figure 2. 4 Time from when the VDD/VLOGIC supplies are powered-up to when a digital interface command can be executed. 5 Time required from execution of power-on software command to when the DAC outputs have settled to 1 V. 2 200A VOH (MIN) - VOL (MAX) 2 CL 50pF 200A IOH Figure 2. Load Circuit for SDO Timing Diagram Rev. A | Page 6 of 20 07994-002 TO OUTPUT PIN IOL AD5504 t1 SCLK t8 t2 t3 t4 t7 SYNC t6 t5 SDI R/W D0 t9 LDAC1 t10 LDAC2 t11 CLR t13 ALARM 3 t12 VOUTx4 07994-003 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. 3IN THE EVENT OF OVERTEMPERATURE CONDITION. 4V OUTx REFERS TO ANY OF VOUTA, VOUTB, VOUTC OR VOUTD. Figure 3. Write Timing Diagram t14 SCLK SYNC R/W A2 A1 A0 X X X X D11 X X t16 t15 SDO X D10 D9 D8 Figure 4. Read Timing Diagram Rev. A | Page 7 of 20 D2 D1 D0 07994-004 SDI AD5504 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter VDD to AGND VLOGIC to DGND VOUTX to AGND1 Digital Input to DGND SDO Output to DGND AGND to DGND Maximum Junction Temperature (TJ Maximum) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Range 1 Rating -0.3 V, + 64 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VLOGIC + 0.3 V -0.3 V to VLOGIC + 0.3 V -0.3 V to +0.3 V 150C THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal resistance is for a JEDEC 4-layer(2S2P) board. Table 6. Thermal Resistance Package Type 16-Lead TSSOP ESD CAUTION -65C to +150C 260C 20 sec to 40 sec VOUTX refers to VOUTA, VOUTB, VOUTC, or VOUTD. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 8 of 20 JA 112.60 Unit C/W AD5504 CLR 1 16 VLOGIC SYNC 2 15 ALARM AD5504 14 VDD TOP VIEW (Not to Scale) 13 R_SEL SDO 5 12 VOUTA DGND 6 11 VOUTB AGND 7 10 VOUTC LDAC 8 9 VOUTD SCLK 3 SDI 4 07994-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. TSSOP Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic CLR 2 SYNC 3 SCLK 4 SDI 5 SDO 6 7 8 DGND AGND LDAC 9 10 11 12 13 VOUTD VOUTC VOUTB VOUTA R_SEL 14 VDD 15 16 ALARM VLOGIC Description Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are set to 0x000 and the outputs to zero scale. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The selected DAC register is updated after the 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 16 MHz. Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Data Output. CMOS output. This pin serves as the readback function for all DAC and control registers. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. Digital Ground Pin. Analog Ground Pin. Load DAC Input. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to update simultaneously. Alternatively, this pin can be tied permanently low. Buffered Analog Output Voltage from DAC D. Buffered Analog Output Voltage from DAC C. Buffered Analog Output Voltage from DAC B. Buffered Analog Output Voltage from DAC A. Range Select Pin. Tying this pin to DGND selects a DAC output range of 0 V to 60 V, alternatively tying R_SEL to VLOGIC selects a DAC output range of 0 V to 30 V. Positive Analog Power Supply. 10 V to 62 V for the specified performance. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Active Low CMOS Output Pin. This pin flags an alarm if the temperature on the die exceeds 110C. Logic Power Supply; 2.3 V to 5.5 V. Decouple this pin with 0.1F ceramic capacitors and 10 F capacitors. Rev. A | Page 9 of 20 AD5504 0.8 45.0025 0.4 45.0000 VOUTX (V) 0 44.9975 -0.4 44.9950 1008 2048 3056 4064 CODE 44.9925 07994-006 -0.8 32 0 0.05 0.10 0.15 07994-009 INL (LSB) TYPICAL PERFORMANCE CHARACTERISTICS 0.20 TIME (ms) Figure 6. Typical INL Figure 9. Output Settling Time (Low to High) 0.50 200 VDD = 62V VOUTx = 30V 0 -0.25 1008 2048 3056 4064 CODE 0 -100 -200 07994-007 -0.50 32 100 0 2.5 5.0 7.5 10.0 TIME (Seconds) 07994-010 OUTPUT VOLTAGE (V) DNL (LSB) 0.25 Figure 10. Output Noise Figure 7. Typical DNL 15.0050 0.70 VDD = 62V VOUTB, VOUTC, AND VOUTD POWERED DOWN IDD (mA) 0.65 15.0000 14.9975 0.60 0.55 0 0.05 0.10 0.15 TIME (ms) 0.20 Figure 8. Output Settling Time (High to Low) 0.50 0 15 30 VOUTA (V) Figure 11. IDD vs. VOUTA Rev. A | Page 10 of 20 45 60 07994-011 14.9950 07994-008 VOUTX (V) 15.0025 AD5504 2.2 0.20 VDD = 62V VOUTA = VOUTB = VOUTC = VOUTD 0.15 0.10 VOUTA (V) 2.0 1.9 0.05 0 -0.05 -0.10 VOUTA VOUTB VOUTB VOUTB -0.15 0 15 30 45 60 OUTPUT VOLTAGE (V) -0.20 07994-012 1.8 0 2 = 30V; VOUTB SWITCHING = 0V TO 30V = 0V TO 45V = 0V TO 60V 4 6 8 10 TIME (s) 07994-202 IDD (mA) 2.1 Figure 15. DAC-to-DAC Crosstalk Figure 12. IDD vs. VOUTA to VOUTD 2 6 5 -2 4 VOUTB LSBs AMPLITUDE (LSB) VOUTD 0 -4 3 -6 2 -8 1 VOUTC 5 10 15 TIME (ms) Figure 13. Digital-to-Analog Negative Glitch Impulse 10 6 4 2 0 -2 -4 10 TIME (ms) 15 07994-014 AMPLITUDE (LSB) 8 5 -0.5 0 0.5 LOAD CURRENT (mA) Figure 16. DAC-to-DAC Mismatch 12 0 0 -1.0 Figure 14. Digital-to-Analog Positive Glitch Impulse Rev. A | Page 11 of 20 1.0 07994-201 0 07994-013 VOUTA -10 AD5504 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Gain Temperature Coefficient The gain temperature coefficient is a measure of the change in gain with changes in temperature. It is expressed in (ppm of full-scale range)/C. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Digital-to-Analog Glitch Impulse Zero-Code Error Zero-code error is a measure of the output error when zero code (0x000) is loaded into the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5504 because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in millivolts. DC and AC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUTA, VOUTB, VOUTC, or VOUTD to a change in VDD for full-scale output of the DAC. It is measured in decibels. For dc PSRR, VDD is dc varied 10%. For ac PSRR, VDD is ac varied 10%. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in V/C. Offset Error A measure of the difference between VOUT (actual) and VOUT (ideal) expressed in millivolts in the linear region of the transfer function. Offset error is measured on the AD5504 with Code 32 loaded in the DAC registers for 60 V mode and with Code 64 loaded in the DAC registers for 30 V mode. Offset error is expressed in millivolts. Offset Error Drift Offset error drift is a measure of the change in offset error with a change in temperature. It is expressed in V/C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFF) is loaded into the DAC register. Full-scale error is expressed in millivolts. Full-Scale Error Drift Full-scale error drift is a measure of the change in full-scale error with a change in temperature. It is expressed in V/C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in millivolts. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in V/mA. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to (SYNC held high). It is specified in nV-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping LDAC high, and then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the glitch is expressed in nV-s. Rev. A | Page 12 of 20 AD5504 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Capacitive Load Stability Capacitive load stability refers to the ability of the amplifier to drive a capacitive load. An amplifier output is considered stable if any overshoot or ringing has stopped before approximately 1.5 times the settling time of the DAC has elapsed. Rev. A | Page 13 of 20 AD5504 THEORY OF OPERATION The AD5504 contains four DACs, four output amplifiers, and a precision reference in a single package. The architecture of a single DAC channel consists of a 12-bit resistor string DAC followed by an output buffer amplifier. The part operates from a single-supply voltage of 10 V to 62 V. The DAC output voltage range is selected via the range select, R_SEL, pin. The DAC output range is 0 V to 30 V if R_SEL is held high and 0 V to 60 V if R_SEL is held low. Data is written to the AD5504 in a 16-bit word format (see Table 8), via a serial interface. format for the AD5501 is straight binary and the output voltage follows the formula VOUT = D x Range 4096 where: D is the code loaded to the DAC. Range = 30, if R_SEL is high, and 60 if R_SEL is low. PRECISION REFERENCE POWER-UP STATE POWER-DOWN MODE Each DAC channel can be individually powered up or powered down by programming the control register (see Table 10). When the DAC channel is powered down, the associated analog circuitry turns off to reduce power consumption. The digital section of the AD5504 remains powered up. The output of the DAC amplifier can be three-stated or connected to AGND via an internal 20 k resistor, depending on the state of Bit C6 in the control register. The power-down mode does not change the contents of the DAC register to ensure that the DAC channel returns to its previous voltage when the power-down bit is set to 1. The AD5504 also offers the user the flexibility of updating the DAC registers during power-down. The control register can be read back at any time to check the status of the bits. DAC CHANNEL ARCHITECTURE The architecture of a single DAC channel consists of a 12-bit resistor string DAC followed by an output buffer amplifier (see Figure 17). The resistor string section is simply a string of resistors, each of Value R from VREF generated by the precision reference to AGND. This type of architecture guarantees DAC monotonicity. The 12-bit binary digital code loaded to the DAC register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. The output amplifier multiplies the DAC output voltage to give a fixed linear voltage output range of 0 V to 60 V if R_SEL = 0 or 0 V to 30 V if R_SEL = 1. Each output amplifier is capable of driving a 60 k load while allowing an output swing within the range of AGND + 0.5 V and VDD - 0.5 V. Because the DAC architecture gives a fixed voltage output range of 0 V to 30 V or 0 V to 60 V, the user should set VDD to at least 30.5 V or 60.5 V to use the maximum DAC resolution. The data INPUT REGISTER 12 DAC REGISTER DAC 12 GAIN VOUTx AGND 07994-015 On power-up, the power-on reset circuitry clears the bits of the control register to 0x40 (see Table 10). This ensures that the analog section is initially powered down, which helps reduce power consumption. The user can program the DAC registers to the required values while typically consuming only 30 A of supply current. The power-on reset circuitry also ensures that all the input and DAC registers power up in a known condition, 0x000, and remain there until a valid write to the device has taken place. The analog section can be powered up by setting any or all of Bit C2 to Bit C5 of the control register to 1. Figure 17. DAC Channel Architecture (Single-Channel Shown) SELECTING THE OUTPUT RANGE The output range of the DACs is selected by the R_SEL pin. When the R_SEL pin is connected to Logic 1, the DAC output voltages can be set between 0 V and 30 V. When the R_SEL pin is connected to Logic 0, the DAC output voltages can be set between 0 V and 60 V. The state of R_SEL can be changed any time when the serial interface is not being used, that is, not during a read or write operation. When the R_SEL pin is changed, the voltage on the output pin remains the same until the next write to the DAC register (and LDAC is brought low). For example, if the user writes 0x800 to the DAC register when in 30 V mode (R_SEL = 1), the output voltage is 15 V (assuming LDAC is low or has been pulsed low). When the user switches to 60 V mode (R_SEL = 0), the output stays at 15 V until the user writes a new value to the DAC register. LDAC must be low or be pulsed low for the output to change. CLR FUNCTION The AD5504 has a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to 0x000. The CLR pulse activation time, that is, the falling edge of CLR to when the output starts to change, is typically 100 ns. LDAC FUNCTION The DAC outputs can be updated using the hardware LDAC pin. LDAC is normally high. On the falling edge of LDAC, data is copied from the input registers to the DAC registers, and the DAC outputs are updated simultaneously (asynchronous update mode, see Figure 3). If the LDAC is kept low, or is low on the falling edge of the 16th SCLK, the appropriate DAC register and DAC output are updated automatically (synchronous update mode, see Figure 3). Rev. A | Page 14 of 20 AD5504 TJ = TA + (PTOTAL x JA) TEMPERATURE SENSOR The AD5504 has an integrated temperature sensor that causes the part to enter thermal shutdown mode when the temperature on the die exceeds 110C. In thermal shutdown mode, the analog section of the device powers down and the DAC outputs are disconnected, but the digital section remains operational, which is equivalent to setting the power-down bit in the control register. To indicate that the AD5504 has entered temperature shutdown mode, Bit 0 of the control register is set to 1 and the ALARM pin goes low. The AD5504 remains in temperature shutdown mode with Bit 0 set to 1 and the ALARM pin low, even if the die temperature falls, until Bit 0 in the control register is cleared to 0. POWER DISSIPATION Drawing current from any of the voltage output pins causes a temperature rise in the die and package of the AD5504. The package junction temperature (TJ) should not exceed 130C for normal operation. If the die temperature exceeds 110C, the AD5504 enters thermal shutdown mode as described in the previous section. The amount of heat generated can be calculated using the formula where: TJ is the package junction temperature. TA is the ambient temperature. PTOTAL is the total power being consumed by the AD5504. JA is the thermal impedance of the AD5504 package (see the Absolute Maximum Ratings section for this value). POWER SUPPLY SEQUENCING The power supplies for the AD5504 can be applied in any order without affecting the device. However, the AGND and DGND pins should be connected to the relevant ground plane before the power supplies are applied. None of the digital input pins (SCLK, SDI, SYNC, R_SEL and CLR) should be allowed to float during power up. The digital input pins can be connected to pull-up (to VLOGIC) or pull-down (to DGND) resistors as required. Rev. A | Page 15 of 20 AD5504 SERIAL INTERFACE initiate the next write sequence. Operate all interface pins close to the supply rails to minimize power consumption in the digital input buffers. The AD5504 has a serial interface (SYNC, SCLK, SDI, and SDO), which is compatible with SPI interface standards, as well with as most DSPs. The AD5504 allows writing of data, via the serial interface, to the input and control registers. The DAC registers are not directly writeable or readable. READ MODE The input shift register is 16 bits wide (see Table 8). The 16-bit word consists of one read/write (R/W) control bit, followed by three address bits and 12 DAC data bits. Data is loaded MSB first. WRITE MODE To write to a register, the R/W bit should be 0. The three address bits in the input register (see Table 9) then determine the register to update. The address bits (A2 to A0) are used for either DAC register selection or for writing to the control register. Data is clocked into the selected register during the remaining 12 clocks of the same frame. Figure 3 shows a timing diagram of a typical AD5504 write sequence. The write sequence begins by bringing the SYNC line low. Data on the SDI line is clocked into the 16-bit shift register on the falling edge of SCLK. On the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (that is, a change in the selected DAC/DACs input register/registers or a change in the mode of operation). The AD5504 does not require a continuous SCLK and dynamic power can be saved by transmitting clock pulses during a serial write only. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 20 ns before the next write sequence for a falling edge of SYNC to The AD5504 allows data readback via the serial interface from every register directly accessible to the serial interface, which is all registers except the DAC registers. To read back a register, it is first necessary to tell the AD5504 that a readback is required. This is achieved by setting the R/W bit to 1. The three address bits then determine the register from which data is to be read back. Data from the selected register is then clocked out of the SDO pin on the next twelve clocks of the same frame. The SDO pin is normally three-stated but becomes driven on the rising edge of the fifth clock pulse. The pin remains driven until the data from the register has been clocked out or the SYNC pin is returned high. Figure 4 shows the timing requirements during a read operation. Note that due to timing requirements of t14 (110 ns), the maximum speed of the SPI interface during a read operation should not exceed 9 MHz. WRITING TO THE CONTROL REGISTER The control register is written when Bits[DB14:DB12] are 1. The control register sets the power-up state of the DAC outputs. A write to the control register must be followed by another write operation. The second write operation can be a write to a DAC input register or a NOP write. Figure 18 shows some typical combinations. Table 8. Input Register Bit Map DB15 R/W DB14 A2 DB13 A1 DB12 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 Data DB4 DB3 DB2 DB1 DB0 Table 9. Input Register Bit Functions Bit R/W Description Indicates a read from or a write to the addressed register. A2, A1, A0 These bits determine if the input registers or the control register are to be accessed. A2 A1 A0 Function/Address 0 0 0 No operation 0 0 1 DAC A input register 0 1 0 DAC B input register 0 1 1 DAC C input register 1 0 0 DAC D input register 1 0 1 Write data contents to all four DAC input registers 1 1 0 Reserved 1 1 1 Control register Data bits D11:D0 Rev. A | Page 16 of 20 AD5504 Table 10. Control Register Functions DB15 R/W 1 2 DB14 1 DB13 1 DB12 1 DB11 X2 DB10 X2 DB9 X2 DB8 X2 DB7 X2 DB6 C6 DB5 C5 DB4 C4 DB3 C3 Read-only bit. This bit should be 0 when writing to the control register. X is don't care. Table 11. Control Register Function Bit Descriptions Bit No. DB0 Bit Name C0 DB1 DB2 C1 C2 1 DB3 C31 DB4 C41 DB5 C51 DB6 C6 If Bit C2 to Bit C5 are set to 0, the part is placed in power-down mode. WRITE TO CONTROL REGISTER NOP WRITE TO CONTROL REGISTER WRITE TO DAC REGISTER WRITE TO CONTROL REGISTER WRITE TO CONTROL REGISTER NOP WRITE TO CONTROL REGISTER WRITE TO CONTROL REGISTER WRITE TO DAC REGISTER WRITE N WRITE N + 1 WRITE N + 2 Figure 18. Control Register Write Sequences Rev. A | Page 17 of 20 07994-120 1 Description C0 = 0: the device is not in thermal shutdown mode. C0 = 1: the device is in thermal shutdown mode. C1 = 0: reserved. This bit should be 0 when writing to the control register. C2 = 0: DAC Channel A power-down (default). C2 = 1: DAC Channel A power-up. C3 = 0: DAC Channel B power-down (default). C3 = 1: DAC Channel B power-up. C4 = 0: DAC Channel C power-down (default). C4 = 1: DAC Channel C power-up. C5 = 0: DAC Channel D power-down (default). C5 = 1: DAC Channel D power-up. C6 = 0: outputs connected to AGND through a 20 k resistor (default). C6 = 1: outputs are three-stated. DB2 C2 DB1 C1 DB01 C0 AD5504 The Analog Devices ADSP-21065L is a floating point DSP with two serial ports (SPORTs). Figure 20 shows how one SPORT can be used to control the AD5504. In this example, the transmit frame synchronization (TFS) pin is connected to the receive frame synchronization (RFS) pin. The transmit and receive clocks (TCLK and RCLK) are also connected together. The user can write to the AD5504 by writing to the transmit register. When a read operation is performed, the data is clocked out of the AD5504 on the last 12 SCLKs. The DSP receive interrupt can be used to indicate when the read operation is complete. INTERFACING EXAMPLES The SPI interface of the AD5504 is designed to allow it to be easily connected to industry-standard DSPs and microcontrollers. Figure 19 shows how the AD5504 can be connected to the Analog Devices, Inc., Blackfin(R) DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5504. Programmable input/output pins are also available and can be used to read or set the state of the digital input or output pins associated with the interface. SYNC RFSx SYNC SCK SCLK TCLKx RCLKx SCLK SDO PF10 R_SEL PF9 LDAC PF8 PF7 CLR ALARM 07994-016 MISO SDI DTxA SDI DRxA SDO FLAG0 R_SEL FLAG1 LDAC FLAG2 CLR FLAG3 ALARM Figure 20. Interfacing to an ADSP-21065L DSP Figure 19. Interfacing to a Blackfin DSP Rev. A | Page 18 of 20 07994-017 TFSx SPISELx MOSI ADSP-BF531 AD5504 ADSP-21065L AD5504 AD5504 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 21. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5504BRUZ AD5504BRUZ-REEL EVAL-AD5504EBZ 1 Temperature Range -40C to +105C -40C to +105C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board Z = RoHS Compliant Part.. Rev. A | Page 19 of 20 Package Option RU-16 RU-16 AD5504 NOTES (c)2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07994-0-10/10(A) Rev. A | Page 20 of 20