AM29LV002BB-120EC - AMD - Datasheet.Directory

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21520 Rev: DAmendment/0

Issue Date: November 18, 1999

Am29LV002B

2 Megabit (256 K x 8-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations and for compatibility with high

performance 3.3 volt microprocessors

■Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29LV002 device

■High performance

— Full voltage range: access times as fast as 70 ns

— Regulated voltage range: access times as fast as

55 ns

■Ultra low power consumption (typical values at 5

MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 15 mA program/erase current

■Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

three 64 Kbyte sectors

— Supports full chip erase

— Sector Protection features:

A hardware method of locking a sector to prevent

any program or erase operations within that

sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■Unlock Bypass Mode Program Command

— Reduces overall programming time when issuing

multiple program command sequences

■Top or bottom boot block configurations

available

■Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■Minimum 1,000,000 write cycle guarantee per

sector

■20-year data retention at 125°C

— Reliable operation for the life of the system

■Package option

— 40-pin TSOP

■Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

■Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■Hardwa re reset pin (RESET#)

— Hardware method to reset the device to reading

array data

2 Am29LV002B

GENERAL DESCRIPTION

The Am29LV002B is an 2 Mbit, 3.0 volt-only Flash

memory organized as 262,144 bytes. The device is

offered in a 40-pin TSOP package. The byte-wide (x8)

data appears on DQ7–DQ0. This devi ce r equires only a

single, 3.0 volt VCC supply to perform read, program,

and erase operations. A standard EPROM programmer

can also be used to program and erase the device.

This device is manufactured using AMD’s 0.32 µm

process technology, and offers all the features and

benefits of the Am29LV002, which was manufactured

using 0.5 µm process technology. In addition, the

Am29LV002B features unlock bypass programming

and in-system sector protection/unprotection.

The standard device offers access times of 55, 70, 90,

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automati-

cally preprograms the array (if it is not already

programmed) before executing the erase operation.

During erase, t he device automatically times the erase

pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

The sector erase architecture a llows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of

memory. This can be achieved in-system or via pro-

gramming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. T rue background erase can thus be achiev ed.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied t o the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the devic e into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

Am29LV002B 3

PRODUCT SELECTOR GUIDE

Note: S ee “AC Chara cte risti cs” for full spe cifi cati ons .

BLOCK DIAGRAM

Family Part Number Am29LV002B

Speed Options Regulated Voltage Range: VCC =3.0–3.6 V -55R

Full Voltage Range: VCC = 2.7–3.6 V -70 -90 -120

Max access time, ns (tACC) 55 70 90 120

Max CE# access time, ns (tCE) 55 70 90 120

Max OE# access time, ns (tOE)30303550

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

CE#

OE#

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A17

21520D-1

4 Am29LV002B

CONNECTION DIAGRAMS

A16

A15

A14

A13

A12

A11

WE#

RESET#

RY/BY#

A17

DQ0

VSS

A10

DQ7

DQ6

DQ5

OE#

VSS

CE#

DQ4

VCC

DQ3

DQ2

DQ1

A16

A15

A14

A13

A12

A11

WE#

RESET#

RY/BY#

A17

DQ0

VSS

A10

DQ7

DQ6

DQ5

CE#

VSS

CE#

DQ4

VCC

DQ3

DQ2

DQ1

21520D-2

Reverse TSO P

Standard TSOP

Am29LV002B 5

PIN CONFIGURATION

A0–A17 = 18 addresses

DQ0–DQ7 = 8 data inputs/outputs

CE# = Chip enable

OE# = Output enable

WE# = Write enable

RESET# = Hardware reset pin, active low

RY/BY# = Ready/Busy# output

VCC = 3.0 volt-only single power supply

(see Product Select or Guide for speed

options and volt age supply toleranc es)

VSS = Device ground

NC = Pin not connected internally

LOGIC SYMBOL

21520D-3

18 8

DQ0–DQ7

A0–A17

CE#

OE#

WE#

RESET#

RY/BY#

6 Am29LV002B

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

Am29LV002B T -55R E C OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40°C to +85 °C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV002B

2 Megabit (256 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program and Erase

Valid Combinations

AM29LV002BT-55R,

AM29LV002BB-55R EC, EI, FC, FI

AM29LV002BT-70,

AM29LV002BB-70

EC, EI, EE, FC, FI, FE

AM29LV002BT-90,

AM29LV002BB-90

AM29LV002BT-120,

AM29LV002BB-120

Am29LV002B 7
DEVICE BUS OPERATIONS
This section des cribes t he requirements  and use of  the
device bus operations, which are initiated through the
internal command register . The command register itself
does not occupy any addressable memory location.
The register is compos ed of latches that  store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control lev els they require, and the res ulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV002B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 
± 
0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A17–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector 
Protection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH. 
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 12 for the timing diagram. ICC1 in
the DC Characteristics table represents the active
current specification for  reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE # to  V IH.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operat ion can e rase  one  sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselec t mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
Operation CE# OE# WE# RESET# Addresses (Note 1) DQ0–DQ7
Read L L H H AIN DOUT
Write L H L H AIN DIN
Standby VCC ± 0.3 V X X VCC ± 0.3 V X High-Z
Output Dis able L H H H X High-Z
Reset X X X L X High-Z
Sector Protect (Note 2) L H L VID Sector Address, A6 = L, A1 
= H, A0 = L DIN, DOUT
Sector Unp rot ect (No te 2) L H L VID Sector Address, A6 = H, A1 
= H, A0 = L DIN, DOUT
Temporary Se ctor  Unpro tec t X X X VID AIN DIN

8 Am29LV002B
  
array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to the Autoselect Mode and
Autoselect Command Sequence sections for more
information.
ICC2 in the DC Characteristics table represents the
active current spec ification for the write mode.  The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase  or program operat ion, the sy stem may
check the status of the operation by reading the status
bits on DQ7–DQ0. St andard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not  reading or writing to the d evice,
it can place the device in the standby mode. In this
mode, current consumption is  greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If  CE# and RESET# are held at VIH, but  not  within
VCC  ± 0.3 V, the device will be in the standb y mode, but
the standby current will be  greater . The devi ce requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
tACC + 30 ns. The automatic sleep mode is indepen-
dent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data
when addresses are changed. While in sleep mode,
output data is latched and always available to the
syst em. ICC4 in t he DC Characteristics t able represents
the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low f or at least a period of  tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS  ± 0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS ± 0.3 V, the  standby current  will
be greater.
If RESET# is asserted during  a program or eras e oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus  monitor RY/BY#  to determine wh ether
the reset operation is complete. If RESET # is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at V IH, output from the de vice is
disabled. The output pins are placed in the  high imped-
ance state.

Am29LV002B 9

Table 2. Am29LV002BT Top Bo ot Block Sector Address Table

Table 3. Am29LV002BB Bottom Boot Block Sector Address Table

Autoselect Mode

The autoselect mode provides manufacturer and

device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect

mode requires VID (11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Table 4. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order address bits (see Tables 2 and 3). Table

4 shows the remaining address bits t hat are don’t c are.

When all neces sary bits have been s et as required, the

programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

does not require VID. See “Command Definitions” for

details on using the autoselect mode.

Table 4. Am29LV002B Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector A17 A16 A15 A14 A13 Sector Size

(Kbytes) Address Range

(in hexadecimal)

SA0 0 0 X X X 64 00000h-0FFFFh

SA1 0 1 X X X 64 10000h-1FFFFh

SA2 1 0 X X X 64 20000h-2FFFFh

SA3 1 1 0 X X 32 30000h-37FFFh

SA4 1 1 1 0 0 8 38000h-39FFFh

SA5 1 1 1 0 1 8 3A000h-3BFFFh

SA6 1 1 1 1 X 16 3C000h-3FFFFh

Sector A17 A16 A15 A14 A13 Sector Size

(Kbytes) Address Range

(in hexadecimal)

SA0 0 0 0 0 X 16 00000h-03FFFh

SA1 0 0 0 1 0 8 04000h-05FFFh

SA2 0 0 0 1 1 8 06000h-07FFFh

SA3 0 0 1 X X 32 08000h-0FFFFh

SA4 0 1 X X X 64 10000h-1FFFFh

SA5 1 0 X X X 64 20000h-2FFFFh

SA6 1 1 X X X 64 30000h-3FFFFh

Description CE# OE# WE#

A17

A13

A12

A10 A9

A7 A6

A2 A1 A0

DQ7

DQ0

Manufacturer ID: AMD L L H X X VID XLXLL 01h

Device ID: Am29LV002BT

(Top Boot Block) LLHXXV

ID XLXLH 40h

Device ID: Am29LV002BB

(Bottom Boot Block) LLHXXV

ID XLXLH C2h

Sector Protec tion Verificati on L L H SA X VID XLXHL

01h

(protected)

00h

(unprotected)

10 Am29LV002B

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase o peratio ns in any sec tor. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

The primary method requires VID on the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 20 shows the timing diagram. This

method uses standard microprocessor bus cycle

timing. For sector unprotect, all unprotected sectors

must first be pro tected prior to the f irst sector un protect

write cycle.

The alternate method intended only for programming

equipment requires VID on address pin A9, OE#, and

RESET#. This method is compatible with programmer

routines written for earlier 3.0 volt-only AMD flash

devices. Publication number 21224 contains further

details; contact an AMD representative to request a

copy.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is protec ted

or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sect ors to change data in-system. The

Sector Unprotect mode is activated by setting the

RESET# pin to VID. During this mode, formerly pro-

tected sectors can be programmed or erased by

selecting the sector addresses. Once VID is removed

from the RESET# pin, all the previously protected

sectors are protected again. Figure 2 shows the algo-

rithm, and Figure 19 shows the timing diagrams, for

this feature.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 for

command definitions). In addition, the following hard-

ware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during VCC

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not

accept any write cycles. This protects data during VCC

power-up and power-down. The command register and

all internal program/erase circuit s are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical In hibit

Write cycles are inhibit ed by holding any one of OE# =

VIL, CE# = VIH or W E# = V IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Po we r - U p Wri t e Inhib it

If WE# = CE# = VIL and OE# = VIH during power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Note:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

21520D-4

Am29LV002B 11

Figure 2. In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

21520D-4

12 Am29LV002B
  
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 defines  the valid regi ster command
sequences. Writing incorrect address and data
values or writing them in the improper sequence
resets the device to reading array data. 
All addresses are latched on the falling edge of  WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the dev ice accept s an Erase S uspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system 
must
 issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command. 
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to
reading array data. Once erasure begin s, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autos elect command sequence.
Once in the  autoselect  mode, the  reset command 
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high  during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devi ces codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements.
This method is an alternative to that shown in Table 4,
which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address 00h retrieves the
manufacturer code. A read cycle at address 01h
returns the device code. A read cycle containing a
sector address (SA) and the  address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Tables 2 and 3 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The byte program command sequence programs one
byte into the device. Programming is a four-bus-cycle
operation. The program command sequence is initi-
ated by writing two unlock write cycles , followe d by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is 
not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verify the programmed cell
margin. Table 5 shows the address and data require-
ments for the byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine t he status of  the  program operati on by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits. 

Am29LV002B 13
Any commands written to the device during the
Embedded Program Algorithm are  ignored. Note  that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0”  back to a “1”.  Attempting to do  so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read  will show t hat the
data is still “0”. Only erase operat ions can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes to t he devic e fast er t han using t he stan-
dard program command sequence. The unloc k bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; th e second cycle contains the pr ogram
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and  Unlock Bypass Reset  commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. The device
then returns to reading array data.
Figure 2 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams.
Chip Erase Command Sequence
Chip erase is  a six  bus cy cle operat ion.  The chip  erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then fol lowed  by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does 
not
 require the system to
preprogram prior to erase.  The Embedded Erase algo-
rithm automatically pr eprograms and v erifi es the  entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to  provide any con-
trols or timings during t hese operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware rese t during the ch ip erase operation  imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, DQ2, or R Y/BY#. See  “W rite
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading ar ray data and addresses are
no longer latched. 
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
START
Write Program
Command Sequence
Data Poll 
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
 Completed
Increment Address
Embedded
Program
algorithm
 in progress
21520D-5
Note: See Table 5 for program command sequence.
Figure 3. Program Operati on

14 Am29LV002B
  
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for  the sector eras e command sequence.
The device does 
not
 require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations. 
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be writte n. L oading t he sector e rase  buf fer
may be done in any sequence, and the number of
sectors may be fr om one sector to  all sectors. The t ime
between these additional cycles must be less than 50
µs, otherwise the las t address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts c an be re-enabled after  the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monito r DQ3 to determin e if the sec tor
erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the
rising edge of the final WE# pulse in the command
sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All other  commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns t o reading array data a nd addresses are
no longer latched. The system can determine the
status of t he erase operation by using DQ7, DQ6,  DQ2,
or RY/BY# . (Refer to “W rite Operat ion Status” for infor-
mation on these status bits.)
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for  parameters, and to
Figure 15 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspe nd command is  written d uring a
sector erase operation,  the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The devic e “erase
suspends” all sectors selected for erasure.) Normal
read and write timings  and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a  sector is actively erasing or is  erase-sus-
pended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is com-
plete, the s ystem can once again read array dat a within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Opera tion Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts  to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselec t Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation . Further
writes of the Resume command are ignored. Another

Am29LV002B 15

Erase Suspend command can be written after the

device has resumed erasing.

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

21520D-6

16 Am29LV002B
  
Table 5. Am29LV002B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. 
Addresses latch on  the falling edge of the WE# or CE# pulse, 
whichever happens later.
PD = Data to be programmed at location P A. Data latches on the 
rising edge of WE# or C E# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or 
erased. Address bits  A17–A13 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all 
commandbus cycles are write operations.
4. Address bits A17–A11 are don’t cares for unlock and 
command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array 
data.
6. The Reset command is required to return to reading array 
data when device is in the autoselect mode, or if DQ5 goes 
high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a 
read cycle.
8. The data is 00h for an unprotected sector and 01h for a 
protected sector. See “Autoselect Command Sequence”for 
more information.
9. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
10. The Unlock Bypass Reset command is required to retu rn to 
reading array data when the device is in the unlock bypass 
mode.
1 1. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend  
mode. The Erase Suspend command is valid only during a 
sector erase operation.
12. The Erase Resume comm and is valid only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Note s 2-4)
First Second Third  Fourth  Fifth  Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Auto-
select
(Note 7)
Manufacturer ID 4 555 A A 2AA 55 555 90 X00 01
Device  ID, Top Boot Block  4 555 AA 2AA 5 5 555 90 X01 40
Device ID, Bottom Boot Block 4 555 AA 2AA 55 555 90 X01 C2
Sector Protect Verify 
(Note 8) 4 555 AA 2AA 55 555 90 (SA)
X02 00
01
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2A A 55 555 20
Unlock Bypass Program (Note 9) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 10) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 11) 1 XXX B0
Erase Resume (Note 12) 1 XXX 30
Cycles

Am29LV002B 17

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 6 and the following subsec-

tions describe the functions of these bits. DQ7,

RY/BY#, and DQ6 each of fe r a method for determining

whether a program or erase operation is complete or in

progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algo rithm is in progres s

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. I f a program address f alls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum out put

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximatel y 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protec ted.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ0 on the

following

read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 16, Data#

Polling Timings (During Embedded Algorithms), in the

“AC Characteristics” section illustrates this.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21520D-7

Figure 4. Data# Polling Algorithm

18 Am29LV002B
  
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is v alid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC.
If the output is  low (Busy), the devic e is actively er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 13, 14
and 15 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase  algorithm is in  progress or  complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either OE#
or CE# to control the read cycles. When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to
reading array data. If not all selected sectors are pro-
tected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorit hm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 6 shows the outputs for Toggle Bit I on DQ6.
Figure 5 shows the toggle bit algorithm. Figure 17 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 18 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, t he Embedded  Erase algo rithm i s in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the fi nal WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for s ector and
mode information. Ref er to  Table 6 t o compare o utputs
for DQ2 and DQ6. 
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 17 shows the toggle bit timing diagram. Figure
18 shows the differences between DQ2 and DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it mus t read DQ7–DQ0 at least t wice in a row to
determine whether a toggle bit is toggling. Typically , the
system would note and store  the value of  t he togg le bit
after the first read. After the second read, the system
would compare the new  value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data. 

Am29LV002B 19

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The s ystem may continue t o monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal puls e count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indic ates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” If the time between additional sector

erase commands from the system can be assumed to

be less than 50 µs, the system need not monitor DQ3.

See also the “Sector Erase Command Sequence”

section.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system soft ware should check the stat us

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

21520D-8

Figure 5. Toggl e Bit Algori thm

(Notes

1, 2)

(Note 1)

20 Am29LV002B

Table 6. Write Ope rati on Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Operation DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

Am29LV002B 21

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#,

and RESET# (Note 2). . . . . . . . .–0.5 V to +12.5 V

All other pins

(Note 1). . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During

voltage transitions, input or I/O pins may overshoot VSS

to –2.0 V for periods of up to 20 ns. See Figure 6.

Maximum DC voltage on input or I/O pins is VCC +0.5 V.

During voltage transitions, input or I/O pins may

overshoot to VCC +2.0 V for periods up to 20 ns. See

Figure 7.

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot VSS to –2.0 V for periods of up

to 20 ns. See Figure 6. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditio ns for exte nd ed per iod s may affe ct dev ice relia bili ty.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . .–40°C to + 85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . .–55°C to +125°C

VCC Supply Voltages

VCC for regulated voltage range . . . . . +3.0 V to 3.6 V

VCC for full voltage range . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

Figure 6. Maximum Negative Overshoot

Waveform

Figure 7. Maximum Positive Overshoot

Waveform

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21520D-9

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

21520D-10

22 Am29LV002B
  
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maxim um ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
5. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Notes 1, 2) CE# = VIL, OE# = VIH 5 MHz 7 12 mA
1 MHz 2 4
ICC2 VCC Active Write Current 
(Notes 2, 3, 5) CE# = VIL, OE# = VIH 15 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode 
(Notes 2, 4) VIH = VCC ± 0.3 V; 
VIL = VSS ± 0.3 V 0.2 5 µA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min  0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage (Note 
4) 2.3 2.5 V

Am29LV002B 23

DC CHARACTERISTICS

Zero Power Flash

00 500 1000 1500 2000 2500 3000 3500 4000

Suppl y Current in mA

Time in ns

Note: Addresses are switching at 1 MHz

21520D-11

Figure 8. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

12345

Frequency in MHz

Supply Current in mA

Note: T = 25

21520D-12

Figure 9. Typical ICC1 vs. Frequency

2.7 V

3.6 V

24 Am29LV002B

TEST CONDITIONS

Table 7. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Test

21520D-13

Figure 10. Test Setup

Note: Diodes are IN3064 or equivalent

Test Condition -55R,

-70, -90,

-120 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput

21520D-14

Figure 11. Input Waveforms and Measurement Levels

Am29LV002B 25

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 10 and Table 7 for test specifications.

Parameter

Description

Speed Option

JEDEC Std Test Setup -55R -70 -90 -120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 55 70 90 120 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns

tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 15 25 30 30 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 15 25 30 30 ns

tOEH Output Enable

Hold Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tAXQX tOH Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

21520D-15

Figure 12. Read Operations Timings

26 Am29LV002B

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100 % test ed.

Parameter

Description Test Setup All Speed Options UnitJEDEC Std

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (Se e Note ) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

21520D-16

Figure 13. RESET# Timings

Am29LV002B 27

AC CHARACTERISTICS

Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Spe ed Op tion s

JEDEC Std Description -55R -70 -90 -120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns

tWLAX tAH Address Hold Time Min 45 45 45 50 ns

tDVWH tDS Data Setup Time Min 35 35 45 50 n s

tWLWH tWP Write Pulse Width Min 35 35 35 50 ns

tAVWL tAS Addre ss Set up Time Min 0 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Outpu t Ena ble Set up Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWHWL tWPH Write Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

28 Am29LV002B

AC CHARACTERISTICS

OE#

WE#

CE#

Data

Addresses

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

BUSY

Note: PA = program address, PD = program data, DOUT is the true data at the program address.

21520D-17

Figure 14. Program Operation Timings

Am29LV002B 29

AC CHARACTERISTICS

OE#

CE#

Addresses

WE#

Data

2AAh SA

WPH

555h for chip erase

10 for Chip Erase

30h

VCS

55h

Progress Complete

WHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

BUSY

Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

21520D-18

Figure 15. Chip/Sector Erase Operation Timings

30 Am29LV002B

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21520D-19

Figure 16. Data# Polling Timings (During Embedd ed Alg orithm s)

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

21520D-20

Figure 17. Toggle Bit Timings (During Embedded Algorithms)

Am29LV002B 31

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

21520D-21

Figure 18. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Pro gra m

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

tVIDR

12 V

0 or 3 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 3 V

21520D-22

Figure 19. Temporary Sector Unprotect Timing Diagram

32 Am29LV002B

AC CHARACTERISTICS

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

ESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

21520D-23

Figure 20. Sector Protect/Unprotect Timing Diagram

Am29LV002B 33

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std Description -55R -70 -90 -120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns

tELAX tAH Address Hold Time Min 45 45 45 50 ns

tDVEH tDS Data Setup Time Min 35 35 45 50 ns

tELEH tCP Write Pulse Width Min 35 35 35 50 ns

tAVEL tAS Address Setup Time Min 0 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS CE# Setup Time Min 0 ns

tEHWH tWH CE# Hold Time Min 0 ns

tEHEL tCPH Write Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs

tWHWH2 tWHWH2 Sector Erase Op era tion (Note 2) Typ 0.7 sec

34 Am29LV002B

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, DOUT is the data written

to the device.

2. Figure indicates the last two bus cycles of the command sequence.

21520D-24

Figure 21. Alternate CE# Controlled Write Operation Timings

Am29LV002B 35

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V (3.0 V for -55R), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5

for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test con ditio ns TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s Exclud es 00h progra mm ing

prior to erasure (Note 4)

Chip Erase Time 5 s

Byte Programming Time 9 300 µs Excludes system level

overhead (No te 5)

Chip Programming Time (Note 3) 2.3 6.8 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE #, and RESE T#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

36 Am29LV002B

PHYSICAL DIMENSIONS

TS 040—40-Pin Standard TSOP (measured in millimeters)*

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

Am29LV002B 37

PHYSICAL DIMENSIONS*

TSR040—40-Pin Reverse TSOP (measured in millimeters)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

38 Am29LV002B

REVISION SUMMARY

Revision B

Expanded data sheet from Advanced Information to

Preliminary version.

Distinctive Characteristics

Changed “Manufactured on 0.35 µm process tech-

nology” to “Manufactured on 0.32 µm process

technology”.

General Description

Second paragraph:

Changed “This device is manufac-

tured using AMD’s 0.35 µm process technology” to

“This device is manufactured using AMD’s 0.32 µm

process technology”

Revision B+1

Global

Added the -55R speed option; deleted the -80 speed

option.

DC Characteristics

Added the note on maximum ICC specifications to

table.

AC Characteristics

Alternate CE# Controlled Erase/Progran Operations:

Corrected the -90 tCP specification.

Revision C

Distinctive Characteri stics

Added:

■20-year data retention at 125°C

— Reliable operation for the life of the system

AC Characteristics—Erase/Program Operations

tDVWH

: Changed the -55R speed option to 35 ns from

20 ns.

tWLWH

: Changed the -55R speed option to 35 ns from

30 ns.

AC Characteristics—Alternate CE# Controlled

Erase/Program Operations

tDVEH

: Changed the -55R speed option to 35 ns from

20 ns.

TSOP Pin Capacitance

Changed from “TSOP and SO Pin Capacitance”.

Revision D (November 18, 1999)

AC Characteristics—Figure 14. Pr ogram

Operations Timing and Figure 15. Chip/Sector

Erase Operations

Deleted tGHWL and changed OE# waveform to start at

high.

Physical Dimensions

Replaced figures with more detailed illustrations.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.