MCP3021A5T-E/OT - MICROCHIP TECHNOLOGY

 2003-2013 Microchip Technology Inc. DS21805B-page 1

MCP3021

Features

• 10-bit resolution

• ±1 LSB DNL, ±1 LSB INL max.

• 250 µA max conversion current

• 5 nA typical standby current, 1 µA max.

•I

2C™ compatible serial interface

-100kHz I

2C Stand ard mod e

-400kHz I

2C Fast mode

• Up to 8 devices on single 2-wire bus

• 22. 3 ksps in I2C Fa st mode

• Single-ended analog input channel

• On-chip sample and hold

• On-chip conversion clock

• Single supply specified operation: 2.7V to 5.5V

• Temperature range:

- Extended: -40°C to +125°C

•Small SOT-23 package

Applications

• Data Logging

• Multi-zone Monitoring

• Hand Held Portable Applications

• Battery Powered Test Equipment

• Remote or Isolated Data Acquisition

Package Type

Description

The Microchip Technology Inc. MCP3021 is a succes-

sive approximation A/D converter (ADC) with 10-bit

resolution. Available in the SOT-23 package, this

device provides one single-ended input with very low

power consumption. Based on an advanced CMOS

technology, the MCP3021 provides a low maximum

conversion current and standby current of 250 µA and

1 µA, respectively. Low current consumption, com-

bined with the small SOT -23 package, make this device

ideal for battery-powered and remote data acquisition

applications.

Communication to the MCP3021 is performed using a

2-wire I2C compatible interface. Standard (100 kHz)

and Fast (400 kHz) I2C modes are available with the

device. An on-chip conversion clock enables indepen-

dent timing for the I2C and conversion clocks. The

device is also addressable, allowing up to eight devices

on a single 2-wire bus.

The MCP3021 runs on a single supply voltage that

operates over a broad range of 2.7V to 5.5V. This

device also provides excellent linearity of ±1 LSB d iffer-

ential non-linearity (DNL) and ±1 LSB integral non-

linearity (INL), maximum.

Functional Block Diagram

5-Pin SOT-23A

SCL

AIN

MCP3021

SDA

VSS

VDD

Comparator

10-Bit SAR

DAC

AIN

VSS

VDD

SCL SDA

Clock

Control Logic

–

Sample

and

Hold

I2C™

Interface

Low Power 10-Bit A/D Converter With I2C™ Interface

MCP3021

DS21805B-page 2  2003-2013 Microchip Technology Inc.

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VDD...................................................................................7.0V

Analog input pin w.r.t. VSS....................... -0.6V to VDD +0.6V

SDA and SCL pins w.r.t . VSS.. ...... .. . ...... .. .- 0 . 6 V to VDD +1.0V

Storage temperature .......... ...........................-65°C to +150°C

Ambient temp. with power applied................-65°C to +125°C

Maximum Junction Temperature...................................150°C

ESD protection on all pins (HBM) ................. ................ 4kV

† Stresses above those listed under “ Maximum ratings” ma y

cause permanent damage to the device. This is a stress rating

only and functional operation of the device at those or any

other conditions above those indicated in the operational list-

ings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reli-

ability.

PIN FUNCTION TABLE

Name Function

VDD +2.7V to 5.5V Power Supply

VSS Ground

AIN Analog I nput

SDA Serial Data In/O ut

SCL Serial Cloc k In

DC ELECTRICAL SP ECIFICATIONS

Electri cal Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k

TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).

Parameters Sym Min Typ Max Units Conditions

DC Accuracy

Resolution 10 bits

Integral Nonl ine ari ty INL — ±0 .25 ±1 LSB

Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes

Offset Error — ±0.75 ±3 LSB

Gain Error — -1 ±3 LSB

Dynamic Performance

Total Harmonic Distortion THD — -70 — dB VIN = 0.1V to 4.9V @ 1 kHz

Signal to Noise and Distortion SINAD — 60 — dB VIN = 0.1V to 4.9V @ 1 kHz

Spuriou s Free D yna mi c Ra ng e SFDR — 74 — dB VIN = 0.1V to 4.9V @ 1 kHz

Analog Input

Input Voltage Range VSS-0.3 — VDD+0.3 V 2.7V  VDD  5.5V

Leakage Current -1 — +1 µA

SDA/SCL (open-drain output)

Data Coding Format Straight Binary

High-level input voltage VIH 0.7 VDD ——V

Low-level input voltage VIL ——0.3 V

DD V

Low-level output voltage VOL ——0.4VI

OL = 3 mA, RPU = 1.53 k

Hysteresis of Schmitt trigger inputs VHYST — 0.05VDD —Vf

SCL = 400 kHz only

Note 1: Sample ti me is the time betwe en con versi ons af ter the addres s byte h as been se nt to the c onver ter. Refer

to Figure 5-6.

2: This parameter is periodically sampled and not 100% tested.

3: RPU = Pull-up resistor on SDA and SCL.

4: SDA and SCL = V SS to VDD at 400 kHz.

5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for rela tion to

SCL.

 2003-2013 Microchip Technology Inc. DS21805B-page 3

MCP3021

TEMPE RATURE SPECIFICATIONS

Input leakage current ILI -1 — +1 µA VIN = VSS to VDD

Output lea ka ge current ILO -1 — +1 µA VOUT = VSS to VDD

Pin capacitance

(all input s /ou tpu ts) CIN,

COUT

——10pFT

AMB = 25°C, f = 1 MHz;

(Note 2)

Bus C apacitanc e CB— — 400 pF SDA drive low, 0.4V

Power Requireme nts

Operati ng Voltage VDD 2.7 — 5.5 V

Conve rsi on C urren t IDD —175250µA

Standby Current IDDS —0.005 1 µASDA, SCL = V

Active bus current IDDA — — 120 µA Note 4

Conversion Rate

Conve r si on Time tCONV —8.96 — µsNote 5

Analog Input Acquisition Time tACQ —1.12 — µsNote 5

Sample Rate fSAMP — — 22.3 ksp s fSCL = 400 kHz (Note 1)

Electri cal Characteristics: All parameters apply across the operating voltage range.

Parameters Symbol Min Typ Max Units Conditions

Temperature Ranges

Extended Temperature Range TA-40 — +125 °C

Operati ng Tempe rature Range TA-40 — +125 °C

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SOT23A JA —256 —°C/W

DC ELECTRICAL SP ECIFICATIONS (CONTINUED)

Electri cal Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k

TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).

Parameters Sym Min Typ Max Units Conditions

Note 1: Sample ti me is the time betwe en con versi ons af ter the addres s byte h as been se nt to the c onver ter. Refer

to Figure 5-6.

2: This parameter is periodically sampled and not 100% tested.

3: RPU = Pull-up resistor on SDA and SCL.

4: SDA and SCL = V SS to VDD at 400 kHz.

5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for rela tion to

SCL.

MCP3021

DS21805B-page 4  2003-2013 Microchip Technology Inc.

TIMING SPECIFICATIONS

FIGURE 1-1: Standard and Fast Mode Bus Timing Data.

Electri cal Characteristics: All parameters apply at VDD = 2.7V - 5.5 V, VSS = GND, TA = -40°C to +85°C.

Parameters Sym Min Typ Max Units Conditions

I2C Standard Mode

Clock frequency fSCL 0—100kHz

Clock high time THIGH 4000 — — ns

Clock low time TLOW 4700 — — ns

SDA and SCL ris e time TR— — 1000 ns From VIL to VIH (Note 1)

SDA and SCL fall time TF——300nsFrom V

IL to VIH (Note 1)

START condition hold time THD:STA 4000 — — ns

START condition setup time TSU:STA 4700 — — ns

Data input setup time TSU:DAT 250 — — ns

STOP condition setup time TSU:STO 4000 — — ns

STOP condition hold time THD:STD 4000 — — ns

Output valid from clock TAA — — 3500 ns

Bus free time TBUF 4700 — — ns Note 2

Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1)

I2C Fast Mode

Clock frequency FSCL 0—400kHz

Clock high time THIGH 600 — — ns

Clock low time TLOW 1300 — — ns

SDA and SCL ris e time TR20 + 0.1CB— 300 ns From VIL to VIH (Note 1)

SDA and SCL fall time TF20 + 0.1CB— 300 ns From VIL to VIH (Note 1)

START condition hold time THD:STA 600 — — ns

START condition setup time TSU:STA 600 — — ns

Data input hold time THD:DAT 0—0.9ms

Data input setup time TSU:DAT 100 — — ns

STOP condition setup time TSU:STO 600 — — ns

STOP condition hold time THD:STD 600 — — ns

Output valid from clock TAA ——900ns

Bus free time TBUF 1300 — — ns Note 2

Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1)

Note 1: This parameter is periodically sampled and not 100% tested.

2: Time the bus must be free before a new transmission can start.

TFTHIGH VHYS TR

TSU:STA

TSP THD:STA

TLOW THD:DAT TSU:DAT TSU:STO

TBUF

TAA

SCL

SDA

OUT

 2003-2013 Microchip Technology Inc. DS21805B-page 5

MCP3021

2.0 TYPICAL PERFORMANCE CURVES

Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-1: INL vs. Clock Rate.

FIGURE 2-2: INL vs. VDD - I2C Standard

Mode (fSCL = 100 kHz).

FIGURE 2-3: INL vs. Code

(Represen tative Par t) .

FIGURE 2-4: INL vs. Clock Rate

(VDD =2.7V).

FIGURE 2-5: INL vs. VDD - I2C Fast Mode

(fSCL = 400 kH z ) .

FIGURE 2-6: INL vs. Code

(Representative Part, VDD = 2.7V).

Note: The g r ap hs and t ables provid ed fol low i ng thi s n ote are a statistical s umm ar y b as ed on a limite d n um ber of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 100 200 300 400

I2C Bus Rate (kHz)

INL (LSB)

Positive INL

Negative INL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

2.533.544.555.5

VDD (V)

INL (LSB)

Positive INL

Negative INL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0 256 512 768 1024

Digital Code

INL (LSB)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 100 200 300 400

I2C Bus Rate (kHz)

INL (LSB)

Positive INL

Negative INL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

2.533.544.555.5

VDD (V)

INL (LSB)

Positive INL

Negative INL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0 256 512 768 1024

Digital Code

INL (LSB)

MCP3021

DS21805B-page 6  2003-2013 Microchip Technology Inc.

Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-7: INL vs. Te mpe ratur e.

FIGURE 2-8: DNL vs. Clock Rate.

FIGURE 2-9: DNL vs. VDD - I2C Standard

Mode (fSCL = 100 kHz).

FIGURE 2-10: INL vs. Te mpe r ature

(VDD =2.7V).

FIGURE 2-11: DNL vs. Clock Rate

(VDD =2.7V).

FIGURE 2-12: DNL vs. VDD - I2C Fast

Mode (fSCL = 400 kHz).

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

Tempera ture (°C)

INL (LSB)

Positive INL

Negative INL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 100 200 300 400

I2C Bus Rate (kHz)

DNL (LS B)

Positive D NL

Negative DNL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

DNL (LSB)

Positive DNL

Negative DNL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50-250 255075100125

Temperature (°C)

INL (LSB)

Negative INL

Positive INL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 100 200 300 400

I2C Bus Rate (kHz)

DNL (LSB)

Negative DNL

Positive DNL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

2.533.544.555.5

VDD (V)

DNL (LS B)

Positive DNL

Negative DNL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

 2003-2013 Microchip Technology Inc. DS21805B-page 7

MCP3021

Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-13: DNL vs. Code

(Represen tative Par t) .

FIGURE 2-14: DNL vs. Temperature.

FIGURE 2-15: Gain Error vs. VDD.

FIGURE 2-16: DNL vs. Code

(Representative Part, VDD = 2.7V).

FIGURE 2-17: DNL vs. Te mpe r ature

(VDD =2.7V).

FIGURE 2-18: Offset Error vs. VDD.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0 256 512 768 1024

Digital Code

DNL (LSB)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

DNL (LSB)

Negative DNL

Positive DNL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

-1

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

2.533.544.555.5

VDD (V)

Gain Error (LSB)

Fast Mode

(fSCL=100 kHz) Standard Mode

(fSCL=400 kHz)

-0.025

-0.05

-0.075

-0.1

-0.15

-0.175

-0.2

-0.225

-0.25

-0.125

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0 256 512 768 1024

Digital Code

DNL (LSB)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

DNL (LSB)

Positive DNL

Negative DNL

0.25

0.20

0.15

0.10

0.005

-0.005

-0.10

-0.15

-0.20

-0.25

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

2.533.544.555.5

VDD (V)

Offset Error (LSB)

fSCL = 100 kHz & 400 kHz

0.25

0.225

0.2

0.175

0.15

0.1

0.075

0.05

0.025

0.125

MCP3021

DS21805B-page 8  2003-2013 Microchip Technology Inc.

Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-19: Gain Error vs. Temperature.

FIGURE 2-20: SNR vs. Input Frequency.

FIGURE 2-21: THD vs. Input Frequency.

FIGURE 2-22: Offset Error vs.

Temperature.

FIGURE 2-23: SINAD vs . Input Fre quen cy.

FIGURE 2-24: SINAD vs . Input Si gna l

Level.

-1.5

-1

-0.5

0.5

1.5

-50 -25 0 25 50 75 100 125

Temperature (°C)

Gain Error (LSB)

VDD = 5V

VDD = 2.7V

0.375

0.250

0.125

-0.125

-0.250

-0.375

110

Input Fr e quency (kHz )

SNR (dB)

VDD = 5V

VDD = 2.7V

-96

-84

-72

-60

-48

-36

-24

-12

110

Input Frequency (kHz)

THD (dB)

VDD = 2. 7 V VDD = 5V

-12

-24

-36

-48

-60

-72

-84

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

Offset Error (LSB)

VDD = 5V

VDD = 2.7V

0.50

0.45

0.40

0.35

0.30

0.25

0.15

0.10

0.05

0.20

110

Input Frequency (kHz)

SINAD (dB)

VDD = 5V

VDD = 2.7V

-40 -30 -20 -10 0

Input Signal Level (dB)

SINAD (dB)

VDD = 5V

VDD = 2.7 V

 2003-2013 Microchip Technology Inc. DS21805B-page 9

MCP3021

Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-25: ENOB vs. VDD.

FIGURE 2-26: SFDR vs. Input Frequency.

FIGURE 2-27: Spectrum Using I2C Fast

Mode (Representative Part, 1 kHz Input

Frequency).

FIGURE 2-28: ENOB vs. Input Frequency.

FIGURE 2-29: Spectrum Using I2C

Standard Mode (Repres entativ e Par t, 1 kHz

Input Frequency).

FIGURE 2-30: IDD (Conversion) vs. VDD.

11.5

11.55

11.6

11.65

11.7

11.75

11.8

11.85

11.9

11.95

2.533.544.555.5

VDD (V)

ENOB (rms)

9.95

9.90

9.85

9.80

9.75

9.70

9.65

9.60

9.55

9.50

110

Input Frequency (kHz)

SFDR (dB)

VDD = 2.7V

VDD = 5 V

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 2000 4000 6000 8000 10000

Frequency (Hz)

Amplitude (dB)

9.5

10.5

11.5

110

Input Fr e quency (kHz )

ENOB (rms)

VDD = 2.7V VDD = 5V

9.5

9.0

8.5

8.0

7.7

7.0

-130

-110

-90

-70

-50

-30

-10

0 500 1000 1500 2000 2500

Frequency (Hz)

Amplitude (dB)

100

150

200

250

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

IDD (µA)

MCP3021

DS21805B-page 10  2003-2013 Microchip Technology Inc.

Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-31: IDD (Conversion) vs. Clock

Rate.

FIGURE 2-32: IDD (Conversion) vs.

Temperature.

FIGURE 2-33: IDDA (Active Bus) vs. VDD.

FIGURE 2-34: IDDA (Active Bus) vs. Clock

Rate.

FIGURE 2-35: IDDA (Active Bu s) vs.

Temperature.

FIGURE 2-36: IDDS (Standby) vs. VDD.

100

120

140

160

180

200

0 100 200 300 400

I2C Clock Rate (kHz)

IDD (µA)

VDD = 5V

VDD = 2.7V

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature (°C)

IDD (µA)

VDD = 5V

VDD = 2.7V

100

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

IDDA (µA)

100

0 100 200 300 400

I2C Clock Rate (kHz)

IDDA (µA)

VDD = 5V

VDD = 2.7V

100

-50 -25 0 25 50 75 100 125

Temperature (°C)

IDDA (µA)

VDD = 5V

VDD = 2.7V

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

IDDS (pA)

 2003-2013 Microchip Technology Inc. DS21805B-page 11

MCP3021

Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-37: IDDS (Standby) vs.

Temperature.

FIGURE 2-38: Analog Input Leakage vs.

Temperature.

2.1 Test Circuit

FIGURE 2-39: Typical Test Configuration.

0.0001

0.001

0.01

0.1

100

1000

-50 -25 0 25 50 75 100 125

Temperature (°C)

IDDS (nA)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Tempera ture (°C)

Analog Input Leakage (nA)

0.1 µF

AIN MCP3021

VDD = 5V

VCM = 2.5V

VIN

VDD

VSS

10 µF

SDA

SCL

2k2k

MCP3021

DS21805B-page 12  2003-2013 Microchip Technology Inc.

3.0 PIN FUNCTIONS

TABLE 3-1: PIN FUNCTION TABLE

3.1 VDD and VSS

The VDD pi n, with respec t to VSS, provides power to the

device, as well as a voltage reference for the conver-

sion process. Refer to Section 6.4, “Device Power and

Layout Considerations”, for tips on power and

grounding.

3.2 Analog Input (AIN)

AIN is the input pin to the sample and hold circuitry of

the Successive Approximation Register (SAR) con-

verter. Care should be take n in driving this pin. Refe r to

Section 6.1, “Driving the Analo g Inpu t”. For proper con-

versions , the voltage on this pin can vary from VSS to

VDD.

3.3 Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open-drain

terminal, therefore, the SDA bus requires a pull-up

resistor to VDD (typically 10 k for 100 kHz and 2 k

for 400 kHz SCL clock speeds (refer to Section 6.2,

“Connecting to the I2C Bus”).

For normal data transfer , SDA is allowed to change only

during SCL low . Changes during SCL high are reserved

for indi cating the START and STOP conditions (refer to

Section 5.1, “I2C Bus Characteristics”).

3.4 Serial Clock (SCL)

SCL is a n inpu t pin used t o sy nchroniz e the d at a trans -

fer to and from the device on the SDA pin and is an

open-drai n terminal . Therefor e, the SCL bus re quires a

pull-up re sistor to VDD (ty pically, 10 k for 100 kHz and

2k for 400 kHz SCL clock speeds. Refer to

Section 6.2, “Connecting to the I2C Bus”).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the START and STOP

conditions (refer to Section 6.1, “Driving the Analog

Input”).

Name Function

VDD +2.7V to 5.5V Power Supply

VSS Ground

AIN Analog Input

SDA Serial Data In/Out

SCL Serial Clock In

 2003-2013 Microchip Technology Inc. DS21805B-page 13

MCP3021

4.0 DEVICE OPERATION

The MCP3021 employs a classic SAR architecture.

This architecture uses an internal sample and hold

cap acitor to store the anal og input while the conver sion

is taking place. At the end of the acquisition time, the

input switch of the con verter opens and the device uses

the collected charge on the internal sample and hold

capacitor to produce a serial 10-bit digital output code.

The acquisition time and conversion is self-timed using

an int ernal clock. After each conver sion, the res ults are

stored in a 10-bit register that can be read at any time.

Comm uni ca tion with the de vi ce is ac com plished with a

2-wire I2C interface. Maximum sample rates of

22.3 ksps are p oss ible with the MCP3 021 in a continu-

ous conversion mode and an SCL clock rate of

400 kHz.

4.1 Digit al Output Code

The digital output co de produced by the M C P30 21 is a

function of the input signal and power supply voltage

(VDD). As the VDD level is reduced, the LSB size is

reduced accordingly . The theoretical LSB size is shown

below.

EQUATION

The outp ut code of t he MCP3021 is transm itted seria lly

with MSB first, the format of the code being straight

binary.

4.2 Conversion Time (tCONV)

The conversion time is the time required to obtain the

digital result once the analog input is disconnected

from the holding capacitor. With the MCP3021, the

specif ied c onvers ion t ime is typic ally 8.96 µs. This time

is depen dent on the internal os cillator a nd indepen dent

of SCL.

4.3 Acquisition Time (tACQ)

The a cquis ition t ime i s the am ount of time the sample

cap array is acquiring charge.

The acquisition time is, typically, 1.12 µs. This time is

depende nt on the inter nal oscilla tor and ind ependent of

SCL.

4.4 Sample Rate

Sample rate is the inverse of the maximum amount of

time that is require d from the poi nt of ac qui si tion of the

first con version to th e point of ac quisition of the secon d

conversion.

The sample rate can be measured either by single or

continuous conversions. A single conversion includes

a Start Bit, Address Byte, Two Data Bytes and a Stop

bit. This sample rate is measured from one Start Bit to

the next Start Bit.

For continuous conversions (requested by the Master

by issuing an acknowledge after a conversion), the

maximum sample rate is measured from conversion to

conversi on, or a total of 18 clocks (two data bytes and

two Acknowledge bits). Refer to Section 5-2, “Device

Addressing”.

FIGURE 4-1: Transfer Function.

LSB SIZE VDD

1024

------------

VDD = Supply voltage

AIN

00 0000 0001 (1)

00 0000 0011 (3)

11 1111 1110 (1022)

Output Code

VDD-1.5 LSB

.5 LSB

1.5 LSB VDD-2.5 LSB

2.5 LSB

00 0000 0000 (0)

00 0000 0010 (2)

11 1111 1111 (1023)

MCP3021

DS21805B-page 14  2003-2013 Microchip Technology Inc.

4.5 Differential Non-Li nearity (DNL)

In the id eal ADC trans fer function, e ach code has a uni-

form width. That is, the difference in analog input volt-

age is constant from one code transition point to the

next. DNL specifies the deviation of any code in the

transfer function from an ideal code width of 1 LSB.

The DNL is determined by subtracting the locations of

successive code transition points after compensating

for any gain and offset errors. A positive DNL implies

that a code is longer than the ideal code width, while a

negative DNL implies that a code is shorter than the

ideal width.

4.6 Integral Non-Linearity (INL)

INL is a result of cumulative DNL errors and specifies

how much the overall transfer function deviates from a

linear response. The method of measurement used in

the MCP3021 ADC to determine INL is the “end-point”

method.

4.7 Offset Error

Off set er ror is define d as a dev iation of the code trans i-

tion points that are present across all output codes.

This has the effect of shifting the entire A/D transfer

functio n. The offs et error is measure d by finding the d if-

ference between the actual location of the first code

transiti on and the des ired lo catio n of the f irst tran sitio n.

The ideal location of the first code transition is located

at 1/2 LSB above VSS.

4.8 Gain Error

The gain error determines the amount of deviation from

the ideal slope of the ADC tr ansfer fu nctio n. Before th e

gain error is determined, the offset error is measured

and subtracted from the conversion result. The gain

erro r c a n the n be de t erm in e d by fi nd i ng th e loc at i on of

the last code transition and comparing that location to

the ideal location. The ideal location of the last code

transition is 1.5 LSBs below full-scale or VDD.

4.9 Conversion Current (IDD)

The average amount of current over the time required

to perform a 10-bit conversion.

4.10 Active Bus Current (IDDA)

The average amount of current over the time required

to monitor the I2C bus. Any current the device con-

sumes while it is not being addressed is referred to as

Active Bus c urrent.

4.11 Standby Current (IDDS)

The average amount of current required while no con-

version is occurring and while no data is being ou tput

(i.e., SCL and SDA lines are quiet).

4.12 I2C Standard Mode Timing

I2C specification where the frequency of SCL is

100 kHz.

4.13 I2C Fast Mode Timing

I2C specification where the frequency of SCL is

400 kHz.

 2003-2013 Microchip Technology Inc. DS21805B-page 15

MCP3021

5.0 SERIAL COMMUNICATIONS

5.1 I2C Bus Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high wi ll be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (refer to Figure 5-1).

5.1.1 BUS NOT BUSY (A)

Both data and clock lines remain high.

5.1.2 START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a START condition. All

commands must be preceded by a START condition.

5.1.3 S TOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a STOP condition. All

operati ons must be ende d with a STOP condition.

5.1.4 DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the high period of t he clock signal.

The data on the line must be changed during the low

period of the cl ock signal. There is one cloc k puls e per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

data bytes transferred between the START and STOP

conditions is determined by the master device and is

unlimited.

5.1.5 ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge bit after the reception of

each byte. The master device must generate an extra

clock pulse that is a ssociated with th is acknowledge bit.

The device that acknowledges has to pull down the

SDA line d uring th e ackn owledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge-related clock pulse. Setup

and hold times must be taken into account. During

reads, a master device must signal an end of data to

the slave by not generating an acknowledge bit on the

last byte that has been clocked out of the slave (NAK).

In th is ca se, the sl ave ( MC P3021 ) wi ll r eleas e th e bus

to allow the master device to generate the STOP con-

dition.

The MCP3021 supports a bidirectional 2-wire bus and

dat a trans miss ion p rotocol . The de vice t hat sends dat a

onto the bu s is the transm itter and the dev ice rec eivin g

data is the receiver. The bus has to be controlled by a

master device that generates the serial clock (SCL),

controls the bus access and gen erat es the START and

ST OP cond itions, wh ile the M CP3021 works as a slav e

device. Both master and slave devices can operate as

either transmitter or receiver, but the master device

determines which mode is activated.

FIGURE 5-1: Data Transfer Sequence on the Serial Bus.

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MCP3021

DS21805B-page 16  2003-2013 Microchip Technology Inc.

5.2 Device Addressing

The addres s byte is the firs t byte receive d following the

START cond iti on from the m aster dev ic e. The first p art

of the c ontrol byte co nsists of a 4-bit device code, which

is set to 1001 fo r the MC P3021. Th e device code is fol-

lowed by three address bits: A2, A1 and A0. The default

addr es s bi ts a re 101 (contact the Microchip factory for

additional address bit options).The address bits allow

up to eigh t MCP302 1 devices on the same b us and are

used to determine which device is accessed.

The eighth bit of the slave address determines if the

master device wants to read conversion data or write to

the MCP3021. When set to a ‘1’, a read operation is

selected. When set to a ‘0’, a write operation is

selected. There are no writable registers on the

MCP3021, therefore, this bit must be set to a ’1’ to

initiate a conversion.

The MC P30 21 is a s la ve de vi ce that is comp at ibl e w i th

the 2-wire I2C serial interface protocol. A hardware

connection diagram is shown in Figure 6-2. Communi-

cation is initiated by the microcontroller (master

device), which sends a START bit followed by the

address byte.

On completion of the conversion(s) performed by the

MCP30 21, the microcontroll er must send a STO P bit to

stop the communication.

The last bit in the device address byte is the R/W bit.

When this bit is a logic ‘1’, a conversion will be exe-

cuted. Setting this bit to logic ‘0’ will also result in an

“acknowledge” (ACK) from the MCP3021, with the

device then releasing the bus. This can be used for

device polling (refer to Section 6.3, “Device Polling”).

FIGURE 5-2: Device Addressing.

5.3 Executing a Conversion

This section will describe the details of communicating

with the MCP3021 device. Initiating the sample and

hold acquisition, reading the conversion data and

executing multiple conversions w ill be discussed.

5.3.1 INITIATING THE SAMPLE AND

HOLD

The acquisition and conversion of the input signal

begins with the falling edge of the R/W bit of the

address byte. At this point, the internal clock initiates

the sam pl e, hol d and convers ion c ycle, all of wh ic h a re

internal to the ADC.

FIGURE 5-3: Initiating the Conversion,

Addres s By te.

FIGURE 5-4: Initiating the Conversion,

Continuous Conversions.

START READ/WRITE

SLAVE ADDR ES S R/W A

1001101

Address Bits1

1 Contact Microchip for additional address bits.

Device Code

123456789

SCL

SDA 1 0 0 1 A2 A1 A0 R/W

ACK

Start

Bit

Address Byte

Address bits Device bits

tACQ + tCONV is

initiated here

SCL

SDA D1 D0 X

ACK

Lower Data Byte (n)

tACQ + tCONV is

initiated here

D4 D3 D2 XD5

ACK

17 18 19 20 21 22 23 24 25 26

 2003-2013 Microchip Technology Inc. DS21805B-page 17

MCP3021

The input signal will initially be sampled with the first

falling edge of the cloc k f oll ow in g the tran sm is si on of a

logic-high R/W bit. Additionally, with the rising edge of

the SCL, the ADC will transmit an acknowledge bit

(ACK = 0). The master must release the data bus dur-

ing this clock pulse to allow the MCP3021 to pull the

line low (refer to Figure 5-3).

For consecutive samples, sampling begins on the last

bit of the lower da ta byte. Refe r to Figure 5-6 for timing

diagram.

5.3.2 READING THE CONVERSION DATA

After the MCP3021 acknowledges the address byte,

the device will transmit four ‘0’ bits followed by the

upper four data bits of the conversion. The master

device will then acknowledge this byte with an

ACK = low. With the following six clock pulses, the

MCP3021 will transmit the lower six data bits from the

conversion. The last two bits are “don’t cares”, and do

not contain valid data. The master then sends an

ACK = high, indicating to the MCP3021 that no more

data is requested . Th e m as ter c an the n s end a sto p b it

to end the transmission.

FIGURE 5-5: Executing a Conversion.

5.3.3 CO N SECUT IV E CON VE RSIONS

For consecutive samples, sampling begins on the fall-

ing edge of the last bit of the lower data byte. See

Figure 5-6 for timing .

FIGURE 5-6: Continuous Conversion.

SDA

tACQ + tCONV is

initiated here

Address Byte

Address bits Devi ce bits

1001AR

Upper Data Byte

0000DDDA

Lower Data Byte

S P

07D

0XX

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SCL

SDA

fSAMP = 22.3 ks ps (fCLK = 400 kHz)

tACQ + tCONV is

initiated here

Address Byte

Address bits

Device bits

1001A2A1A0

Upper Data Byte (n )

Lower Data Byte (n)

tACQ + tCONV is

initiated here

0000

DDD

987D

0XX

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SCL

MCP3021

DS21805B-page 18  2003-2013 Microchip Technology Inc.

6.0 APPLICATIONS INFORMATION

6.1 Driving the Analog Input

The MCP3021 has a single-ended analog input (AIN).

For proper conversion results, the voltage at the AIN

pin mus t be kept between VSS and VDD. If the converter

has no offset error, gain error, INL or DNL errors and

the voltage level of AIN is equal to or less than

VSS + 1/2 LSB, the resultant code will be 000h. Addi-

tionally, if the voltage at AIN is equal to or greater than

VDD - 1.5 LSB, the output code will be 1FFh.

The analog input model is shown in Figure 6-1. In this

diagram, the source impedance (RSS) adds to the int er-

nal sa mpling swit ch (RS) impedance, directly affecting

the time required to charge the capacitor (CSAMPLE).

Consequently, a larger source impedance increases

the of fset error , g ain error and integra l linearity er rors of

the conversion. Ideally, the impedance of the signal

source should be near zero. This is achievable with an

operat io nal am pli fie r su ch as the MCP6022 , w hi ch ha s

a closed-loop output impedance of tens of ohms.

FIGURE 6-1: Analog Input Model, AIN.

6.2 Connecting to the I2C Bus

The I2C bus is an open collector bus, requiring pull-up

resistors connected to the SDA and SCL lines. This

configuration is shown in Figure 6-2.

FIGURE 6-2: Pull-up Resistors on I2C

Bus.

The number of devices connected to the bus is limited

only by the maximum bus capacitance of 400 pF. A

possible configuration using multiple devices is shown

in Figure 6-3.

FIGURE 6-3: Multip le D evi ce s on I 2C Bus.

CPIN

RSS AIN

7pF

VT = 0.6V

VT = 0.6V ILEAKAGE

Sampling

Switch

SS RS = 1 k

CSAMPLE

= DAC capacitance

VSS

VDD

= 20 pF

±1 nA

Legend

VA= s ign al sourc e

RSS = source impedance

AIN = analog input pad

CPIN = analog input pin capacitance

VT= threshold voltage

ILEAKAGE = leakage current at the pin

due to various junctions

SS = sampling switch

RS= sampling switch resistor

CSAMPLE = sample/hold capacitance

PIC®

SDA

SCL

VDD

RPU

RPU is typically: 10 k for fSCL = 100 kHz

2k for fSCL = 400 kHz

MCP3021

Analog

Input

Signal

Microcontroller

AIN

SDA SCL

PIC16F876

Microcontroller

MCP3021

10-bit ADC

TC74

Temperature

Sensor

24LC01

EEPROM

 2003-2013 Microchip Technology Inc. DS21805B-page 19

MCP3021

6.3 Device Polling

In some instances, it may be necessary to test for

MCP3021 presence on the I2C bus w ithout performing

a convers ion, described in Fi gure 6-4. Here we are set-

ting the R/W bit in the address byte to a zero. The

MCP3021 will then acknowledge by pulling SDA low

during the AC K clo ck and the n rel eas e th e bu s ba ck to

the I2C ma ster. A stop or repeated st art bit can then be

issued from the master and I2C communication can

continue.

FIGURE 6-4: Device Polling.

6.4 Device Power and Layout

Considerations

6.4.1 POWERING THE MCP3021

VDD supplie s the po wer to th e device a s well as the r ef-

erence voltage. A bypass capacitor value of 0.1 µF is

recommended. Adding a 10 µF capacitor in parallel is

recommended to attenuate higher frequency noise

pres ent in som e sy ste ms .

FIGURE 6-5: Powering the MCP3021.

6.4.2 LAYOUT CONSIDERATIONS

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

nois e wh erever possible. A bypass capacitor from VDD

to ground should always be used with this device and

should be placed as clos e as pos sible to th e device pi n.

A bypass capacitor value of 0.1 µF is recommended.

Digit al and analog t races sh ould be sep arated as much

as possible on the board, with no traces running

underneath the device or the bypass capacitor. Extra

precautions should be taken to keep traces with high

frequency signals (such as clock lines) as far as

possible from analog traces .

The MC P3021 sho uld be co nnected en tirely to t he ana-

log ground place, as well as the analog power trace.

The pull-up resistors can be placed close to the

microcontroller and tied to the digital power or VCC.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing VDD connections to

devices in a “star” configuration can also reduce noise

by eliminating current return paths and associated

errors (Fig ure 6-6). For more i nforma tio n on lay out tips

when using the MCP3021 or other ADC devices, refer

to AN688, “Layout Tips for 12-Bit A/D Converter

Applications”.

FIGURE 6-6: VDD traces arranged in a

‘S tar’ configuration in order to reduce errors

caused by current return paths.

6.4.3 USING A REFERENCE FOR

SUPPLY

The MCP3021 uses VDD as pow er and also as a refer-

ence. In som e appl icati ons, i t may be ne cess ary to use

a stable reference to achieve the required accuracy.

Figur e 6-7 shows an example using the MCP1541 as a

4.096V 2% reference.

FIGURE 6-7: Stable Power and

Reference Configuration.

123456789

SCL

SDA 1001 A2A1A0 0

ACK

Start

Bit

Address Byte

Address bits Device bits R/W Start

Bit

MCP3021 r esponse

VDD

AIN SCL

SDA To

Microcontroller

10 µF

MCP3021

0.1 µF

VCC

RPU

VDD

Connection

Device 1

Device 2

Device 3

Device 4

VDD

4.096V

Reference

1µF

0.1 µF MCP1541 CL

AIN

Microcontroller

MCP3021

VCC

RPU

SCL

SDA

MCP3021

DS21805B-page 20  2003-2013 Microchip Technology Inc.

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

2 13

5-Pin SOT-23A (EIAJ SC-74) Device



Part Number Address Option SOT-23

MCP3021A0T-E/OT 000 GP

MCP3021A1T-E/OT 001 GS

MCP3021A2T-E/OT 010 GK

MCP3021A3T-E/OT 011 GL

MCP3021A4T-E/OT 100 GM

MCP3021A5T-E/OT 101 GJ *

MCP3021A6T-E/OT 110 GQ

MCP3021A7T-E/OT 111 GR

* Default option. Contact Microchip Factory for other address

options.

Legend: XX...X Customer-specific information

Y Year code (last di git of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Mi croch ip p art numb er ca nnot be mark ed on one l ine, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2003-2013 Microchip Technology Inc. DS21805B-page 21

MCP3021

5-Lead Plastic Small Outline Transistor (OT) (SOT23)

10501050



Mold Draft Angle Bottom 10501050



Mold Draft Angle Top 0.500.430.35.020.017.014BLead Width 0.200.150.09.008.006.004

Lead Thickness 10501050



Foot A ngle 0.550.450.35.022.018.014LFoot Length 3.102.952.80.122.116.110DOverall Length 1.751.631.50.069.064.059E1Molded Pa ckag e Width 3.002.802.60.118.110.102EOverall Width 0.150.080.00.006.003.000A1Standoff § 1.301.100.90.051.043.035A2M old ed Pa ckag e Thick ness 1.451.180.90.057.046.035AOverall Height 1.90.075

Outside lead pitch (basic) 0.95

.038

Pitch 55

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units







* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-178

Drawing No. C04-091

§ Significant Characteristic

Note: For th e mo st c ur re nt pac ka ge d r awi n gs , p l ease se e t he M ic r oc hi p Pack a gi ng Specifi c ati on lo ca te d

at http://www.microchip.com/packaging

MCP3021

DS21805B-page 22  2003-2013 Microchip Technology Inc.

8.0 REVISION HISTORY

Revision B (January 2013)

Added a note to each package outline drawing.

 2003-2013 Microchip Technology Inc. DS21805B-page 23

MCP3021

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Device: MCP3021T: 10-Bit 2-Wire Serial A/D Converter

(Tape and Reel)

Temperature Range: E= -40C to +125C

Address Options: XX A2 A1 A0

A0 = 0 0 0

A1 = 0 0 1

A2 = 0 1 0

A3 = 0 1 1

A4 = 1 0 0

A5 * = 1 0 1

A6 = 1 1 0

A7 = 1 1 1

* Default option. Contact Microchip factory for other

address options

Package: OT = SOT-23, 5-lead (Tape and Reel)

PART NO. XXX

Address Temperature

Range

Device

Examples:

a) MCP3021A0T-E/OT: Extended, A0 Address,

Tape and Reel

b) MCP3021A1T-E/OT: Extended, A1 Address,

Tape and Reel

c) MCP3021A2 T-E/OT: Extended, A2 Address,

Tape and Reel

d) MCP3021A3T-E/OT: Extended, A3 Address,

Tape and Reel

e) MCP3021A4T-E/OT: Extended, A4 Address,

Tape and Reel

f) MCP3021A5T-E/OT: Extend ed, A5 Address,

Tape and Reel

g) MCP3021A6T-E/OT: Extended, A6 Address,

Tape and Reel

h) MCP3021A7T-IE/OT: Extend ed, A7 Address,

Tape and Reel

/XX

Package

Options

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Worldwide Site (www. micro chip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

Customer Notification System

MCP3021

DS21805B-page 24  2003-2013 Microchip Technology Inc.

NOTES:

 2003-2013 Microchip Technology Inc. DS21805B-page 25

Information contained in this publication regarding device

applications a nd the lik e is provided only f or yo ur convenience

and may be supers ed ed by u pda t es . It is y our responsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTA RT, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip T echnology

Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Contr ol Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense , HI- TIDE, In-Circuit Serial

Programm ing, ICSP, Mindi, MiWi, MPAS M, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PI CC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Tec hnolo gy Germ any II GmbH & Co. & KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 9781620769003

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure famili es of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellec tual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPI C® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

DS21805B-page 26  2003-2013 Microchip Technology Inc.

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11/29/12