2003-2013 Microchip Technology Inc. DS21805B-page 1
MCP3021
Features
• 10-bit resolution
• ±1 LSB DNL, ±1 LSB INL max.
• 250 µA max conversion current
• 5 nA typical standby current, 1 µA max.
•I
2C™ compatible serial interface
-100kHz I
2C Stand ard mod e
-400kHz I
2C Fast mode
• Up to 8 devices on single 2-wire bus
• 22. 3 ksps in I2C Fa st mode
• Single-ended analog input channel
• On-chip sample and hold
• On-chip conversion clock
• Single supply specified operation: 2.7V to 5.5V
• Temperature range:
- Extended: -40°C to +125°C
•Small SOT-23 package
Applications
• Data Logging
• Multi-zone Monitoring
• Hand Held Portable Applications
• Battery Powered Test Equipment
• Remote or Isolated Data Acquisition
Package Type
Description
The Microchip Technology Inc. MCP3021 is a succes-
sive approximation A/D converter (ADC) with 10-bit
resolution. Available in the SOT-23 package, this
device provides one single-ended input with very low
power consumption. Based on an advanced CMOS
technology, the MCP3021 provides a low maximum
conversion current and standby current of 250 µA and
1 µA, respectively. Low current consumption, com-
bined with the small SOT -23 package, make this device
ideal for battery-powered and remote data acquisition
applications.
Communication to the MCP3021 is performed using a
2-wire I2C compatible interface. Standard (100 kHz)
and Fast (400 kHz) I2C modes are available with the
device. An on-chip conversion clock enables indepen-
dent timing for the I2C and conversion clocks. The
device is also addressable, allowing up to eight devices
on a single 2-wire bus.
The MCP3021 runs on a single supply voltage that
operates over a broad range of 2.7V to 5.5V. This
device also provides excellent linearity of ±1 LSB d iffer-
ential non-linearity (DNL) and ±1 LSB integral non-
linearity (INL), maximum.
Functional Block Diagram
5-Pin SOT-23A
SCL
AIN
MCP3021
1
2
3
5
SDA
VSS
VDD
4
Comparator
10-Bit SAR
DAC
AIN
VSS
VDD
SCL SDA
Clock
Control Logic
–
+
Sample
and
Hold
I2C™
Interface
Low Power 10-Bit A/D Converter With I2C™ Interface
MCP3021
DS21805B-page 2 2003-2013 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD...................................................................................7.0V
Analog input pin w.r.t. VSS....................... -0.6V to VDD +0.6V
SDA and SCL pins w.r.t . VSS.. ...... .. . ...... .. .- 0 . 6 V to VDD +1.0V
Storage temperature .......... ...........................-65°C to +150°C
Ambient temp. with power applied................-65°C to +125°C
Maximum Junction Temperature...................................150°C
ESD protection on all pins (HBM) ................. ................ 4kV
† Stresses above those listed under “ Maximum ratings” ma y
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at those or any
other conditions above those indicated in the operational list-
ings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reli-
ability.
PIN FUNCTION TABLE
Name Function
VDD +2.7V to 5.5V Power Supply
VSS Ground
AIN Analog I nput
SDA Serial Data In/O ut
SCL Serial Cloc k In
DC ELECTRICAL SP ECIFICATIONS
Electri cal Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k
TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).
Parameters Sym Min Typ Max Units Conditions
DC Accuracy
Resolution 10 bits
Integral Nonl ine ari ty INL — ±0 .25 ±1 LSB
Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes
Offset Error — ±0.75 ±3 LSB
Gain Error — -1 ±3 LSB
Dynamic Performance
Total Harmonic Distortion THD — -70 — dB VIN = 0.1V to 4.9V @ 1 kHz
Signal to Noise and Distortion SINAD — 60 — dB VIN = 0.1V to 4.9V @ 1 kHz
Spuriou s Free D yna mi c Ra ng e SFDR — 74 — dB VIN = 0.1V to 4.9V @ 1 kHz
Analog Input
Input Voltage Range VSS-0.3 — VDD+0.3 V 2.7V VDD 5.5V
Leakage Current -1 — +1 µA
SDA/SCL (open-drain output)
Data Coding Format Straight Binary
High-level input voltage VIH 0.7 VDD ——V
Low-level input voltage VIL ——0.3 V
DD V
Low-level output voltage VOL ——0.4VI
OL = 3 mA, RPU = 1.53 k
Hysteresis of Schmitt trigger inputs VHYST — 0.05VDD —Vf
SCL = 400 kHz only
Note 1: Sample ti me is the time betwe en con versi ons af ter the addres s byte h as been se nt to the c onver ter. Refer
to Figure 5-6.
2: This parameter is periodically sampled and not 100% tested.
3: RPU = Pull-up resistor on SDA and SCL.
4: SDA and SCL = V SS to VDD at 400 kHz.
5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for rela tion to
SCL.
2003-2013 Microchip Technology Inc. DS21805B-page 3
MCP3021
TEMPE RATURE SPECIFICATIONS
Input leakage current ILI -1 — +1 µA VIN = VSS to VDD
Output lea ka ge current ILO -1 — +1 µA VOUT = VSS to VDD
Pin capacitance
(all input s /ou tpu ts) CIN,
COUT
——10pFT
AMB = 25°C, f = 1 MHz;
(Note 2)
Bus C apacitanc e CB— — 400 pF SDA drive low, 0.4V
Power Requireme nts
Operati ng Voltage VDD 2.7 — 5.5 V
Conve rsi on C urren t IDD —175250µA
Standby Current IDDS —0.005 1 µASDA, SCL = V
DD
Active bus current IDDA — — 120 µA Note 4
Conversion Rate
Conve r si on Time tCONV —8.96 — µsNote 5
Analog Input Acquisition Time tACQ —1.12 — µsNote 5
Sample Rate fSAMP — — 22.3 ksp s fSCL = 400 kHz (Note 1)
Electri cal Characteristics: All parameters apply across the operating voltage range.
Parameters Symbol Min Typ Max Units Conditions
Temperature Ranges
Extended Temperature Range TA-40 — +125 °C
Operati ng Tempe rature Range TA-40 — +125 °C
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT23A JA —256 —°C/W
DC ELECTRICAL SP ECIFICATIONS (CONTINUED)
Electri cal Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k
TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).
Parameters Sym Min Typ Max Units Conditions
Note 1: Sample ti me is the time betwe en con versi ons af ter the addres s byte h as been se nt to the c onver ter. Refer
to Figure 5-6.
2: This parameter is periodically sampled and not 100% tested.
3: RPU = Pull-up resistor on SDA and SCL.
4: SDA and SCL = V SS to VDD at 400 kHz.
5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for rela tion to
SCL.
MCP3021
DS21805B-page 4 2003-2013 Microchip Technology Inc.
TIMING SPECIFICATIONS
FIGURE 1-1: Standard and Fast Mode Bus Timing Data.
Electri cal Characteristics: All parameters apply at VDD = 2.7V - 5.5 V, VSS = GND, TA = -40°C to +85°C.
Parameters Sym Min Typ Max Units Conditions
I2C Standard Mode
Clock frequency fSCL 0—100kHz
Clock high time THIGH 4000 — — ns
Clock low time TLOW 4700 — — ns
SDA and SCL ris e time TR— — 1000 ns From VIL to VIH (Note 1)
SDA and SCL fall time TF——300nsFrom V
IL to VIH (Note 1)
START condition hold time THD:STA 4000 — — ns
START condition setup time TSU:STA 4700 — — ns
Data input setup time TSU:DAT 250 — — ns
STOP condition setup time TSU:STO 4000 — — ns
STOP condition hold time THD:STD 4000 — — ns
Output valid from clock TAA — — 3500 ns
Bus free time TBUF 4700 — — ns Note 2
Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1)
I2C Fast Mode
Clock frequency FSCL 0—400kHz
Clock high time THIGH 600 — — ns
Clock low time TLOW 1300 — — ns
SDA and SCL ris e time TR20 + 0.1CB— 300 ns From VIL to VIH (Note 1)
SDA and SCL fall time TF20 + 0.1CB— 300 ns From VIL to VIH (Note 1)
START condition hold time THD:STA 600 — — ns
START condition setup time TSU:STA 600 — — ns
Data input hold time THD:DAT 0—0.9ms
Data input setup time TSU:DAT 100 — — ns
STOP condition setup time TSU:STO 600 — — ns
STOP condition hold time THD:STD 600 — — ns
Output valid from clock TAA ——900ns
Bus free time TBUF 1300 — — ns Note 2
Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: Time the bus must be free before a new transmission can start.
TFTHIGH VHYS TR
TSU:STA
TSP THD:STA
TLOW THD:DAT TSU:DAT TSU:STO
TBUF
TAA
SCL
SDA
IN
SDA
OUT
2003-2013 Microchip Technology Inc. DS21805B-page 5
MCP3021
2.0 TYPICAL PERFORMANCE CURVES
Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-1: INL vs. Clock Rate.
FIGURE 2-2: INL vs. VDD - I2C Standard
Mode (fSCL = 100 kHz).
FIGURE 2-3: INL vs. Code
(Represen tative Par t) .
FIGURE 2-4: INL vs. Clock Rate
(VDD =2.7V).
FIGURE 2-5: INL vs. VDD - I2C Fast Mode
(fSCL = 400 kH z ) .
FIGURE 2-6: INL vs. Code
(Representative Part, VDD = 2.7V).
Note: The g r ap hs and t ables provid ed fol low i ng thi s n ote are a statistical s umm ar y b as ed on a limite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 100 200 300 400
I2C Bus Rate (kHz)
INL (LSB)
Positive INL
Negative INL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.533.544.555.5
VDD (V)
INL (LSB)
Positive INL
Negative INL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 256 512 768 1024
Digital Code
INL (LSB)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 100 200 300 400
I2C Bus Rate (kHz)
INL (LSB)
Positive INL
Negative INL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.533.544.555.5
VDD (V)
INL (LSB)
Positive INL
Negative INL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 256 512 768 1024
Digital Code
INL (LSB)
MCP3021
DS21805B-page 6 2003-2013 Microchip Technology Inc.
Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-7: INL vs. Te mpe ratur e.
FIGURE 2-8: DNL vs. Clock Rate.
FIGURE 2-9: DNL vs. VDD - I2C Standard
Mode (fSCL = 100 kHz).
FIGURE 2-10: INL vs. Te mpe r ature
(VDD =2.7V).
FIGURE 2-11: DNL vs. Clock Rate
(VDD =2.7V).
FIGURE 2-12: DNL vs. VDD - I2C Fast
Mode (fSCL = 400 kHz).
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50 -25 0 25 50 75 100 125
Tempera ture (°C)
INL (LSB)
Positive INL
Negative INL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 100 200 300 400
I2C Bus Rate (kHz)
DNL (LS B)
Positive D NL
Negative DNL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
DNL (LSB)
Positive DNL
Negative DNL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50-250 255075100125
Temperature (°C)
INL (LSB)
Negative INL
Positive INL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 100 200 300 400
I2C Bus Rate (kHz)
DNL (LSB)
Negative DNL
Positive DNL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.533.544.555.5
VDD (V)
DNL (LS B)
Positive DNL
Negative DNL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
2003-2013 Microchip Technology Inc. DS21805B-page 7
MCP3021
Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-13: DNL vs. Code
(Represen tative Par t) .
FIGURE 2-14: DNL vs. Temperature.
FIGURE 2-15: Gain Error vs. VDD.
FIGURE 2-16: DNL vs. Code
(Representative Part, VDD = 2.7V).
FIGURE 2-17: DNL vs. Te mpe r ature
(VDD =2.7V).
FIGURE 2-18: Offset Error vs. VDD.
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 256 512 768 1024
Digital Code
DNL (LSB)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50 -25 0 25 50 75 100 125
Temperature (°C)
DNL (LSB)
Negative DNL
Positive DNL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
2.533.544.555.5
VDD (V)
Gain Error (LSB)
Fast Mode
(fSCL=100 kHz) Standard Mode
(fSCL=400 kHz)
0
-0.025
-0.05
-0.075
-0.1
-0.15
-0.175
-0.2
-0.225
-0.25
-0.125
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 256 512 768 1024
Digital Code
DNL (LSB)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50 -25 0 25 50 75 100 125
Temperature (°C)
DNL (LSB)
Positive DNL
Negative DNL
0.25
0.20
0.15
0.10
0.005
-0.005
-0.10
-0.15
-0.20
-0.25
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2.533.544.555.5
VDD (V)
Offset Error (LSB)
fSCL = 100 kHz & 400 kHz
0.25
0.225
0.2
0.175
0.15
0.1
0.075
0.05
0.025
0
0.125
MCP3021
DS21805B-page 8 2003-2013 Microchip Technology Inc.
Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-20: SNR vs. Input Frequency.
FIGURE 2-21: THD vs. Input Frequency.
FIGURE 2-22: Offset Error vs.
Temperature.
FIGURE 2-23: SINAD vs . Input Fre quen cy.
FIGURE 2-24: SINAD vs . Input Si gna l
Level.
-1.5
-1
-0.5
0
0.5
1
1.5
-50 -25 0 25 50 75 100 125
Temperature (°C)
Gain Error (LSB)
VDD = 5V
VDD = 2.7V
0.375
0.250
0.125
-0.125
-0.250
-0.375
12
24
36
48
60
72
84
96
110
Input Fr e quency (kHz )
SNR (dB)
VDD = 5V
VDD = 2.7V
Y
84
72
60
48
36
24
12
0
-96
-84
-72
-60
-48
-36
-24
-12
110
Input Frequency (kHz)
THD (dB)
VDD = 2. 7 V VDD = 5V
0
-12
-24
-36
-48
-60
-72
-84
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-50 -25 0 25 50 75 100 125
Temperature (°C)
Offset Error (LSB)
VDD = 5V
VDD = 2.7V
0.50
0.45
0.40
0.35
0.30
0.25
0.15
0.10
0.05
0
0.20
12
24
36
48
60
72
84
96
110
Input Frequency (kHz)
SINAD (dB)
VDD = 5V
VDD = 2.7V
84
72
60
48
36
24
12
0
12
24
36
48
60
72
84
96
-40 -30 -20 -10 0
Input Signal Level (dB)
SINAD (dB)
VDD = 5V
VDD = 2.7 V
84
72
60
48
36
24
12
0
2003-2013 Microchip Technology Inc. DS21805B-page 9
MCP3021
Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-25: ENOB vs. VDD.
FIGURE 2-26: SFDR vs. Input Frequency.
FIGURE 2-27: Spectrum Using I2C Fast
Mode (Representative Part, 1 kHz Input
Frequency).
FIGURE 2-28: ENOB vs. Input Frequency.
FIGURE 2-29: Spectrum Using I2C
Standard Mode (Repres entativ e Par t, 1 kHz
Input Frequency).
FIGURE 2-30: IDD (Conversion) vs. VDD.
11.5
11.55
11.6
11.65
11.7
11.75
11.8
11.85
11.9
11.95
12
2.533.544.555.5
VDD (V)
ENOB (rms)
10
9.95
9.90
9.85
9.80
9.75
9.70
9.65
9.60
9.55
9.50
12
24
36
48
60
72
84
96
110
Input Frequency (kHz)
SFDR (dB)
VDD = 2.7V
VDD = 5 V
84
72
60
48
36
24
12
0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
0 2000 4000 6000 8000 10000
Frequency (Hz)
Amplitude (dB)
9
9.5
10
10.5
11
11.5
12
110
Input Fr e quency (kHz )
ENOB (rms)
VDD = 2.7V VDD = 5V
10
9.5
9.0
8.5
8.0
7.7
7.0
-130
-110
-90
-70
-50
-30
-10
10
0 500 1000 1500 2000 2500
Frequency (Hz)
Amplitude (dB)
0
50
100
150
200
250
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
IDD (µA)
MCP3021
DS21805B-page 10 2003-2013 Microchip Technology Inc.
Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-31: IDD (Conversion) vs. Clock
Rate.
FIGURE 2-32: IDD (Conversion) vs.
Temperature.
FIGURE 2-33: IDDA (Active Bus) vs. VDD.
FIGURE 2-34: IDDA (Active Bus) vs. Clock
Rate.
FIGURE 2-35: IDDA (Active Bu s) vs.
Temperature.
FIGURE 2-36: IDDS (Standby) vs. VDD.
0
20
40
60
80
100
120
140
160
180
200
0 100 200 300 400
I2C Clock Rate (kHz)
IDD (µA)
VDD = 5V
VDD = 2.7V
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
Temperature (°C)
IDD (µA)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
70
80
90
100
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
IDDA (µA)
0
10
20
30
40
50
60
70
80
90
100
0 100 200 300 400
I2C Clock Rate (kHz)
IDDA (µA)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125
Temperature (°C)
IDDA (µA)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
IDDS (pA)
2003-2013 Microchip Technology Inc. DS21805B-page 11
MCP3021
Note: Unles s otherw ise indica ted, VDD = 5V, VSS = 0V, I2C F ast Mode T iming (SCL = 400 kHz), Co ntinuous Conversio n
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-37: IDDS (Standby) vs.
Temperature.
FIGURE 2-38: Analog Input Leakage vs.
Temperature.
2.1 Test Circuit
FIGURE 2-39: Typical Test Configuration.
0.0001
0.001
0.01
0.1
1
10
100
1000
-50 -25 0 25 50 75 100 125
Temperature (°C)
IDDS (nA)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-50 -25 0 25 50 75 100 125
Tempera ture (°C)
Analog Input Leakage (nA)
0.1 µF
AIN MCP3021
VDD = 5V
VCM = 2.5V
VIN
VDD
VSS
10 µF
SDA
SCL
2k2k
MCP3021
DS21805B-page 12 2003-2013 Microchip Technology Inc.
3.0 PIN FUNCTIONS
TABLE 3-1: PIN FUNCTION TABLE
3.1 VDD and VSS
The VDD pi n, with respec t to VSS, provides power to the
device, as well as a voltage reference for the conver-
sion process. Refer to Section 6.4, “Device Power and
Layout Considerations”, for tips on power and
grounding.
3.2 Analog Input (AIN)
AIN is the input pin to the sample and hold circuitry of
the Successive Approximation Register (SAR) con-
verter. Care should be take n in driving this pin. Refe r to
Section 6.1, “Driving the Analo g Inpu t”. For proper con-
versions , the voltage on this pin can vary from VSS to
VDD.
3.3 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to VDD (typically 10 k for 100 kHz and 2 k
for 400 kHz SCL clock speeds (refer to Section 6.2,
“Connecting to the I2C Bus”).
For normal data transfer , SDA is allowed to change only
during SCL low . Changes during SCL high are reserved
for indi cating the START and STOP conditions (refer to
Section 5.1, “I2C Bus Characteristics”).
3.4 Serial Clock (SCL)
SCL is a n inpu t pin used t o sy nchroniz e the d at a trans -
fer to and from the device on the SDA pin and is an
open-drai n terminal . Therefor e, the SCL bus re quires a
pull-up re sistor to VDD (ty pically, 10 k for 100 kHz and
2k for 400 kHz SCL clock speeds. Refer to
Section 6.2, “Connecting to the I2C Bus”).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the START and STOP
conditions (refer to Section 6.1, “Driving the Analog
Input”).
Name Function
VDD +2.7V to 5.5V Power Supply
VSS Ground
AIN Analog Input
SDA Serial Data In/Out
SCL Serial Clock In
2003-2013 Microchip Technology Inc. DS21805B-page 13
MCP3021
4.0 DEVICE OPERATION
The MCP3021 employs a classic SAR architecture.
This architecture uses an internal sample and hold
cap acitor to store the anal og input while the conver sion
is taking place. At the end of the acquisition time, the
input switch of the con verter opens and the device uses
the collected charge on the internal sample and hold
capacitor to produce a serial 10-bit digital output code.
The acquisition time and conversion is self-timed using
an int ernal clock. After each conver sion, the res ults are
stored in a 10-bit register that can be read at any time.
Comm uni ca tion with the de vi ce is ac com plished with a
2-wire I2C interface. Maximum sample rates of
22.3 ksps are p oss ible with the MCP3 021 in a continu-
ous conversion mode and an SCL clock rate of
400 kHz.
4.1 Digit al Output Code
The digital output co de produced by the M C P30 21 is a
function of the input signal and power supply voltage
(VDD). As the VDD level is reduced, the LSB size is
reduced accordingly . The theoretical LSB size is shown
below.
EQUATION
The outp ut code of t he MCP3021 is transm itted seria lly
with MSB first, the format of the code being straight
binary.
4.2 Conversion Time (tCONV)
The conversion time is the time required to obtain the
digital result once the analog input is disconnected
from the holding capacitor. With the MCP3021, the
specif ied c onvers ion t ime is typic ally 8.96 µs. This time
is depen dent on the internal os cillator a nd indepen dent
of SCL.
4.3 Acquisition Time (tACQ)
The a cquis ition t ime i s the am ount of time the sample
cap array is acquiring charge.
The acquisition time is, typically, 1.12 µs. This time is
depende nt on the inter nal oscilla tor and ind ependent of
SCL.
4.4 Sample Rate
Sample rate is the inverse of the maximum amount of
time that is require d from the poi nt of ac qui si tion of the
first con version to th e point of ac quisition of the secon d
conversion.
The sample rate can be measured either by single or
continuous conversions. A single conversion includes
a Start Bit, Address Byte, Two Data Bytes and a Stop
bit. This sample rate is measured from one Start Bit to
the next Start Bit.
For continuous conversions (requested by the Master
by issuing an acknowledge after a conversion), the
maximum sample rate is measured from conversion to
conversi on, or a total of 18 clocks (two data bytes and
two Acknowledge bits). Refer to Section 5-2, “Device
Addressing”.
FIGURE 4-1: Transfer Function.
LSB SIZE VDD
1024
------------
=
VDD = Supply voltage
AIN
00 0000 0001 (1)
00 0000 0011 (3)
11 1111 1110 (1022)
Output Code
VDD-1.5 LSB
.5 LSB
1.5 LSB VDD-2.5 LSB
2.5 LSB
00 0000 0000 (0)
00 0000 0010 (2)
11 1111 1111 (1023)
MCP3021
DS21805B-page 14 2003-2013 Microchip Technology Inc.
4.5 Differential Non-Li nearity (DNL)
In the id eal ADC trans fer function, e ach code has a uni-
form width. That is, the difference in analog input volt-
age is constant from one code transition point to the
next. DNL specifies the deviation of any code in the
transfer function from an ideal code width of 1 LSB.
The DNL is determined by subtracting the locations of
successive code transition points after compensating
for any gain and offset errors. A positive DNL implies
that a code is longer than the ideal code width, while a
negative DNL implies that a code is shorter than the
ideal width.
4.6 Integral Non-Linearity (INL)
INL is a result of cumulative DNL errors and specifies
how much the overall transfer function deviates from a
linear response. The method of measurement used in
the MCP3021 ADC to determine INL is the “end-point”
method.
4.7 Offset Error
Off set er ror is define d as a dev iation of the code trans i-
tion points that are present across all output codes.
This has the effect of shifting the entire A/D transfer
functio n. The offs et error is measure d by finding the d if-
ference between the actual location of the first code
transiti on and the des ired lo catio n of the f irst tran sitio n.
The ideal location of the first code transition is located
at 1/2 LSB above VSS.
4.8 Gain Error
The gain error determines the amount of deviation from
the ideal slope of the ADC tr ansfer fu nctio n. Before th e
gain error is determined, the offset error is measured
and subtracted from the conversion result. The gain
erro r c a n the n be de t erm in e d by fi nd i ng th e loc at i on of
the last code transition and comparing that location to
the ideal location. The ideal location of the last code
transition is 1.5 LSBs below full-scale or VDD.
4.9 Conversion Current (IDD)
The average amount of current over the time required
to perform a 10-bit conversion.
4.10 Active Bus Current (IDDA)
The average amount of current over the time required
to monitor the I2C bus. Any current the device con-
sumes while it is not being addressed is referred to as
Active Bus c urrent.
4.11 Standby Current (IDDS)
The average amount of current required while no con-
version is occurring and while no data is being ou tput
(i.e., SCL and SDA lines are quiet).
4.12 I2C Standard Mode Timing
I2C specification where the frequency of SCL is
100 kHz.
4.13 I2C Fast Mode Timing
I2C specification where the frequency of SCL is
400 kHz.
2003-2013 Microchip Technology Inc. DS21805B-page 15
MCP3021
5.0 SERIAL COMMUNICATIONS
5.1 I2C Bus Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stab le when ever th e clock lin e is high . Change s in
the data line while the clock line is high wi ll be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (refer to Figure 5-1).
5.1.1 BUS NOT BUSY (A)
Both data and clock lines remain high.
5.1.2 START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a START condition. All
commands must be preceded by a START condition.
5.1.3 S TOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a STOP condition. All
operati ons must be ende d with a STOP condition.
5.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the high period of t he clock signal.
The data on the line must be changed during the low
period of the cl ock signal. There is one cloc k puls e per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between the START and STOP
conditions is determined by the master device and is
unlimited.
5.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge bit after the reception of
each byte. The master device must generate an extra
clock pulse that is a ssociated with th is acknowledge bit.
The device that acknowledges has to pull down the
SDA line d uring th e ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Setup
and hold times must be taken into account. During
reads, a master device must signal an end of data to
the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave (NAK).
In th is ca se, the sl ave ( MC P3021 ) wi ll r eleas e th e bus
to allow the master device to generate the STOP con-
dition.
The MCP3021 supports a bidirectional 2-wire bus and
dat a trans miss ion p rotocol . The de vice t hat sends dat a
onto the bu s is the transm itter and the dev ice rec eivin g
data is the receiver. The bus has to be controlled by a
master device that generates the serial clock (SCL),
controls the bus access and gen erat es the START and
ST OP cond itions, wh ile the M CP3021 works as a slav e
device. Both master and slave devices can operate as
either transmitter or receiver, but the master device
determines which mode is activated.
FIGURE 5-1: Data Transfer Sequence on the Serial Bus.
SCL
SDA
(A) (B) (D) (D) (A)(C)
START
CONDITION ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION