me v -, aE a ene ee re ee, _!____. em we a Ys Features e CMOS for optimum speed/power High speed 25 ns max set-up 12 ns clock to output CY7C225 CYPRESS SEMICONDUCTOR 512x e Slim 300-mil, 24-pin plastic or her- metic DIP, 28-pin LCC, or 28-pin PLCC @ 5V +10% Vcc, commercial and military e TTL-compatible /O Low power . Dire replacement for bipolar 495 mW (commercial) c bl twithstandi ter th a e Capable of withstanding greater than 660 mW (military) 1500V static discharge e Synchronous and asynchronous out- Functional Description put enables On-chip edge-triggered registers Buffered common PRESET and CLEAR inputs EPROM technology, 100% The CY7C225 is a high-performance 512 word by 8 bit electrically programmable read only memory packaged in a slim 300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, and 28-pin PLCC. 8 Registered PROM floating gate technology and byte-wide in- telligent programming algorithms. The CY7C225 replaces bipolar devices and offers the advantages of lower power, superior performance, and high program- ming yield. The EPROM cell requires only 13.5V for the supervoltage and low current requirements allow for gang pro- gramming. The EPROM cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsu- lation. Each PROM is also tested for AC performance to guarantee that after cus- tomer programming the product will meet AC specification limits. programmable The memory cells utilize proven EPROM Logic Block Diagram Pin Configurations DIP tn Top View Ao | 7 Ay L\ > Og ROW - Ag wl ADDRESS PROGRAMMABLE L MULTIPLEXER|__ O A 5 B-BIT = EDGE- As mm ADDRESS TRIGGERED On hs | BECODER [| REGISTER 03 Ag Ay 02 As _ gl O1 LCC/PLCC PS Oo Top View on ond 8 wn cr LEEZL AD cP Es E 225-1 Selection Guide 70225-25 7C225-30 7225-35 70225-40 Maximum Set-Up Time (ns) 25 30 35 40 Maximum Clock to Output (ns) 12 15 20 25 Maximum Operating Commercial 90 90 90 Current (mA) Military 120 120 120or = eee CY7C225 : SEMICONDUCTOR Maximum Ratings Static Discharge Voltage .......--. 0. cece eee eens >1500V (Above which the useful life may be impaired. For user guidelines, (per MIL-STD-883, Method 3015) not tested.) Latch-Up Current ......... 2-0. e cee eee eee >200 mA Storage Temperature .......---...00-- 65C to +150C : Ambient Temperature with Operating Range Power Applied .............0.0 ee eeee 55C to +125C Ambient Supply Voltage to Ground Potential Range Temperature Yec (Pin 24 to Pin 12) .......-2. ce eee ee eee 0.5V to +7.0V Commercial 0C to +70C SV + 10% DC Voltage Applied to Outputs I trial!) 40 5V + 10% in High Z State .....-.0.00..0eeeeee ee 0.5V to +7.0V ndus a sorcro #85 2 DC Input Voltage ..... 0.0. 0e ccc eeeee ees 3.0V to +7.0V Military = 55C to + 125C SV + 10% DC Program Voltage (Pins 7, 18, 20) .............-+- 14.0V Electrical Characteristics Over the Operating Rangel? 4] Parameter Description Test Conditions Min. Max. Unit Vou Output HIGH Voltage Vec = Min., Ion = 4.0mA 2.4 Vv Vin = Vir or Vit VoL Output LOW Voltage Vcc = Min., Io = 16 mA 0.4 Vv Vin = Vin or Vit VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for 2.0 Vv All Inputs Vit Input LOW Level Guaranteed Input Logical LOW Voltage for All 0.8 Vv Inputs Ix Input Leakage Current GND < Vin < Vec - 10 +10 uA Veo Input Clamp Diode Voltage | Note 4 Toz Output Leakage Current GND < Vo < Vcc, Output Disabledl5! - 40 +40 pA Ios Output Short Circuit Current | Voc = Max., Vout = 0.0VIEl 20 90 mA Icc Power Supply Current Tout = 0 mA. Commercial 90 mA Voc = Max.l/ = Military 120 Vpp Programming Supply Voltage 13 14 Vv Ipp Programming Supply Current 50 mA Vinp Input HIGH Programming 3.0 Vv Voltage VILP Input LOW Programming 0.4 Vv Voltage Capacitancel*! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 10 pF CoutT Output Capacitance Voc =5.0V 10 pF Notes: 1. Contact a Cypress representative for industrial temperature range 5. specifications. 2. Ty, is the instant on case temperature. 3. See the last page of this specification for Group A subgroup testing in- formation. 4. See the Introduction to CMOS PROMs section of the Cypress Data Book for general information on testing. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Due to the design of the differential cell in this device, Ic can only be accurately measured on a programmed array.SEMICONDUCTOR CY7C225 AC Test Loads and Waveforms!) R1 250 R1 2502 5V O_w 5V OUTPUT OUTPUT 50 pF I R2 5 pF | R2 1672 1672 INCLUDING + = 6 INCLUDING & > 8 JIG AND 7 ~ JIG AND ~ ~ SCOPE SCOPE (a) Normal Load (b) High Z Load Equivalent to: THEVENIN EQUIVALENT 100Q OUTPUT ows 10 2.0V 225-6 Operating Modes The CY7C225 incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is provided with synchronous (Es) and asynchronous (E) output enables and CLEAR and PRESET inputs. Upon power-up, the synchronous enable (Es) flip-flop will be in the set condition causing the outputs (Op O7) to be in the OFF or high-impedance state. Data is read by applying the memory lo- cation to the address inputs (Ag Ag) and a logic LOW to the en- able (Es) input. The stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (Op O7) pro- vided the asynchronous enable (E) is also LOW. The outputs may be disabled at any time by switching the asynchro- nous enable (E) toa logic HIGH, and may be returned to the active state by switching the enable to a logic LOW. Regardless of the condition of E, the outputs will go to the OFF or high-impedance state > upon the next positive clock edge after the synchronous enable (Es) input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW, the subsequent positive clock edge will return the output to the active state if E is LOW. Following a positive clock edge, the address and synchro- C225-4 ALL INPUT PULSES GND C225-5 nous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C225 decoders and sense am- plifiers to access the next location while previously addressed data remains stable on the outputs. System timing is simplified in that the on-chip edge-triggered regis- ter allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers avail- able in the market. The CY7C225 has buffered asynchronous CLEAR and PRESET inputs. Applying a LOW to the PRESET input causes an immedi- ate load of all ones into the master and slave flip-flops of the regis- ter, independent of all other inputs, including the clock (CP). Ap- plying a LOW to the CLEAR input, resets the flip-flops to all zeros. The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (E) LOW. When power is applied, the (internal) synchronous enable flip-flop willbe ina state such that the outputs will be in the high-impedance state. In order to enable the outputs, a clock must occur and the Es input pin must be LOW at least a set-up time prior to the clock LOW-to-HIGH transition. The E input may then be used to enable the outputs.CY7C225 Switching Characteristics Over the Operating Rangel? 4] CYPRESS SEMICONDUCTOR 7C22525 7C22530 7C22535 7C225~-40 Parameter Description Min. | Max. | Min. } Max. | Min. | Max. | Min. | Max. | Unit tsa Address Set-Up to Clock HIGH 25 30 35 40 ns tHa Address Hold from Clock HIGH 0 0 0 0 ns tco Clock HIGH to Valid Output 12 15 20 25 ns tpwe Clock Pulse Width 10 15 20 20 ns tsEs Es Setup to Clock HIGH 10 10 10 10 ns tyrs Es Hold from Clock HIGH 0 5 5 5 ns tps toc Delay from PRESET or CLEAR to Valid Output 20 20 20 20 ns trp tre PRESET or CLEAR Recovery to Clock HIGH | 15 20 20 20 ns tpwra tpwc | PRESET or CLEAR Pulse Width 15 20 20 20 ns tcos Valid Output from Clock HIGHI8] 20 20 25 30 ns tuzc Inactive Output from Clock HIGHI8) 20 20 25 30 ns tpoE Vatid Output from E LOW 20 20 25 30 ns tuzE Inactive Output from E HIGH 20 20 25 30 ns Switching Waveforms'4! Ao Ato tses tHeEs ES cP Oo O7 E top toc PS or CLR t 0225-7 PWP tpwo Note: 8. Applies only when the synchronous (Es) function is used.=, CY7C225 Programming Information Programming support is available from Cypress aswellasfroma see the PROM Programming Information located at the end of number of third-party software vendors. For detailed program- this section. Programming algorithms can be obtained from any ming information, including alisting of software packages, please Cypress representative. Table 1. Mode Selection CYPRESS SEMICONDUCTOR Pin Function!) Read or Output Disable Ag Ag cP Es CLR E PS O7 - Oo Mode Other Ag - Ag PGM VFY Vpp E PS Dy _ Do Read Ag Ao x Vin Vin Vit Vin O7 Oo = Output Disable Ag Ao x Vin Vin x Ving High Z Output Disable As Ag x x Vin Vin Vin Highz | & Clear Ag Ag xX Vit Vit Vin Vin Zeros Preset Ag ~ Ag x Vit Ving VIL Vit Ones Program Ag Ao VILP Vinp Vpp Vip VInP D7 Do Program Verify Ag Ag Vinp VILP Vpp Vinp VinP O07 Oo Program Inhibit Ag Ag Vine Vine Vpp VIP VIP High Z Intelligent Program Ag - Ag Vitp VInp Vpp Vinp Vine D; - Do Blank Check Ones Ag Ag Vpp Vitp ViLp VILP Vinp Ones Blank Check Zeros Ag Ag Vpp Vinp VILP VILP Vinp Zeros Note: 9. X = dont care but not to exceed Voc +5%. LCC/PLCC Top View Qo Oo Veco PLZ LL As 4 3 2,1, 282726 PS ~ 25) 0225-9 Figure 1. Programming PinoutsFn: if ies CY7C225 3 SEMICONDUCTOR Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT w CLOCK TO OUTPUT TIME ys. SUPPLY VOLTAGE ys. AMBIENT TEMPERATURE Ss vs. Vcc 1.6 1.2 F 16 e 2 14 A F 1.4 3 J B44 20 5 s N 1.2 4 a 4 Ma z 3 1.0 5 = < 6 < 1.0 b> = a 1.0 2 | 5 5 2 2 09 wu , Ta = 25C NY N 08 0.8 N 0. 1 = fax z Ta = 25C =z A a | = | 0.6 0.8 & 06 4.0 45 5.0 55 60 55 25 126 9 40 45 5.0 55 60 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) w CLOCK TO OUTPUT TIME NORMALIZED SET-UP TIME NORMALIZED SET-UP TIME Ss vs. TEMPERATURE vs. SUPPLY VOLTAGE vs. TEMPERATURE F 1.6 1.2 16 z 2 ~~ a 2 14 F 1.0 5 14 4 2 TN 4 oO ; a F142 ti NM] 9 x . oO 8 a 08 a a4 WwW a een B 1.0 N = 1.0 a = = ivr < x N o8 = 0.6 8 0.8 z 3 Ta = 25C , = Zz = 06 04 | 0.6 Q -55 25 125 4.0 45 5.0 55 60 55 25 125 AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT TYPICAL ACCESS TIME CHANGE OUTPUT SINK CURRENT vs. VOLTAGE vs. OUTPUT LOADING vs. OUTPUT VOLTAGE < 30.0 gq 175 = E = 150 2 25.0 5 8 a Ce u 125 = 20.0 x G $ 3B 100 3 - 15.0 x 2 < 3 7 =] n nr Voc = 5.0V 9 Q 10.0 5 50 Ta = 25C E 5 Ta = 25C E & 5.0 Voc = 4.5V 3 25 a 0 5 0.0 0 1.0 2.0 3.0 4.0 0 200 400 600 800 1000 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) CAPACITANCE (pF) OUTPUT VOLTAGE (V) 225-10Switching Characteristics Parameter Subgroups tsa 7, 8, 9, 10, 11 tHa 7, 8, 9, 10, 11 tco 7, 8, 9, 10, 11 tpp 7, 8,9, 10, 11 tre 7, 8, 9, 10, 11 apr CY7C225 SEMICONDUCTOR Ordering Information!) Speed (ns) . Ordering Package Operating tsa | tco Code Name Package Type Range 25 | 12 | CY7C225-25DC D14 24-Lead (300-Mil) CerDIP Commercial CY7C225 25JC J64 28-Lead Plastic Leaded Chip Carrier CY7C22525PC P13 24-Lead (300-Mil) Molded DIP 30 | 15 | CY7C225-30DC p14 24-Lead (300-Mil) CerDIP Commercial CY7C22530JC J64 28-Lead Plastic Leaded Chip Carrier CY7C225-30PC P13 24-Lead (300-Mil) Molded DIP CY7C225-30DMB D14 24-Lead (300-Mil) CerDIP Military CY7C22530LMB L64 28-Square Leadless Chip Carrier 35 | 20 | CY7C225-35DMB D14 24-Lead (300-Mil) CerDIP Military CY7C225-35LMB L64 28-Square Leadless Chip Carrier 40 | 25 | CY7C225-40DC D4 24-Lead (300-Mil) CerDIP Commercial CY7C225 40JC J64 28-Lead Plastic Leaded Chip Carrier CY7C22540PC P13 24-Lead (300-Mil) Molded DIP CY7C225-40DMB D14 24-Lead (300-Mil) CerDIP Military CY7C22540LMB L64 28-Square Leadless Chip Carrier Note: 10. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product avail- ability. MILITARY SPECIFICATIONS SMD Cross Reference Group A Subgroup Testing SMD Cypress woe Number Suffix Number DC Characteristics 5962-88518 O1LX =| CY7C225-30DMB Parameter Subgroups 5962-88518 013X = | CY7C22530LMB Vou 1, 2,3 5962-88518 02LX = | CY7C22535DMB VoL 1, 2,3 5962-88518 023X | CY7C225-35LMB Vin 1, 2,3 ViL 1, 2,3 5962-88518 03LX = | CY7C22540DMB Ix 1, 2,3 5962-88518 033X | CY7C225~40LMB loz 1, 2,3 Tec 12,3 Document #: 3800002E PROMs a