Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 FEATURES Supported Critical Link Modules o MitySOM-1810 and 1810F o MityDSP-L138 and L138F o MitySOM-1808 and 1808F o MityDSP-6748F Software Included: Real-Time Linux Kernel uBoot User Boot Loader Digital Interfaces: RS-232 Serial Interface USB Host Interface USB OTG Interface 10/100 MBit Ethernet Interface Electrically Isolated CAN Bus Interface UART Expansion for PROFIBUS/RS-485 or RS232 Interface DVI Video Interface SD/MMC Card Socket Audio Output SATA MityDSP-L138F Installed APPLICATIONS: PROFIBUS Development Process Automation Factory Automation Industrial Automation Embedded Instrumentation Rapid Prototyping Expansion: 3 50-pin IO Expansion Slots Integrated +3V/+5V/12V Power Supply DESCRIPTION The Industrial IO Development Kit provides all the hardware and software support for system designers and developers to evaluate the AM1810, AM1808 or OMAPL138 Microprocessors. Included is your choice of a Critical Link MitySOM-1810, MitySOM1808, MityDSP-6748F or MityDSP-L138 series System on Modules. In addition, the Industrial IO Development Kit includes on board RS-232, 10/100 MBit Ethernet, Universal Serial Bus (USB) Host and USB-On The-Go (OTG) communication interfaces and an Electrically Isolated CAN interface. The single UART expansion port allows for the connection of either the PROFIBUS(module dependent)/RS-485 expansion board (optional) with 2500V galvanic isolation barrier or a simple RS232 serial port expansion kit (optional). Integrated Digital Video Interface (DVI) controller for external display connection with DDC support. Interface to QVGA\WQVGA display via 5 pair LVDS link with additional SPI interface for resistive touch controller (requires an FPGA based module to be installed), Multi Media Card (MMC) interface, 3 I/O Expansion connectors for custom add-on card and integrated power supply with +3V/+5V/12V outputs from single 12VDC input. 1 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 A block diagram of the Industrial IO Development Kit is illustrated in Figure 1. All available processor GPIO ports and FPGA I/O lines (if FPGA module is installed) are either used directly by the Industrial IO Development Kit or are routed to the 3 50-pin Expansion IO connectors. Control of the on-board interface hardware and connected Expansion IO cards require proper configuration of the MitySOM / MityDSP ARM, DSP, and FPGA. While not required, it is strongly recommended that the MitySOM software and firmware development kit and supplied API be used to manage these interfaces. Industrial IO Development Kit USB1 USB-A Connector PC Micro-USB Connector USB0 SD Card Micro-SD Connector MMCSD 0 Disk SATA Header Serial Ethernet Profinet Modbus TCP EtherCAT Master MMCSD0 IO 10-pin Header RJ-45 & Magnetics TLK100 Ethernet PHY 10-pin Hdr ISO 1050 MCP2515 Audio Line Out 1/8" stereo jack Filter DSD1791 Monitor 10-pin Hdr UART[2] DVI TFP410 QVGA\WQVGA Panel w/Touch or GPIO LCD / Touch Header +12V Power Management AM1810/AM1808/OMAP-L138 ARM Microprocessor or C6748 DSP Only from Texas Instruments SATA TRS232E RS232 PHY CAN RS232 RS485/ Profibus Modbus Battery (RTC) Expansion Header 1 2x25 2-mm UART[1] I2C [0] MII/ MDIO +3.3V IO +5V MitySOM/MityDSP SPI[1] [CS1] McBSP[1] I/O User Programmable Xilinx Spartan 6 FPGA IO Bank 1 Expansion Header 3 2x25 2-mm HID / Thumb drive +3.3V +12V -12V I/O (available on the MityARM/MityDSP FPGA Modules - Contact Critical Link for additional information) IO Bank 1 Expansion Header 2 2x25 2-mm +5V ISO 1 (CAN) +5V ISO 2 (RS-485) +5V (Audio) +3.3V -12V Figure 1: Industrial IO Development Kit Block Diagram RS-232 Interface Description The on-board RS-232 level driver provides standard serial interface at data rates up to 115,200 baud. The serial interface is routed to the primary MitySOM / MityDSP serial bootloading port in order to allow remote code download and FLASH upgrades on an attached MitySOM / MityDSP from this connector. USB Interface Description The on-board USB interface utilizes dedicated HOST and OTG controllers inside OMAP processor. Linux drivers are available. 2 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 Ethernet Interface Description The on-board Ethernet interface features a network PHY capable of running at 10/100Mbit including link auto-negotiation and MII/MDIO capability. An industry standard RJ-45 connector is provided for external connection. This Ethernet interface may be used to perform remote code download and FLASH upgrades on an attached MitySOM or MityDSP module. QVGA/WQVGA LVDS Interface Description The Industrial IO Development Kit provides a flat-ribbon cable low profile interface for five Low Voltage Differential Signaling (LVDS) pairs. The interface design is intended to support high speed off board interconnects. In addition to custom user interfacing, the pairs may be used to interface to a Quarter VGA LCD screen using the MitySOM / MityDSP hardware and software development kit LCD interface libraries and an appropriate daughterboard interface. Off-the-shelf display solutions for WQVGA interfaces are provided by Critical Link. The interface can also be customized to support 17 IO lines at +3.3V CMOS/LVTTL signaling levels based on FPGA configuration. This interface is available only with an FPGA based MitySOM or MityDSP module installed. DVI Interface Description The Industrial IO Development Kit provides a standard DVI interface for external monitor connection. Based on CPU utilization, recommended resolution should be limited to VGA (640x480) with 5-6-5 color pallet. CAN Interface Description The on-board CAN provides a CAN V2.0B compliant interface. This interface is managed by a Microchip MCP2515 CAN controller connected to MitySOM / MityDSP via the SPI1 interface. The galvanic isolation is provided by a dedicated TI ISO1050 transceiver. The ISO1050 is powered by an isolated power supply with 1000V* isolation from the primary supply. Jumper JP504 can provide dedicated bus termination of 120Ohm. To enable termination, place shorting jumper across JP504. The Electrical interface is provided via J501, 10-pin shrouded header. Linux Driver and API examples are available to support CAN functionality. 3 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 UART Expansion Interface Description (80-000268RI-2 Assemblies) The on-board dedicated UART port provides standard serial interface at data rates up to 115,200 baud. The serial interface is routed to the UART2 serial port of MitySOM / MityDSP. This expansion port can accept an optional PROFIBUS/RS485 Expansion Board or an RS232 Expansion Board. Please contact your Critical Link representative. See the compatibility chart below to determine which modules can support the PROFIBUS protocol. Module Type MitySOM-1810 MitySOM-1810F MityDSP-L138 MityDSP-L138F MitySOM-1808 MitySOM-1808F MityDSP-6748F PROFIBUS Support Yes Yes Yes Yes No No No RS485 Support Yes Yes Yes Yes Yes Yes Yes The port also provides a +5.0V@100mA power via isolated power supply with 1000V* isolation from the primary supply as well as +3.3V@300mA from the main non-isolated power supply with a common ground. A single enable GPIO is also routed to this port in addition to the TX and RX UART signals. The Electrical interface is provided via J504, 10-pin shrouded header When the PROFIBUS/RS485 Expansion Board is used it provides galvanic isolation by a dedicated TI ISO1176 transceiver. The ISO1176 is powered by an isolated power supply with 2500Vrms* isolation from the primary supply. Jumpers on the PROFIBUS/RS485 Expansion Board can provide dedicated bus termination. Please see the PROFIBUS/RS485 Expansion Board documentation found here: http://www.mitydsp.com/products-services/base-boards/interface-modules/expansion-profibus-rs485/ When the RS232 Expansion Board is used the transceiver on it is powered from the +3.3V supply of the Development Kit. It does not provide any isolation. Please see the RS232 Expansion Board documentation found here: http://www.mitydsp.com/products-services/base-boards/interface-modules/expansion-rs232/ Note: On older Industrial IO Development Kit base boards, 80-000268RI-1 assemblies, the PROFIBUS/RS485 hardware was installed directly on the base board. The expansion board was not necessary and therefore not included. Please contact Critical Link for details or a previous datasheet if necessary. Real Time Clock Battery 4 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 The Industrial IO Development Kit includes a battery used to provide power to the installed modules real time clock. This battery has been sized to allow for approximately 6 months of unpowered time with a module installed until the battery will be depleted. 5 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS If Military/Aerospace specified cards are required, please contact the Critical Link Sales Office or unit Distributors for availability and specifications. Ambient Temperature Range Humidity Maximum Supply Voltage Storage Temperature Range 0 to 70C 0 to 95% Noncondensing 13.2 V 0 to 80C ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Power Dissipation VS Supply Voltage. IS Supply Current Real Time Clock (RTC) Battery Idraw Current draw on battery with Module Installed Tduration Battery life with Module Installed and no input power supplied Notes: 1. Typical Limit Units (Limits) 125% 1 0.45 V A 10 6 uA Months Power Supply load is dependent on Development Kit configuration and utilization. Notes: 1. Expansion card is not attached, 100% DSP/FPGA utilization, RS-232 and Ethernet are enabled and active. 6 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 ELECTRICAL INTERFACE DESCRIPTION Input Power The Industrial IO Development Kit power interface, J600, requires a single +12Volt power supply. Table 1: Input Power Interface Pin Description Signal J600 Position +12V 1 GND 2 QVGA/WQVGA LVDS /Auxiliary Interface Description The Auxiliary / LVDS interface connector provides up to 5 pairs of LVDS signals connected to the Spartan 6 device on a connected MitySOM / MityDSP (modules with FPGA only). The interface uses a standard 2mm 24 position male header. Table 3 defines the LVDS connector pinout when an FPGA enabled module is installed, Table 2 defines the pinout for Auxiliary interfaces from the module when a non-FPGA module is installed. In this case the signals are routed directly from the AM1810 or OMAP-L138 to this connector. A cable using AMP (R) TBD connector (or equivalent) should be used. Use of the LVDS pairs as outputs will require addition of termination resistors (100 Ohm) on externally designed circuit assemblies. Use of the LVDS pairs as inputs will require population of 0603 sized termination resistors on the Industrial IO Development Kit on the provided solder pads. Refer to the detailed schematic and assembly drawing for further information. Critical Link offers a line of off the shelf display solutions including a WQVGA 4.3" LCD Display with touchscreen that includes the necessary driver board, display and cable for quick development. Information is available about this solution on our website at: http://www.mitydsp.com/products-services/base-boards/interface-modules/expansion-wqvga/ 7 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 Table 2: J104 Aux / LVDS Interface Pin Description - MitySOM/MityDSP without FPGA Pin Signal Type Standard Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +5 V +5 V GND GND VP_CLKOUT3 LCD_MCLK RESET_OUT VP_CLKIN3 EMA_CS4 EMA_CS5 EMA_RAS EMA_CS2 GND GND EMA_WE EMA_CAS GND EMA_D11 EMA_D12 EMA_D13 EMA_D14 EMA_A12 EMA_D15 EMA_A13 Power Power Power Power I/O I/O I/O I/O I/O I/O I/O I/O Power Power I/O I/O Power I/O I/O I/O I/O I/O I/O I/O 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 500 mA Max. 500 mA Max. Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO 3.3V LVCMOS 3.3V LVCMOS Software configurable OMAP IO Software configurable OMAP IO 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Note that these signals are pin-muxed in the CPU and may be available for a variety of functions. Table 3: J104 Aux / LVDS Interface Pin Description - MitySOM/MityDSP with FPGA Installed Pin Signal Type Standard Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +5 V +5 V GND GND DISP_A0_P DISP_A0_N DISP_A1_P DISP_A1_N DISP_A2_P DISP_A2_N DISP_A3_P DISP_A3_N GND GND DISP_CLKIN_P DISP_CLKIN_N GND SPARE IO DISP_I2 DISP_I1 DISP_I0 DISP_O2 DISP_O1 DISP_O0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O O O LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS CMOS CMOS CMOS CMOS CMOS CMOS CMOS 500 mA Max. 500 mA Max. Display/LVDS Data channel 0 Display/LVDS Data channel 0 Display/LVDS Data channel 1 Display/LVDS Data channel 1 Display/LVDS Data channel 2 Display/LVDS Data channel 2 Display/LVDS Data channel 3 Display/LVDS Data channel 3 Display/LVDS Clock (or Data) Display/LVDS Clock (or Data) Display Aux. I/O Display Touch-screen Input 2 Display Touch-screen Input 1 Display Touch-screen Input 0 Display Touch-screen Output 2 Display Touch-screen Output 1 Display Touch-screen Output 0 Alternatively all IO can be configured as 3.3V CMOS and LVTTL IO 8 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 Expansion IO Interface The Industrial IO Development Kit provides three expansion IO connectors. Each connector includes one 50 position dual row receptacle. Mating connectors for these receptacles is a 2x25 2mm male header. Table 4 provides the signals descriptions for each pin when any type of supported MitySOM/MityDSP module is installed in the Industrial IO Development Kit. Table 5 and Table 7 provide signal descriptions for each pin when a MitySOM/MityDSP without an FPGA is installed. Table 6 and Table 8 provide signals description for each pin when a MitySOM/MityDSP with an FPGA installed. The modules with FPGA's include an on-board, user programmable Spartan-6 FPGA which provides the electrical standards for the various nets. 9 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Industrial IO Development Kit 6 March 2014 Table 4: J700 Connector Pin Assignments - MitySOM/MityDSP (with or without FPGA) Signal Type Standard Notes GND Power GND Power GND Power GND Power +3.3V Power 250mA Max (Per pin) +3.3V Power 250mA Max (Per pin) +3.3V Power 250mA Max (Per pin) +3.3V Power 250mA Max (Per pin) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED OMAP_GP0_5 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_15 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_13 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_6 I/O 3.3V LVCMOS Software configurable GPIO MMCSD0_CLK1 3.3V LVCMOS MMC Interface Clock MMCSD0_CMD1 3.3V LVCMOS MMC Interface Command\ata MMCSD0_DAT01 3.3V LVCMOS MMC Interface Data Bit 0 MMCSD0_DAT31 3.3V LVCMOS MMC Interface Data Bit 3 MMCSD0_DAT11 3.3V LVCMOS MMC Interface Data Bit 1 MMCSD0_DAT21 3.3V LVCMOS MMC Interface Data Bit RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GND Power RESERVED GND Power GND Power GND Power GND Power GND Power Note 1 - The MMCSD0 signals require the installation of 33 Ohm 0402 resistors for R700, R701, R702, R703, R704, and R705. Without the resistors, the corresponding pins on J700 are no-connects. Contact Critical Link for additional information. Note that these signals are pin-muxed in the CPU and may be available for a variety of functions. 10 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Industrial IO Development Kit 6 March 2014 Table 5: J701 Connector Pin Assignments Signal Type GND Power GND Power VP_CLKIN1 UPP_CH1_START UPP_CH1_D14 / RMII_TXD0 UPP_CH1_D15 / RMII_TXD1 UPP_CH1_D12 / RMII_RXD1 UPP_CH1_D13 / RMII_TXEN UPP_CH1_D10 / RMII_RXER UPP_CH1_D11 / RMII_RXD0 UPP_CH1_D8 / RMII_CRS_DV UPP_CH1_D9 / RMII_REF_CLK UPP_CH1_D6 UPP_CH1_D7 GND Power GND Power OMAP_GP0_5 I/O OMAP_GP0_15 I/O OMAP_GP0_6 I/O OMAP_GP0_13 I/O OMAP_GP0_1 I/O OMAP_GP0_4 I/O OMAP_GP0_3 I/O OMAP_GP0_2 I/O OMAP_GP0_0 I/O RESERVED I2C0_SDA3 I/O I2C0_SCL3 I/O GND Power GND Power GND Power GND Power -12V4 Power -12V4 Power -12V4 Power -12V4 Power +3.3V4 Power +3.3V4 Power +3.3V4 Power +3.3V4 Power +5V4 Power +5V4 Power +5V4 Power +5V4 Power +12V4 Power +12V4 Power +12V4 Power +12V4 Power GND Power GND Power - MitySOM/MityDSP without FPGA Standard Notes 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO 3.3V LVCMOS 3.3V LVCMOS Software configurable OMAP IO Software configurable OMAP IO 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) 250mA Max (Per pin) Note that these signals are pin-muxed in the CPU and may be available for a variety of functions. 11 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Industrial IO Development Kit 6 March 2014 Table 6: J701 Connector Pin Assignments - MitySOM/MityDSP with FPGA Installed Signal Type Standard Notes GND Power GND Power FPGA_IO_48_N1,2 Hardware Configurable FPGA IO FPGA_IO_48_P1,2 Hardware Configurable FPGA IO FPGA_IO_46_N1,2 Hardware Configurable FPGA IO FPGA_IO_46_P1,2 Hardware Configurable FPGA IO FPGA_IO_44_N1,2 Hardware Configurable FPGA IO FPGA_IO_44_P1,2 Hardware Configurable FPGA IO FPGA_IO_42_N1,2 Hardware Configurable FPGA IO FPGA_IO_42_P1,2 Hardware Configurable FPGA IO FPGA_IO_40_N1,2 Hardware Configurable FPGA IO FPGA_IO_40_P1,2 Hardware Configurable FPGA IO FPGA_IO_38_N1,2 Hardware Configurable FPGA IO FPGA_IO_38_P1,2 Hardware Configurable FPGA IO GND Power GND Power OMAP_GP0_5 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_15 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_6 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_13 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_1 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_4 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_3 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_2 I/O 3.3V LVCMOS Software configurable GPIO OMAP_GP0_0 I/O 3.3V LVCMOS Software configurable GPIO RESERVED I2C0_SDA3 I/O 3.3V LVCMOS Software configurable GPIO I2C0_SCL3 I/O 3.3V LVCMOS Software configurable GPIO GND Power GND Power GND Power GND Power -12V4 Power 250mA Max (Per pin) -12V4 Power 250mA Max (Per pin) -12V4 Power 250mA Max (Per pin) -12V4 Power 250mA Max (Per pin) +3.3V4 Power 250mA Max (Per pin) +3.3V4 Power 250mA Max (Per pin) +3.3V4 Power 250mA Max (Per pin) +3.3V4 Power 250mA Max (Per pin) +5V4 Power 250mA Max (Per pin) +5V4 Power 250mA Max (Per pin) +5V4 Power 250mA Max (Per pin) +5V4 Power 250mA Max (Per pin) +12V4 Power 250mA Max (Per pin) +12V4 Power 250mA Max (Per pin) +12V4 Power 250mA Max (Per pin) +12V4 Power 250mA Max (Per pin) GND Power GND Power Notes: 1 3.3V CMOS or 3.3V LVTTL Standard signal levels. 2 <signal_name>_N/_P can be configured as a differential pair or single-ended FPGA I/O 3 The I2C bus controlled by MitySOM / MityDSP hardware. Slave address 0x90 reserved for Power Management Controller IC. User should not attempt to write any data to this address as it will result in module damage. 4 Maximum current per power bus should be limited to 1.0Amp, it is advised to have input fuses on expansion board. 12 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 Table 7: J702 Connector Pin Assignments - MitySOM/MityDSP without FPGA Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal GND GND UPP_CH1_D5 UPP_CH1_ENABLE UPP_CH1_D3 UPP_CH1_D4 UPP_CH1_WAIT UPP_CH1_D2 UPP_CH1_D0 UPP_CH1_D1 UPP_CH0_ENABLE UPP_CH1_CLK VP_CLKIN2 VP_CLKOUT2 UPP_CH0_START UPP_CH0_WAIT VP_CLKIN0 UPP_CH0_CLK EMA_OE EMA_CS0 EMA_BA1 EMA_BA0 EMA_A1 EMA_A0 EMA_A3 EMA_A2 EMA_A5 EMA_A4 EMA_A11 EMA_A10 EMA_A9 EMA_A8 EMA_A7 EMA_A6 EMA_D8 EMA_D9 Reserved Reserved EMA_CLK EMA_SDCKE EMA_WEN_DQM1 EMA_WEN_DQM0 EMA_D0 EMA_D1 EMA_D2 EMA_D3 EMA_D4 EMA_D5 GND GND Type Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Power Standard 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 3.3V LVCMOS 13 Notes Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Software configurable OMAP IO Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 Table 8: J702 Connector Pin Assignments - MitySOM/MityDSP with FPGA Installed Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal GND GND FPGA_IO_36_N1 FPGA_IO_36_P1 FPGA_IO_34_N FPGA_IO_34_P FPGA_IO_32_N FPGA_IO_32_P FPGA_IO_30_N FPGA_IO_30_P FPGA_IO_28_N FPGA_IO_28_P FPGA_IO_26_N FPGA_IO_26_P FPGA_IO_24_N FPGA_IO_24_P FPGA_IO_22_N FPGA_IO_22_P FPGA_IO_47_N FPGA_IO_47_P FPGA_IO_45_N FPGA_IO_45_P FPGA_IO_43_N FPGA_IO_43_P FPGA_IO_41_N FPGA_IO_41_P FPGA_IO_39_N FPGA_IO_39_P FPGA_IO_33_N FPGA_IO_33_P FPGA_IO_35_N FPGA_IO_35_P FPGA_IO_37_N FPGA_IO_37_P FPGA_IO_23_N FPGA_IO_23_P RESERVED RESERVED FPGA_IO_11_N FPGA_IO_11_P FPGA_IO_13_N FPGA_IO_13_P FPGA_IO_15_N FPGA_IO_15_P FPGA_IO_17_N FPGA_IO_17_P FPGA_IO_19_N FPGA_IO_19_P GND GND Type Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Power Standard Notes LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL LVDS, 3.3V LVCMOS/LVTTL Notes: 1 <signal_name>_N/_P can be configured as a differential pair or single-ended FPGA IO. 14 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 Signal Naming Description Signal FPGA_IO_##_N/P OMAP_GP0_## DO_## DI_## Table 9: Daughter Card Signal Description Type Standard Notes I/O LVDS/3.3V CMOS/ Direct Interface to MitySOM / 3.3V LVTTL MityDSP Spartan6 FPGA. I/O 3.3V CMOS Direct Interface to MitySOM / MityDSP processor O 3.3V CMOS Digital Output. Update Rate of 20 nsec. DO_CLK provides sampling clock - outputs should be sampled on rising edge. I 3.3V CMOS Digital Input. Sampling interval < 2 s. CAN Interface Table 10: J501 Connector Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 Signal RESERVED CANL GND RESERVED RESERVED RESERVED CANH RESERVED +5V RESERVED Type Standard I/O Power Notes CAN Bus Signal L CAN Bus Isolated Ground I/O CAN Bus Signal H Power Isolated +5V Output, 20mA Max Notes: please see Figure 2 for physical pin-out of connector UART Expansion Interface (80-000268RI-2 Assemblies) Table 11: J504 Connector Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 Signal RS485_TX_ENB RS485_RX Type I/O I/O +3.3V RESERVED GND_ISO485 RS485_TX I/O GND RESERVED RESERVED +5V_RS485 Standard Notes Software configurable OMAP IO Software configurable OMAP IO (UART2_RX/I2C_SCL/GPIO) +3.3V 300mA Max Power IO Isolated RS485 GND Power System GND Power Isolated +5V Output, 100mA Max Software configurable OMAP IO (UART2_TX/I2C1_SDA/GPIO) Notes: please see Figure 2 for physical pin-out of connector Note: On older Industrial IO Development Kit base boards, 80-000268RI-1 assemblies, the PROFIBUS/RS485 hardware was installed directly on the base board. The expansion board was not necessary and therefore not included. Please contact Critical Link for details or a previous datasheet if necessary. 15 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 RS-232 Interface Table 12: J502 Connector Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 Signal RESERVED RS232_RX RS232_TX RESERVED GND RESERVED RESERVED RESERVED RESERVED RESERVED Type Standard Notes I O RS232-level Input Signal RS232-level Output Signal Power RS-232 Ground Notes: please see Figure 2 for physical pin-out of connector 5 4 3 2 1 10 9 8 7 6 Figure 2: J501, J502, J504 Pin-out (Top View) 16 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 MECHANICAL INTERFACE DESCRIPTION Main Board Interface / Mounting Board mounting is compatible to ETX standard. 92.50 95.00 4x O 2.90 2.50 3.00 111.00 114.00 Figure 3: Industrial IO Development Kit Outline and Mounting Holes Locations (Top View, mm) 17 Copyright (c) 2007-2013, Critical Link LLC 1 3 47 49 4 48 50 Industrial IO Development Kit 6 March 2014 2 Critical Link, LLC www.CriticalLink.com 2 1 2 1 4 3 4 3 48 47 48 47 50 49 50 49 88.00 56.00 10.00 6.25 44.25 90.25 107.75 Figure 4: Mounting holes for expansion I/O connectors based on Molex 79109-1224 connector (Top View, mm) 18 Copyright (c) 2007-2013, Critical Link LLC Critical Link, LLC www.CriticalLink.com Industrial IO Development Kit 6 March 2014 ORDERING INFORMATION Development Kits The following table lists the standard Development Kit configurations. For shipping status, availability, and lead time of these or other configurations please contact your Critical Link representative. Table 13: Standard Model Numbers Development Kit PROFIBUS Module Included Model Support 80-000365 L138-FI-225-RC Yes 80-000382 L138-FI-236-RL Yes 80-000395 L138-FG-225-RC Yes 80-000413 L138-DG-225-RI Yes 80-000454 L138-DI-225-RI Yes 80-000334 L138-FX-225-RC Yes 80-000315 1808-FG-225-RC No 80-000317 1808-FX-225-RC No 80-000320 1810-DG-225-RC Yes 80-000348 1810-DX-225-RC Yes *Contact Critical Link 6748-FG-225-RC No LVDS/LCD Support Yes Yes Yes Yes Yes No Yes No Yes No Yes Expansions Kits The following table lists the available expansion kits for the above development kits. For shipping status, availability, and lead time of these or other configurations please contact your Critical Link representative. Table 14: Expansion Kit Model Numbers Expansion Kit Model 80-000541 80-000540 80-000536 Type Interface Port RS232 Expansion Board PROFIBUS/RS485 Expansion Board WQVGA LCD w/Driver Board J504 J504 J104 Notes Any module See above table. All modules support RS485. Any module WITH an FPGA REVISION HISTORY Date 22-NOV-2010 27-AUG-2012 27-SEP-2012 27-MAR-2013 5-MAR-2014 Change Description Initial revision. 80-000268-RI-1 assemblies. General updates and changes for 80-000268-RI-2 assemblies. Updated J700 info regarding MMC signals and removed SPI_CS0 (pin 29) as it is reserved for SPI NOR FLASH. Addressed pin naming issues for J700, J701 and J702. Updated 5V Isolated current output to 100mA from 150mA Update MitySOM product name. Corrected J702 pin 26. 19 Copyright (c) 2007-2013, Critical Link LLC Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Critical Link: 80-000315 80-000317 80-000320 80-000334 80-000348 80-000395 80-000365 80-000382 80-000413 80000454 80-000536