CY14B101L 1 Mbit (128K x 8) nvSRAM Features Functional Description [1] Pin compatible with STK14CA8 Hands off Automatic STORE on Power Down with only a small Capacitor STORE to QuantumTrap Nonvolatile Elements is initiated by software, hardware, or AutoStore on Power Down RECALL to SRAM initiated by Software or Power Up Unlimited READ, WRITE, and RECALL Cycles 200,000 STORE Cycles to QuantumTrap 20 year Data Retention at 55C Single 3V +20%, -10% Operation Commercial and Industrial Temperature 32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages RoHS Compliance The Cypress CY14B101L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. ig ns 25 ns , 35 ns, and 45 ns Access Times fo r N ew D es d Logic Block Diagram VCC de QuantumTrap 1024 x 1024 ec DQ 0 RECALL STORE/ RECALL CONTROL DQ 2 DQ 3 ot DQ 4 DQ 5 DQ 6 HSB SOFTWARE DETECT A15 - A 0 COLUMN IO INPUT BUFFERS R DQ 1 N STATIC RAM ARRAY 1024 X 1024 POWER CONTROL STORE om ROW DECODER m en A5 A6 A7 A8 A9 A 12 A 13 A 14 A 15 A 16 VCAP COLUMN DEC A 0 A 1 A 2 A 3 A 4 A 10 A 11 DQ 7 OE CE WE Note 1. 25 ns speed in Industrial temperature range is over the operating voltage range of 3.3V+ 0.3V only. Cypress Semiconductor Corporation Document Number: 001-06400 Rev. *M * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 5, 2010 [+] Feedback CY14B101L Contents Operating Range ................................................................. 8 DC Electrical Characteristics ............................................ 8 Data Retention and Endurance ......................................... 8 Capacitance ........................................................................ 9 Thermal Resistance ............................................................ 9 AC Test Conditions ............................................................ 9 SRAM Read Cycle ...................................................... 10 SRAM Write Cycle....................................................... 11 AutoStore or Power Up RECALL .................................... 12 Software Controlled STORE/RECALL Cycle .................. 13 Switching Waveforms ...................................................... 14 Part Numbering Nomenclature ........................................ 15 Ordering Information ........................................................ 15 Package Diagrams ............................................................ 17 Sales, Solutions, and Legal Information ........................ 20 Worldwide Sales and Design Support......................... 20 Products ...................................................................... 20 es D ew N fo r N ot R ec om m en de d Functional Description ....................................................... 1 Logic Block Diagram .......................................................... 1 Contents .............................................................................. 2 Pinouts ................................................................................ 3 Device Operation ................................................................ 4 SRAM Read ......................................................................... 4 SRAM Write ......................................................................... 4 AutoStore Operation .......................................................... 4 Hardware STORE (HSB) Operation ................................... 4 Hardware RECALL (Power Up) .......................................... 5 Software STORE ................................................................. 5 Software RECALL ............................................................... 5 Data Protection ................................................................... 5 Noise Considerations ......................................................... 5 Low Average Active Power ................................................ 5 Preventing Store ................................................................. 6 Best Practices ..................................................................... 6 Maximum Ratings ............................................................... 8 ig ns Features ............................................................................... 1 Document Number: 001-06400 Rev. *M Page 2 of 21 [+] Feedback CY14B101L Pinouts Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP A3 A2 A1 A0 DQ1 DQ2 NC NC Table 1. Pin Definitions I/O Type Input DQ0-DQ7 34 33 32 31 30 29 28 27 26 25 NC DQ6 OE A10 CE DQ7 DQ5 DQ4 DQ3 VCC ig ns HSB WE A13 A8 A9 NC A11 NC NC NC VSS NC Top View (not to scale) 19 20 21 22 23 24 Description d Alt A0-A16 VCC A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM. de Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 es A16 A14 A12 A7 A6 A5 NC A4 NC NC NC VSS NC NC DQ0 D VCAP VCC A15 HSB WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 ew 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 fo r VCAP A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE G Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. om m en WE VSS Ground Ground for the Device. The device is connected to ground of the system. Power Supply Power Supply Inputs to the Device. HSB Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional). R No Connect No Connect. This pin is not connected to the die. N NC Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. ot VCAP ec VCC Document Number: 001-06400 Rev. *M Page 3 of 21 [+] Feedback CY14B101L Device Operation Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC Electrical Characteristics on page 8 for the size of VCAP. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up is placed on WE to hold it inactive during power up. The CY14B101L nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The CY14B101L supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. Figure 2. AutoStore Mode ig ns V CC 10k Ohm es V CAP 0.1UF V CC V CAP WE ew N fo r d The CY14B101L performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0-16 determines the 131,072 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. D SRAM Read de SRAM Write m en A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. ec om The data on the common IO pins DQ0-7 are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. R AutoStore Operation N ot The CY14B101L stores data to nvSRAM using one of three storage operations: 1. Hardware store activated by HSB 2. Software store activated by an address sequence 3. AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101L. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored, unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull-up resistor is shown connected to HSB. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Hardware STORE (HSB) Operation The CY14B101L provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B101L conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14B101L continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. If HSB is not used, it is left unconnected. Document Number: 001-06400 Rev. *M Page 4 of 21 [+] Feedback CY14B101L Hardware RECALL (Power Up) Data Protection During power up or after any low power condition (VCC < VSWITCH), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. The CY14B101L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC is less than VSWITCH. Software STORE If the CY14B101L is in a WRITE mode (both CE and WE are low) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions. ig ns Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B101L software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. es Noise Considerations D The CY14B101L is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise. Low Average Active Power fo r N CMOS technology provides the CY14B101L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 3 shows the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14B101L depends on the following items: de d To initiate the software STORE cycle, the following READ sequence is performed: 1. Read address 0x4E38, Valid READ 2. Read address 0xB1C7, Valid READ 3. Read address 0x83E0, Valid READ 4. Read address 0x7C1F, Valid READ 5. Read address 0x703F, Valid READ 6. Read address 0x8FC0, Initiate STORE cycle ew Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. The duty cycle of chip enable The overall cycle rate for accesses The ratio of READs to WRITEs CMOS versus TTL input levels The operating temperature Software RECALL The VCC level IO loading ec om m en The software sequence is clocked with CE controlled READs or OE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation. Figure 3. Current Versus Cycle Time N ot R Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x4E38, Valid READ 2. Read address 0xB1C7, Valid READ 3. Read address 0x83E0, Valid READ 4. Read address 0x7C1F, Valid READ 5. Read address 0x703F, Valid READ 6. Read address 0x4C63, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. Document Number: 001-06400 Rev. *M Page 5 of 21 [+] Feedback CY14B101L Preventing Store Best Practices Disable the AutoStore function by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, perform the following sequence of CE controlled READ operations: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8B45 AutoStore Disable nvSRAM products have been used effectively for over 15 years. While ease of use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, the best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). N ew D es ig ns The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on must always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. fo r Re-enable the AutoStore by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, perform the following sequence of CE controlled READ operations: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4B46 AutoStore Enable The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because higher inrush currents may reduce the reliability of the internal pass transistor. Customers that want to use a larger VCAP value to make sure there is extra store charge should discuss their VCAP size selection with Cypress to understand any impact on the Vcap voltage level at the end of a tRECALL period. N ot R ec om m en de d If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) is issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled. If AutoStore is firmware disabled, it does not reset to "autostore enabled" on every power down event captured by the nvSRAM. The application firmware should re-enable or re-disable autostore on each reset sequence based on the behavior desired. Document Number: 001-06400 Rev. *M Page 6 of 21 [+] Feedback CY14B101L . Table 2. Hardware Mode Selection WE X OE X A15 - A0 Mode IO Power X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active[3] L L X X Write SRAM Input Data Active L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output Data Output Data Output Data Output Data Output Data Output Data Active[2, 3, 4] L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output Data Output Data Output Data Output Data Output Data Output Data Active[2, 3, 4] L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Output Data Active ICC2[2, 3, 4] Output Data Output Data Output Data Output Data Output High Z L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z es D ew N fo r d de Active[2, 3, 4] N ot R ec om m en ig ns CE H Notes 2. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle. 3. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes. 4. IO state depends on the state of OE. The IO table shown is based on OE Low. Document Number: 001-06400 Rev. *M Page 7 of 21 [+] Feedback CY14B101L Maximum Ratings Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Surface Mount Lead Soldering Temperature (3 Seconds) .......................................... +260C DC output Current (1 output at a time, 1s duration) .... 15 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Supply Voltage on VCC Relative to GND ..........-0.5V to 4.1V Latch Up Current ................................................... > 200 mA Voltage Applied to Outputs in High Z State ....................................... -0.5V to VCC + 0.5V Operating Range Range Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. -2.0V to VCC + 2.0V Commercial Over the operating range (VCC = 2.7V to 3.6V) [5, 6] Description Test Conditions Min tRC = 25 ns Commercial tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Industrial Values obtained without output loads. IOUT = 0 mA. d fo r Average VCC Current 2.7V to 3.6V 2.7V to 3.6V N ICC1 0C to +70C -40C to +85C ew DC Electrical Characteristics Parameter VCC D Industrial Ambient Temperature es Input Voltage...........................................-0.5V to Vcc + 0.5V ig ns Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Max Unit 65 55 50 mA mA 70 60 55 mA mA mA Average VCC Current during STORE All Inputs Do Not Care, VCC = Max Average current for duration tSTORE 6 mA ICC3 Average VCC Current at WE > (VCC - 0.2V). All other inputs cycling. tRC= 200 ns, 5V, 25C Dependent on output loading and cycle rate. Values obtained without output loads. Typical 10 mA ICC4 Average VCAP Current All Inputs Do Not Care, VCC = Max during AutoStore Cycle Average current for duration tSTORE 3 mA ISB VCC Standby Current 3 mA IIX -1 +1 A IOZ Input Leakage Current VCC = Max, VSS < VIN < VCC Off State Output VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL Leakage Current -1 +1 A VIH Input HIGH Voltage 2.0 VCC + 0.5 V VSS - 0.5 0.8 m en om ec Input LOW Voltage Output HIGH Voltage IOUT = -2 mA Output LOW Voltage IOUT = 4 mA Storage Capacitor Between VCAP pin and Vss, 6V rated. N VOL CE > (VCC - 0.2V). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. R ot VIL VOH de ICC2 VCAP V 2.4 17 V 0.4 V 120 uF Data Retention and Endurance Min Unit DATAR Parameter Data Retention at 55C Description 20 Years NVC Nonvolatile STORE Operations 200 K Notes 5. The HSB pin has IOUT = -10 A for VOH of 2.4 V. This parameter is characterized but not tested. 6. VIH changes by 100 mV when VCC > 3.5V. Document Number: 001-06400 Rev. *M Page 8 of 21 [+] Feedback CY14B101L Capacitance In the following table, the capacitance parameters are listed.[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0V Max Unit 7 pF 7 pF In the following table, the thermal resistance parameters are listed.[7] JA Description JC Test Conditions 32-SOIC 48-SSOP Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 33.64 32.9 C/W 16.35 C/W es Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) ew Figure 4. AC Test Loads R1 577 R1 577 For Tri-state Specs 3.0V N 3.0V 13.6 D Parameter ig ns Thermal Resistance Output fo r Output R2 789 5 pF R2 789 de d 30 pF AC Test Conditions N ot R ec om m en Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times (10% to 90%) ...................... <5 ns Input and Output Timing Reference Levels .................... 1.5V Note 7. These parameters are guaranteed by design and are not tested. Document Number: 001-06400 Rev. *M Page 9 of 21 [+] Feedback CY14B101L AC Switching Characteristics SRAM Read Cycle 25 ns[1] Min Switching Waveforms Max Min 45 ns Max 25 45 35 15 3 3 3 3 45 20 ig ns 25 12 10 3 3 13 0 0 10 15 0 13 15 0 25 Max 45 35 0 Min 35 25 es Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 35 ns D Description ew Parameter Cypress Alt Parameter tACE tELQV tAVAV, tELEH tRC [8] tAA [9] tAVQV tDOE tGLQV tAXQX tOHA [9] tLZCE [10] tELQX tHZCE [10] tEHQZ tGLQX tLZOE [10] tHZOE [10] tGHQZ tPU [7] tELICCH tEHICCL tPD [7] 0 35 45 Unit ns ns ns ns ns ns ns ns ns ns ns N Figure 5. SRAM Read Cycle 1: Address Controlled [8, 9, 11] fo r W5& de W $$ d $''5(66 m en W2+$ '4 '$7$287 '$7$9$/,' om Figure 6. SRAM Read Cycle 2: CE and OE Controlled [8, 11] R W$&( W3' W/=&( W+=&( ot &( ec $''5(66 W5& N 2( W+=2( W'2( W/=2( '4 '$7$287 '$7$9$/,' W 38 ,&& $&7,9( 67$1'%< Notes 8. WE and HSB must be HIGH during SRAM READ cycles. 9. Device is continuously selected with CE and OE both Low. 10. Measured 200 mV from steady state output voltage. 11. HSB must remain high during READ and WRITE cycles. Document Number: 001-06400 Rev. *M Page 10 of 21 [+] Feedback CY14B101L SRAM Write Cycle 25 ns[1] Description tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [10,12] tLZWE [10] Min Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write Max Min 25 20 20 10 0 20 0 0 35 25 25 12 0 25 0 0 10 3 Switching Waveforms 45 ns Max es Alt 35 ns Min Max 45 30 30 15 0 30 0 0 13 3 D Cypress Parameter ig ns Parameter 15 3 Unit ns ns ns ns ns ns ns ns ns ns ew Figure 7. SRAM Write Cycle 1: WE Controlled [12, 13] N tWC ADDRESS CE de d tAW tSA fo r tSCE m en WE tSD tHD tHZWE tLZWE HIGH IMPEDANCE PREVIOUS DATA DATA OUT tPWE DATA VALID om DATA IN tHA ec Figure 8. SRAM Write Cycle 2: CE and OE Controlled [12, 13] tWC R ot ADDRESS WE tHA tSCE tSA N CE tAW tPWE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Notes 12. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 13. CE or WE must be greater than VIH during address transitions. Document Number: 001-06400 Rev. *M Page 11 of 21 [+] Feedback CY14B101L AutoStore or Power Up RECALL Alt tHRECALL [14] tSTORE [15, 16] VSWITCH tVCCRISE CY14B101L Min Max 20 12.5 2.65 150 Description tRESTORE tHLHZ Power up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time Switching Waveforms es Figure 9. AutoStore/Power Up RECALL STORE occurs only if a SRAM write has happened ms ms V s No STORE occurs without atleast one SRAM write D VCC Unit ig ns Parameter N ew VSWITCH fo r tVCCRISE AutoStore tSTORE POWER-UP RECALL tHRECALL tHRECALL om Read & Write Inhibited m en de d tSTORE N ot R ec Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below VSWITCH Notes 14. tHRECALL starts from the time VCC rises above VSWITCH. 15. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place. 16. Industrial Grade devices requires 15 ms max. Document Number: 001-06400 Rev. *M Page 12 of 21 [+] Feedback CY14B101L Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [17, 18] Parameter Alt 25 ns[1] Description Min 35 ns Max Min Max 45 ns Min Max Unit tAVAV STORE/RECALL Initiation Cycle Time 25 35 45 ns tSA tAVEL Address Setup Time 0 0 0 ns tCW tELEH Clock Pulse Width 20 25 tHA tGHAX, tELAX Address Hold Time 1 1 120 30 ns 1 ns 120 120 s es RECALL Duration tRECALL ig ns tRC[18] Switching Waveforms tRC ew tRC tSA ADDRESS # 6 N ADDRESS # 1 ADDRESS D Figure 10. CE Controlled Software STORE/RECALL Cycle [18] tSCE fo r CE d tHA de OE m en t STORE / t RECALL DATA VALID DATA VALID DQ (DATA) HIGH IMPEDANCE om Figure 11. OE Controlled Software STORE/RECALL Cycle [18] ADDRESS # 6 R N CE ADDRESS # 1 tRC ot ADDRESS ec tRC tSA tSCE OE tHA DQ (DATA) DATA VALID t STORE / t RECALL DATA VALID HIGH IMPEDANCE Notes 17. The software sequence is clocked on the falling edge of CE controlled READs or OE controlled READs. 18. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. Document Number: 001-06400 Rev. *M Page 13 of 21 [+] Feedback CY14B101L Hardware STORE Cycle Parameter tPHSB tDELAY [19] Alt CY14B101L Description Min tHLHX Hardware STORE Pulse Width 15 tHLQZ , tBLQZ Time Allowed to Complete SRAM Cycle 1 tss[20, 21] Soft Sequence Processing Time ns 70 s 70 us ig ns Switching Waveforms Unit Max es Figure 12. Hardware STORE Cycle de d fo r N ew D 3+6% m en Figure 13. Soft Sequence Processing[20, 21] om 6RIW6HTXHQFH &RPPDQG $GGUHVV W6$ $GGUHVV W&: 6RIW6HTXHQFH &RPPDQG $GGUHVV W66 $GGUHVV W&: ec $GGUHVV W66 &( N ot R 9&& Notes 19. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete. 20. This is the amount of time to take action on a soft sequence command. Vcc power must remain high to effectively register command. 21. Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command. Document Number: 001-06400 Rev. *M Page 14 of 21 [+] Feedback CY14B101L Part Numbering Nomenclature CY 14 B 101 L - SZ 25 X C T Option T - Tape and Reel Blank - Std. ig ns Temperature C - Commercial (0 to 70C) I - Industrial (-40 to 85C) Speed 25 - 25 ns 35 - 35 ns 45 - 45 ns Density 101 - 1 Mb ew Data Bus L - x8 D Package SZ - 32 SOIC SP - 48 SSOP es Pb-Free fo r N Voltage B - 3.0V de d NVSRAM 14 - AutoStore + Software Store + Hardware Store Ordering Information m en Cypress om These parts are not recommended for new designs. Speed (ns) Operating Voltage Range CY14B101L-SZ25XCT 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SZ25XC 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101LL-SP25XCT 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101LL-SP25XC 51-85061 2.7V to 3.6V 48-pin SSOP ec R 25 Package Diagram Ordering Code Package Type 51-85127 3.0V to 3.6V 32-pin SOIC CY14B101L-SZ25XI 51-85127 3.0V to 3.6V 32-pin SOIC CY14B101L-SP25XIT 51-85061 3.0V to 3.6V 48-pin SSOP CY14B101L-SP25XI 51-85061 3.0V to 3.6V 48-pin SSOP N ot CY14B101L-SZ25XIT Document Number: 001-06400 Rev. *M Operating Range Commercial Industrial Page 15 of 21 [+] Feedback CY14B101L Ordering Information These parts are not recommended for new designs. CY14B101L-SZ35XCT 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SZ35XC 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SP35XCT 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101L-SP35XC 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101L-SZ35XIT 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SZ35XI 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SP35XIT 51-85061 2.7V to 3.6V 48-pin SSOP Operating Range Package Type Commercial ig ns 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101L-SZ45XCT 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SZ45XC 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SP45XCT 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101L-SP45XC 51-85061 2.7V to 3.6V CY14B101L-SZ45XIT 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SZ45XI 51-85127 2.7V to 3.6V 32-pin SOIC CY14B101L-SP45XIT 51-85061 2.7V to 3.6V 48-pin SSOP CY14B101L-SP45XI 51-85061 2.7V to 3.6V 48-pin SSOP Industrial Commercial ew D CY14B101L-SP35XI N 45 Operating Voltage Range fo r 35 Package Diagram Ordering Code es Speed (ns) 48-pin SSOP Industrial N ot R ec om m en de d All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts Document Number: 001-06400 Rev. *M Page 16 of 21 [+] Feedback CY14B101L Package Diagrams 51-85127 *B N ot R ec om m en de d fo r N ew D es ig ns Figure 14. 32-Pin (300 Mil) SOIC (51-85127) Document Number: 001-06400 Rev. *M Page 17 of 21 [+] Feedback CY14B101L Package Diagrams (continued) 51-85061 *D N ot R ec om m en de d fo r N ew D es ig ns Figure 15. 48-Pin Shrunk Small Outline Package (51-85061) Document Number: 001-06400 Rev. *M Page 18 of 21 [+] Feedback CY14B101L Document History Page Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM Document Number: 001-06400 Rev. ECN No. Orig. of Change Submission Date Description of Change 425138 TUP See ECN New data sheet 437321 TUP See ECN Show data sheet on External Web *B 471966 TUP See ECN Changed ICC3 from 5 mA to 10 mA Changed ISB from 2 mA to 3 mA Changed VIH(min) from 2.2V to 2.0V Changed tRECALL from 40 s to 50 s Changed Endurance from 1 million Cycles to 500K Cycles Changed Data Retention from 100 years to 20 years Added Soft Sequence Processing Time Waveform Updated Part Numbering Nomenclature and Ordering Information *C 503272 PCI See ECN Changed from Advance to Preliminary Changed the term "Unlimited" to "Infinite" Changed Endurance from 500K Cycles to 200K Cycles Added temperature specification to Data Retention - 20 years at 55C Removed Icc1 values from the DC table for 25 ns and 35 ns industrial grade Changed Icc2 value from 3 mA to 6 mA in the DC table Added a footnote on VIH Changed VSWITCH(min) from 2.55V to 2.45V Added footnote 17 related to using the software command Updated Part Nomenclature Table and Ordering Information Table *D 597002 TUP See ECN Removed VSWITCH(min) specification from the AutoStore/Power Up RECALL table Changed tGLAX specification from 20 ns to 1 ns Added tDELAY(max) specification of 70 s in the hardware STORE cycle table Removed tHLBL specification Changed tSS specification from 70 s (min) to 70 s (max) Changed VCAP(max) from 57 F to 120 F *E 688776 VKN *F 1349963 UHA/SFV *G 2427986 *H 2546756 m en de d fo r N ew D es ig ns ** *A om See ECN Added footnote related to HSB Changed tGLAX to tGHAX Changed from Preliminary to Final Updated Ordering Information table GVCH See ECN Move to external web GVCH/AESA 08/01/2008 Aligned part number nomenclature Corrected typo in ordering information Changed pin definition of NC pin Updated data sheet template N ot R ec See ECN Document Number: 001-06400 Rev. *M Page 19 of 21 [+] Feedback CY14B101L Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM Document Number: 001-06400 Rev. ECN No. Orig. of Change Submission Date *I 2625139 GVCH/PYRS 01/30/09 *J 2695908 GVCH/AESA 04/20/2009 Removed part numbers CY14B101L-SP25XC and CY14B101L-SP25XCT. Added part numbers CY14B101LL-SP25XC and CY14B101LL-SP25XCT. *K 2814390 GVCH 11/25/2009 Added Note in the Ordering information section mentioning that these parts are not recommended for new designs. Added "Not recommended for new designs" watermark in the PDF. *L 2895330 GVCH 03/18/2010 *M 2902517 GVCH 03/31/2010 Description of Change d fo r N ew D es ig ns Updated "features" Added data retention at 55oC Updated WE pin description Added best practices Added ICC1 spec for 25ns and 35ns access speed for industrial temperate Updated VIH from Vcc+0.3 to Vcc+0.5 Removed footnote 4 and 5 Added Data retention and Endurance Table Added Thermal resistance values Changed parameter tAS to tSA Changed tRECALL from 50us to 120us (Including tss of 70us) Renamed tGLAX to tHA Updated figure 11 and 12 Renamed tHLHX to tPHSB Updated Figure 13 Added watermark "Not Recommended for New Designs" in pdf version. Move to external web. N ot R ec om m en de Added foot note 1 for 25ns access speed. Updated Package Diagrams. Added Operating Voltage Range column to Ordering Information. Document Number: 001-06400 Rev. *M Page 20 of 21 [+] Feedback CY14B101L Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC Solutions cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 ig ns Automotive cypress.com/go/powerpsoc es cypress.com/go/plc Memory cypress.com/go/memory cypress.com/go/image PSoC D Optical & Image Sensing cypress.com/go/psoc cypress.com/go/touch ew Touch Sensing USB Controllers cypress.com/go/USB cypress.com/go/wireless R ec om m en de d fo r N Wireless/RF N ot (c) Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06400 Rev. *M Revised April 5, 2010 Page 21 of 21 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback