CY14B101L
1 Mbit (128K x 8) nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-06400 Rev. *M Revised April 5, 2010
Features
■25 ns[1], 35 ns, and 45 ns Access Times
■Pin compatible with STK14CA8
■Hands off Automatic STORE on Power Down with only a small
Capacitor
■STORE to QuantumTrap Nonvolatile Elements is initiated by
software, hardware, or AutoStore on Power Down
■RECALL to SRAM initiated by Software or Power Up
■Unlimited READ, WRITE, and RECALL Cycles
■200,000 STORE Cycles to QuantumTrap
■20 year Data Retention at 55°C
■Single 3V +20%, –10% Operation
■Commercial and Industrial Temperature
■32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
■RoHS Compliance
Functional Description
The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
1024 X 1024
QuantumTrap
1024 x 1024
STORE
RECALL
COLUMN IO
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
15
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
11
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
Note
1. 25 ns speed in Industrial temper ature range is over the operating voltage range of 3.3V+ 0. 3V only.
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Contents
Features ...............................................................................1
Functional Description ...................... .................................1
Logic Block Diagram .............. .. ..........................................1
Contents .............................................................................. 2
Pinouts ................................................................................3
Device Operation ................................................................4
SRAM Read .........................................................................4
SRAM Write .........................................................................4
AutoStore Operation ..........................................................4
Hardware STORE (HSB) Operation ...................................4
Hardware RECALL (Power Up) ..........................................5
Software STORE .................................................................5
Software RECALL ...............................................................5
Data Protection ...................................................................5
Noise Considerations .........................................................5
Low Average Active Power ....................... ... ... ...................5
Preventing Store .................................................................6
Best Practices .....................................................................6
Maximum Ratings ...............................................................8
Operating Range .................................................................8
DC Electrical Characteristics ............ ... .............................8
Data Retention and Endurance .........................................8
Capacitance ........................................................................9
Thermal Resistance ............................................................9
AC Test Conditions ................. ... .............. .............. ............9
SRAM Read Cycle...................................................... 10
SRAM Write Cycle....................................................... 11
AutoStore or Power Up RECALL ....................................12
Software Controlled STORE/RECALL Cycle ..................13
Switching Waveforms ......................................................14
Part Numbering Nomenclature ....... .................................15
Ordering Information ........................................................15
Package Diagrams ............................................................17
Sales, Solutions, and Legal Information ........................20
Worldwide Sales and Design Support......................... 20
Products...................................................................... 20
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Pinouts Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
Table 1. Pin Definitions
Pin Name Alt I/O Type Description
A0–A16 Input Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM.
DQ0-DQ7Input or Output Bidirectional Data IO Lines. Used as input or output lines dependi ng on operation.
WE WInput Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE EInput Chip Enable Input, Active LOW . When LOW , selects the chip. When HIGH, deselects the chip.
OE GInput Output Enable, Active LOW . The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS Ground Ground for the Device. The device is connected to gro und of the system.
VCC Power Supply Power Supply Inputs to the Device.
HSB Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
NC No Connect No Connect. This pin is not connected to the die.
VCAP
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
VCC
A15
HSB
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
VSS
DQ2DQ3
DQ4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
16
NC
DQ7
DQ6
DQ5
NC
DQ4
V
CC
DQ3
DQ2
DQ1
DQ0
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
NC
HSB
WE
NC
NC
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Top View
(not to scale)
OE
CE
V
CC
V
SS
V
CAP
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Device Operation
The CY14B101L nvSRAM is made up of two functional compo -
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B101L supports unlimited re ads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The CY14B101L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0–16 determines the 131,072 data bytes accessed.
When the READ is initiated by an address transition, the outputs
are valid after a delay of tAA (READ cycle 1). If the READ is
initiated by CE or OE, the outputs are valid at tACE or at tDOE,
whichever is later (READ cycle 2). The data outputs repeatedly
respond to address changes within the tAA access time without
the need for transitions on any control input pins, and remains
valid until another address chan ge or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle.
The data on the common IO pins DQ0–7 are written into the
memory if it has valid tSD, before the end of a WE controlled
WRITE or before th e end of an CE controlled WRITE. Keep OE
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE is left LOW, internal circuitry turns off
the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B101L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an addre ss sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by defa ult on th e CY 14B101L.
During normal operation, the device draws current from V CC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operati on. Refe r to the DC Electrical
Characteristics on page 8 for the size of VCAP. The voltage on
the VCAP pin is driven to 5V by a charge pump internal to the chip.
A pull up is placed on WE to hold it inactive during power up.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whe ther a WRITE o peration has taken
place. An optional pull-up resistor is shown conn ected to HSB .
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW , the CY14B101L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internall y
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin should be exter-
nally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations, that are in progress when
HSB is driven LOW by any me ans, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B101L continues SRAM operations fo r tDELAY. During
tDELAY, multiple SRAM READ operations take place. If a WRITE
is in progress whe n HSB is pu lled LOW, it allows a time, t DELAY
to complete. However , any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
If HSB is not used, it is left unconnected.
Figure 2. AutoStore Mode
V
CC
V
CC
V
CAP
V
CAP
WE
10k Ohm
0.1 F
U
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Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
VSWITCH), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is perform ed :
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x8FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs or
OE controlled READs. When the sixth address in th e sequ ence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the tSTORE cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycl e,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x4C63, Initiate RECALL cycle
Internally , RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Data Protection
The CY14B101L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH.
If the CY14B101L is in a WRITE mode (both CE and WE are low)
at power up after a RECALL or after a STORE, the WRITE is
inhibited until a negative transition on CE or WE is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Noise Considerations
The CY14B101L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF co nnected
between VCC and VSS, using leads and traces tha t are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, an d signals reduce circuit noise.
Low Average Active Power
CMOS technology provides the CY14B101L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between ICC and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabl ed. The overall
average current drawn by the CY14B101L depends on the
following items:
■The duty cycle of chip enable
■The overall cycle rate for accesses
■The ratio of READs to WRITEs
■CMOS versus TTL input levels
■The operating temp erature
■The VCC level
■IO loading
Figure 3. Current Versus Cycle Time
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Preventing Store
Disable the AutoS tore function by initiating an AutoS tore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoS tore Disable sequence, perform the following sequence of
CE controlled READ operations:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation . To initiate the
AutoStore Enable sequence, p erfo rm the follo wing sequence of
CE controlled READ operations:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality as surance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on must always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, the best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■If AutoStore is firmware disabled, it does not reset to “autostore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
autostore on each reset sequence based on the behavior
desired.
■The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
higher inrush currents may reduce the reliability of the internal
pass transistor. Customers that want to use a larger VCAP value
to make sure there is extra store charge should discuss their
VCAP size selection with Cypress to understand any impact on
the Vcap voltage level at the end of a tRECALL period.
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.
Tab le 2. Hardware Mode Selection
CE WE OE A15 – A0Mode IO Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active[3]
L L X X Write SRAM Input Data Active
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[2, 3, 4]
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[2, 3, 4]
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Stor e
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[2, 3, 4]
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[2, 3, 4]
Notes
2. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
3. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.
4. IO state depends on t he state of OE. The IO table shown is based on OE Low.
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Maximum Rat ings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................... ... ... ... .. .–65°C to +150°C
Ambient Temperature with
Power Applied ..................... .......................–55°C to +125°C
Supply Voltage on VCC Relative to GND..........–0.5V to 4.1V
Voltage Applied to Outputs
in High Z State.......................................–0.5V to VCC + 0.5V
Input Voltage............. ............................ ..–0.5V to Vcc + 0.5V
Tran sient Voltage (<20 ns) on
Any Pin to Ground Potential..................–2.0V to VCC + 2.0V
Package Power Dissipation
Capability (TA = 25°C) ...................................................1.0W
Surface Mount Lead Soldering
Temperature (3 Seconds).......................................... +260°C
DC output Current (1 output at a time, 1s duration) ....15 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial -40°C to +85°C 2.7V to 3.6V
DC Electrical Characteristics
Over the operating range (VCC = 2.7V to 3.6V) [5, 6]
Parameter Description Test Conditions Min Max Unit
ICC1 Average VCC Current tRC = 25 ns
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
IOUT = 0 mA.
Commercial 65
55
50
mA
mA
Industrial 70
60
55
mA
mA
mA
ICC2 Average VCC Current
during STORE All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE 6mA
ICC3 Average VCC Current at
tRC= 200 ns, 5V, 25°C
Typical
WE > (VCC – 0.2V). All other inputs cycling.
Dependent on output loading and cycle rate. V alues obtained
without output loads.
10 mA
ICC4 Average VCAP Current
during AutoStore Cycle All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE 3mA
ISB VCC Standby Current CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Input s are stati c. f = 0 MHz.
3mA
IIX Input Leakage Current VCC = Max, VSS < VIN < VCC -1 +1 μA
IOZ Off State Output
Leakage Current VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL -1 +1 μA
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage VSS – 0.5 0.8 V
VOH Output HIGH Voltage IOUT = –2 mA 2.4 V
VOL Output LOW Voltage IOUT = 4 mA 0.4 V
VCAP Storage Capacitor Between VCAP pin and Vss, 6V rated. 17 120 uF
Data Retention and Endurance
Parameter Description Min Unit
DATARData Retention at 55°C20Years
NVCNonvolatile STORE Operations 200 K
Notes
5. The HSB pin has IOUT = –10 μA for VOH of 2.4 V. This parameter is characterized but not tested.
6. VIH changes by 100 mV when VCC > 3.5V.
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Capacitance
In the following table, the capacitance parameters are listed.[7]
Parameter Description Test Conditio ns Max Unit
CIN Input Capacit ance TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V 7pF
COUT Output Capacitance 7 pF
Thermal Resist ance
In the following table, the thermal resistance parameters are listed.[7]
Parameter Description Test Conditions 32-SOIC 48-SSOP Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
33.64 32.9 °C/W
ΘJC Thermal Resistance
(Junction to Case) 13.6 16.35 °C/W
Figure 4. AC Test Loads
AC Test Conditions
3.0V
Output
30 pF
R1 577Ω
R2
789Ω
3.0V
Output
5 pF
R1 577
Ω
R2
789
Ω
For Tri - state Specs
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% to 90%)...................... <5 ns
Input and Output Timing Referenc e Levels.................... 1.5V
Note
7. These parameters are guaranteed by design and are not tested.
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AC Switching Characteristics
SRAM Read Cycle
Parameter Description 25 ns[1] 35 ns 45 ns Unit
Min Max Min Max Min Max
Cypress
Parameter Alt
tACE tELQV Chip Enable Access Time 25 35 45 ns
tRC [8] tAVAV, tELEH Read Cycle Time 25 35 45 ns
tAA [9] tAVQV Address Access T ime 25 35 45 ns
tDOE tGLQV Output Enable to Data Valid 12 15 20 ns
tOHA [9] tAXQX Output Hold After Address Change 3 3 3 ns
tLZCE [10] tELQX Chip Enable to Output Active 3 3 3 ns
tHZCE [10] tEHQZ Chip Disable to Output Inactive 10 13 15 ns
tLZOE [10] tGLQX Output Enable to Output Active 0 0 0 ns
tHZOE [10] tGHQZ Output Disable to Output Inactive 10 13 15 ns
tPU [7] tELICCH Chip Enable to Power Active 0 0 0 ns
tPD [7] tEHICCL Chip Disable to Power Standby 25 35 45 ns
Switching Waveforms Figure 5. SRAM Read Cycle 1: Address Controlled [8, 9, 11]
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [8, 11]
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W
38
'4'$7$287
,&&
Notes
8. WE and HSB must be HIGH during SRAM READ cycles.
9. Device is continuously selected with CE and OE both Low.
10.Measured ±200 mV from steady state output voltage.
11. HSB must remain high during READ and WRITE cycles.
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CY14B101L
Document Number: 001-06400 Rev. *M Page 11 of 21
SRAM Write Cycle
Parameter Description 25 ns[1] 35 ns 45 ns Unit
Min Max Min Max Min Max
Cypress
Parameter Alt
tWC tAVAV Write Cycle Time 25 35 45 ns
tPWE tWLWH, tWLEH Write Pulse Width 20 25 30 ns
tSCE tELWH, tELEH Chip Ena ble To End of Write 20 25 30 ns
tSD tDVWH, tDVEH Data Setup to End of Write 10 12 15 ns
tHD tWHDX, tEHDX Data Hold After End of Write 0 0 0 ns
tAW tAVWH, tAVEH Address Setup to End of Write 20 25 30 ns
tSA tAVWL, tAVEL Ad dress Setup to Start of Write 0 0 0 ns
tHA tWHAX, tEHAX Address Hold After End of Write 0 0 0 ns
tHZWE [10,12] tWLQZ Write Enable to Output Disable 10 13 15 ns
tLZWE [10] tWHQX Output Active After End of W r ite 3 3 3 ns
Switching Waveforms Figure 7. SRAM Write Cycle 1: WE Controlled [12, 13]
Figure 8. SRAM Write Cycle 2: CE and OE Controlled [12, 13]
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
12.If WE is Low when CE goes Low, the outputs remain in the high impedance state.
13.CE or WE must be greater than VIH during address transitions.
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CY14B101L
Document Number: 001-06400 Rev. *M Page 12 of 21
AutoStore or Power Up RECALL
Parameter Alt Description CY14B101L Unit
Min Max
tHRECALL [14] tRESTORE Power up RECALL Duration 20 ms
tSTORE [15, 16] tHLHZ STORE Cycle Duration 12.5 ms
VSWITCH Low Voltage Trigger Level 2.65 V
tVCCRISE VCC Rise Time 150 μs
Switching Waveforms Figure 9. AutoStore/Power Up RECALL
V
CC
V
SWITCH
t
STORE
t
STORE
t
HRECALL
t
HRECALL
AutoStore
POWER-UP RECALL
Read & Write Inhibited
STORE occurs only
if a SRAM write
has happened
No STORE occurs
without atleast one
SRAM write
t
VCCRISE
Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below VSWITCH
Notes
14.tHRECALL starts from the time VCC rises above VSWITCH.
15.If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
16.Industrial Grade devices requires 15 ms max.
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Document Number: 001-06400 Rev. *M Page 13 of 21
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [17, 18]
Parameter Alt Description 25 ns[1] 35 ns 45 ns Unit
Min Max Min Max Min Max
tRC[18] tAVAV STORE/RECALL Initia tion Cycle Time 25 35 45 ns
tSA tAVEL Addre s s Setup Time 0 0 0 ns
tCW tELEH Clock Pulse Width 20 25 30 ns
tHA tGHAX, tELAX Address Hold Time 1 1 1 ns
tRECALL RECALL Duration 120 120 120 μs
Switching Waveforms Figure 10. CE Controlled Software STORE/RECALL Cycle [18]
Figure 1 1. OE Controlled Software STORE/RECALL Cycle [18]
tRC tRC
tSA tSCE
tHA
tSTORE / tRECALL
DATA VALID
DATA VALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
tRC tRC
6#SSERDDA1#SSERDDA
ADDRESS
tSA tSCE
tHA tSTORE / tRECALL
DATA VALID
DATA VALID HIGH IMPEDANCE
CE
OE
DQ (DATA)
Notes
17.The software sequence is clocked on the falling edge of CE controlled READs or OE controlled READs.
18.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
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Document Number: 001-06400 Rev. *M Page 14 of 21
Hardware STORE Cycle
Parameter Alt Description CY14B101L Unit
Min Max
tPHSB tHLHX Hardware STORE Pulse Width 15 ns
tDELAY [19] tHLQZ , tBLQZ Time Allowed to Complete SRAM Cycle 1 70 μs
tss[20, 21] Soft Sequence Processing Time 70 us
Switching Waveforms
Figure 12. Hardware STORE Cycle
Figure 13. Soft Sequence Processing[20, 21]
3+6%
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&RPPDQG
W66 W66
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Notes
19.On a hardware STO R E initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles t o complete.
20.This is the amount of time to take action on a soft sequence command. Vcc power must remain high to effectively register command.
21.Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
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CY14B101L
Document Number: 001-06400 Rev. *M Page 15 of 21
Ordering Information
These parts are not recommended for new designs.
Speed
(ns) Ordering Code Package Diagram Operating Voltage
Range Package Type Operating
Range
25 CY14B101L-SZ25XCT 51-85127 2.7V to 3.6V 32-pin SOIC Commercial
CY14B101L-SZ25XC 51-85127 2.7V to 3.6V 32-pin SOIC
CY14B101LL-SP25XCT 51-85061 2.7V to 3.6V 48-pin SSOP
CY14B101LL-SP25XC 51-85061 2.7V to 3.6V 48-pin SSOP
CY14B101L-SZ25XIT 51-85127 3.0V to 3.6V 32-pin SOIC Indu strial
CY14B101L-SZ25XI 51-85127 3.0V to 3.6V 32-pin SOIC
CY14B101L-SP25XIT 51-85061 3.0V to 3.6V 48-pin SSOP
CY14B101L-SP25XI 51-85061 3.0V to 3.6V 48-pin SSOP
Option
T - Tape and Reel
Blank - Std.
Speed
25 - 25 ns
35 - 35 ns
45 - 45 ns
Package
SZ - 32 SOIC
SP - 48 SSOP Data Bus
L - x8 Density
101 - 1 Mb
Voltage
B - 3.0V
Cypress
Part Numbering Nomenclature
CY 14 B 101 L - SZ 25 X C T
NVSRAM
14 - AutoStore + Software Store + Hardware Store
Temperature
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
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CY14B101L
Document Number: 001-06400 Rev. *M Page 16 of 21
35 CY14B101L-SZ35XCT 51-85127 2.7V to 3.6V 32-pin SOIC Commercial
CY14B101L-SZ35XC 51-85127 2.7V to 3.6V 32-pin SOIC
CY14B101L-SP35XCT 51-85061 2.7V to 3.6V 48-pin SSOP
CY14B101L-SP35XC 51-85061 2.7V to 3.6V 48-pin SSOP
CY14B101L-SZ35XIT 51-85127 2.7V to 3.6V 32-pin SOIC Industria l
CY14B101L-SZ35XI 51-85127 2.7V to 3.6V 32-pin SOIC
CY14B101L-SP35XIT 51-85061 2.7V to 3.6V 48-pin SSOP
CY14B101L-SP35XI 51-85061 2.7V to 3.6V 48-pin SSOP
45 CY14B101L-SZ45XCT 51-85127 2.7V to 3.6V 32-pin SOIC Commercial
CY14B101L-SZ45XC 51-85127 2.7V to 3.6V 32-pin SOIC
CY14B101L-SP45XCT 51-85061 2.7V to 3.6V 48-pin SSOP
CY14B101L-SP45XC 51-85061 2.7V to 3.6V 48-pin SSOP
CY14B101L-SZ45XIT 51-85127 2.7V to 3.6V 32-pin SOIC Indu strial
CY14B101L-SZ45XI 51-85127 2.7V to 3.6V 32-pin SOIC
CY14B101L-SP45XIT 51-85061 2.7V to 3.6V 48-pin SSOP
CY14B101L-SP45XI 51-85061 2.7V to 3.6V 48-pin SSOP
All part s are Pb-free. The above table contains Final informati on. Please contact your local Cypress sales representative for availability of these parts
Ordering Information
These parts are not recommended for new designs.
Speed
(ns) Ordering Code Package Diagram Operating Voltage
Range Package Type Operating
Range
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Package Diagrams Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
51-85127 *B
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Figure 15. 48-Pin Shrunk Small Outline Package (51-85061)
Package Diagrams (continued)
51-85061 *D
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CY14B101L
Document Number: 001-06400 Rev. *M Page 19 of 21
Document History Page
Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM
Document Number: 00 1-06400
Rev. ECN No. Orig. of
Change Submission
Date Descriptio n of Change
** 425138 TUP See ECN New data sheet
*A 437321 TUP See ECN Show data sheet on External Web
*B 471966 TUP See ECN Changed ICC3 from 5 mA to 10 mA
Changed ISB from 2 mA to 3 mA
Changed VIH(min) from 2.2V to 2.0V
Changed tRECALL from 40 μs to 50 μs
Changed Endurance from 1 millio n Cycles to 500K Cycles
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Wave form
Updated Part Numbering Nomenclature and Ordering Information
*C 503272 PCI See ECN Changed from Advance to Preliminary
Changed the term “Unlimited” to “Infinite”
Changed Endurance from 500K Cycles to 200K Cycles
Added temperature specification to Data Retention - 20 years at 55°C
Removed Icc1 values from the DC table for 25 ns and 35 ns industrial
grade
Changed Icc2 value from 3 mA to 6 mA in the DC table
Added a footnote on VIH
Changed VSWITCH(min) from 2.55V to 2.45V
Added footnote 17 related to using th e software command
Updated Part Nomenclature Table and Ordering Information Table
*D 597002 TUP See ECN Removed VSWITCH(min) specification from the AutoStore/Power Up RE-
CALL table
Changed tGLAX specification from 20 ns to 1 ns
Added tDELAY(max) specification of 70 μs in the hardware STORE cycle
table
Removed tHLBL specification
Changed tSS specification from 70 μs (min) to 70 μs (max)
Changed VCAP(max) from 57 μF to 120 μF
*E 688776 VKN See ECN Added footnote related to HSB
Changed tGLAX to tGHAX
*F 1349963 UHA/SFV See ECN Changed from Preliminary to Final
Updated Ordering Information table
*G 2427986 GVCH See ECN Move to external web
*H 2546756 GVCH/AESA 08/01/2008 Aligned part number nomenclature
Corrected typo in ordering information
Changed pin definition of NC pin
Updated data sheet template
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Document Number: 001-06400 Rev. *M Page 20 of 21
*I 2625139 GVCH/PYRS 01/30/09 Updated “features”
Added data retention at 55oC
Updated WE pin description
Added best practices
Added ICC1 spec for 25ns and 35ns access speed for industrial temper-
ate
Updated VIH from Vcc+0.3 to Vcc+0.5
Removed footnote 4 and 5
Added Data retention and Endurance Table
Added Thermal resistance values
Changed parameter tAS to tSA
Changed tRECALL from 50us to 120us (Including tss of 70us)
Renamed tGLAX to tHA
Updated figure 11 and 12
Renamed tHLHX to tPHSB
Updated Figure 13
*J 2695908 GVCH/AESA 04/20/2009 Removed part numbers CY14B101L-SP25XC and
CY14B101L-SP25XCT.
Added part numbers CY14B101LL-SP25XC and
CY14B101LL-SP25XCT.
*K 2814390 GVCH 11/25/2009 Added Note in the Ordering information section mentioning that these
parts are not recommended for new designs.
Added “Not recommended for new designs” watermark in the PDF.
*L 2895330 GVCH 03/18/2010 Added foot note 1 for 25ns access speed. Updated Package Diagrams.
Added Operating Voltage Range column to Ordering Information.
*M 2902517 GVCH 03/31/2010 Added watermark "Not Recommended for New Designs" in pdf version.
Move to external web.
Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM
Document Number: 00 1-06400
Rev. ECN No. Orig. of
Change Submission
Date Descriptio n of Change
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Document Number: 001-06400 Rev. *M Revised April 5, 2010 Page 21 of 21
All products and company names mentioned in this document may be the tradem arks of their respective holders.
CY14B101L
© Cypress Semicondu ctor Corpor ation, 2006-2010. The informatio n cont ained herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed nor int e nd ed to be used fo r
medical, life supp or t, lif e savi n g, critical control or safety applicatio ns, unless pursuant to an express written agreement wit h Cypr ess. Fu rth erm ore, Cyp ress doe s not author i ze its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypre ss) and is protected by and subject to worldwide patent pro tectio n (United States and foreig n),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s t o license e a pers onal, no n-excl usive , non-tr ansferab le license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only i n conjunction with a Cyp ress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this Sour ce Code except as spe cified above is p rohibited wit hout
the express written permiss i on of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY A ND FITNESS FOR A PARTICULAR PURPOSE. Cypre ss reserves the right to make changes without further notice to the materials described herei n. Cypress d oes not
assume any liabil ity arisi ng ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts for use as critical compon ent s in life-suppo rt systems where
a malfuncti on or failure may reasonab ly be expected to resu lt in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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