1
®
FN6009.3
ISL5761
10-bit, +3.3V, 130/210+MSPS, High Speed
D/A Conver ter
The ISL5761 is a 10-bit, 130/210+MSPS (Mega Samples
Per Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in high
perf ormance communication systems such as base
transceiver stations utilizing 2.5G or 3G cellular protocols.
This device complements the ISL5x61 family of high speed
converters, which include 10, 12, and 14-bit devices.
Features
Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS
Low Power . . . . . 103mW with 20mA Output at 130MSPS
Adjustable Full Scale Output Current. . . . . 2mA to 20mA
+3.3V Po wer Supply
3V LVCMOS Compatible Inputs
Excellent Spurious Free Dynamic Range
(71dBc to Nyquist, fS = 130MSPS, fOUT = 10MHz)
UMTS Adjacent Channel Power = 65dB at 19.2MHz
EDGE/GSM SFDR = 83dBc at 11MHz in 20MHz Window
Pin compatible, 3 .3 V, Lower Power Replacement For Th e
AD9750 and HI5760
Pb-free available
Applications
Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS-
95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
BWA Infrastructure
Medical/Test Instrumentation
Wireless Communication Systems
High Resolution Imaging Systems
Arbitrary Waveform Generators
Pinout ISL5761
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE
(oC) PACKAGE PKG.
DWG. # CLOCK
SPEED
ISL5761IB -40 to 85 28 Ld SOIC M28.3 130MHz
ISL5761IBZ
(See Note) -40 to 85 28 Ld SOIC
(Pb-free) M28.3 130MHz
ISL5761IA -40 to 85 28 Ld TSSOP M28.173 130MHz
ISL5761IAZ
(See Note) -40 to 85 28 Ld TSSOP
(Pb-free) M28.173 130MHz
ISL5761/2IB -40 to 85 28 Ld SOIC M28.3 210MHz
ISL5761/2IBZ
(See Note) -40 to 85 28 Ld SOIC
(Pb-free) M28.3 210MHz
ISL5761/2IA -40 to 85 28 Ld TSSOP M28.173 210MHz
ISL5761/2IAZ
(See Note) -40 to 85 28 Ld TSSOP
(Pb-free) M28.173 210MHz
IS L576 1EVAL 1 25 SOIC Evaluation Platform 210MHz
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
DCOM
NC
AVDD
COMP
IOUTB
NC
FSADJ
REFIO
REFLO
SLEEP
DVDD
IOUTA
ACOM
DCOM
DCOM
DCOM
DCOM
Data Sheet August 2004
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2004, All Rights Reserved
2
Typical Applications Circuit
Functional Block Diagram
D9 (1)
D8 (2)
D7 (3)
D6 (4)
D5 (5)
D4 (6)
D9
D8
D7
D6
D5
D4
DCOM (26, 11-14)
CLK (28)
(24) AVDD
(22) IOUTA
(21) IOUTB
(18) FSADJ
(16) REFLO
ISL5761
DVDD (27)
0.1µF
10µF
(20) ACOM
50
(15) SLEEP
(17) REFIO
0.1µF
1.91k
FERRITE
10µH
(23) COMP
0.1µF
+
BEAD
RSET
D3
D2
D1
D0
D3 (7)
D2 (8)
D1 (9)
D0 (LSB) (10)
0.1µF
10µH
+
BEAD
(25, 19) NC
ACOMDCOM
10µF+3.3V (VDD)
50(50)
1:1, Z1:Z2
ONE CONNECTION
ANY 50 LOAD
REPRESENTS
UPPER
VOLTAGE
REFERENCE
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D9
CLK
D7
D8 5-BIT
DECODER
REFIO
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
BIAS
GENERATION
INT/EXT
36 36
31 MSB
SEGMENTS
5 LSBs +
COMP
IOUTA IOUTB
INPUT
LATCH
REFLO FSADJ SLEEP
ISL5761
3
Pin Descriptions
PIN NO. PIN NAME DESCRIPTION
1-10 D9 (MSB) Through
D0 (LSB) Digital Data Bit 9, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
15 SLEEP Control Pin for P ower-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin
has internal 20µA activ e pulldown current.
16 REFLO Connect to analog ground to enable internal 1.2V ref erence or connect to A VDD to disab le internal reference.
17 REFIO Reference v oltage input if internal reference is disabled. Reference vo ltage output if internal reference is
enab led. Us e 0. F cap to ground when internal reference is enabled.
18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current
= 32 x VFSADJ/RSET.
19, 25 NC No Connect. These should be gr ounded, bu t can be left disconnected .
21 IOUTB The complementary current output of the device. Full scale output current is achieved when all input bits are
set to binary 0.
22 IOUTA Current output of the de vice . Fu ll scale output current is achie v e d when all input b its are set to binary 1.
23 COMP Connect 0.1µF capacitor to A COM.
24 AVDD Analog Supply (+3.0V to +3.6V).
20 ACOM Connect to An alog Ground.
26, 11-14 DCOM Connect to Digital Ground.
27 DVDD Digital Supply (+3.0V to +3.6V).
28 CLK Clock Input.
ISL5761
4
Absolute Maximum Ratings Thermal Info rmation
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +3.6V
Grounds, ACOM TO DCOM. . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA(oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values
PARAMETER TEST CONDITIONS
TA = -40oC TO 85oC
UNITSMIN TYP MAX
SYSTEM PERFORMANCE
Resolution 10 - - Bits
Integral Linearity Error, INL “Best Fit” Straight Line (Note 7) -0.5 ±0.1 +0.5 LSB
Differential Linearity Error, DNL (Note 7) -0.5 ±0.1 +0.5 LSB
Offset Error, IOS IOUTA (Note 7) -0.006 +0.006 % FSR
Offset Drift Coefficient (Note 7) - 0.1 - ppm
FSR/oC
Full Scale Gain Error, FSE With External Reference (Notes 2, 7) -3 ±0.5 +3 % FSR
With Internal Reference (Notes 2, 7) -3 ±0.5 +3 % FSR
Full Scale Gain Drift With External Reference (Note 7) - ±50 - ppm
FSR/oC
With Internal Reference (Note 7) - ±100 - ppm
FSR/oC
Full Scale Output Current, IFS 2-20mA
Output Voltage Compliance Range (Note 3) -1.0 - 1.25 V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK ISL5761/2IA, ISL5761/2IB 210 250 - MHz
Maximum Clock Rate, fCLK ISL5761IA, ISL5761IB 130 150 - MHz
Output Rise Time Full Scale Step - 1.5 - ns
Output Fall Time Full Scale Step - 1.5 - ns
Output Capacitance -10- pF
Output Noise IOUTFS = 20mA - 50 - pA/Hz
IOUTFS = 2mA - 30 - pA/Hz
AC CHARACTERISTICS (Using Figure 13 with RDIFF = 50 and RLOAD= 50, Full Scale Output = -2.5dBm)
Spurious Free Dynamic Range,
SFDR Within a Window fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz Span (Notes 4, 7) - 72 - dBc
fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz Span (Notes 4, 7) - 75 - dBc
fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 4, 7) - 77 - dBc
ISL5761
5
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2) fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 7) - 50 - dBc
fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 7, 9) - 58 - dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = 25oC (Notes 4, 7) 58 60 - dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = -40oC to 85oC (Notes 4, 7) 56 - - dBc
fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 7) - 55 - dBc
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 7) - 60 - dBc
fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 7) - 68 - dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 7) - 70 - dBc
fCLK = 130MSPS, fOUT = 5.05MHz, T = 25oC (Notes 4, 7) 68 75 - dBc
fCLK = 130MSPS, fOUT = 5.05MHz, T = -40oC to 85oC (Notes 4, 7) 66 - - dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 7) - 58 - dBc
fCLK = 80MS PS , fOUT = 30.3MHz (Notes 4, 7) - 61 - dBc
fCLK = 80MS PS , fOUT = 20.2MHz (Notes 4, 7) - 67 - dBc
fCLK = 80MS PS , fOUT = 10.1MHz (Notes 4, 7, 9) - 69 - dBc
fCLK = 80MS PS , fOUT = 5.05MHz (Notes 4, 7) - 74 - dBc
fCLK = 50MS PS , fOUT = 20.2MHz (Notes 4, 7) - 66 - dBc
fCLK = 50MS PS , fOUT = 10.1MHz (Notes 4, 7) - 72 - dBc
fCLK = 50MS PS , fOUT = 5.05MHz (Notes 4, 7) - 75 - dBc
Spurious Free Dynamic Range,
SFDR in a Window with Eight Tones fCLK = 210MSPS, fOUT = 28 .3 M H z to 45 .2 M H z , 2.1MHz Spacing,
50MHz Span (Notes 4, 7, 9) -63- dBc
fCLK = 130MSPS, fOUT =17.5MHz to 27.9MHz, 1.3MHz Spacing,
35MHz Span (Notes 4, 7) -66- dBc
fCLK = 80MS PS , fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing,
15MHz Span (Notes 4, 7) -73- dBc
fCLK = 50MS PS , fOUT = 6.7MHz t o 10 . 8MHz , 490kHz Spacing,
10MHz Span (Notes 4, 7) -75- dBc
Spurious Free Dynamic Range,
SFDR in a Window with EDGE or GSM fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz Window , RBW=30kHz
(Notes 4, 7, 9) -83- dBc
Adjacent Channel Power Ratio,
ACPR with UMTS fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW=30kHz (Notes 4, 7, 9) - 65 - dB
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ Pin 18 Voltage with Internal Reference 1.2 1.23 1.3 V
Internal Reference Voltage Drift -±40 - ppm/oC
Internal Reference Output Current
Sink/Source Capability Reference is not intended to be externally loaded (REFIO pin) - 0 - µA
Reference Input Impedance -1-M
Reference Input Multiplying Bandwidth (Note 7) - 1.0 - MHz
DIGITAL INPUTS D9-D0, CLK
Input Logic High Voltage with
3.3V Supply, VIH (Note 3) 2.3 3.3 - V
Input Logic Low Voltage with
3.3V Supply, VIL (Note 3) - 0 1.0 V
Sleep Input Current, IIH -25 - +25 µA
Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
PARAMETER TEST CONDITIONS
TA = -40oC TO 85oC
UNITSMIN TYP MAX
ISL5761
6
Input Logic Current, IIH, IL -20 - +20 µA
Clock Input Current, IIH, IL -10 - +10 µA
Digital Input Capacitance, CIN -5- pF
TIMING CHARACTERISTICS
Data Setup Time, tSU See Figure 15 - 1.5 - ns
Data Hold Time, tHLD See Figure 15 - 1.5 - ns
Propagation Delay Time, tPD See Figure 15 - 1 - Clock
Cycles
CLK Pulse Width, tPW1, tPW2 See Figure 15 (Note 3) 2 - - ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply (Note 8) 2.7 3.3 3.6 V
DVDD Power Supply (Note 8) 2.7 3.3 3.6 V
Analog Supply Current (IAVDD) 3.3V, IOUTFS = 20mA - 27.5 28.5 mA
3.3V, IOUTFS = 2mA - 10 - mA
Digital Supply Current (IDVDD) 3.3V (Note 5) - 3.7 5 mA
3.3V (Note 6) - 6.5 8 mA
Supply Current (IAVDD) Sleep Mode 3.3V, IOUTFS = Don’t Care - 1.5 - mA
Power Dissipation 3.3V, IOUTFS = 20mA (Note 5) - 103 111 mW
3.3V, IOUTFS = 20mA (Note 6) - 110 120 mW
3.3V, IOUTFS = 2mA (Note 5) - 45 - mW
Power Supply Rejection Single Supply (Note 7) -0.125 - +0.125 %FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was
used at different clock rates, producing different output frequencies but at the same ratio to the clock rate.
5. Measured with the clock at 130MSPS and the output frequency at 5MHz.
6. Measured with the clock at 200MSPS and the output frequency at 20MHz.
7. See “Definition of Specifications”.
8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in
analog output current may be necessary to maintain spectral performance.
9. See Typical Performance Plots.
Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
PARAMETER TEST CONDITIONS
TA = -40oC TO 85oC
UNITSMIN TYP MAX
ISL5761
7
Typical Perf ormance (+3.3V Supply, Using Figure 13 with RDIFF = 100 and RLOAD= 50)
FIGURE 1. EDGE AT 11MHz, 78MSPS CLOCK
(83+dBc @ f = +6MHz) FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK (75dBc -
NYQUIST, 6dB PAD)
FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK
(86+dBc @ f = +6MHz, 3dB PAD) FIGURE 4. GSM AT 11MHz, 78MSPS CLOCK (78dBc -
NYQUIST, 9dB PAD)
FIGURE 5. FOUR EDGE CARRIERS A T 12.4-15.6MHz, 800kHz
SPACING, 78MSPS (67dBc - 20MHz WINDOW) FIGURE 6. FOUR GSM CARRIERS A T 12.4-15.6MHz, 78MSPS
(71dBc - 20MHz WINDOW, 6dB PAD)
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
ISL5761
8
FIGURE 7. UMTS AT 19.2MHz, 76.8MSPS (65dB 1stA CPR,
64dB 2ndACPR) FIGURE 8. ONE T ONE A T 10.1MHz, 80MSPS CLOCK (71dBc -
NYQUIST, 6dB PAD)
FIGURE 9. ONE TONE A T 40.4MHz, 210MSPS CLOCK (61dBc
- NYQUIST, 6dB PAD) FIGURE 10. EIGHT TONES (CREST FACT OR=8.9) AT 37MHz,
210MSPS CLOCK, 2.1MHz SPACING
(64dBc - NYQUIST)
FIGURE 11. TWO T ONES (CF=6) AT 8.5MHz, 50MSPS CLOCK,
500kHz SPACING (80dBc - 10MHz WINDOW,
6dB PAD)
FIGURE 12. FOUR TONES (CF=8.1) AT 14MHz, 80MSPS
CLOCK, 800kHz SPACING (70dBc - NYQUIST,
6dB PAD)
Typical Perf ormance (+3.3V Supply, Using Figure 13 with RDIFF = 100 and RLOAD= 50) (Continued)
SPECTRAL MASK
UMTS TDD
P>43dBm BTS
ISL5761
9
Definition of Specifications
Adjacent Channel Power Ratio, ACPR, is the ratio of the
average power in the adjacent frequency channel (or offset)
to the average power in the transmitted frequency channel.
Differential Li neari ty Error, DNL, is the measure of the
step size output de viation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guara nt ee s mo notonicity.
EDGE, Enhanced Da ta for Global Evolution, a TDMA
standard for cellular applications which uses 200kHz BW, 8-
PSK modulated carriers.
Full Scale Gain Drift, is measured b y setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
from TMIN to TMAX. It is defined as the maximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX. The units are ppm of FSR
(full scale range) per oC.
Full Scale Gain Er ror, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through R SET).
GSM, Global Syst em for Mobile Comm unication, a TDMA
standard for cellular applications which uses 200kHz BW,
GMSK modulated carr iers.
Integral Linearity Error, INL, is the measure of the worst
case point that deviates fro m a best fit straight line of data
values along the transfer curve.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX.
The units are ppm per oC.
Offset Drift, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage at IOUTA
through a known resistance as the temperature is varied
from TMIN to TMAX. It is defined as the maximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX. The units are ppm of FSR
(full scale range) per degree oC.
Offset Error, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage of IOUTA
through a known resistance. Offset error is defined as the
maximum deviation of the IOUTA output current from a value
of 0mA.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedan ce should be
chosen such that the voltage developed does not violate the
compliance range.
P ower Sup ply Rejection, is measured using a single power
supply. The nominal supp ly voltage is varied ±10% and the
change in the DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal wa vef orm as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output wa vef orm is 0.707
(-3dB) of its original value.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harm onically or non-harmonically related spur within the
specified frequency wi ndow.
Total Harmonic Distortio n, THD, is the ratio of the RMS
value of the fundamental output signal to the RMS sum of
the first five harmoni c components.
UMTS, Universal Mobile Telecommunications System, a
W-CDMA standard for cellular applications which uses
3.84MHz modulated carriers.
Detailed Description
The ISL5761 is a 10-bit, current out, CMOS, digital to analog
converter. The maximum update rate is at least 210+MSPS
and can be powered by a single power supply in the
recommended range of +3.0V to +3.6V. Operation with clock
rates higher than 210MSPS is possible; please contact the
factory for more information. It consumes less than 120 mW
of power when using a +3.3V supply, the maximum 20mA of
output current, and the data switching at 210MSPS. The
architecture is based on a segmented current source
arrangement that reduces glitch by reducing the amount of
current swi tchi ng at any one time. In previous architectures
that contained all binary weighted current sources or a
binary weighted resistor ladder, the converter might have a
substantially larger amount of current turning on and off at
certain, worst-case transition points such as midscale and
quarter scale transitions. By greatly reducing the amount of
current switching at these major transitions, the ov erall glitch
of the converter is dramatically reduced, improving settling
time, transient problems, and accuracy.
Digital Inputs and Termination
The ISL5761 digital inputs are guaranteed to 3V LVCMOS
levels. The internal register is updated on the rising edge of
the clock. To minimize reflections, proper termination should
be implemented. If the lines driving the clock and the digital
inputs are long 50 lines, then 50 termination resistors
should be placed as close to the conv erter inputs as possible
connected to the digital ground plane (if separate grounds
are used). These termination resistors are not likely needed
as long as the digital wav eform source is within a few inches
of the DAC. For pattern drivers with very high speed edge
rates, it is recommended that the user consider series
termination (50-200Ω) prior to the DAC’s inputs in order to
reduce the amount of noise.
ISL5761
10
Power Supply
Separate digital and analog power supplies are
recommended. The allowab le supply range is +2.7V to
+3.6V. The recommended supply range is +3.0 to 3.6V
(nominally +3.3V) to maintain optimum SFDR. However,
operation down to +2.7V is possibl e with some degradation
in SFDR. Reducing the analog output current can help the
SFDR at +2.7V. The SFDR values stated in the table of
specifications were obtained with a +3.3V supply.
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components sho uld be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane.
Noise Reduction
To minimize po wer supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD. Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD. Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.23V with a ±40ppm/oC drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(16) selects the reference. The internal reference can be
selected if pin 16 is tied low (ground). If an e xternal reference
is desired, then pin 16 should be tied high (the analog supply
voltage) and the external reference driven into REFIO, pin
17. The full scale output current of the conv erter is a function
of the vo ltage reference used and the value of RSET. IOUT
should be within the 2mA to 20mA range, though operation
below 2mA is possible, with performance degradation.
If the internal reference is used, VFSADJ will equal
appro ximately 1.2V (pin 18). If an external ref erence is used,
VFSADJ will equal th e e x ternal ref e renc e . The calc ula tion for
IOUT (Full Scale) is:
IOUT(Full Scale) = (VFSADJ/RSET) X 32.
If the full scale output curren t is set to 20mA by using the
inter nal voltage reference (1.2V) and a 1.91k RSET
resistor , then the input coding to output current will resemble
the following:
Analog Output
IOUTA and IOU TB are complementary current outputs. Th e
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output vo ltage
compliance range of -1.0V to 1.25V. ROUT (the impedance
loading each current output) should be chose n so that the
desired output voltage is produced in conj unction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
VOUT = IOUT X ROUT.
The most effectiv e method for reducing the power
consumption is to reduce the anal og output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-single-
ended arrangement to achieve better harmonic rejection.
With RDIFF= 50and RLOAD=50, the circuit in Figure 13
will provide a 500mV (-2.5dBm) signal at the output of the
transformer if the full scale output current of the D AC is set to
20mA (used for the electrical specifications table). Values of
RDIFF= 100and RLOAD=50 were used for the typical
performance curves. The center tap in Figure 13 must be
grounded.
In the circuit in Figure 14, the user is lef t wi th th e op ti on to
ground or float the center tap. The DC voltage that will exist
at either IOUTA or IOUTB if the center tap is floating is
IOUTDC x (RA//RB) V because RDIFF is DC shorted by the
transf ormer. If the center tap is grounded, the DC voltage is
0V. Recommended values for the circuit in Figure 14 are
RA=RB=50, RDIFF=100, assuming RLOAD=50. The
performance of Figure 13 and Figure 14 is basically the
same, however leaving the center tap of Figure 14 floating
allows the circuit to find a more balanced virtual ground,
theoretically improving the even order harmonic rejection,
but li kely reducing the si gn a l swing a vailable due to the
output voltage compliance range limitations.
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH
INTERNAL REFERENCE AND RSET=1.91K
INPUT CODE (D9-D0) IOUTA (mA) IOUTB (mA)
11111 11111 20 0
10000 00000 10 10
00000 00000 0 20
ISL5761
11
Propagation Delay
The converter requires two clock rising edges fo r data to be
represented at the output. Each risi ng edge of the clock
captures the present data word and outputs the previous
data. The propagation dela y is theref ore 1/CLK, plus <2ns of
processing. See Fig ure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form. The form can be found by doing an ‘enti re
site search’ at www.intersil.com on the words ‘DAC
Testdrive’. Or, send a request to the technical support center .
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
PIN 21
PIN 22 RDIFF
ISL5761
RLOAD
IOUTB
IOUTA
VOUT = (2 x IOUTA x REQ)V
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
1:1
REQ = 0.5 x (RLOAD // RDIFF)
AT EACH OUTPUT
FIGURE 14. ALTERNATIVE OUTPUT LOADING
PIN 21
PIN 22
ISL5761
IOUTB
IOUTA
VOUT = (2 x IOUTA x REQ)V
REQ = 0.5 x (RLOAD // RDIFF// RA) , WHERE RA=RB
AT EACH OUTPUT
RLOAD
RDIFF
RA
RB
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
Timing Diagram
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
IOUT
50%
tPW1 tPW2
tSU
tHLD
tSU tSU
tPD
tHLD tHLD
D9-D0 W0W1W2W3
OUTPUT=W0
OUTPUT=W1
tPD
OUTPUT=W-1
ISL5761
12
ISL5761
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
3-13
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
ISL5761
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.378 0.386 9.60 9.80 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N28 287
α0o8o0o8o-
Rev. 0 6/98