To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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Renesas Electronics document. W e appreciate your understanding.
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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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Rev.2.00 Sep 07, 2005 page 1 of 6
2SK1764
Silicon N Channel MOS FET REJ03G0970-0200
(Previous : AD E-208- 1 317)
Rev.2.00
Sep 07, 2005
Application
• Low frequency ampl ifier
• High speed switc hing
Features
• Low on-resistance
• High speed switc hing
• 4 V Gate drive device can be driven from 5 V source
• Suitable for switching regulator, DC-DC converter
Outline
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK )
R
1. Gate
2. Drain
3. Source
4. Drain
4
321D
G
S
Note: Marking is "KY".
*UPAK is a trademark of Renesas Technology Corp.
2SK1764
Rev.2.00 Sep 07, 2005 page 2 of 6
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 60 V
Gate to source voltage VGSS ±20 V
Drain current ID 2 A
Drain peak current ID(pulse)*1 4 A
Body to drain diode reverse drain current IDR 2 A
Channel power dissipation Pch*2 1 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10 %
2. Value on the alumina ceramic board (12.5 x 20 x 0.7 mm)
Electrical Characteristics
(Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS 60 — — V ID = 10 mA, VGS = 0
Gate to source breakdown voltage V(BR)GSS ±20 — — V IG = ±100 µA, VDS = 0
Gate to source cutoff volta ge VGS(off) 1 — 2 V VDS = 10 V, ID = 1 mA
Drain to source cutoff current IDSS — — 10 µA VDS = 50 V, VGS = 0
Gate to source cutoff current IGSS — — ±5 µA VGS = ±15 V, VDS = 0
Static drain to source on state
resistance RDS(on)1 — 0.3 0.45 Ω V
GS = 10 V, ID = 1 A*3
Static drain to source on state
resistance RDS(on)2 — 0.4 0.60 Ω V
GS = 4 V, ID = 1 A*3
Forward transfer admittance |yfs| 0.9 1.7 — S VDS = 10 V, ID = 1 A*3
Input capacitan ce Ciss — 140 — pF
Output capacitance Coss — 75 — pF
Reverse transfer capacitance Crss — 20 — pF
VDS = 10 V, VGS = 0,
f = 1 MHz
Turn on time ton — 18 — ns
Turn off time toff — 80 — ns
VDS = 10 V, ID = 1 A*3,
RL = 30 Ω
Note: 3. Pulse Test
2SK1764
Rev.2.00 Sep 07, 2005 page 3 of 6
Main Characteristics
Typical Output Characteristics
6
Drain to Source Voltage V
DS
(V)
842 10
Drain Current ID (A)
0
1
2
3
4
0
5
V
GS
= 2.5 V
Pulse Test
10 V
5 V
4 V
3 V
3.5 V
4.5 V
7 V
Typical Transfer Characteristics
3
Gate to Source Voltage V
GS
(V)
42105
1
2
3
4
5
0
Drain Current ID (A)
–25°C
T
C
= 25
°
C
75°C
V
DS
= 10 V
Pulse Test
Drain to Source Saturation Voltage
vs. Gate to Source Voltage
6
Gate to Source Voltage V
GS
(V)
842010
0.4
0.6
0.8
1.0
0
0.2
Drain to Source Saturation Voltage
VDS (on) (V)
Pulse Test
I
D
= 0.5 A
2 A
1 A
0.5
Drain Current I
D
(A)
1.00.20.1 5
0.2
0.5
1.0
2
5
0.05
0.1
0.05
2
Static Drain to Source On State
Resistance vs. Drain Current
Static Drain to Source on State Resistance
RDS (on) (Ω)
V
GS
= 4 V
10 V
Pulse Test
1.6
1.2
0.8
0.4
0
Channel Power Dissipation Pch** (W)
(** on the almina ceramic board)
50 100 150 200
Ambient Temperature Ta (°C)
Maximum Channel Power
Dissipation Curve
0.1
Drain Current ID (A)
Drain to Source Voltage VDS (V)
10
3
1.0
0.3
0.1
0.03
0.01
0.3 1.0 3 10 30 100
Operation in
this area is
limited by R
DS(on)
Ta = 25°C
1 ms
PW = 10 ms (1shot)
DC operation
Safe Operation Area
2SK1764
Rev.2.00 Sep 07, 2005 page 4 of 6
80
Case Temperature TC (°C)
120400
0.2
0.4
0.6
0.8
1.0
–40
0
160
Static Drain to Source on State
Resistance vs. Temperature
Static Drain to Source on State Resistance
RDS (on) (Ω)
I
D
= 2 A
Pulse Test
V
GS
= 4 V
V
GS
= 10 V
0.5 A
1 A
1 A
0.5 A
2 A
Forward Transfer Admittance
vs. Drain Current
5
2
1.0
0.5
0.2
0.1
0.05
0.05 0.1 0.2 0.5 1.0 5
Drain Current ID (A)
2
Forward Transfer Admittance yfs (S)
T
C
= 25°C
V
DS
= 10 V
Pulse Test
–25
°
C
75
°
C
1000
500
200
100
50
20
10
0.05 0.1 0.5 5
Reverse Drain Current IDR (A)
1.0
0.2 2
Body to Drain Diode Reverse
Recovery Time
Reverse Recovery Time trr (ns)
di/dt = 50 A/µs, Ta = 25°C
V
GS
= 0
Pulse Test
Typical Capacitance vs.
Drain to Source Voltage
1000
300
100
30
3
1
Capacitance C (pF)
01020 5
0
Drain to Source Voltage VDS (V)
30
10
40
V
GS
= 0
f = 1 MHz
Ciss
Coss
Crss
100
80
60
40
20
02 6
8
Gate Charge Qg (nc)
4
20
16
12
8
4
Dynamic Input Characteristics
Drain to Source Voltage VDS (V)
Gate to Source Voltage VGS (V)
10
0
V
DS
V
GS
V
DD
= 50 V
10 V
25 V
V
DD
= 50 V
25 V
10 V
I
D
= 1.5 A
Switching Characteristics
100
50
20
10
2
1
0.05 0.1 0.5 5
Drain Current ID (A)
1.0
0.2 2
Switching Time t (ns)
5
td (off)
tf
V
GS
= 10 V V
DD
= 30 V
PW = 2 µs, duty < 1 %
td (on)
tr
•
•
2SK1764
Rev.2.00 Sep 07, 2005 page 5 of 6
2.0
1.6
1.2
0.8
0.4
0 0.4 1.2 1.6 2.0
Source to Drain Voltage VSD (V)
0.8
Reverse Drain Current vs.
Source to Drain Voltage
Reverse Drain Current IDR (A)
V
GS
= 0, –5 V
Pulse Test
5 V
10 V
15 V
2SK1764
Rev.2.00 Sep 07, 2005 page 6 of 6
Package Dimensions
4.5 ± 0.1
1.8 Max 1.5 ± 0.1
0.44 Max
0.44 Max
0.48 Max
0.53 Max
1.5 1.5
3.0
2.5 ± 0.1
4.25 Max
0.8 Min
φ1
0.4
(1.5)
(2.5)
(0.4)
(0.2)
Package Name
PLZZ0004CA-A UPAK / UPAKV
MASS[Typ.]
0.050g
SC-62
RENESAS CodeJEITA Package Code
Unit: mm
Ordering Information
Part Name Quantity Shipping Container
2SK1764KYTL-E 3000 pcs Taping, φ178 mm Reel
2SK1764KYTR-E 3000 pcs Taping, φ178 mm Reel
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
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Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
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