74HC/HCT373 MSI OCTAL D-TYPE TRANSPARENT LATCH; 3-STATE FEATURES ; TYPICAL @ 3-state non-inverting outputs for SYMBOL PARAMETER CONDITIONS UNIT bus oriented applications Hc HCT Common 3-state output enable propagation delay input tpHL/ Dp to On C, = 15 pF 12 | 14 | as @ Functionally identical to the 563, tPLH LE toQ, Vec=5V 15 | 13 | ns "673" and 533"" @ Output capability: bus driver Cy input capacitance 3.5 3.5 pF @ lec category: MSI dissipati power aisstpation GENERAL DESCRIPTION Crp capacitance per latch notestand2 =| 45 | 41 | pF The 74HC/HCT373 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT373 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The 373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dp inputs enters the latches. In this condition the latches are transparent, ie. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OF F-state. Operation of the OE input does not affect the state of the latches. The 373 is functionally identical to the 533", 563" and 573, but the 563 and '533 have inverted outputs and the 563 and 573" have a different pin arrangement. GND = 0 V; Tamb = 25 C: ty = ty = 6 ns Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in W): Pp =Cppx Vcc x fi + = (CL x Vcc? x fo) where: fi; = input frequency in MHz CL = output load capacitance in pF fo = output frequency in MHz VCC = supply voltage in V Z (CL x Voc? x fg) = sum of outputs 2. For HC the condition is Vj = GND to Vcc For HCT the condition is V} = GND to Vcc 1.5 V PACKAGE OUTLINES 20-lead DIL; plastic (SOT146). 20-lead mini-pack; plastic (SO20; SOT163A). PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 OE 3-state output enable input (active LOW) 2,5, 6, G, 12, 7 15, 16,19 Qg to 07 3-state latch outputs 3,4, 7, 8, 13, : 14, 17, 18 Dg to D7 data inputs 10 GND ground (0 V} 11 LE latch enable input (active HIGH) 20 Voc positive supply voltage aL | Yee 2 [2 [19] a7 eo ha] of FF) %6 a,[5 16] Og a 373 ee d2[7] [14] Ds, D3 [B] [13] D4 a3 [2] [12] 4 np [10 ia] ve 7293250 Fig. 1 Pin configuration. 3409 = Agf-2 440 a,/5 74D. OP 6 84D; Qgh 9 13 Dy Q4p 12 141D05 Og - 15 17~4 Dg Og te t6 18 1D, Q7 19 OE 1 7293251 7293252 Fig. 2 Logic symbol. Fig. 3 1EC logic symbol. September 1993 61974HC/HCT373 MSI 3-STATE OUTPUTS 7290987.1 7293253 Fig. 4 Functional diagram. Fig. 5 Logic diagram (one latch}. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES } Tones OE] LE} Dp, Qg to Q7 enable and read L H L L L register L H H H H t t fe (transparent mode} H = HIGH voltage level h = HIGH voltage level one set-up time prior to the latch and read L L | L L register L L oth H H HIGH-to-LOW LE transition L = LOW voltage level latch register and H x |x x Z | = LOW voltage level one set-up time prior to the disable outputs H |X [|X x Z HIGH-to-LOW LE transition X = dont care Z = high impedance OFF-state Do Dy By D3 Dy Ds Dg Dy Do ah D ah D ah, D ar D at o ar D aR D Qa LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH 1 2 3 4 5 6 7 8 te Le LE Le iE Le TE Le TE Le LE LE LE LE TE LE I L] LI LI ] J J le | | | | | eee Q a, a, Q3 ay a5 Og a, 7293255 Fig. 6 Logic diagram. 620 September 1993Octal D-type transparent latch; 3-state 74HC/HCT373 MSI DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: bus driver loc category: MS! AC CHARACTERISTICS FOR 74HC GND = 0 V; ty = t= 6 ns; Cy = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 40 to +85 | 40 to +125 Vv min.; typ. | max. | min.} max. | min. | max. . 41 150 190 225 2.0 (PHL! | Propagation delay 15 | 30 38 45 [ns | 45 | Fig.7 PLH nrohn 12 | 26 33 38 6.0 tPHL/ Propagation delay 50 ae mo 28 20 Fig. 8 t LE to0 18 5 3 ns 5 ig. PLH n 14 | 30 37 45 6.0 . 44 | 150 190 225 2.0 2H! Sarete output enable time 16 | 30 38 45 | ns 45 | Fig.9 PZL n 13 | 26 33 38 6.0 tpHz/ 3-state output disable time 47 150, 190 225 2.0 . t OE toO 17 | 30 38 45 ns 4.5 | Fig.9 PLZ n 14 | 26 33 38 6.0 t / 14 | 60 75 90 2.0 ab output transition time 5 12 15 18 ns 4.5 Fig. 7 TLH 4 | 10 13 15 6.0 . 80 | 17 100 120 2.0 tw r pulse width 16 |6 20 24 ns 45 | Fig.8 14 |5 17 20 6.0 . 50 | 14 65 75 2.0 teu oe le 10 15 13 15 ns 4.5 | Fig. 10 nto 9 |4 11 13 6.0 . 5 -8 5 5 2.0 th nla time 5 |-3 5 5 ns | 4.5 | Fig. 10 n 5 |-2 5 5 6.0 September 1993 62174HC/HCT373 MSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: bus driver Ice category: MSI Note to HCT types The value of additional quiescent supply current (Alec) for a unit load of 1 is given in the family specifications. To determine Alcg per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT Dn 0.30 LE 1.50 OE 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V: ty = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74CHT SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 ~40to +85 | 40 to +125 Vv min.| typ. | max. | min./ max. | min. | max. 'PHL/ _| Propagation delay 17, | 30 38 45 [ns | 458 | Fig.7 tPLH Dp to Oy tPHL/ propagation delay is | 32 40 48 | ns 45 | Fig 8 tPLH LE toQ, tpzy/ 3-state output enable time 45 | Fig 9 tPZL OE to O, 19 | 32 40 48 ns ig. tpHz/ 3-state output disable time 18 | 30 38 45 ns 45 | Fig.9 tPLZ OE to O, tTHL/ output transition time 5 12 15 18 ns 4.5 Fig. 7 tTLH tw rae wan 16 | 4 20 24 ns =| 45 | Fig. 8 set-up time 8 45 Fig. 10 tsu D, to LE 12 16 15 1 ns ig hold time _ 45 Fic. 10 th Dn to LE 4 1 4 4 ns ig. 622 September 1993Octal D-type transparent latch; 3-state | L 74HC/HCT373 Ms! AC WAVEFORMS LE INPUT a, OUTPU Q,, OUTPUT n OUTPUT 7287876 el eT THLE aml le tTLH 7293261 tTHL >! bee at le TTLH Fig. 8 Waveforms showing the latch enable input Fig. 7 Waveforms showing the input (Dj) (LE) pulse width, the latch enable input to output to output (Op) propagation delays and (Q,) propagation delays and the output transition the output transition times. times. D, INPUT OE INPUT Q,, OUTPUT LOW-to-OFF LE INPUT OFF -to- LOW 7287866 OQ, OUTPUT Oe ine Fig. 10 Waveforms showing the data set-up and hold times for Dy input to LE input. outputs wle outputs l- outputs 7Z93848 enabled disabled enabled Note to Fig. 410 The shaded areas indicate when the input is permitted to change for predictable output Fig. 9 Waveforms showing the 3-state enable and performance. disable times. Note to AC waveforms (1) HC: Vyy = 50%; Vy = GND to Vcc. HCT: Vy = 1.3-V; Vy = GND to 3V. September 1993 623