500 MHz Dual DCL ADATE206 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC (18, 19, 57, 58, 77, 78, 89, 98, 99) VIT VIL VIH DR_INV DR_DATA_P_T DR_DATA_N_T DR_DATA_N DR_EN_P DR_EN_P_T DR_EN_N_T DR_EN_N VTEN LDEN 7 69 8 ADATE206 68 9 67 6 70 22 10 54 B SO Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment GENERAL DESCRIPTION The ADATE206 is a complete, single-chip solution that performs the pin electronics functions of driver, comparator, and active load (DCL) for ATE applications. The active load can be powered down if not used. O The driver is a proprietary design that features three active modes: data high mode, data low mode, and term mode, as well as an inhibit state. The driver has low leakage (<10 nA) in High-Z mode. The output voltage range is -1.5 V to +6.5 V to accommodate a wide variety of test devices. The ADATE206 supports four programmable Tr/Tf times for applications where slower edge rates are required. The edge rate selection is done via two static digital CMOS select bits. The input data to the driver can be inverted using a single CMOS logic bit. This feature can be used for system calibration or applications where complement input data is needed. CVH COMP_H_P COMP_H_N CLLM COMP_L_P COMP_L_N CVL 65 23 11 53 66 CLAMPL CLAMPH 24 52 25 51 26 81 DRIVER LOGIC 95 DUT 50 27 49 28 48 29 47 15 61 14 62 91 85 31 45 COMP_H 32 44 13 63 34 42 COMP_L 35 41 90 86 IOL LOAD LOGIC VCOM VIOL VIOH GNDREF 1 75 1x 4 72 3 IOH 73 2 TEMP SENSOR (5 DIODES) 74 VEE (16, 17, 33, 43, 59, 60, 84, 87, 92) 88 TEMP GND (5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97,100) 05738-001 APPLICATIONS SHIELDS (80, 82, 94, 96) TE DR_DATA_P NC (30, 46) LE Driver, comparator, and active load 500 MHz toggle rate Inhibit mode function Dynamic clamps Operating voltage range: -1.5 V to 6.5 V Output voltage swing: 200 mV to 8 V Four range adjustable slew rate True/complement data mode bit 100-lead TQFP package, exposed pad Low per channel power 1.4 W with load off 1.75 W with load programmed at 20 mA nominal Low leakage (<10 nA) in High-Z mode Driver 50 output resistance 1 ns minimum pulse width for a 3 V step Load: -35 mA to +35 mA maximum current range Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006-2008 Analog Devices, Inc. All rights reserved. ADATE206 TABLE OF CONTENTS Absolute Maximum Ratings ............................................................8 Applications ....................................................................................... 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................9 Functional Block Diagram .............................................................. 1 Typical Performace Characteristics ............................................. 12 Table of Contents .............................................................................. 2 Theory of Operation ...................................................................... 15 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 16 Specifications..................................................................................... 3 Ordering Guide .......................................................................... 16 REVISION HISTORY LE Electrical Characteristics ............................................................. 3 10/08-- Rev. 0 to Rev. A Changes to the VCOM Buffer Offset Parameter, Table 1 ............ 7 O B SO 1/06-- Revision 0: Initial Version TE Features .............................................................................................. 1 Rev. A | Page 2 of 16 ADATE206 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCC = 10.0 V, VEE = -5.0 V, TJ = 75C, unless otherwise noted. Table 1. Typ DC Output Characteristics Logic Range, VIL, VIH, VIT Amplitude [VH to VL] Output Resistance PSRR, Drive or Term Mode Static Current Limit O Absolute Accuracy--VIH, VIL, VIT VIH Offset Max Unit Test Conditions/Comments 5.5 +10 V V A VIN = 0 V, 3.3 V CMOS_VDD/2 TE 0 -10 CMOS_VDD/2 0 -10 +600 (@ 3.3 V) 1 5.5 +800 V V A mA +3.5 VIN = 0 V, 3.3 V VIN = 5.5 V -2.0 250 -10 300 +2 +10 V mV A -10 -2 +10 A Maximum value bias of reference sweep +25 A Maximum value bias of reference sweep +6.5 8 52.5 B SO VIT Reference Inputs Input Bias Current Min LE Parameter DRIVER Single-Ended Logic Input Characteristics (VTEN, DRV_INV) Threshold Voltage Voltage Range Bias Current Single-Ended Logic Input Characteristics (SLEW0, SLEW1) Threshold Voltage Voltage Range Bias Current Bias Current Differential Logic Input Characteristics (DR_DATA_N, DR_DATA_P, DR_EN_N, DR_EN_P) Voltage Range Differential Voltage with LVPECL Levels Bias Current VIH, VIL Reference Inputs Input Bias Current -25 +12 -1.5 -125 10 110 +125 V V mV/V mA -100 +30 +100 mV 1.02 V/V 47.5 VIH Gain Error 0.98 VIH Linearity Error -15 +5 +15 mV VIL Offset VIL Gain Error -100 0.98 +30 +100 1.02 mV V/V VIL Linearity Error -15 +5 +15 mV VIT Offset -100 +30 +100 mV VIT Gain Error 0.98 1.02 V/V Rev. A | Page 3 of 16 VIN = 3.24 V, 3.495 V VCC, VEE 1% Output to -1.5 V, VH = 6.5 V, VT = 0 V Data = H, VH = 0 V, VL = -1.5 V, VT = 3 V Data = H, VH = 0 V to 5 V, VL = -1.5 V, VT = 3 V Data = VH relative to line between 0 V to 5 V; full range of VIH = -1.4 V to +6.5 V Data = L, VL = 0 V to 5 V, VH = 6.5 V, VT = 3 V Data = VH relative to line between 0 V to 5 V; full range of VIH = -1.4 V to +6.5 V Data = VT, VT = 0 V, VL = 0 V, VH = 3 V Data = VT, VT = 0 V to 5 V, VL = 0 V, VH = 3 V ADATE206 Parameter VIT Linearity Error Min -15 Typ +5 Max +15 Offset Tempco Driver Interaction VH Interaction to VL -2 +2 mV VH Interaction to VT -2 +2 mV VL Interaction to VH -2 +2 mV VL Interaction to VT -2 +2 mV VT Interaction to VH -2 VT Interaction to VL -2 Rise/Fall Times at Device Under Testing (DUT) 0.2 V Swing: Rise/Fall Time 0.5 V Swing: Rise/Fall Time 1 V Swing: Rise/Fall Time 3 V Swing: Rise/Fall Time 350 mV +2 mV ps 350 ps 500 ps 650 ps 450 B SO 3 V Swing: Rise/Fall Time +2 LE 300 V/C 550 ps 5 V Swing: Rise/Fall Time 1.1 ns Minimum Pulse Width at DUT 500 mV Swing 1 500 ps 800 ps 500 MHz 1.4 ns Propagation Delay Tempco2 2.0 ps/C Delay Matching, Edge-to-Edge Delay Change vs. Pulse Width2 20 30 ps ps Delay Change vs. Duty Cycle2 5 ps 1.5 V Swing1 Toggle Rate @ 3 V O Dynamic Performance, Drive (VH and VL) Propagation Delay Time 2 Rev. A | Page 4 of 16 Test Conditions/Comments Data = VH relative to line between 0 V to 5 V; full range of VIH = -1.4 V to +6.5 V 65C to 105C VIH = 5.0 V; VIL = -1.5 V, +4.7 V, +4.8 V, +4.9 V VIH = 3.0 V; VIT = -1.5 V, +2.9 V, +3.1 V, +6.5 V VIL = 0.0 V; VIH = 0.1 V, 0.2 V, 0.3 V, 6.5 V VIL = 0.0 V; VIT = -1.5 V, -0.1 V, +0.1 V, +6.5 V VIT = 1.5 V, VIL = -1.0 V; VIH = -0.8 V, +1.4 V, +1.6 V, +6.5 V VIT = 1.5 V, VIH = 6.0 V; IL = -1.5 V, +1.4 V, +1.6 V, +5.8 V TE 80 Unit mV Terminated 20% to 80%, VIH = 400 mV, VIL = 0 V, VIT = 0 V Terminated 10% to 90%, VIH = 1.0 V, VIL = 0 V, VIT = 0 V Terminated 10% to 90%, VIH = 2.0 V, VIL = 0 V, VIT = 0 V Unterminated 10% to 90%, VIH = 3.0 V, VIL = 0 V, VIT = 0 V Terminated 20% to 80%, VIH = 3.0 V, VIL = 0 V, VIT = 0 V using DUT comparator Unterminated 10% to 90%, VIH = 5.0 V, VIL = 0 V, VIT = 0 V Terminated, VIH = 1.0 V, VIL = 0 V, VIT = 0 V Terminated, VIH = 3.0 V, VIL = 0 V, VIT = 0 V Unterminated, 50/50 dc measured frequency when amplitude drops 10% Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 1s period, pulse width = 50 ns to 1 ns Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 1 s period; 10%, 50%, and 90% duty cycle ADATE206 Parameter Settling Time to 15 mV Min Max Unit ns 32 ns 2 ps/C 1 V Swing 2 ps/C 3 V Swing 2 ps/C 5 V Swing 2 Rise and Fall Time Temperature Coefficient 500 mV Swing Delay Time, Active Low to Inhibit3 % % % % 3.1 ns 2.1 ns 2.5 ns B SO Delay Time, Inhibit to Active High3 1 1 2 2 ps/C LE Overshoot and Preshoot 200 mV swing Overshoot and Preshoot 1 V swing Overshoot and Preshoot 3 V swing Overshoot and Preshoot 5 V swing Dynamic Performance, Inhibit Delay Time, Active High to Inhibit 3 Delay Time, Inhibit to Active Low3 3.9 ns I/O Spike 350 mV CLAMPS VCPH, VCPL Clamp Inputs VCPH Voltage Range VCPL Voltage Range Input Bias Current O Absolute Accuracy VCPH, VCPL VCPH Offset VCPH Gain Error VCPH Linearity Error VCPL Offset VCPL Gain Error VCPL Linearity Error COMPARATOR DC SPECIFICATIONS 4 DC Input Characteristics (VOH, VOL) Bias Current Voltage Range Differential Voltage CLAMPL -1.8 -50 -100 -100 -10 -1.5 -8.0 Test Conditions/Comments Terminated, VIH = 3 V, VIL = 0.0 V, VIT = 0.0 V Terminated, VIH = 3 V, VIL = 0.0 V, VIT = 0.0 V Terminated 10% to 90%, VIH = 1.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Terminated 10% to 90%, VIH = 2.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Unterminated 10% to 90%, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Unterminated 10% to 90%, VIH = 5.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Terminated, VIH = 400 mV Terminated, VIH = 2 V Unterminated Unterminated TE Settling Time to 4 mV Typ 8 6.8 CLAMPH +50 V V A +55 1 +10 +100 mV V/V mV +55 1 +10 +100 +5 +10 +6.5 +8.0 -2 Rev. A | Page 5 of 16 mV V/V mV A V V Terminated, VIH = 3.0 V, VIL = -1.0 V VH = 3.0 V, VL = -1.0 V, terminated 50 Terminated, VIH = 3.0 V, VIL = -1.0 V Terminated, VIH = 3.0 V, VIL = -1.0 V Terminated, VIH = 0.0 V, VIL = 0.0 V, VIT = 0.0 V Maximum value bias of reference sweep = -1.8 V to +6.8 V Driver = INH, VCPH = 0 V Driver = INH, relative to line between 0 V to 4.5 V, VCPH = -1.5 V to +6.5 V, VCPL = -1.8 V Driver = INH, VCPL = 0 V Driver = INH, relative to line between 0 V to 4.5 V, VCPL = -1.5 V to +6.5 V, VCPH = 6.5 V VOH and VOL = -1.5 V to +6.5 V ADATE206 Min -15 Typ Max +15 Unit mV % FSR mV Test Conditions/Comments Common mode = 0 V VIN = -1.5 V to +6.5 V VIN = -1.5 V to +6.5 V 5.5 +200 V V A A VIN = 0 V, 3.3 V VIN = 5.5 V 3.4 3.1 450 V V mV Terminated 50 to 3.3 V Terminated 50 to 3.3 V Terminated 50 to 3.3 V ps ps/C VIN = 3 V p-p, 2 V/ns VIN = 3 V p-p, 2 V/ns ps VIN = 0 V to 3 V, 2 V/ns, driver in VTERM, VIT = 0 V, period = 10 ns; dc = 1 ns, 5 ns, 9 ns VIN = 0 V to 3 V, driver in VTERM, VIT = 0 V VIN = 0 V to 500 mV, 0 V to 1 V, 0 V to 3 V, 2 V/ns, driver in VTERM, VIT = 0 V VIN = 0 V to 1 V, <50 ps, 20% to 80% rise time, driver in VTERM = 0V VIN = 0 V to 3 V, 2 V/ns; pulse width = 3 ns, 4 ns, 5 ns, 10 ns; driver in VTERM, VIT = 0 V Settling to 8 mV, VIN = 0 V to 3 V, driver in VTERM, VIT = 0 V 2 V terminated, 1 V at the comparator, driver in VTERM, VIT = 0 V, 1 s period, pulse width = 50 ns to 1 ns VIN = 100 mV, sweep CVL and CVH HCOMP rise to LCOMP rise, HCOMP fall to LCOMP fall 1 3 CMOS_VDD/2 3.1 2.7 350 +160 260 3.26 2.86 400 500 1.0 40 TE 0 -10 LE Parameter Offset Gain Error Linearity Error Single-Ended Logic Input Characteristics Threshold Voltage (CLLM) Voltage Range Bias Current Bias Current Digital Output Characteristics (VOH, VOL Levels) Logic 1 Logic 0 Differential Levels COMPARATOR AC SPECIFICATIONS Propagation Delay Input to Output Propagation Delay Tempco Propagation Delay Change with Respect to PD vs. Duty Cycle Slew Rate: 1 V/ns, 2 V/ns, 3 V/ns 30 ps 30 ps 225 ps Pulse-Width Linearity 20 ps Settling Time 5.5 ns Minimum Pulse Width 1 ns Hysteresis 6 mV 50 ps Amplitude: 500 mV, 1.0 V, 3.0 V O B SO Equivalent Input Rise Time Comparator Propagation Delay Matching, HCOMP to LCOMP LOAD DC SPECIFICATIONS Single-Ended Logic Input Characteristics Threshold Voltage (LDEN) Voltage Range Bias Current Input Characteristics VIOL Current Program Range 0 -10 CMOS_VDD/2 5.5 +10 V V A 0.0 3.5 V VIOH Current Program Range 0.0 3.5 V VIOH, VIOL Input Bias Current -10 +10 A VDUT Range -1.5 +6.5 V Rev. A | Page 6 of 16 VIN = 0 V, 3.3 V VDUT = -1.5 V, +6.5 V; IOL = 0 mA to 35 mA VDUT = -1.5 V, +6.5 V; IOH = 0 mA to 35 mA VIOL = 0 V, 3.5 V; VIOH = 0 V, 3.5 V |VDUT - VCOM| > 1.0 V ADATE206 Parameter VDUT Range Min -1.5 VDUT Range -1.5 Output characteristics Gain 9.5 Typ 10 Max +6.5 Unit V +6.5 V 10.5 mA/V Load Offset, IOH, IOLT -200 +200 A Load Nonlinearity, IOH, IOLT -50 +50 A Dynamic Performance Propagation Delay--IMAX to INHIBIT INHIBIT to IMAX +3 +1 1 -10 +1 Output Leakage Current, Low Leakage Mode Output Capacitance Power Supplies 5 Total Supply Range Positive Supply, VCC Negative Supply, VEE Positive Supply Current, VCC +50 +10 1.01 mV A V/V +10 mV 2.3 ns 2.3 ns -1.5 +0.28 +1.5 A -200 +10 +200 nA B SO TOTAL FUNCTION Output Leakage Current -50 -10 0.99 A/C 2 10.0 -5.0 210 15.5 10.25 -4.75 245 V V V mA 240 270 300 mA Total Power Dissipation 2.5 3.5 4 W Positive Supply Current Load Disabled, VCC 145 165 200 mA Negative Supply Current Load Disabled, VEE 190 220 250 mA Total Power Dissipation 1.8 2.8 3.3 W O Temperature Sensor Gain Factor 10 1 IOL, IOH = 20 mA, VCOM = 0 V VCOM = -1.5 V to +6.5 V IOL, IOH = 20 mA, VCOM = -1.5 V to +6.5 V IOL, IOH = 20 mA, VCOM = -1.5 V to +6.5 V, relative to a line at 0 V and 5 V VTT = 2 V, VCOM = 4 V/0 V, IOL = 20 mA, IOH = 20 mA VTT = 2 V, VCOM = 4 V/0 V, IOL = 20 mA, IOH = 20 mA Driver = INH, VDUT swept from -1.5 V to +6.5 V Driver = INH, VDUT swept from -1.5 V to +6.5 V pF 9.75 -5.25 190 Negative Supply Current, VEE Slope of line between 5 mA and 30 mA IOH and IOL programmed at 20 mV (200 A) Relative to a line from 5 mA to 30 mA; IOL, IOH from 200 A to 35 mA Measured at IOH, IOL = 30 mA TE VCOM Buffer Linearity Error 3 LE Output Current Tempco, IOH, IOLT VCOM Buffer (Through Bridge) VCOM Buffer Offset VCOM Buffer Bias Current VCOM Buffer Gain Test Conditions/Comments VDUT - VCOM > 1.0 V; IOH = 0 mA to 35 mA VCOM - VDUT > 1.0 V; IOL = 0 mA to 35 mA mV/C Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Five diodes in series 1 s period, pulse width = 50 ns to 500 ps, pulse width measured when amplitude drops 10%. Measured at 50% of input amp to 50% of output amp. 3 tPD measured from the 50% of enable signal to 50% of output. 4 The low leakage mode of the comparator, controlled by VLLM input, reduces the leakage due to the comparator input. The comparator operates in this mode, but its bandwidth is compromised and is not guaranteed. 5 Under no circumstances should the input voltages exceed the supply voltages. 2 Rev. A | Page 7 of 16 ADATE206 ABSOLUTE MAXIMUM RATINGS Table 2. Rating 245 mA 300 mA +10.5 V -5.5 V +150C -65C to +150C 1500 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. LE TE Parameter Maximum Current for VCC Maximum Current for VEE Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Operating Temperature (Junction) Storage Temperature Range ESD (Human Body Model) ESD CAUTION O B SO ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 8 of 16 ADATE206 GND VCC VCC GND GND/SHIELDS DUT_2 GND/SHIELDS GND VEE CVH_2 CVL_2 VEE TEMP VCC CVL_1 CVH_1 VEE GND GND/SHIELDS DUT_1 GND/SHIELDS GND VCC VCC GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 75 VCOM_2 74 VIOH_1 GNDREF_2 3 73 VIOH_2 VIOL_1 4 72 VIOL_2 GND 5 71 GND D_INV_1 6 VIT_1 7 VIL_1 8 VIH_1 9 PIN 1 TE VCOM_1 GNDREF_1 70 D_INV_2 69 VIT_2 68 VIL_2 67 VIH_2 66 CLAMPH_2 65 CLAMPL_2 64 GND 63 CLLM_2 62 LDEN_2 61 VTEN_2 60 VEE 59 VEE 58 VCC 57 VCC 56 GND 55 GND 54 DR_DATA_P_2 DR_DATA_P_T_1 23 53 DR_DATA_P_T_2 DR_DATA_N_T_1 24 52 DR_DATA_N_T_2 DR_DATA_N_1 25 51 DR_DATA_N_2 ADATE206 CLAMPL_1 10 TOP VIEW (Not to Scale) CLAMPH_1 11 GND 12 CLLM_1 13 LE LDEN_1 14 VTEN_1 15 VEE 16 VEE 17 VCC 18 VCC 19 GND 20 GND 21 B SO DR_DATA_P_1 22 O Figure 2. Pin Configuration Rev. A | Page 9 of 16 05738-002 DR_EN_P_2 DR_EN_P_T_2 DR_EN_N_T_2 DR_EN_N_2 NC COMP_H_P_2 COMP_H_N_2 VEE COMP_L_P_2 COMP_L_N_2 GND SLEW0 CMOS_VDD SLEW1 GND COMP_L_N_1 COMP_L_P_1 VEE COMP_H_N_1 COMP_H_P_1 NC DR_EN_N_1 DR_EN_N_T_1 DR_EN_P_1 DR_EN_P_T_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ADATE206 Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97, 100 6 7 8 9 10 11 13 14 15 Mnemonic VCOM_1 GNDREF_1 VIOH_1 VIOL_1 GND Description Commutation Reference Voltage. Reference GND for VIOL, VIOH. Program Voltage for IOH (Sink). Program Voltage for IOL (Source). Device Ground. D_INV_1 VIT_1 VIL_1 VIH_1 CLAMPL_1 CLAMPH_1 CLLM_1 LDEN_1 VTEN_1 VEE VCC Positive Power Supply. DR_DATA_P_1 DR_DATA_P_T_1 24 DR_DATA_N_T_1 High Speed Data Inputs. Sets high/low state of driver output (see Table 4). Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. Termination Resistors for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. Complement of DR_DATA_P_1. High Speed Enable Inputs. Multifunction depending on status of VTEN_1 and LDEN_1. Causes driver to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see Table 4). Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. Complement of DR_EN_P_1. No Connect. High Comparator Output. Complement of COMP_H_P_1. Low Comparator Output. Complement of COMP_L_P_1. Logic Signals Controlling Driver Slew Rates for Both Drivers. 00 codes for maximum slew voltage; 11 codes for minimum slew voltage. CMOS Supply (Internal / 2 = Single-Ended Logic Reference). Complement of COMP_L_P_1. Low Comparator Output. Complement of COMP_H_P_1. High Comparator Output. DR_DATA_N_1 DR_EN_P_1 27 DR_EN_P_T_1 28 DR_EN_N_T_1 DR_EN_N_1 NC COMP_H_P_1 COMP_H_N_1 COMP_L_P_1 COMP_L_N_1 SLEW1, SLEW0 O 29 30, 46 31 32 34 35 37, 39 38 41 42 44 45 LE B SO 25 26 TE 16, 17, 33, 43, 59, 60, 84, 87, 92 18 19, 57, 58, 77, 78, 89, 98, 99 22 23 Driver Invert. Driver Term Voltage Reference. Driver Low Voltage Reference. Driver High Voltage Reference. Low Clamp. High Clamp. Comparator Low Leakage Mode. Determines Whether LD Responds to DR_EN_1 or is Disabled (see Table 4). Low Speed Control Signal. When high, DR_EN_1 forces driver output to VIT. Otherwise, DR_EN_1 forces driver to high impedance (see Table 4). Negative Power Supply. CMOS_VDD COMP_L_N_2 COMP_L_P_2 COMP_H_N_2 COMP_H_P_2 Rev. A | Page 10 of 16 ADATE206 Mnemonic DR_EN_N_2 DR_EN_N_T_2 DR_EN_P_T_2 50 DR_EN_P_2 51 52 53 DR_DATA_N_2 DR_DATA_N_T_2 DR_DATA_P_T_2 54 61 DR_DATA_P_2 VTEN_2 62 63 65 66 67 68 69 LDEN_2 CLLM_2 CLAMPL_2 CLAMPH_2 VIH_2 VIL_2 VIT_2 Description Complement of DR_EN_P_2. Complement of DR_EN_P_T_2. Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. High Speed Enable Input. Multifunction depending on status of VTEN_2 and LDEN_2. Causes driver to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see Table 4). Complement of DR_DATA_P_2. Complement of DR_DATA_P_T_2. Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. High Speed Data Input. Sets high/low state of driver output (see Table 4). Low Speed Control Signal. When high, DR_EN_2 forces driver output to VT; otherwise, DR_EN_2 forces driver to high impedance (see Table 4). Determines Whether LD Responds to DR_EN_2 or is Disabled (see Table 4). Comp Low Leakage Mode. Low Clamp. High Clamp. Driver High Voltage Reference. Driver Low Voltage Reference. Driver Term Voltage Reference. 70 72 73 74 75 80, 82, 94, 96 81 85 86 88 90 91 95 D_INV_2 VIOL_2 VIOH_2 GNDREF_2 VCOM_2 GND/SHIELDS DUT_2 CVH_2 CVL_2 TEMP CVL_1 CVH_1 DUT_1 Driver Invert. Program Voltage for IOL (Source). Program Voltage for IOH (Sink). Reference GND for VIOL, VIOH. Commutation Reference Voltage. Device Ground or Pin Shield. Output/Input Pin. Window High Reference Level. Window Low Reference Level. Temperature Sense, Five Diode String, Reference to GND. Window Low Reference Level. Window High Reference Level. Output/Input Pin. O B SO LE TE Pin No. 47 48 49 Rev. A | Page 11 of 16 ADATE206 TYPICAL PERFORMACE CHARACTERISTICS 2400 5 VIH = 5V 2000 3 LINEARITY ERROR (mV) VIL = 0V TERMINATION = 50 1400 VIH = 3V 1200 1000 800 600 400 0 2 4 6 8 10 0 -1 -2 -3 05738-003 12 14 16 -5 -6 -2 18 2ns/DIV -1 0 1 3 4 6 VIH = 500mV 4 VIL = 0V TERMINATION = 50 160 140 120 100 80 40 B SO VIH = 200mV 60 0 0 2 4 6 8 10 12 14 16 3 2 1 0 -1 -2 -3 05738-004 VIH = 100mV 20 -4 -5 -2 18 -1 0 1 2ns/DIV TRAILING RISE EDGE -20 O -30 -40 -50 -60 -70 4 8 5 6 7 DRIVER = VTERM 6 LINEARITY ERROR (mV) -10 3 Figure 7. Driver VIL Linearity vs. Output TRAILING FALL EDGE 0 2 VDUT (V) Figure 4. Driver Small Signal Response 10 7 LE 200 180 6 DRIVER = VIL 5 LINEARITY ERROR (mV) 220 5 Figure 6. Driver VIH Linearity vs. Output 240 4 2 0 -2 -4 -80 -90 -100 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 2.5ns/DIV -6 -8 -2 05738-008 05738-005 10ps/DIV 2 VDUT (V) Figure 3. Driver Large Signal Response 20mV/DIV 1 -4 VIH = 1V 200 0 2 05738-007 200mV/DIV 1600 TE 1800 DRIVER = VIH 4 05738-006 2200 -1 0 1 2 3 4 5 VDUT (V) Figure 5. Driver Trailing Edge Timing Error vs. Pulse Width Figure 8. Driver VTERM Linearity vs. Output Rev. A | Page 12 of 16 6 7 ADATE206 1.0004 4.0 1.0003 3.5 1.0002 3.0 OFFSET (mV) 1.0000 0.9999 0.9998 2.0 1.5 1.0 0.9997 90 100 0 -2 110 -1 0 1 2 12 14 16 18 20 05738-016 9500 9000 8500 8000 7500 8000 6500 5500 5000 05738-017 500ps/DIV Figure 11. Comparator Differential Output Response Figure 14. Comparator Schmoo at 600 ps Rise and Fall Time Rev. A | Page 13 of 16 9500 10 tBASE (2ns/DIV) 9000 8 8500 6 8000 4 7500 2 5500 05738-011 40 20 5000 60 3500 80 3000 100 2500 120 2000 140 1500 50mV/DIV O 160 VIN = 0V TO 1V <50ps 20% TO 80% RISE TIME DRIVER IN VTERM = 0V 1000 180 1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 -50 -100 0 200 4500 500ps/DIV 500 220 7 Figure 13. Comparator Schmoo at 1 ns Rise and Fall Time Figure 10. Driver Offset vs. Temperature 240 4000 110 4500 100 3500 90 TEMPERATURE (C) 4000 80 3000 70 0 05738-010 -1.5 60 6 VIN = 0V TO 1V <50ps 20% TO 80% RISE TIME DRIVER IN VTERM = 0V 2500 B SO -0.5 2000 0 1500 0.5 1000 50mV/DIV LE 1.0 1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 -50 -100 8000 1.5 -1.0 5 Figure 12. Comparator Offset vs. Common-Mode Voltage 2.0 20mV/DIV 4 TE Figure 9. Driver Gain vs. Temperature 0 3 COMMON-MODE VOLTAGE (V) TEMPERATURE (C) 6000 80 6500 70 6000 0.9995 60 05738-012 0.5 05738-009 0.9996 OFFSET (mV) 2.5 500 GAIN (V/V) 1.0001 ADATE206 32.0 30.0 18 14 25.0 LINEARITY ERROR (A) 22.0 20.0 15.0 12.5 10.0 7.5 5.0 05738-018 0 8 6 4 2 1 2 3 4 5 6 7 8 9 -2 -4 10 0 5 10 15 20 25 30 35 IOL (mA) TE 1ns/DIV Figure 15. Comparator tPD vs. Pulse Width Figure 17. Active Load Linearity vs. IOH 40 14 VCOM = 1V IOH = IOL = 35mA 12 VCOM = 2V IOH = 0V VDUT = 0V 10 LINEARITY ERROR (A) LE 20 10 IDUT (mA) 10 0 2.5 30 12 05738-014 2.5ps/DIV 17.5 -3.0 VCOM = 0V IOL = 0V VDUT = 2V 16 27.5 0 -10 -20 8 6 4 2 0 -1 0 1 2 3 4 5 6 7 VDUT (V) O Figure 16. Active Load Commutation Region Rev. A | Page 14 of 16 05738-015 -40 -2 05738-013 -30 B SO -2 -4 -6 0 5 10 15 20 25 IOL (mA) Figure 18. Active Load Linearity vs. IOL 30 35 ADATE206 THEORY OF OPERATION These differential input pins provide 50 input termination resistors for use as desired. The single-ended inputs have an input range compatible with most logic families and are high impedance to make driving them very easy. The switching threshold for the single-ended inputs is preset to one-half of the voltage at the CMOS_VDD pin. TE The ADATE206 has two general classes of logic inputs: differential inputs for controlling functions that generally need to be operated at high speed, and single-ended CMOS inputs for setting operating modes or other low speed functions. The differential inputs have a wide common-mode range that allows them to be used with a variety of logic families. The differential inputs can be used single-ended, with one input from each pair of inputs tied to a fixed reference. However, this makes precise timing more difficult to achieve. Table 4. Driver and Load Modes DR_EN (High Speed Differential) DR_DATA (High Speed Differential) Driver Status Load Status 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 1 X 0 1 X 0 1 X 0 1 High-Z VIL VIH VIT VIL VIH High-Z VIL VIH High-Z High-Z High-Z High-Z High-Z High-Z ON High-Z High-Z LE VTEN (CMOS Single-Ended) B SO LDEN (CMOS Single-Ended) 0 0 0 0 0 0 1 1 1 Table 5. Comparator Low Leakage Mode CLLM (CMOS Single-Ended) Typical DUT Pin Bias Current 0 1 1 A 10 nA Table 6. Rise/Fall Time Selection 3 V, 10% to 90%, Unterminated Slew0 0 1 0 1 O Slew1 0 0 1 1 Tr/Tf (ns) 0.7 0.95 1.4 2.8 Table 7. Comparator Logic Function DUT Pin Voltage >CVL >CVH >CVL <CVH <CVL >CVH <CVL <CVH COMP_L_P 1 1 0 0 COMP_L_N 0 0 1 1 Rev. A | Page 15 of 16 Output States COMP_H_P 1 0 1 0 COMP_H_N 0 1 0 1 ADATE206 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 76 75 PIN 1 76 75 100 1 TOP VIEW (PINS DOWN) BOTTOM VIEW EXPOSED PAD (PINS UP) 0 MIN 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY 50 25 26 51 49 VIEW A 6.50 SQ VIEW A ROTATED 90 CCW 25 50 26 TE 1.05 1.00 0.95 0.50 BSC LEAD PITCH 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD ORDERING GUIDE Temperature Range -40C to +85C Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] O B SO Model ADATE206BSV LE Figure 19. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-2) Dimensions shown in millimeters (c)2006-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05738-0-10/08(A) Rev. A | Page 16 of 16 Package Option SV-100-2