   
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FEATURES
APPLICATIONS
1
2
3
4
8
7
6
5
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
PW PACKAGE
(TOP VIEW)
DESCRIPTION
TYPICAL APPLICATION
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115PW 0.1 µF
0.1 µF
CLRL
IN1: 2.8 - 5.5 V
IN2: 2.8 - 5.5 V
RILIM
Switch Status
R1
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
AUTOSWITCHING POWER MULTIPLEXER
•Available in a TSSOP-8 Package•Two-Input, One-Output Power MultiplexerWith Low r
DS(on)
Switches:
•PCs– 84 mΩTyp (TPS2115)
•PDAs– 120 mΩTyp (TPS2114)
•Digital Cameras•Reverse and Cross-Conduction Blocking
•Modems•Wide Operating Voltage Range: 2.8 V to 5.5 V
•Cell phones•Low Standby Current: 0.5 µA Typical
•Digital Radios•Low Operating Current: 55 µA Typical
•MP3 Players•Adjustable Current Limit•Controlled Output Voltage Transition Times,Limits Inrush Current and Minimizes OutputVoltage Hold-Up Capacitance•CMOS and TTL Compatible Control Inputs•Manual and Auto-Switching Operating Modes•Thermal Shutdown
The TPS211x family of power multiplexers enables seamless transition between two power supplies, such as abattery and a wall adapter, each operating at 2.8-5.5 V and delivering up to 1 A. The TPS211x family includesextensive protection circuitry, including user-programmable current limiting, thermal protection, inrush currentcontrol, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These featuresgreatly simplify designing power multiplexer applications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PACKAGE DISSIPATION RATINGS
ABSOLUTE MAXIMUM RATINGS
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
FEATURE TPS2110 TPS2111 TPS2112 TPS2113 TPS2114 TPS2115
Current limit adjustment range 0.31-0.75A 0.63-1.25A 0.31-0.75A 0.63-1.25A 0.31-0.75A 0.63-1.25AManual Yes Yes No No Yes YesSwitching modes
Automatic Yes Yes Yes Yes Yes YesSwitch status output No No Yes Yes Yes YesPackage TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8
ORDERING INFORMATION
T
A
PACKAGE ORDERING NUMBER
(1)
MARKINGS
TPS2114PW 2114-40°C to 85°C TSSOP-8 (PW)
TPS2115PW 2115
(1) The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2114PWR) to indicate tape and reel.
DERATING FACTOR T
A
≤25°C T
A
= 70°C T
A
= 85°CPACKAGE
ABOVE T
A
= 25°C POWER RATING POWER RATING POWER RATING
TSSOP-8 (PW) 3.87 mW/°C 386.84 mW 212.76 mW 154.73 mW
over operating free-air temperature range unless otherwise noted
(1)
TPS2114, TPS2115
V
I
Input voltage range IN1, IN2, D0, D1, ILIM
(2)
-0.3 V to 6 VV
O
Output voltage range
(2)
OUT, STAT -0.3 V to 6 VI
O
Output sink current STAT 5 mATPS2114 0.9 AI
O
Continuous output current
TPS2115 1.5 AContinuous total power dissipation See Dissipation Rating TableT
J
Operating virtual junction temperature range -40°C to 125°CT
stg
Storage temperature range -65°C to 150°CLead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND.
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RECOMMENDED OPERATING CONDITIONS
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
ELECTRICAL CHARACTERISTICS
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
MIN MAX UNIT
V
I(IN2)
≥2.8 V 1.5 5.5V
I
Input voltage at IN1 VV
I(IN2)
< 2.8 V 2.8 5.5V
I(IN1)
≥2.8 V 1.5 5.5V
I
Input voltage at IN2 VV
I(IN1)
< 2.8 V 2.8 5.5V
I
Input voltage at D0, D1 0 5.5 VTPS2114 0.31 0.75I
O(OUT)
Current limit adjustment range ATPS2115 0.63 1.25T
J
Operating virtual junction temperature -40 125 °C
MIN MAX UNIT
Human body model 2 kVCDM 500 V
over recommended operating junction temperature range, V
I(IN1)
= V
I(IN2)
= 5.5 V, R
(ILIM)
= 400 Ω(unless otherwise noted)
TPS2114 TPS2115PARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
POWER SWITCH
V
I(IN1)
= V
I(IN2)
= 5.0 V 120 140 84 110T
J
= 25°C,
V
I(IN1)
= V
I(IN2)
= 3.3 V 120 140 84 110 mΩI
L
= 500 mA
V
I(IN1)
= V
I(IN2)
= 2.8 V 120 140 84 110Drain-source on-stater
DS(on)
(1)
resistance (INx-OUT)
V
I(IN1)
= V
I(IN2)
= 5.0 V 220 150T
J
= 125°C,
V
I(IN1)
= V
I(IN2)
= 3.3 V 220 150 mΩI
L
= 500 mA
V
I(IN1)
= V
I(IN2)
= 2.8 V 220 150
(1) The TPS211x can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specificcase, the lower supply voltge has no effect on the IN1 and IN2 switch on-resistances.
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ELECTRICAL CHARACTERISTICS
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
over operating free-air temperature range (unless otherwise noted)
TPS2115PARAMETER TEST CONDITIONS UNITMIN TYP MAX
LOGIC INPUTS (D0 AND D1)
V
IH
High-level input voltage 2 VV
IL
Low-level input voltage 0.7 VD0 or D1 = High, sink current 1Input current at D0 or D1 µAD0 or D1 = Low, source current 0.5 1.4 5
SUPPLY AND LEAKAGE CURRENTS
D1 = High, D0 = Low (IN1 active), V
I(IN1)
= 5.5 V,
55 90V
I(IN2)
= 3.3 V, I
O(OUT)
= 0 AD1 = High, D0 = Low (IN1 active), V
I(IN1)
= 3.3 V,
1 12V
I(IN2)
= 5.5 V, I
O(OUT)
= 0 ASupply current from IN1 (operating) µAD0 = D1 = Low (IN2 active), V
I(IN1)
= 5.5 V,
75V
I(IN2)
= 3.3 V, I
O(OUT)
= 0 AD0 = D1 = Low (IN2 active), V
I(IN1)
= 3.3 V,
1V
I(IN2)
= 5.5 V, I
O(OUT)
= 0 AD1 = High, D0 = Low (IN1 active), V
I(IN1)
= 5.5 V,
1V
I(IN2)
= 3.3 V, I
O(OUT)
= 0 AD1 = High, D0 = Low (IN1 active), V
I(IN1)
= 3.3 V,
75V
I(IN2)
= 5.5 V, I
O(OUT)
= 0 ASupply current from IN2 (operating) µAD0 = D1 = Low (IN2 active), V
I(IN1)
= 5.5 V,
1 12V
I(IN2)
= 3.3 V, I
O(OUT)
= 0 AD0 = D1 = Low (IN2 active), V
I(IN1)
= 3.3 V,
55 90V
I(IN2)
= 5.5 V, I
O(OUT)
= 0 AD0 = D1 = High (inactive), V
I(IN1)
= 5.5 V,
0.5 2V
I(IN2)
= 3.3 V, I
O(OUT)
= 0 AQuiescent current from IN1 (STANDBY) µAD0 = D1 = High (inactive), V
I(IN1)
= 3.3 V,
1V
I(IN2)
= 5.5 V, I
O(OUT)
= 0 AD0 = D1 = High (inactive), V
I(IN1)
= 5.5 V,
1V
I(IN2)
= 3.3 V, I
O(OUT)
= 0 AQuiescent current from IN2 (STANDBY) µAD0 = D1 = High (inactive), V
I(IN1)
= 3.3 V,
0.5 2V
I(IN2)
= 5.5 V, I
O(OUT)
= 0 AForward leakage current from IN1 D0 = D1 = High (inactive), V
I(IN1)
= 5.5 V, IN2 open,
0.1 5 µA(measured from OUT to GND) V
O(OUT)
= 0 V (shorted), T
J
= 25°CForward leakage current from IN2 D0 = D1= High (inactive), V
I(IN2)
= 5.5 V, IN1 open,
0.1 5 µA(measured from OUT to GND) V
O(OUT)
= 0 V (shorted), T
J
= 25°CReverse leakage current to INx D0 = D1 = High (inactive), V
I(INx)
= 0 V,
0.3 5 µA(measured from INx to GND) V
O(OUT)
= 5.5 V, T
J
= 25°C
CURRENT LIMIT CIRCUIT
R
(ILIM)
= 400 Ω0.51 0.63 0.80TPS2114
R
(ILIM)
= 700 Ω0.30 0.36 0.50Current limit
Aaccuracy
R
(ILIM)
= 400 Ω0.95 1.25 1.56TPS2115
R
(ILIM)
= 700 Ω0.47 0.71 0.99Time for short-circuit output current to settle withint
d
Current limit settling time
(1)
1 ms10% of its steady state value.Input current at ILIM V
I(ILIM)
= 0 V, I
O(OUT)
= 0 A -15 0 µA
(1) Not tested in production.
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TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range (unless otherwise noted)
TPS2115PARAMETER TEST CONDITIONS UNITMIN TYP MAX
UNDERVOLTAGE LOCKOUT
Falling edge 1.15 1.25IN1 and IN2 UVLO VRising edge 1.30 1.35IN1 and IN2 UVLO hysteresis
(2)
30 57 65 mVFalling edge 24 2.53Internal V
DD
UVLO (the higher of IN1 and IN2) VRising edge 2.58 2.8Internal V
DD
UVLO hysteresis
(2)
30 50 75 mVUVLO deglitch for IN1, IN2
(2)
Falling edge 110 µs
REVERSE CONDUCTION BLOCKING
D0 = D1 = high, V
I(INx)
= 3.3 V. Connect OUT to a 5Minimum output-to-input voltage V supply through a series 1-kΩresistor. Let∆V
O(I_block)
80 100 120 mVdifference to block switching D0 = low. Slowly decrease the supply voltage untilOUT connects to IN1.
THERMAL SHUTDOWN
Thermal shutdown threshold
(2)
TPS211x is in current limit. 135Recovery from thermal shutdown
(2)
TPS211x is in current limit. 125 °CHysteresis
(2)
10
IN2-IN1 COMPARATORS
Hysteresis of IN2-IN1 comparator 0.1 0.2 VDeglitch of IN2-IN1 comparator, (both↑↓ )
(2)
90 150 220 µs
STAT OUTPUT
Leakage current V
O(STAT)
= 5.5 V 0.01 1 µASaturation voltage I
I(STAT)
= 2 mA, IN1 switch is on 0.13 0.4 VDeglitch time (falling edge only) 150 µs
(2) Not tested in production.
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SWITCHING CHARACTERISTICS
TRUTH TABLE
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
over recommended operating junction temperature range, V
I(IN1)
= V
I(IN2)
= 5.5 V, R
(ILIM)
= 400 Ω(unless otherwise noted)
TPS2114 TPS2115PARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
POWER SWITCH
T
J
= 25°C, C
L
= 1 µF,Output rise time from ant
r
V
I(IN1)
= V
I(IN2)
= 5 V I
L
= 500 mA, 0.5 1.0 1.5 1 1.8 3 msenable
(1)
See Figure 1 (a)T
J
= 25°C, C
L
= 1 µF,Output fall time from at
f
V
I(IN1)
= V
I(IN2)
= 5 V I
L
= 500 mA, 0.35 0.5 0.7 0.5 1 2 msdisable
(1)
See Figure 1(a)IN1 to IN2 transition, T
J
= 125°C,V
I(IN1)
= 3.3 V, C
L
= 10 µF, 40 60 40 60V
I(IN2)
= 5 V I
L
= 500 mA [Measuretransition time ast
t
Transition time
(1)
µs10-90% rise time orIN2 to IN1 transition,
from 3.4 V to 4.8 VV
I(IN1)
= 5 V, 40 60 40 60on V
O(OUT)
],V
I(IN2)
= 3.3 V
See Figure 1 (b)T
J
= 25°C,V
I(IN1)
= V
I(IN2)
= 5 V,Turnon propagation delay C
L
= 10 µF,t
PLH1
Measured from enable 0.5 1 msfrom enable
(1)
I
L
= 500 mA,to 10% of V
O(OUT)
SeeFigure 1 (a)T
J
= 25°C,V
I(IN1)
= V
I(IN2)
= 5 V,Turnoff propagation delay C
L
= 10 µF,t
PHL1
Measured from disable 3 5 msfrom a disable
(1)
I
L
= 500 mA,to 90% of V
O(OUT)
See Figure 1 (a)Logic 1 to Logic 0 tran-sition on D1,
T
J
= 25°C,V
I(IN1)
= 1.5 V,Switch-over rising C
L
= 10 µF,t
PLH2
V
I(IN2)
= 5 V, 0.17 1 0.17 1 mspropagation delay
(1)
I
L
= 500 mA,V
I(D0)
= 0 V,
See Figure 1 (c)Measured from D1 to10% of V
O(OUT)
Logic 0 to Logic 1 tran-sition on D1,
T
J
= 25°C,V
I(IN1)
= 1.5 V,Switch-over falling C
L
= 10 µF,t
PHL2
V
I(IN2)
= 5V, 2 3 10 2 5 10 mspropagation delay
(1)
I
L
= 500 mA,V
I(D0)
= 0 V, Measured
See Figure 1 (c)from D1 to 90% ofV
O(OUT)
(1) Not tested in production.
D1 D0 V
I(IN2)
> V
I(IN1)
STAT OUT
(1)
0 0 X Hi-Z IN20 1 No 0 IN10 1 Yes Hi-Z IN21 0 X 0 IN11 1 X 0 Hi-Z
(1) The under-voltage lockout circuit causes the output OUT to go Hi-Zif the selected power supply does not exceed the IN1/IN2 UVLO, orif neither of the supplies exceeds the internal V
DD
UVLO.
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FUNCTIONAL BLOCK DIAGRAM
Q2 is ON
1STAT
Control
Logic
D1
D0
UVLO (IN1)
UVLO (IN2)
UVLO (VDD)
Q2 is ON Q1 is ON
_
+
_
++
0.6 V
EN2 EN1
Cross-Conduction
Detector
_
+
Q2
Q1
Charge
Pump
0.5 V
TPS2114: k = 0.2%
TPS2115: k = 0.1%
k* IO(OUT)
_
+
VO(OUT) > VI(INx) +
100 mV
_
+
IO(OUT)
Vf = 0 V
EN1
IN2
IN1
7
4
OUT
ILIM
Internal VDD
Vf = 0 V
VDD
ULVO
Thermal
Sense
1 µA
IN2
ULVO
1 µA
IN1
ULVO
8
6
2
3
5
IN1
IN2
D0
D1
GND
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
D0 2 I TTL and CMOS compatible input pins. Each pin has a 1-µA pullup resistor. The truth table shown above illustratesthe functionality of D0 and D1.D1 3 IGND 5 I GroundIN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold andat least one supply exceeds the internal V
DD
UVLO.IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO thresholdand at least one supply exceeds the internal V
DD
UVLO.ILIM 4 I A resistor R
(ILIM)
from ILIM to GND sets the current limit I
L
to 250/R
(ILIM)
and 500/R
(ILIM)
for the TPS2114 andTPS2115, respectively.OUT 7 O Power switch outputSTAT 1 O STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT isHi-Z (i.e., EN is equal to logic 0).
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PARAMETER MEASUREMENT INFORMATION
0 V 10%
90%
Switch Enabled
Switch Off Switch Off
90%
10%
3.3 V
5 V
Switch #1 Enabled Switch #2 Enabled
4.8 V
3.4 V
DO-D1
1.5 V 1.85 V
4.65 V
Switch #2 EnabledSwitch #1 Enabled Switch #1 Enabled
5 V
trtf
tPLH1 tPHL1
VO(OUT)
tt
VO(OUT)
VO(OUT)
DO-D1 tPLH2 tPHL2
(a)
(b)
(c)
DO-D1
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
Figure 1. Propagation Delays and Transition Timing Waveforms
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TYPICAL CHARACTERISTICS
VI(DO)
VI(D1)
VO(OUT)
t - Time - 1 ms/div
2V/Div
2V/Div
2V/Div
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115PW 0.1 µF
0.1 µF
50 Ω
5 V
3.3 V
400 Ω
f = 28 Hz
78% Duty Cycle
Output Switchover Response Test Circuit
OUTPUT SWITCHOVER RESPONSE
NC
1
µF
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
Figure 2.
Figure 3.
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CL = 1 µF
CL = 0 µF
t - Time - 40 µs/div
VI(DO)
VI(D1)
VO(OUT)
2V/Div
2V/Div
2V/Div
Output Switchover Voltage Droop Test Circuit
OUTPUT SWITCHOVER VOLTAGE DROOP
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115PW 0.1 µF
0.1 µF
50 Ω
400 Ω
f = 580 Hz
90% Duty Cycle
5 V
NC
0 µF
CL
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Figure 4.
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0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.1 1 10 100
RL = 10 Ω
RL = 50 Ω
VI = 5 V
- Output Voltage Droop - V
CL - Load Capacitance - µF
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115PW 0.1 µF
0.1 µF
VI
400 Ω
0.1 µF 1 µF10 µF 47 µF100 µF50 Ω10 Ω
f = 28 Hz
50% Duty Cycle
Output Switchover Voltage Droop Test Circuit
O(OUT)
∆V
NC
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Figure 5.
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0
50
100
150
200
250
300
0 20 40 60 80 100
VI = 5 V
VI = 3.3 V
Inrush Current - mA
CL - Load Capacitance - µF
INRUSH CURRENT
vs
LOAD CAPACITANCE
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115PW 0.1 µF
0.1 µF
VI
400 Ω
0.1 µF47 µF10 µF
50 Ω
To Oscilloscope
1 µF100 µF
f = 28 Hz
90% Duty Cycle
Output Capacitor Inrush Current Test Circuit
II-
NC
NC
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Figure 6.
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−50 0 50 100 150
TJ − Junction Temperature − °C
60
80
100
120
140
160
180
TPS2114
TPS2115
− Switch On-Resistance − mΩ
rDS(on)
2 3 4 5 6
VI(INx) − Supply Voltage − V
80
85
90
95
100
105
110
115
120
TPS2114
TPS2115
− Switch On-Resistance − mΩ
rDS(on)
40
42
44
46
48
50
52
54
56
58
60
2 3 4 5 6
VI(IN1) − Supply Voltage − V
I(IN1)− IN1 Supply Current − Aµ
IN1 Switch is ON
VI(IN2) = 0 V,
IO(OUT) = 0 A
I
0.82
0.84
0.86
0.88
0.90
0.92
0.94
0.96
23456
I(IN1) Aµ
VI(IN1)− IN1 Supply Voltage − V
Device Disabled
VI(IN2) = 0 V
IO(OUT) = 0 A
I− IN1 Supply Current −
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
SWITCH ON-RESISTANCE SWITCH ON-RESISTANCEvs vsJUNCTION TEMPERATURE SUPPLY VOLTAGE
Figure 7. Figure 8.
IN1 SUPPLY CURRENT IN1 SUPPLY CURRENTvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 9. Figure 10.
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0
10
20
30
40
50
60
70
80
−50 0 50 100 150
II(IN1)
II(IN2)
TJ − Junction Temperature − °C
IN1 Switch is ON
VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V
IO(OUT) = 0 A
I(INx) Supply Current − − Aµ
I
0
0.2
0.4
0.6
0.8
1
1.2
−50 0 50 100 150
II(IN1) = 5.5 V
II(IN2) = 3.3 V
Device Disabled
TJ − Junction Temperature − °C
I(INx) Supply Current − − Aµ
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
I
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT SUPPLY CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 11. Figure 12.
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APPLICATION INFORMATION
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115PW 0.1 µF
C2
0.1 µF
CLRL
IN1: 2.8 - 5.5 V
IN2: 2.8 - 5.5 V
RILIM
NC
Switch Status
R1
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115PW 0.1 µF
0.1 µF
CLRL
IN1: 2.8 - 5.5 V
IN2: 2.8 - 5.5 V
RILIM
Switch Status
R1
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
The circuit in Figure 13 allows one or two battery packs to power a system. Two battery packs allow a longer runtime. The TPS2114/5 cycles between the battery packs until both packs are drained.
Figure 13. Running a System From Two Battery Packs
In Figure 14 , the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connectsto IN1 if D1 is logic 1, otherwise OUT connects to IN2. The logic thresholds for the D1 terminal are compatiblewith both TTL and CMOS logic.
Figure 14. Manually Switching Power Sources
15
www.ti.com
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
MANUAL SWITCHING MODE
N-CHANNEL MOSFETs
CROSS-CONDUCTION BLOCKING
REVERSE-CONDUCTION BLOCKING
CHARGE PUMP
CURRENT LIMITING
OUTPUT VOLTAGE SLEW-RATE CONTROL
TPS2114
TPS2115
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to thehigher of IN1 and IN2.
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic1, otherwise OUT connects to IN2.
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logicselects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes sooutput-to-input current cannot flow when the FET is off. An integrated comparator prevents turnon of a FETswitch if the output voltage is greater than the input voltage.
The switching circuitry ensures that both power switches never conduct at the same time. A comparator monitorsthe gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage ofthe other FET is below the turnon threshold voltage.
When the TPS211x switches from a higher-voltage supply to a lower-voltage supply, current can potentially flowback from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211xdoes not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage.Once a supply has been connected to the output, it remains connected regardless of output voltage.
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to thecurrent limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
A resistor R
(ILIM)
from ILIM to GND sets the current limit to 250/ R
(ILIM)
and 500/R
(ILIM)
for the TPS2114 andTPS2115, respectively. Setting resistor R
(ILIM)
equal to zero is not recommended as that disables current limiting.
The TPS2114/5 slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state(see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents canadversely effect the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—likepit the connector power contacts, when hot plugging a load like a PCI card. The TPS2114/5 slews the outputvoltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the outputvoltage droop and reduces the output voltage hold-up capacitance requirement.
16
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2114PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2114PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2115PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2115PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2115PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2115PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2115PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2115PWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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