Fa a a Ek ee MOTOROLA SC {LOGIC} D2 DEP b3u7a52 oosoz0L 3 Af , MOTOROLA T-lbb-O1se ms SEMICONDUCTOR soa TECHNICAL DATA MC54/74HC138 1-of-8 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS J SUFFIX ij M i CERAMIC The MC54/74HC138 is identical in pinout to the L$138. The device inputs.are 16 Y CASE 620-69 compatible with standard CMOS outputs; with pullup resistors, they are compatible ' with LSTTL outputs. : N SUFFIX The HC138 decodes a three-bit Address to one-of-eight active-low outputs. This PLASTIC device features three Chip Select inputs, two active-low and one active-high to fa- CASE 648-06 cilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplex- 16 ing function is accomplished by using the Address inputs to select the desired 1 device output; one of the Chip Selects is used as a data input while the other Chip D SUFFIX Selects are held in their active states. Ds vr . soic @ Output Drive Capability: 10 LSTTL Loads i. Phd CASE 7518-03 @ Outputs Directly Interface to CMOS, NMOS, and TTL @ Operating Voltage Range: 2 to6 V @ Low Input Current: 1 pA . ORDERING INFORMATION @ High Noise immunity Characteristic of CMOS Devices - @ In Compliance with the Requirements Defined by JEDEC Standard No. 7A ~ MC74HCXXXN Plastic @ Chip Complexity: 116 FETs or 29 Equivalent Gates MCB4HCXXXS Ceramic MC74HCXXXD soic TA= 65 to 125C for all packages. Dimensions in Chapter 7. LOGIC DIAGRAM ao ! 18 vo - PIN ASSIGNMENT nous. Al 2 4 ov / Ao fie Voc Al YO ag 34 b 13 y 4 2 A2q Yi p Y3 Active-Low cs2 g y2 " Outputs p Y4 cs3 3 b!9. v5 cst g Y4 9 \ Y7 q Y5 7 GND Y6 b 7 6 | FUNCTION TABLE csi Chip- 4 , Select cS2. _______ Inputs Outputs Inputs css 2 CS1 CS2 cs3lA2 A1 Adl Yo Y1 Y2 Y3 Y4 Y5 Y6 Y7 xX X H|X X X/H HHHHHHH Pin 16=Vcc X H X]X X X}H HH HHHHH Pin 8 =GND tL XxX xX{X X X}H HHHHHHH H L LIL L LIL HHHHHHR H L LIL LH/HLHHHHHH H L LIL HLJHHLHHHHH HL Lit HH{HHHLHHHH H L LIHLLHHHHLAHH H L LHL H}HHHHHLHH H tL LH HL]IHHHHHHLH Hot LIHRHIH HHH HHH L H=high level (steady state} L= low level (steady state) X= dont care MOTOROLA HIGH-SPEED CMOS LOGIC DATA 5-142eas MOTOROLA SC {LOGIC} O82 a | bab?2Se OO80207 s He 80207 OD _ MC54/74HC138 V-lblo-a\ -55 MAXIMUM RATINGS* Symbol Parameter Value Unit This device contains protection Vec | DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V circuitry to guard against damage due to high static voltages or electric Vin DC Input Voltage (Referenced to GND) 1.6 to Vec+1.5 v fields. However, precautions must Vout | DC Output Voltage (Referenced to GND) 0.5 to Vcc +0.5 v be taken to avoid applications of any lin DC Input Current, per Pin +20 mA voltage higher than maximum rated - voltages to this high-impedance fout__] PC Output Current, per Pin - 25 mA circuit. For proper operation, Vin and Icc__ | DC Supply Current, Voc and GND Pins +50 mA Vout should be constrained to the Pp Power Dissipation in Still Air, Plastic or Ceramic DIPt 750 mw range GND <(Vin or Vout) s Vcc. SOIC Packaget 500 Unused inputs must always be tied _ to an appropriate logic voltage level |_Tstg | Storage Temperature 85 to +160 << {e.g., either GND or Voc). Unused TL Lead Temperature, 1.mm from Case for 10 Seconds Cc outputs must be left open. - {Plastic DIP or SOIC Package) 260 (Ceramic DIP) 300 *Maximum Ratings are those values beyond which damage to the device may occur, Functional operation should be restricted to the Recommended Operating Conditions. tDerating Plastic DIP: 10 mW/C from 65 to 126C Ceramic DIP: 10 mW/C from 100 to 125C SOIC Package: 7 mW/C from 65 to 125C For high frequency or heavy load considerations, sea Chapter 4. RECOMMENDED OPERATING CONDITIONS. Symbol! Parameter Min Max Unit Vcc _| DC Supply Voltage (Referanced to GND) 2.0 6.0 v Vin-Vout | DC Input Voltage, Output Voltage (Referenced to GND) 0 Vcc Vv Ta Operating Temperature, All Package Types 55 +125 c tr, tg | Input Rise and Fall Time Vec=2.0V 0 1000 ns (Figure 2) Vec=45V| 0 500 Vec=6.0V} 0 400 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Vv Guaranteed Limit Symbol Parameter Test Conditions cc Unit Y Vi | C to | asec | <tasc -55C ViH_ = | Minimum High-Level Input Vout=0.1 V or Vec-0.1 V 2.0 1.6 1.5 1.5 v Voltage llout]$20 pA 45 3.15 3.15 3.15 6.0 4.2 4.2 4.2 VIL Maximum Low-Level Input Vout=0.1 V or Vcc -0.1 V 2.0 0.3 0.3 - 0.3 Vv Voltage [lout] $20 pA 4.5 0.9 0.9 0.9 6.0 1.2 1.2 1.2 VoH | Minimum High-Level Output Vin=VIH or Vit 2.0 1.9 1.9 1.9 v Voltage Hout! $20 pA 4.5 4.4 44 4.4 . 6.0 5.9 . 5.9 5.9 Vin= Vir or VIL [out] 34.0 mA} 4.5 3.98 3.84 3.70 Hout] $5.2 mA| 6.0 5.48 5.34 5.20 VoL | Maximum Low-Level Output Vin = VIH or Vit 2.0 01 0.1 0.1 Vv Voltage lout] $20 nA 4.5 0.1 0.1 0.1 6.0 0.1 0.1 0.1 Vin=VIH or Vit [lout] 34.0 MA} 4.5 0.26 0.33 0.40 lloutls5.2 mA} 6.0 0.26 0.33 0.40 lin Maximum Input Leakage Current | Vinp=Vcc or GND 6.0 0.1 +1.0 +1.0 BA lec Maximum Quiescent Supply Vin=Vcc or GND 6.0 8 8 160 BA Current (per Package) lout=0 pA NOTE: Information on typical parametric values can be found in Chapter 4, MOTOROL LOGIC DATA HIGH-SPEED CMO 5-143E MOTOROLA SC {LOGIC} G2 ve b3b725e2 OO8o020a 7 J MC54/74HC138 T-ble-91-55 AC ELECTRICAL CHARACTERISTICS (C, =50 pF, Input t-=t=6 ns) V Guaranteed Limit cc . Symbol] Parameter v 25C to essec | <125C Unit -55C tpLH | Maximum Propagation Delay, Input A to Output Y 2.0 460 190 225 ns (Figures 1 and 4) 4.5 30 38 45 . : / 6.0 26 33 38 tPHL 2.0 200 250 300 45 40 50 60 6.0 34 43 51 tpLy. |Maximum Propagation Delay, CS1 to Output Y 2.0 150 190 225 ns tPHL (Figures 2 and 4) 45 30 38 45 6.0 26 33 38 tpLH | Maximum Propagation Delay, CS2 or CS3 to Output Y 2.0 150 190 225 ns (Figures 3 and 4) 4.5 30 38 45 . 6.0 26 33 38 tPHL 2.0 175 220 265 4.5 35 44 8 6.0 30 37 45 tri. | Maximum Output Transition Time, Any Output 2.0 75 95 110 ns tTHL (Figures 2 and 4) 4.5 15 19 22 - | 60 13 16 19 Cin Maximum Input Capacitance - - 10 10 10 pF NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 4. 2. Information on typical parametric values can be found in Chapter 4. Cpp | Power Dissipation Capacitance (Per Package) Typical @ 25C, Voc =5.0 V Used to determine the no-load dynamic power consumption: . Pp=Cpp Vec*t+Icc Voc 55 pF For load considerations, see Chapter 4. SWITCHING WAVEFORMS FIGURE 1 : FIGURE 2 Vec inputA Input CS1 GND tPLH Output Y 50% Output Y FIGURE 3 FIGURE 4 TEST CIRCUIT Test Point Input ; Output CS2, CS3 Unie nder c* Test Output Y | * Includes all probe and jig capacitance. MOTOROLA HIGH-SPEED CMOS LOGIC DATA 5-144i MC54/74HC138 MOTOROLA SC {LOGIC} Oe DEB b347252 o080c04% 4 i D T-lelo-Qi-s5 PIN DESCRIPTIONS ADDRESS INPUTS AO, A1, A2 (PINS 1, 2, 3) Address inputs. These inputs, when the chip is selected, determine which of the elght outputs is active- low. CONTROL INPUTS CS1, CS2, CS3 (PINS 6, 4, 5} Chip select inputs. For CS1 ata high level and CS2, CS3 at a low level, the chip is selected and the outputs follow the Address inputs. For any other combination of CS1, CS2, and CS3, the outputs are at a lagic high. OUTPUTS YO-Y7 (PINS 15, 14, 13, 12, 11, 10, 9, 7) Active-low Decoded outputs. These outputs assume a low lavel when addressed and the chip is selected. These outputs remain high when not addressed or the chip is not selected, EXPANDED LOGIC DIAGRAM AQ Al CS3 cs2 csi MOTOROLA HIGH-SPEED CMOS LOGIC DATA . ; 5-145