Si8499DB
www.vishay.com Vishay Siliconix
S15-0932-Rev. B, 20-Apr-15 1Document Number: 65906
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P-Channel 20 V (D-S) MOSFET
Marking Code: xxxx = 8499
xxx = Date / lot traceability code
Ordering Information:
Si8499DB-T2-E1 (Lead (Pb)-free and halogen-free)
FEATURES
• TrenchFET® power MOSFET
• Ultra-small 1.5 mm x 1 mm maximum outline
• Ultra-thin 0.59 mm maximum height
• Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
APPLICATIONS
• Low on-resistance load switch,
charger switch and battery switch
for portable devices
- Low power consumption
- Increased battery life
Notes
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. Refer to IPC/JEDEC® (J-STD-020), no manual or hand soldering.
d. Case is defined as the top surface of the package.
e. Based on TC = 25 °C.
f. Maximum under steady state conditions is 85 °C/W.
PRODUCT SUMMARY
VDS (V) RDS(on) ()I
D (A) eQg (TYP.)
-20
0.032 at VGS = -4.5 V -16
14.5 nC
0.046 at VGS = -2.5 V -14.3
0.065 at VGS = -2.0 V -12
0.120 at VGS = -1.8 V -2.5
MICRO FOOT® 1.5 x 1
Backside View
1
1 mm
1.5 mm
xxxx
xxx
Bump Side View
5
D
6
S
1
G
D
4
S
3
S
2S
G
D
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS -20 V
Gate-Source Voltage VGS ± 12
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
ID
-16
A
TC = 70 °C -13.7
TA = 25 °C -7.8 a, b
TA = 70 °C -6.3 a, b
Pulsed Drain Current IDM -20
Continuous Source-Drain Diode Current TC = 25 °C IS
-10.8
TA = 25 °C -2.3 a, b
Maximum Power Dissipation
TC = 25 °C
PD
13
W
TC = 70 °C 8.4
TA = 25 °C 2.77 a, b
TA = 70 °C 1.77 a, b
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150 °C
Package Reflow Conditions cIR/Convection 260
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYPICAL MAXIMUM UNIT
Maximum Junction-to-Ambient a, f RthJA 37 45 °C/W
Maximum Junction-to-Case (Drain) Steady State RthJC 79.5
Si8499DB
www.vishay.com Vishay Siliconix
S15-0932-Rev. B, 20-Apr-15 2Document Number: 65906
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0, ID = -250 μA -20 - - V
VDS Temperature Coefficient VDS/TJ ID = -250 μA --20-
mV/°C
VGS(th) Temperature Coefficient VGS(th)/TJ -2.2-
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = -250 μA -0.5 - -1.3 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 12 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = -20 V, VGS = 0 V - - -1 μA
VDS = -20 V, VGS = 0 V, TJ = 70 °C - - -10
On-State Drain Current a ID(on) V
DS -5 V, VGS = -4.5 V -5 - - A
Drain-Source On-State Resistance a RDS(on)
VGS = -4.5 V, ID = -1.5 A - 0.026 0.032
VGS = -2.5 V, ID = -1.5 A - 0.036 0.046
VGS = -2 V, ID = -1 A - 0.048 0.065
VGS = -1.8 V, ID = -0.5 A - 0.060 0.120
Forward Transconductance agfs VDS = -10 V, ID = -1.5 A - 10 - S
Dynamic b
Input Capacitance Ciss
VDS = -10 V, VGS = 0 V, f = 1 MHz
- 1300 -
pFOutput Capacitance Coss - 250 -
Reverse Transfer Capacitance Crss - 200 -
Total Gate Charge Qg
VDS = -10 V, VGS = -5 V, ID = -1.5 A - 20 30
nC
VDS = -10 V, VGS = -4.5 V, ID = -1.5 A
- 14.5 22
Gate-Source Charge Qgs -2-
Gate-Drain Charge Qgd -4.1-
Gate Resistance RgVGS = -0.1 V, f = 1 MHz - 7 -
Turn-On Delay Time td(on)
VDD = -10 V, RL = 6.7
ID -1.5 A, VGEN = -4.5 V, Rg = 1
-2040
ns
Rise Time tr-2550
Turn-Off Delay Time td(off) -50100
Fall Time tf-3060
Turn-On Delay Time td(on)
VDD = -10 V, RL = 6.7
ID -1.5 A, VGEN = -10 V, Rg = 1
-715
Rise Time tr-1020
Turn-Off Delay Time td(off) -55110
Fall Time tf-3060
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode
Current ISTC = 25 °C - - -10.8 A
Pulse Diode Forward Current ISM ---20
Body Diode Voltage VSD IS = -1.5 A, VGS = 0 - -0.8 -1.2 V
Body Diode Reverse Recovery Time trr
IF = -1.5 A, dI/dt = 100 A/μs, TJ = 25 °C
-4080ns
Body Diode Reverse Recovery Charge Qrr -2245nC
Reverse Recovery Fall Time ta-15-ns
Reverse Recovery Rise Time tb-25-
Si8499DB
www.vishay.com Vishay Siliconix
S15-0932-Rev. B, 20-Apr-15 3Document Number: 65906
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
5
10
15
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VGS =5Vthru2.5V
VGS =1.5V
VGS =2V
VGS =1V
VDS- Drain-to-Source Voltage (V)
- Drain Current (A)ID
0.00
0.05
0.10
0.15
0.20
0 5 10 15 20
VGS =2V
VGS =4.5V
VGS =1.8V
VGS =2.5V
- On-Resistance (Ω)R DS(on)
ID- Drain Current (A)
0
2
4
6
8
10
0 5 10 15 20 25 30
ID=1.5A
VDS=10V
VDS=5V
VDS=16V
- Gate-to-Source Voltage (V)
Qg- Total Gate Charge (nC)
VGS
0
1
2
3
4
5
0.0 0.5 1.0 1.5 2.0
TC= 25 °C
TC= 125 °C
TC= - 55 °C
VGS -Gate-to-Source Voltage (V)
- Drain Current (A)ID
Crss
0
400
800
1200
1600
2000
048121620
Ciss
Coss
VDS- Drain-to-Source Voltage (V)
C - Capacitance (pF)
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
- 50 - 25 0 25 50 75 100 125 150
VGS =1.8V;I
D=0.5A
VGS =2V;
VGS =4.5V;I
D=1A
TJ- Junction Temperature (°C)
(Normalized)
- On-ResistanceRDS(on)
ID=1A
Si8499DB
www.vishay.com Vishay Siliconix
S15-0932-Rev. B, 20-Apr-15 4Document Number: 65906
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
Threshold Voltage
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
Safe Operating Area, Junction-to-Ambient
0.1
1
10
100
0.0 0.2 0.4 0.6 0.8 1.0 1.2
TJ= 25 °C
TJ= 150 °C
VSD-Source-to-Drain Voltage (V)
- Source Current (A)I S
0.4
0.5
0.6
0.7
0.8
0.9
1.0
- 50 - 25 0 25 50 75 100 125 150
ID= 250 μA
(V)VGS(th)
TJ- Temperature (°C)
0.00
0.02
0.04
0.06
0.08
0.10
0.12
012345
TJ= 25 °C
ID=- 1.5A
TJ= 125 °C
- On-Resistance (Ω)RDS(on)
VGS -Gate-to-Source Voltage (V)
0
5
10
15
20
25
30
Power (W)
Pulse (s)
10 10000.10.010.001 1001
100
1
0.1 1 10 100
0.01
10
0.1 TA= 25 °C
Single Pulse
Limited by RDS(on)*
BVDSS Limited
1ms
100 μs
10 ms
1s,10s
100 ms
VDS- Drain-to-Source Voltage (V)
*V
GS > minimum VGS at which RDS(on) isspecied
- Drain Current (A)
ID
DC
Si8499DB
www.vishay.com Vishay Siliconix
S15-0932-Rev. B, 20-Apr-15 5Document Number: 65906
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Current Derating* Power Derating
* The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in
settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when
this rating falls below the package limit.
0
4
8
12
16
20
0 25 50 75 100 125 150
Package Limited
TC-Case Temperature (°C)
ID- Drain Current (A)
0
3
6
9
12
15
25 50 75 100 125 150
TC - Case Temperature (°C)
Power Dissipation (W)
Si8499DB
www.vishay.com Vishay Siliconix
S15-0932-Rev. B, 20-Apr-15 6Document Number: 65906
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65906.
10-3 10-2 000101110-1
10-4 100
0.2
0.1
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
t1
t2
Notes:
PDM
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 85 °C/W
3. TJM - TA = PDMZthJA(t)
t1
t2
4. Surface Mounted
Duty Cycle = 0.5
Single Pulse
0.02
0.05
10-3 10-2 10-1
10-4
1
0.1
0.2
0.1
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
0.02
0.05
Single Pulse
Package Information
www.vishay.com Vishay Siliconix
Revison: 20-Apr-15 1Document Number: 69426
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
MICRO FOOT®: 6-Bump
(1.5 mm x 1 mm, 0.5 mm Pitch, 0.250 mm Bump Height)
Notes
(unless otherwise specified)
1. Six (6) solder bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ti/Ni/Ag layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
6. • is the location of pin 1
Note
• Use millimeters as the primary measurement.
DIM. MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.510 0.575 0.590 0.0201 0.0226 0.0232
A10.220 0.250 0.280 0.0087 0.0098 0.0110
A20.290 0.300 0.310 0.0114 0.0118 0.0122
b 0.297 0.330 0.363 0.0116 0.0129 0.0143
b1 0.250 0.0098
e 0.500 0.0197
s 0.210 0.230 0.250 0.0082 0.0090 0.0098
D 0.920 0.960 1.000 0.0362 0.0378 0.0394
E 1.420 1.460 1.500 0.0559 0.0575 0.0591
K 0.028 0.065 0.102 0.0011 0.0025 0.0040
ECN: T15-0140-Rev. A, 20-Apr-15
DWG: 6035
D
es
A
A1 A2
s
E
e s
s
XXXX
XXX
Mark on Backside of Die e
e
ee
D
D
S
G
S
S
NOTE 5
ABC
Recommended Land Pattern
6x Ø b1
Bump (Note 2)
K
b
6x Ø 0.24 to 0.26 (Note 3)
Solder mask ~ Ø 0.25
Legal Disclaimer Notice
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Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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