XRT71D03IV-F - EXAR - Datasheet.Directory

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www . exa r .c om

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XRT71D03

3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

SEPTEMBER 2001 REV. 1.2.0

GENERAL DESCRIPTION

The XRT71D03 is a three channel, single chip Jitter

Attenuator, that meets the Jitter transfer characteris-

tics requirements specified in the ETSI TBR-24,

Bellco re GR-4 99 and GR -2 53 stan dards.

In addition, the XRT71D03 also meets the Jitter and

Wander specifications described in the ANSI

T1.105.03b 1997, Bellcore GR-253 and GR-499 stan-

dards.

FEATURES

•Meets the E3/DS3/STS-1 jitter requirements

•No external components required

•Compliant with jitter transfer template outlined in

ITU G.751, G.752, G.755, GR-235-CORE, GR-

499-CORE,1995 sta ndards

•Meets output ji tter requ irem ent as specifi ed by

ETSI TBR24

•Meets the Jitter and Wander specifications

described in T1.105.03b,GR-253 and GR-499 stan-

dards.

•Selectable buffer size of 16 and 32 bits

•Jitter attenuator can be disabled

•Available in a 64 pin LQFP package .

•Single 3.3V or 5.0V supply.

•Operates over - 40° C to 85° C temperature range.

APPLICATIONS

•E3/DS3 Access Equipment.

•DSLAMs

FIGURE 1. BLOCK DIAGRAM OF THE XRT71D03

Timing Control Block

Phase locked Loop

RRCLK_n

RRPOS_n

RRNEG_n

FL_n

DJA_n

RClk_n

RClkES

RPOS_n

RNEG_n

FSS

ICT

MCLK_n

STS1_n

DS3/E3_n

Microprocessor Serial

Interface

CS SDI SDO SClk

HOST

Reset

Channel 0

Channel 1

Channel 2

XRT71D03

n = 0, 1, 2

MODE_CTRL

Read ClockWrite Clock

16/32 Bit FIFO

RRCLKES

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

FIGURE 2. PIN OUT OF THE XRT71 D03

XRT71D03

AVDD

GND

RRCLK_0

RRPOS_0

RRNEG_0

RRCLKES

Reset

DS3/E3_1

VDD

MODE_CTRL

ICT

HOST

FLRST

GND

AGND

FL_2

STS1_2

DJA_2/CS

MCLK_2

GND

RCLK_2

VDD

RNEG_2

RPOS_2

GND

DJA_0/SCLK

DS3/E3_0

STS1_0

FL0

AGND

AVDD

GND

RRCLK_1

RRPOS_1

RRNEG_1

RCLKES

VDD

DS3/E3_2

SDO

FSS

RRNEG_2

RRPOS_2

RRCLK_2

GND

AVDD

AGND

FL1

STS1_1

MCLK_1

GND

RCLK_1

RPOS_1

RNEG_1

VDD

RNEG_0

RPOS_0

RCLK_0

GND

MCLK_0

DJA_1/SDI

AGND

OR DERING INFORMATION

PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE

XRT71D03IV 64 Pin TQFP -40°C to +85°C

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................. 1

FEATURES ............................................................................................................................................... .... 1

APPLICATIONS ............................................................................................................................................. 1

Figure 1. Block Diagram of the XRT71D03 ........................................................................................... 1

Figure 2. Pin Out of the XRT71D03 ........................................................................................................ 2

ORDERING INFORMATION ................................................................................................................. .... 2

TABLE OF CONTENTS........... ....... ...... ....... ................... ....... ...... ...... ....... ...... ....... ................... ....... ...... ............. I

PIN DESCRIPTIONS ........................................................................................................... 3

ELECTRICAL CHARACTERISTICS ................................................................................... 9

Figure 3. Input/Output Timing ............................................................................................................ .... 9

Figure 4. Timing Diagram for the Microprocessor Serial Interface .................................................. 10

SYSTEM DESCRIPTION ................................................................................................... 12

Figure 5. Illustration of a typical Channel_n of the XRT71D03 configured to operate in the Hardware

Mode ........................................................................................................................................ 12

Figure 6. Illustration of a typical Channel_n of the XRT71D03 (configured to operate in the Host

Mode) ....................................................................................................................................... 13

1.0 Jitter Attenuator PLL .............................................................................................................................. 13

1.1 BACKGROUND INFORMATION DEFINITION OF JITTER ....................................................................................................13

1.2 JITTER TRANSFER CHARACTERISTICS.........................................................................................................................13

Figure 7. Category 1 DS3 Jitter Transfer Mask .................................................................................. 14

1.2.1 Jitter Tolerance .............................................................................................................................................14

1.2.2 Jitter Generation............................................................................................................................................14

1.2.3 Jitter Attenuation ...........................................................................................................................................14

1.3 XRT71D03 JITTER TRANSFER AND TOLERANCE.........................................................................................................15

ABLE

1: XRT71D03 J

ITTER

RANSFER

UNCTION

.................................................................................. 15

Figure 8. DS3 Jitter Transfer Characteristics ..................................................................................... 16

Figure 9. E3 Jitter Transfer Characteristics ........................................................................................ 16

Figure 10. STS-1 Jitter Transfer Characteristics ................................................................................ 17

ABLE

2: XRT71D03 M

AXIMUM

ITTER

OLERANCE

................................................................................. 18

2.0 Operating Modes .................................................................................................................................... 19

2.1 HARDWARE MODE.....................................................................................................................................................19

ABLE

3: F

UNCTIONS

DUAL

MODE

PINS

ARDWARE

ODE

CONFIGURATION

...................................... 19

2.2 HOST MODE.............................................................................................................................................................19

ABLE

4: A

DDRESS

AND

ORMATS

THE

OMMAND

EGISTERS

...................................................... 19

3.0 Microprocessor Serial Interface ............................................................................................................ 19

3.1 SERIAL INTERFACE OPERATION..................................................................................................................................19

3.1.1 Bit 1—R/W (Read/Wri te) Bit................. ................. ...... ..... ...... ..... ................. ...... ..... ...... ..... . ................ ...... ....19

3.1.2 Bits 2 through 5—A0, A1, A2, A3, and A4 ....................................................................................................19

3.1.3 Bit 7—A5.......................................................................................................................................................19

3.1.4 Bit 8—A6.......................................................................................................................................................19

3.1.5 Read Operation.............................................................................................................................................19

3.1.6 Write Operation.............................................................................................................................................20

Figure 11. Microprocessor Serial Interface Data Structure .. ....... ...... ....... ................... ....... ...... ....... .. 20

3.1.7 Simplified Interface Option............................................................................................................................20

Figure 12. Timing Diagram for the Microprocessor Serial Interface ................................................ 21

ORDERING INFORMATION ............................................................................................. 22

PACKAGE DIMENSIONS ........... ..... ..... .............. .... ..... ..... .............. .... ..... ..... .............. .... .. 22

REVISION HISTORY ..................................................................................................................................... 23

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

PIN DESCRIPTIONS

PIN DESCRIPTION

PIN #N

AME TYPE DESCRIPTION

1AVDD **** Analog Power Supply = 5V±5% or 3.3V±5%

2GND **** Digital Power Supply = 5V±5% or 3.3V±5%

3RRCLK_0 O Received Recovered Output (De-jittered) Cloc k - channel 0:

Output the de-jittered or smoothed clock if the jitter attenuator is enabled. The

de-jittered data, RRPOS/RRNEG are clocked to this signal.

If RRCLKES is “low”, RRPOS/RRNEG will be updated at the falling edge of

RRCLK.

If RRCLKES is “high”, RRPOS/RRNEG will be updated at the rising edge of

RRCLK.

4RRPOS_0 O Received Recovered Positive Data (De-Jittered) Output - channel

De-jittered positive data output. Updated on the rising or falling edge of

RRCLK, depending upon the state of the RRCLKES input pin (or bit-field set-

ting).

5RRNEG_0 O Re ceived Recovered Negative Data (De-Ji ttered) Outp ut - ch annel

De-jittered negative data output. Updated on the rising or falling edge of

RRCLK, depending upon the state of the RRCLKES input pin (or bit-field set-

ting).

6RRCLKES I Received Recovered Clock Edge Select Input:

Hardware Mode:

1. When RRCLKES = “0”, then RRPOS and RRNEG are updated on the fall-

ing edge of RRCLK

2. When RRCLKES = “1”, then RRPOS and RRNEG are updated on the rising

edge of RRCLK

OTE

: This applies to all channels.

Host Mode

Connect this pin to GND when the 71D03 is configured in the Host Mode.

Internal 50 K Ohm pull-down resistor.

7NC No Connection

8Rest IReset Input. (Active-Low):

A high-low transition will re-center the internal FIFO, and will clear the Com-

mand R e gis te r s (for Host M od e operation). Re setting this pin may corrupt data

within the d evice.

For normal operation, pull this pin to VDD.

Internal 50 K Ohm pull-up resistor.

9DS3/E3_1 I DS3/E3 Select Input - channel 1:

This pin along with the STS-1 mode select pin se lects t he operat ing mode . The

following table provides the configuration:

STS-1 DS3/E3 XRT71D04 Operating Mode

0 0 DS3 (44.736 MHz)

0 1 E3 (34.368 MHz)

1 0 STS-1 (51.84 MHz)

1 1 E3 (34.368 MHz)

Internal 50 K Ohm pull-down resistor.

10 VDD **** Digital Power Supply = 5V±5% or 3.3V±5%

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

11 MODE_CTRL I Mode Control:

When “High” in Multimode, all channels are independent. When “Low”, the

Master Channel (channel0) controls DS3/E3_n, STS1_n, RCLKES, FSS and

MCLKn. DJA is NOT affected.

Internal 50 K Ohm pull-up resistor.

12 ICT IIn Circuit Testing Input. (Active low):

With this pin tied to ground, all output pins will be in high impedance mode for

in-circuit-testing.

For normal operation this input pin should be tied to VDD.

Internal 50 K Ohm pull-up resistor.

13 HOST I Host/Hardware Mode Select:

An active-high input enables the Host mode. Data is written to the command

registers to configure the XRT71D04.

In the Host mode, the states of discrete input pins are inactive.

An active-low input enables the Hardware Mode.In this mode, the discrete

inputs are active.

Internal 50 K Ohm pull-down resistor.

14 FLRST I Fifo Limit Reset

Hardware Mode

Whene ver the FIFO is w ithin 2 bi ts of either un derflo w or overflow, the FLn) will

be set high.

This pin allows the user to reset the state of FL_n, (FIFO Limit) output pin.

This pin when pulsed “High”, resets the the FL_n output pin, (toggles to GND).

OTE

: The FL_n could be set “High” again if the FIFO is within 2 bits of either

underflow or overflow.

Host Mode

Reading the FL_n bits in the status registers clears the FL_n pin. Master

RESET also clears the FL_n output.

This pin is tied to GND. FLRST has no effect in this mode.

Internal 50 K Ohm pull-down resistor.

15 GND **** Digital Ground

16 NC No Connection

17 AGND **** Analog Ground

18 FL_0 O FIFO Limit - channel 0:

This outp ut pin is driv en hig h whene v er the inte rnal FIFO comes wit hin tw o-bits

of being underflow or overflow.

19 STS1_0 I SONET STS1 Mode Select - channel 0:

This pin along wi th the DS3/E3_ 0 select p in configu res the XR T 71D03 ei ther in

E3, DS3 or STS-1 mode.

A table relating to the setting of the pins is given below:

STS-1 DS3/E3 XRT71D03 Operating Mode

0 0 DS3 (44.736 MHz)

0 1 E3 (34.368 MHz)

1 0 STS-1 (51.84 MHz)

1 1 E3 (34.368 MHz)

This input pin is active only in the Hardware Mode

PIN DESCRIPTION

PIN #N

AME TYPE DESCRIPTION

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

20 DS3/E3_0 I DS3/E3 Select Input - channel 0:

See description pin 8.

Internal 50 K Ohm pull-down resistor.

21 DJA_0/SCLK I Hardware Mode

Disable Jitter Attenuator Input - Channel 0:

An active-high disables the Jitter Attenuator. The RPOS/RNEG and RCLK will

be passed through without jitter attenuation.

Host Mode

Microprocessor Serial Interface Clock Signal:

This signal will be used to sample the data on the SDI pin, on the rising edge

of this s ignal. Additio nally, during “Re ad” oper atio ns , the Mi cropro cessor Serial

Interface will update the SDO output on the falling edge of this signal.

Internal 50 K Ohm pull-down resistor.

22 GND **** Digital Ground

23 RPOS_2 I Received Positive Data (Jittery) Input: - channel 2:

Data that is input on this pin is sampled on either the rising or falling edge of

RCLK depending on the setting of the RCLKES pin (pin 10).

If RCLKES is “high”, then RPOS will be sampled on the falling edge of RCLK.

If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.

Internal 50 K Ohm pull-up resistor.

24 RNEG_2 I Received Negative Data (Jittery) - channel 2:

The input jittery negative data is sampled either on the rising or falling edge of

RCLK depending on the setting of RCLKES.

If RCLKES is “high”, then RNEG will be sampled on the f alling edge of RCLK.

If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.

This pin is typically tied to the “RNEG” output pin of the LIU.

Internal 50 K Ohm pull-up resistor.

25 VDD **** Digital Power Supply = 5V±5% or 3.3V±5%

26 RCLK_2 I Received Clock (Ji ttery) - channel 2:

Clock input RCLK2 should be connected to the recovered clock.

Internal 50 K Ohm pull-up resistor.

27 GND **** Digital Ground

28 MCLK_2 I Master Clock Input - channel 2:

Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/-

20ppm. This clock must be continuous and jitter free with duty cycle between

30 to 70%.

It is permissible to use the EXCLK signal orSTS1 clock.

Internal 50 K Ohm pull-up resistor.

29 DJA_2/CS IHardware Mode

Disable Jitter Attenuator Input - Channel 2:

See description of pin 25

Host Mode

Chip Select Input:

An active-low input enables the serial interface.

Internal 50 K Ohm pull-down resistor.

30 STS1_2 I SONET STS1 Mode Select - channel 2:

See description pin 19

PIN DESCRIPTION

PIN #N

AME TYPE DESCRIPTION

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

31 FL_2 O FIFO Limit - channel 2:

See description pin 18

32 AGND **** Analog Ground

33 AVDD **** Analog Power Supply =5±5% or 3.3V±5%

34 GND **** Digital Ground

35 RRCLK_2 O Received Recovered Output (De-jittered) Cloc k - channel 2:

See description of pin 3

36 RRPOS_2 O Received Recovered Positive Data (De-Jittered) Output - channel

See description of pin 4

37 RRNEG_2 O Re ceived Recovered Negative Data (De-Ji ttered) Outp ut - ch annel

See description of pin 5

38 FSS I FIFO Size Select Input:

When “High”: Selects 32 bits FIFO.

When “Low”: Selects 16 bits FIFO.

Internal 50 K Ohm pull-down resistor.

39 SDO O Serial Data Output:

This pin will serially output the contents of the specified Command Register,

during “Read” Operations. The data, on this pin, will be updated on the falling

edge of the SCLK input signal. This pin will be tri-stated upon completion of

data tr ansfer.

40 DS3/E3_2 I DS3/E3 Select Input - channel 2:

See description pin 8

Internal 50 K Ohm pull-down resistor.

41 VDD **** Digital Power Supply = 5V±5% or 3.3V±5%

42 NC No Connection

43 RCLKES I Received Clock Edge Select Input:

Hardware Mode

1. When RCLKES = “0”, then RPOS and RNEG are updated on the falling

edge of RCLK

2. When RCLKES = “1”, then RPOS and RNEG are updated on the rising

edge of RCLK

OTE

: This applies to all channels.

Host Mode

Connect this pin to GND when the 71D03 is configured in the Host Mode.

Internal 50 K Ohm pull-down resistor.

44 RRNEG_1 O Re ceived Recovered Negative Data (De-Ji ttered) Outp ut - ch annel

See description of pin 5

45 RRPOS_1 O Received Recovered Positive Data (De-Jittered) Output - channel

See description of pin 4

PIN DESCRIPTION

PIN #N

AME TYPE DESCRIPTION

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

46 RRCLK_1 O Received Recovered Output (De-jittered) Cloc k - channel 1:

See description of pin 3.

47 GND **** Digital Ground

48 AVDD **** Analog Power Supply = 5 V±5% or 3.3V±5%

49 AGND **** Analog Ground

50 FL_1 O FIFO Limit - channel 1:

See description pin 18

51 STS1_1 I SONET STS1 Mode Select - channel 1:

See description pin 19

52 MCLK_1 I Master Clock Input - channel 1:

See description pin 28.

Internal 50 K Ohm pull-up resistor.

53 GND **** Digital Ground

54 RCLK_1 I Received Clock (Ji ttery) - channel 1:

See description of pin 26.

Internal 50 K Ohm pull-up resistor.

55 RPOS_1 I Received Positive Data (Jittery) Input: - channel 1:

See description of pin 23.

Internal 50 K Ohm pull-up resistor.

56 RNEG_1 I Received Negative Data (Jittery) - channel 1:

See description of pin 24.

Internal 50 K Ohm pull-up resistor.

57 VDD **** Digital Power Supply = 5V±5% or 3.3V±5%

58 RNEG_0 I Received Negative Data (Jittery) - channel 0:

See description of pin 24.

Internal 50 K Ohm pull-up resistor.

59 RPOS_0 I Received Positive Data (Jittery) Input: - channel 0:

See description of pin 23.

Internal 50 K Ohm pull-up resistor.

60 RCLK_0 I Received Clock (Ji ttery) - channel 0:

See description of pin 26.

Internal 50 K Ohm pull-up resistor.

61 GND **** Digital Ground

62 MCLK_0 I Master Clock Input - channel 0:

See description pin 28.

Internal 50 K Ohm pull-up resistor.

PIN DESCRIPTION

PIN #N

AME TYPE DESCRIPTION

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

63 DJA_1/SDI I Hardware Mode

Disable Jitter Attenuator Input - Channel 1:

See description of pin 25

Host Mode

Serial Data Input

The addre ss value (of the c om mand register s) or th e d ata value is eith er R ea d

or Written through this pin.

The input data will be sampled on the rising edge of the SCLK pin.

Internal 50 K Ohm pull-down resistor.

64 AGND **** Analog Ground

PIN DESCRIPTION

PIN #N

AME TYPE DESCRIPTION

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

ELECTR ICAL CHARACTERISTICS

AC Electrical Characteristics

Electrical Characteristics (TA = 25°C, VDD = 3.3 V t0 5.0 V± 5% unless otherwise specified)

SYMBOL PARAMETER MIN TYP MAX UNITS.

MClk Duty Cycle 30 50 70 %

MClk Frequency E3 + 20 ppm 34.36 8 MHz

MClk Frequency DS3 + 20 ppm 44.736 MHz

MClk Frequency STS-1 + 20 ppm 51.84 MHz

RClk Duty Cycle 30 50 70 %

RClk Rise Time 5ns

RClk Fall Time 5ns

tsu RPOS/RNEG to RClk rise time setup 3 2 ns

thRPOS/RNEG to RClk risi ng hold time 1 2 ns

tdRRPOS/RRNEG delay from RRClk rising 3 5 ns

teRRPOS/RRNEG delay from RRClk falling 3 5 ns

FIGURE 3. INPUT/OUTPUT TIMING

tsu

RCLK

RPOS/RNEG

RCLK

RPOS/RNEG

RCLK

RClkES = 0

RClkES = 1

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

Microprocessor Serial Interface Timing ( see Figure 4 )

Electrical Characteristics (TA = 25°C, VDD = 3.3 V t0 5.0 V± 5 % unless otherwise specified)

SYMBOL PARAMETER MIN TYP MAX UNITS.

t21 CS Low to Rising Edge of SClk Setup Time 50 ns

t22 SClk to CS Hold Time 20 ns

t23 SDI to Rising Edge of SClk Setup Time 50 ns

t24 SDI to Rising Edge of SClk Hold Time 50 ns

t25 SClk “Low” Time 240 ns

t26 SClk “High” Time 240 ns

t27 SClk Period 500 ns

t28 SClk to CSB Hold Time 50 ns

t29 CS “Inactive” Time 250 ns

t30 Falling Edge of SClk to SDO Valid Time 200 ns

t31 Falling Edge of SClk to SDO Invalid Time 100 ns

t32 Falling Edge of SClk, or rising edge of CS to High Z 100 ns

FIGURE 4. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE

SDI R/W A1

SClk

SDI

SDO D0 D1 D2 D7

t22

t21

t23 t24

t25 t26

t27 t28

t29

t30 t31 t32t33

Hi-Z

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

DC Electrical Characteristics (TA = 25 °C, VDD = 3.3 V ± 5% unless otherwise specified)

PARAMETER SYMBOL MIN TYP MAX UNITS

Power Supply Voltage VDD 3.135 3.3 3.465 V

Input High Voltage VIH 2.0 5.25 V

Input Low Voltage VIL -0.5 0.8 V

Output High Voltage @ IOH=-5mA VOH 2.4 V

Output Low Voltage @ IO L=5mA VOL 0.4 V

Supply Current (E3) @VDD = 3.465V Icc 75 85 mA

Supply Current (DS3) @VDD = 3.465V Icc 95 109 mA

Supply Current (STS-1) @VDD = 3.465V Icc 105 120

Input Leakage Current (except Input pins with Pull-up resistor). IL ± 10 µA

Input Capacitance CI 5.0 pF

Output Load Capacitance CL 25 pF

DC Electrical Characteristics (TA = 25 °C, VDD = 5.0 V ± 5% unless otherwise specified)

PARAMETER SYMBOL MIN TYP MAX UNITS

Power Supply Voltage VDD 4.75 5.0 5.25 V

Input High Voltage VIH 2.0 5.25 V

Input Low Voltage VIL -0.5 0.8 V

Output High Voltage @ IOH=-5mA VOH 2.4 V

Output Low Voltage @ IO L=5mA VOL 0.4 V

Supply Current (E3) @VDD = 5.25V Icc 120 136 mA

Supply Current (DS3) @VDD = 5.25V Icc 145 160 mA

Supply Current (STS-1) @VDD = 5.25V Icc 160 180

Input Leakage Current (except Input pins with Pull-up resistor). IL ± 10 µA

Input Capacitance CI 5.0 pF

Output Load Capacitance CL 25 pF

ABSOLUTE MAXIMUM RATINGS:

Supply Range -0.5 V to + 6.0 V

ESD Rating > 2000 V on all pins

Operating Temperature -400C to +850C

Storage Te mperature -65°C to + 150°C

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

SYSTEM DESCRIPTION

The XRT71D03 is an integrated 3-channel E3/DS3/

STS-1 jitter attenuator that attenuates the jitter from

the input clock and data. The jitter attenuation perfor-

mance meets the latest specifications such as Bellcore

GR-499 CORE,GR-253 CORE, ETSI TBR24,ITU-T

G.751,ITU-T G.752 and ITU-T G.755 standards.

In addition, the XRT71D03 also meets both the map-

ping and pointer adjustment jitter generation criteria

for both Category I and Category II interfaces as

specifi ed in Bel lc ore GR- 2 53.

The XRT71D03 also mee ts the DS3 wande r speci fi -

cation that apply to SONET and asynchronous inter-

faces as specified in the ANSI T1.105.03b 1997 stan-

dard.

Additionally, to support loop-timing applications, the

XRT71D03 can also be used to reduce and limit the

amount of jitter in the recovered line clock signal.

Figure 5 presents a simple block diagram of the

XRT71D03, when it is configured to operate in the

Hardware Mode and Figure 6 presents a simple b lock

diagram of the XRT71D03, when it is configured to

operate in the Host Mode.

FIGURE 5. ILLUSTRATION OF A TYPICAL CHANNEL_N OF THE XRT71D03 CONFIGURED TO OPERATE IN THE HARD-

WARE MODE

FSS

HOST

Rest

DS3/E3_n

16/32 Bit FIFO

Timing Control Block /

Phase locked Loop

Write Clock Read Clock RRCLK_n

RRPOS_n

RRNEG_n

FL_n

DJA_n

RClk_n

RCLKES

RPOS_n

RNEG_n

ICT

MCLK_n

Jittery

Clock Smoothed

Clock

RRCLKES

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

The XRT71D03 DS3/E3 Jitter Attenuator IC consists

of the following functional blocks:

•The Jitter-Attenuator PLL

•Timing Control Block

•The 2-Channel 16/32 Bit FIFO

•Serial Microprocessor Interface

1.0 JITTER ATTENUATOR PLL

1.1 BACKGROUND INFORMATION DEFINITION OF JIT-

TER

One of the most important and least understood mea-

sures of clock performance is jitter. The International

Telecommunication Union defines jitter as short term

variations of the significant instants of a digital signal

from their ideal positions in time. Jitter can occur due

to any of the following:

1) Imperfect timing recovery circuit in the system

2) Cross-talk noise

3) Inter-symbol interference/Signal Distortion

1.2 JITTER TRANSFER CHARACTERISTICS

The primary purpose of jitter transfer requirements is

to prevent performance degradations by limiting the

accumulation of jitter through the system such that it

does not exceed the network interface jitter require-

ments. Thus, it is more important that a system meet

the jitter transfer criteria for relatively high input jitter

amplitudes. The jitter transferred through the system

must be under the jitter mask f or any input jitter ampli-

tude within the range as shown in Figure 7

FIGURE 6. ILLUSTRATION OF A TYPICAL CHANNEL_N OF THE XRT71D03 (CONFIGURED TO OPERATE IN THE HOST

MODE)

HOST

Reset

16/32 Bit FIFO

Microprocessor Serial

Interface

Timing Control Block /

Phase locked Loop

Write Clock Read Clock RRCLK_n

RRPOS_n

RRNEG_n

FL_n

RCLK_n

RPOS_n

RNEG_n

ICT

CS SDI SDO SClk

MClk_n

Smoothed

Clock

Jittery

Clock

RRCLKES

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

1.2.1 Jitter Tol era nce

The jitter tolerance in the network element is defined

as the maximum amount of jitter in the incoming sig-

nal that it can receive in an error-free manner.

1.2.2 Jitte r Ge ne ra tio n

Jitter generation is defined in Section 7.3.3 of GR-

499-CORE. Jitter generation criteria exists for both

Category I and II interfaces, which consist of mapping

and pointer adjustment jitter generation.

Mapping jitter is the sum of the intrinsic payload map-

ping jitter and the jitter that is generated as a result of

the bit stuffing mechanisms used in all of the asyn-

chronous DSn mapping into STS SPE.

1.2.3 Jitter Attenuation

A digital Jitter Attenuation loop combined with the

FIFO provides Jitter attenuation. The Jitter Attenuator

requires no e xternal components except for the refer-

ence clock.

Data is clocked into the FIFO with the associated

clock signal (TClk or RClk) and clocked out of the

FIFO with the dejittered clock and data. When the

FIFO is within 2 bits of being completely full, the FIFO

Limit (FL) will be set.

In Figure 5 and Figure 6, this de-jittered clock is la-

beled Smoothed Clock. This Smoothed Clock is now

used to Read Out the Recov ered Data from the 16/32

bit FIFO. This Smoothed Clock will also be output to

the Terminal Equipment via the RRClk output pin.

Likewise, the Smoothed Recovered Data will output

to the Terminal Equipment via the RRPOS and

RRNEG output pins.

The XRT71D03 is designed to work as a companion

device with XRT73L03 (STS-1/DS3/E3) Line Inter-

fa ce Unit.

ETSI TBR24 specifies the maximum output jitter in

loop timing must be no more than 0.4UIpp when mea-

sured between 100Hz to 800KHzwith up to 1.5UI in-

put jitter at 100Hz. This means a jitter attenuator with

bandwidth less than 100Hz is required to be compli-

ant with the standard. ITU G.751 is another applica-

tion where low bandwidth jitter attenuator is needed

to smooth the gapped clock output in the de-multi-

plexer system.

FIGURE 7. CATEGORY 1 DS3 JITTER TRANSFER MASK

0.1

Jitter Gain

(dB)

Acceptable

Range

Frequency (Hz)

slope = -20 dB/decade

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

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1.3 XRT71D03 J ITTER TRANSFER AND TOLERANCE

Table 1 summarizes the results of jitter transf er char-

acteristics testing, performed on the XRT71D03.

Table 2 summarizes the results of jitter tolerance test-

ing, performed on the XRT71D03.

Graphs of the measured Jitter Transfer are shown in

Figure 8, Figure 9 and Figure 10.

TABLE 1: XRT71D03 JITTER TRANSFER FUNCTION

APPLICATION DS3 E3 STS-1

INPUT JITTER 1UIPP 10UIPP 1UIPP 10UIPP 1UIPP 10UIPP

FREQ. (HZ) Jitter Gain (dB) Jitter Gain (dB) Jitter Gain (dB)

10 -0.10 -0.30 -0.15 -0.22 0.22 0.53

20 -2.04 -2.24 -3.16 -3.24 -0.69 -1.09

30 -3.63 -4.33 -5.51 -5.93 -5.92 -3.01

40 -5.98 -6.16 -7.68 -7.99 -8.10 -4.74

50 -7.55 -7.82 -10.36 -9.61 -10.17 -6.33

60 -9.57 -9.17 -12.50 -11.27 -11.24 -7.64

80 -12.54 -11.28 -15.20 -13.59 -13.65 -9.98

100 -14.67 -13.36 -16.22 -15.51 -14.78 -11.92

125 -16.67 -14.91 -17.38 -17.07 -16.94 -13.75

150 -17.32 -16.78 -19.45 -18.75 -17.38 -15.23

200 -18.77 -18.96 -20.36 -21.11 -19.57 -17.41

300 -21.43 -21.81 -22.96 -24.46 -21.96 -21.69

500 -22.22 -26.09 -23.78 -28.84 -23.59 -25.47

>1000 -25.42 -33.44 -23.51 -35.77 -25.76 -32.99

2000 -26.27 -39.83

3000 -27.41 -41.95

5000 -26.15 -44.16

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FIGURE 8. DS3 JITTER TRANSFER CHARACTERISTICS

DS3 Jit t er Transfer

-40

-35

-30

-25

-20

-15

-10

-5

510 100 1,000

Fre quency (Hz )

Jitter Gain (dB)

1UIpp

10UIpp

Mask

FIGURE 9. E3 JITTER TRANSFER CHARACTERISTICS

E3 Jit t er Transfer

-40

-35

-30

-25

-20

-15

-10

-5

510 100 1,000

Fre quency (Hz )

Jitter Gain (dB)

1UIpp

10UIpp

Mask

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FIGURE 10. STS-1 JITTER TRANSFER CHARACTERISTICS

STS-1 Ji t t er Transf er

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

510 100 1,000 10,000

Fre quency (Hz )

Jitter Gain (dB)

1UIpp

10UIpp

Mask

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

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TABLE 2: XRT71D03 MAXIMUM JITTER TOLERANCE

APPLICATION DS3 E3 STS-1

FIFO SIZE 16 32 16 32 16 32

FREQ. (HZ) UI (PEAK TO PEAK)UI (

PEAK TO PEAK)UI (

PEAK TO PEAK)

10 34.313 >64 26.689 53.313 38.938 >64

20 21.439 43.188 18.564 37.438 22.689 44.813

30 18.314 36.813 16.689 33.938 18.939 37.688

40 16.939 34.313 16.064 32.688 17.439 34.938

50 16.314 33.188 15.689 32.063 16.814 33.563

60 16.064 32.563 15.564 31.689 16.439 32.813

80 15.689 31.814 15.314 31.314 16.064 32.063

100 15.439 31.439 15.314 31.189 15.814 31.814

125 15.439 31.314 15.189 31.064 15.689 31.564

150 15.314 31.189 15.189 31.064 15.689 31.439

200 15.314 31.064 15.189 30.939 15.564 31.314

300 15.189 30.939 15.064 30.939 15.564 31.189

500 15.189 30.939 15.064 30.939 15.564 31.189

>1000 15.0189 30.939 15.189 30.939 15.439 31.189

15.439 31.189

15.439 26.189

15.439 16.189

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

2.0 OPERATING MODES

2.1 HARDWARE MODE

The HOST pin is used to select the operating mode of

the XRT71D03. In Hardware mode (connect this pin

to ground), the seri al processor interface is disabled

and hard-wired pins are used to control configuration

and report status.

2.2 HOST MODE

In Host mode (connect the HOST pin to VDD), the se-

rial port interface pins are used to control configura-

tion and status report. In this mode, serial interface

pins, SDI, SDO,SCLK and CS are used.

A listing of these Command Registers, their Address-

es and their bit-formats are listed below in Table 4.

3.0 MICROPROCESSOR SERIAL INTERFACE

The serial interface for the XRT71D03 and the

XRT73L00 family of E3/DS3/STS-1 LIU’s are the

same, which makes it easy to configure both the

XRT71D03 and the LIU with a single CS, SDI, SDO

and SClk input and output pins.

3.1 SERIAL INTERFACE OPERATION.

Serial interface data structure and timings are provid-

ed in Figure 5 and 6 respectively.

The clock signal is provided to the SClk and the CS is

asserted for 50 ns prior to the first rising edge of the

SClk.

3.1.1 Bit 1—R/W (Read/Write) Bit

This bit will be clocked into the SDI input, on the first

rising edge of SClk (after CS has been asserted).

This bit indicates whether the current operation is a

Read or Write operation.

A “1” in this bit specifies a Read operation, a “0” in

this bit specifies a Write operation.

3.1.2 Bits 2 through 5—A0, A1, A2, A3, and A4

The five (5) bit Address Values (labeled A0, A1, A2,

A3, and A4).

The next fiv e rising edges of the SClk signal will clock

in the 5-bit address value for this particular Read (or

Write) operation. The address selects the Command

address bits to the SDI input pin is applied in ascend-

ing order with the LSB (least significant bit) first.

3.1.3 Bit 7—A5

A5 must be set to “0”, as shown in Figure 11.

3.1.4 Bit 8—A6

The value of A6 is a don’t care.

Once these first 8 bits hav e been written into the Seri-

al Interface, the subsequent action depends upon

whether the current operation is a Read or Write op-

eration.

3.1.5 Read Operation

Once the last address bit (A4) has been clocked into

the SDI input, the Read operation will proceed

through an idle period, lasting three SClk periods. On

TABLE 3: FUNCTIONS OF DUAL MODE PINS IN

HARDWARE MODE CONFIGURATION

PIN #P

IN NAME FUNCTION, WHILE IN THE

HARDWARE MODE

63 DJA_1/(SDI) DJA_1

21 DJA_0/SCLK DJA_0

29 DJA_2(CS)DJA_2

TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS

ADDR COMMAND

0X06 CR6 R/W *** *** STS-1_0 DS3/E3_0 DJA_0 RRClkES_0 RClkES_0 FSS_0

0x07 CR7 RO *** *** *** *** *** *** FL_0

0x0E CR14 R/W *** *** STS-1_1 DS3/E3_1 DJA_1 RRClkES_1 RClkES_1 FSS_1

0x0F CR15 RO *** *** *** *** *** *** FL_1

0x16 CR22 R/W *** *** STS-1_2 DS3/E3_2 DJA_2 RRClkES_2 RClkES_2 FSS_2

0x17 CR23 RO *** *** *** *** *** *** FL_2

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

the falling edge of SClk Cycle #8 (see Figure 11) the

serial data output signal (SDO) becomes active. At

this point the user can begin reading the data con-

tents of the addressed Command Register (at Ad-

dress [A4, A3, A2, A1, A0]) via the SDO output pin.

The Serial Interface will output this eight bit data word

(D0 through D7) in ascending order (with the LSB

first), on the falling edges of the SClk. The data (on

the SDO output pin) is stable for reading on the very

next rising edge of the SClk.

3.1.6 Write Operation

Once the last address bit (A4) has been clocked into

the SDI input, the Write operation will proceed

through an idle period, lasting three SClk periods. Pri-

or to the rising edge of SClk Cycle #9, the eight bit

data word is applied to SDI input. Data on SDI is

latched on the rising edge of SClk.

OTES

1. A5 is always “0”.

2. R/W = “1” for Read Operations

3. R/W = “0” for Write Operations

4. Denotes a “don’t care” value (shaded areas)

3.1.7 Simplified Interface Option

The user can simplify the design of the circuitry con-

necting to the Microprocessor Serial Interface by ty-

ing both the SDO and SDI pins together, and reading

data from and/or writing data to this combined signal.

This simplification is possible because on ly one of

FIGURE 11. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE

D0 D1 D2 D7D6D5D4D3

High Z

SDO

A0 D0R/W D1A60A4A3A2A1 D7D6D5D4D3D2

SDI

12345678910111213141516

SClk

High Z

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REV. 1.2.0

these signals are active at any given time. The inac-

tive signal will be tri-stated.

FIGURE 12. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE

SDI R/W A1

SClk

SDI

SDO D0 D1 D2 D7

t22

t21

t23 t24

t25 t26

t27 t28

t29

t30 t31 t32t33

Hi-Z

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

ORDERING INFORMATION

PACKA GE DIMENSIONS

PART #P

ACKAGE OPERATING TEMPERATURE RANGE

XRT71D03IV 64 Pin TQFP -40oC to +85oC

THERMAL INFORMATION Theta - JA = 38° C /W Theta JC = 7° C/W

SYMBOL MIN MAX MIN MAX

A 0.055 0.063 1.40 1.60

A1 0.002 0.006 0.05 0.15

A2 0.053 0.057 1.35 1.45

B 0.007 0.011 0.17 0.27

C 0.004 0.008 0.09 0.20

D 0.465 0.480 11.80 12.20

D1 0.390 0.398 9.90 10.10

e 0.0020 BSC 0.05 BSC

L 0.018 0.050 0.45 0.75

α0° 7° 0° 7°

aaa - 0.003 - 0.08

7° typ 7° typ

INCHES MILLIMETERS

64 Lead Thin Quad Flat Pack

(10 x 10 x 1.4 mm LQFP)

Note: Control Dimensions are the Millimeter Column

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XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

NOTICE

EXAR Corporation reserv es the right to make changes to the products contained in this pub lication in order

to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of

any circuits described herein, conveys no license under any patent or other right, and makes no represen-

tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for

illustration purposes and may vary depending upon a user’s specific application. While the information in

this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where

the failure or malfunction of the product can reasonably be e x pected to cause failure of the lif e support sys-

tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-

tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury

or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-

ration is adequately protected under the circumstances.

Datasheet September 2001.

Reproduction, in part or who le, without the prior written consent of EXAR Corporation is prohibited.

REVISION HISTORY

Rev. P1.0.1; Revised pull-up/pull-down resistors on various pins.

Rev. P1.0.2; Changed date and made minor edits to page 1.

Rev. P1.0.3; Corrected Pin List descriptions. Modified pin names to be consistent, ie MCLK0, RPOS0,

RNEG0, etc. changed to MCLK_0, RPOS_0, RNEG_0, etc. Changed VSS to GND. Changed figures to re-

flect pin name changes.

Rev. 1.1.0 Removed preliminary designation. Added electrical tables.

Rev. 1.1.1 Corrected Table 4 adding RRClkES_n as data D2, STS-1_n as D5, added D7. Corrected the

description of the section 3 Serial Microprocessor Interface. Moved figure 9 into Electrical Characteristics

Section. Moved Jitter Transfer/Tolerance tables into Jitter Attenuator Section 1. Edited electrical tables.

Rev. 1.1.2 Corrected ordering information from XRT71DO3 to 71D03IV.

Rev. 1.2.0 Removed all reference to STS-1 to DS3 desynchronizer.