SST32VF401-70-4C-L3K - Silicon Storage Technology, Inc.

S71196-00-000 6/01 541

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Advance Information

FEATURES:

• MPF + SRAM ComboMemory

– SST32VF201: 128K x16 Flash + 64K x16 SRAM

– SST32V F20 2 : 128K x16 Flash + 128K x16 SRAM

– SST32VF401: 256K x16 Flash + 64K x16 SRAM

– SST32V F40 2 : 256K x16 Flash + 128K x16 SRAM

•Single 2.7-3.6V Read and Write Operations

•Concurrent Operation

–Read from or write to SRAM while

Erase/Program Flash

•Superior Reliability

–Endurance: 100,000 Cycles (typical)

–Greater than 100 years Data Retention

•Low Power Consumption:

–Active Current: 15 mA (typical) for

Flash or SRAM Read

–Standby Current: 20 µA (typical)

•Flexible Erase Capability

–Uniform 2 KWord sectors

–Unif orm 32 KWord size blocks

•Fast Read Access Times:

–Flash: 70 ns

–SRAM: 70 ns

•Latched Address and Data for Flash

•Flash Fast Erase and Word-Program:

–Sector- E rase Time: 18 ms (typical)

–Block-Erase Time: 18 ms (typical)

–Chip-Erase Time: 70 ms (typical)

–Word-Program Time: 14 µs (typical)

–Chip Rewrite Time:

SST32VF201/202: 2 seconds (typical)

SST32VF401/402: 4 seconds (typical)

•Flash Automatic Erase and Program Timing

–Internal VPP Generation

•Flash End-of-Write Detection

–Toggle Bit

–Data# Polling

•CMOS I/O Compatibility

•JEDEC Standard Command Set

•Conforms to Flash pinout

•Package Available

–48-ball LFBGA (6mm x 8mm)

PRODUCT DESCRIPTION

The SST32VF20x/40x ComboMemory devices integrate a

128K x1 6 or 256K x16 CMOS flash memor y bank with a

64K x16 or 128K x16 CMOS SRAM memory bank in a

Multi- Chip Packag e (MCP), manufactured with SST’s pro-

prietary, high perf ormance SuperFlash technolog y.

Featuring high performance Word-Program, the flash

memory bank provides a maximum W ord-Program time of

14 µsec. The entire flash memory bank can be erased and

programmed word-by-word in typically 2 seconds for the

SST32VF201/202 and 4 seconds for the SST32VF401/

402 , when using interface features such as Toggle Bit or

Data# P olling to indicate the completion of Program opera-

tion. To protect against inadvertent flash write, the

SST32VF20x/40x devices contain on-chip hardware and

software data protection schemes.The SST32VF20x/40x

devices offer a guaranteed endurance of 10,000 cycles.

Data retention is rated at greater than 100 years.

The SS T 32 VF2 0x /4 0x devices consist of t wo in dependent

memory banks with respective bank enable signals. The

Flash and SRAM memory banks are superimposed in the

same memory addr ess sp ace. B oth mem or y bank s sha re

common address lines, data lines, WE# and OE#. The

memory bank selection is done by memory bank enable

signal s. The S RAM bank en able signa l, BES # se lects the

SRAM bank. The flash memory bank enable signal, BEF#

sele cts the fl as h mem ory bank . The W E# si gna l ha s to be

used with Software Data Protection (SDP) command

sequenc e whe n c on tr ol ling the Erase an d P rogram ope ra-

tions in the flash memory bank. The SDP command

sequence protects the data stored in the flash memory

bank from accidental alteration.

The SST32VF20x/40x provide the added functionality of

being able to simultaneously read from or write to the

SRAM bank while erasing or programming in the flash

memory bank. The SRAM memory bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Word-Program concurrently. All

flash memory Er ase and Program operations will automati-

cally latch the input addres s and data signals and complete

the operation in background without fur ther in put stimulus

requirement. Once the internally controlled erase or pro-

gram cycle i n the flash bank has co mmenced , the SRAM

bank can be accessed f or read or write.

The SST32VF20x/40x devices are suited for applications

that use both flash memory and SRAM memory to store

code or data. For systems requiring low power and small

form factor, the SST32VF20x/40x devices significantly

improve performance and reliability, while lowering power

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

SST32VF201 / 202 / 401 / 402SRAM (x16) ComboMemories

Advance Information

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

consumption, wh en c o mpa r ed w ith mu lt ip le ch ip solutions.

The SST32VF20x/40x inherently use less energy during

erase and program than alternative flash technologies. The

total energy consumed is a function of the applied voltage,

current, and time of application. Since f or any given voltage

range, the SuperFlash technology uses less current to pro-

gram and has a shorter erase time, the total energy con-

sumed during any Er ase or Program operation is less than

alternative flash technologies.

The SuperF lash t echnology provides f ixed Erase and Pro-

gr am times, independent of the number of Er ase/Prog ram

cycles that have occurred. Therefore the system software

or hardwa re does not hav e t o be modif ied or de-rated as is

necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Prog ram cycles.

Device Operatio n

The ComboMemory uses BES# and BEF# to control oper-

ation of either the SRAM or the flash memory bank. When

BES# is low, the SRAM Bank is activated for Read and

Wr ite operatio n. When BE F# is low the flash ban k is act i-

vated for Read, Program or Erase operation. BES# and

BEF# cannot be at low le v el at the same time. If BES# and

BEF# are both asserted to low level bus contention will

result and the device may suffer permanent damage. All

address , data, and control lines are shared by SRAM Bank

and flash bank which minimizes power consumption and

loading. The device goes into standby when both bank

enables are high.

SRAM Operation

With BES# low and BEF# high, the SST32VF201/401

operate as 64K x16 CMOS SRAM, and the SST32VF202/

402 opera tes as 12 8K x16 CMOS SRAM, wit h fully stat ic

operation requiring no external clocks or timing strobes.

The SST32VF201/401 SRAM is mapped into the first 64

KWord address space of the device, and the

SST32VF202/402 SRAM is mapped into the first 128

KWord address space. When BES# and BEF# are high,

both m emory bank s ar e dese lect ed and the d evice enters

standb y mode. Read and Write cycle times are equal. The

control signals UBS# and LBS# provide access to the

upper data byte and lower data byte. See Table 3 for SRAM

read and write data byte control modes of operation.

SRAM Read

The SRAM Read operation of the SST32VF20x/40x is

controlled by OE# and BES#, both have to be low with

WE# high for the system to obtain data from the outputs.

BES# is us ed for SRAM bank se le ct ion. OE# is the ou tpu t

cont rol and is us ed to gate dat a from the ou tput pins. The

data bus is in high impedance state when OE# is high. See

Figure 2 for the Read cycle timing diagr am.

SRAM Write

The SRAM Write oper ation of the SST32VF20x/40x is con-

trolled by WE# and BES#, both have to be low for the sys-

tem to write to the SRAM. During the Word-Write

operation, the addresses and data are referenced to the

risi ng edg e o f ei the r BE S# or W E #, wh ichever occurs fi rst .

The write time is measur ed from the last f alling edge to the

first rising edge of BES# or WE#. See Figures 3 and 4 for

the Write cycle timing diagrams.

Flash Operation

With B EF# ac tive, the SST 32VF2 01/202 opera te as 128K

x16 flas h memor y and the SST3 2VF401/4 02 operates as

256K x16 flash memory. The flash memory bank is read

using the common address lines, data lines, WE# and

OE#. Erase and Program operations are initiated with the

JEDEC standard SDP command sequences. Address and

data are latched during the SDP commands and during the

internally timed Erase and Program operations .

Flash Read

The Read operation of the SST32VF20x/40x devices is

controlled by BEF# and OE#. Both have to be low, with

WE# high, for the system to obtain data from the outputs.

BEF# is used for flash memory bank selection. When

BEF# and BES# are high, both banks are deselected and

only standby power is consumed. OE# is the output con-

trol and is used to gate d ata from the ou tput pins. The data

bus is in high impedance stat e when OE# is high. Ref er to

Figure 5 for furt her details.

Flash Erase/Program Operation

SDP commands are us ed to initiate the flash memory bank

Program and Erase operations of the SST32VF20x/40x.

SDP commands are loaded to the flash memory bank

using standard microprocessor write sequences. A com-

mand is loaded b y asserting WE# low while keeping BEF#

low and OE# high. The address is latched on the falling

edge of WE# or BEF#, wh ichever occur s last. The dat a is

latched on the rising edge of WE# or BEF#, whichever

occurs first.

Flash Word-Program Operation

The flash memory bank of the SST32VF2 0x/40x devices is

programmed on a word-by-word basis. Before Program

operations, the memory must be erased first. The Program

Advance Information

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

operation consists of three steps. The first step is the three-

byte-load sequence for Software Data Protection. The sec-

ond step is to load word address and word data. During the

W ord-Prog ram operation, the addresses are latched on the

falling edge of either BEF# or WE#, whichever occurs last.

The data is latched on the rising edge of either BEF# or

WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or BEF#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed, within 20

µs. See Figures 6 and 7 for WE# and BEF # controlled Pro-

gram operation timing diagrams and Figure 17 for flow-

charts. During the Program operation, the only valid flash

Read operations are Data# Polling and Toggle Bit. During

the internal Program operation, the host is free to perform

additional tasks. Any SDP commands loaded during the

internal Program operation will be ignored.

Flash Sector/Block-Erase Operation

The Fl ash Sector/Block-Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST32VF20x/40x offer both Sector-

Erase and Block-Erase mode. The sector architecture is

based on unif orm sector siz e of 2 KWord. The Bloc k-Erase

mode is based on uniform block size of 32 KWord. The

Sector-Erase operation is initiated by executing a six-byte

command sequence with Sector-Erase command (30H)

and sector address (SA) in the last b us cycle. The address

lines A16-A11, for SST32VF201/202, and A17-A11, for

SST32VF401/402, are used to determine the sector

address. The Block-Erase operation is initiated by execut-

ing a six- byte comm and sequenc e with Block-Erase co m-

mand (5 0H) and block address (BA) in the last bus cycle.

The add res s lines A16-A15, for SST32VF201/202, and A17-

A15, for SST32VF401/402, are used to determine the b lock

address. The sector or block address is latched on the fall-

ing edge of the sixth WE# pulse, while the command (30H

or 50H) is latched on the rising edge of the sixth WE#

pulse. The internal Erase operation begins after the sixth

WE# pulse. The End-of-Erase operation can be deter-

mined using either Data# Polling or Toggle Bit methods.

See Figures 11 and 12 for timing waveforms. Any com-

mands i s su ed during the S ec tor - or B l ock-Erase op erat io n

are ignored.

Flash Chip-Erase Operation

The SST32VF20x/40x provide a Chip-Erase operation,

which allows the user to erase the entire memor y array to

the “1” state . This is useful w hen the e ntire de vice m ust be

quickly er ased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only v alid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 9 for timing diagram,

and Figure 20 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Opera ti on Status De te ct ion

The SST32VF20x/40x provide two software means to

detect the c ompleti on o f a wr ite (Pro gram or E rase) c ycle,

in o rder t o optim ize the syste m wri te cycle ti me. The so ft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal program or erase operation.

The act ual co mple tion of the nonvolatile wr ite is asyn chr o-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data ma y appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the write cycle, otherwise the rejec-

tion is valid.

Flash Data# Polling (DQ7)

When the SST32VF20x/40x flash memory banks are in

the internal Program operation, any attempt to read DQ7

will produce the complement of the true data. Once the

Program operation is completed, DQ7 will produce true

data. The flash memory bank is then ready for the next

operatio n. Duri ng inter nal Erase o peration, any attempt to

read DQ7 will produce a ‘0’. On ce the i nternal Er ase o pera -

tion is completed, DQ7 will produce a ‘1’. The Data# P olling

is valid after the rising edge of the fourth WE# (or BEF#)

pulse for Program operation. For Sector- or Block-Erase,

the Data# Polling is valid after the rising edge of the sixth

WE# (or B EF# ) pulse. See Figure 8 f or Data# P ollin g timing

diagram and Figure 18 for a flowchart.

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alter nating 1s

and 0s, i.e., toggling between 1 and 0. When the internal

Program or E rase ope ration is com plete d, the toggl ing wi ll

stop. The flash memory bank is then ready for the next

Advance Information

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

operation. The Toggle Bit is v alid after the rising edge of the

fourth WE# (or BEF#) pulse for Program operation. For

Secto r- or Ba nk-Era se, the Toggl e Bit i s val id afte r the rising

edge of the sixth WE# (or BEF#) pulse. See Figure 9 for

Toggle Bit timing diagram and Figure 18 for a flowchart.

Flash Memory Data Protection

The SST32VF20x/40x flash memory bank provides both

hardware an d software feature s to protec t nonvolatile data

from inadv ertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit M ode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Flash Write operation. This prevents

inadvertent writes during power-up or power-down.

Flash Software Data Protection (SDP)

The SST32VF20x/40x provide the JEDEC approved soft-

ware data protection scheme for all flash memory bank

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three-byte sequence. The three byte-load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST32VF20x/40x devices are shipped with the software

data protection per manently enabled. See Table 4 for the

specific software command codes. During SDP command

sequenc e, invalid S DP com mands w ill abort the device to

the read mode, within Read Cycle Time (TRC).

Concurrent Read and Write Operations

The SST32V F20x/40x provide the uni que benefit of being

able to read from or write to SRAM, while simultaneously

erasing or programming the Flash. This allows data alter-

ation code to be executed from SRAM, while altering the

data in Flash. The following tab le lists all valid states.

The device will ignor e a ll S DP co mma nds when an Era se

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operation is in prog ress .

Product Identifica tion

The product identification mode identifies the devices as

the SST32VF20x/40x and manufacturer as SST. This

mode may be accessed by software operations only.

The hardware device ID Read operation, which is typi-

cally used by programmers, cannot be used on this

device beca u se of th e shar ed lines b e twe en f la sh and

SRAM in the multi-chip package. Therefore, applica-

tion of high v oltage to pin A9 may damage this device.

Users ma y use the softw are product identification operation

to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same sock et. For detail s, see

Tables 3 and 4 for software operation, Figure 13 for the

software ID entry and Read timing diagram, and Figure 19

f or the ID entry command sequence flowchart.

Product Identification Mode Exit/Reset

In order to r et urn to the sta nda r d read mod e, the So ftwar e

Product Identification mode must be exited. Exiting is

accomplished by issuing the Exit ID command sequence,

which returns the device to the Read operation. Please

note that the software-reset command is ignored during an

inter nal Pr ogram or Era se operatio n. See Table 4 for soft-

ware comm and cod es, Figur e 14 for timing wavefor m an d

Figure 19 for a flowchart.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capac-

itor to be placed as close as possible between VDD and

VSS, e.g., less than 1 cm away from the VDD pin of the

device. Additionally, a low frequency 4.7 µF electrolytic

capacitor from VDD to VSS should be placed within 1 cm of

the VDD pin.

CONCURRENT READ/WRITE STATE TABLE

Flash SRAM

Program/Erase Read

Program/Erase Write

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H 00BFH

Device ID

SST32VF201/202 0001H 2789H

SST32VF401/402 0001H 2780H

T1.0 541

Advance Information

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LFBG A

I/O Buffers

541 ILL B1.0

Address Buffers

DQ15 - DQ8

AMS-A0

WE#

SuperFlash

Memory

SRAM

Control Logic

BES#

BEF#

OE#

Address Buffers

& Latches

LBS#

UBS#

DQ7 - DQ0

FUNCTIONAL BLOCK DIAGRAM

541 ILL F01a.0

SST32VF201/202

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

BES#

A12

A14

A10

LBS#

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

USB#

DQ14

DQ12

DQ10

DQ8

BEF#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

541 ILL F01b.0

SST32VF401/402

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

BES#

A12

A17

A14

A10

LBS#

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

USB#

DQ14

DQ12

DQ10

DQ8

BEF#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

Advance Information

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide flash addresses, A16-A0 for 2M and A17-A0 for 4M.

To provide SRAM addresses, A15-A0 for 1M and A16-A0 for 2M .

DQ15-DQ0Data Input/output To output data during Read cycles and receiv e input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle.

The outputs are in tri-state when OE# or BES# and BEF# are high.

BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low.

BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply 2.7-3.6V Power Supply

Vss Ground

UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8

LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0

NC No Connection Unconnected Pins

T2.0 541

1. AMS = Most significant address

TABLE 3: OPERATION MODES SELECTION

Mode BES#1

1. Do not apply BE S#=VIL and BEF#=VIL at the same time

BEF#1OE# WE# UBS# LBS# DQ15 to DQ8DQ7 to DQ0Address

Not Allowed VIL VIL X2

2. X can be VIL or VIH, but no other value.

XXX X X X

Flash

Read VIH VIL VIL VIH XX D

OUT DOUT AIN

Program VIH VIL VIH VIL XX D

IN DIN AIN

Erase X VIL VIH VIL X X X X Sector or Block address,

XXH for Chip-Erase

SRAM

Read VIL VIH VIL VIH VIL VIL DOUT DOUT AIN

VIL VIH VIL VIH VIL VIH DOUT High Z AIN

VIL VIH VIL VIH VIH VIL High Z DOUT AIN

Write VIL VIH XV

IL VIL VIL DIN DIN AIN

VIL VIH XV

IL VIL VIH DIN High Z AIN

VIL VIH XV

IL VIH VIL High Z DIN AIN

Standby VIHC VIHC X X X X High Z High Z X

Flash Write Inhibit X X VIL XXXHigh Z / D

OUT High Z / DOUT X

XXXV

IH XXHigh Z / D

OUT High Z / DOUT X

IH XX X XHigh Z / D

OUT High Z / DOUT X

Output Disable VIH VIL VIH VIH X X High Z High Z X

VIL VIH XXV

IH VIH High Z High Z X

VIL VIH VIH VIH X X High Z High Z X

Product Identification

Softw are Mode VIH VIL VIL VIH XXManufacturer’s ID (00BFH)

Device ID3

3. Device ID for: SST32VF201/202 = 2789H and SST32VF401/4024 = 2780H

AMSF4-A1=VIL, A0=VIH

(See Table 4)

4. AMS = Most significant flash address

T3.2 541

Advance Information

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA2Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX330H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX350H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Softw are ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H

Softw are ID Exit XXH F0H

Softw are ID Exit 5555H AAH 2AAAH 55H 5555H F0H

T4.1 541

1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.

2. WA = Program Word address

3. SAX for Sector-Erase; uses AMS-A11 address lines

BAX, for Block-Erase; uses AMS-A15 address lines

AMS = Most significant address

AMS = A16 for SST32VF201/202 and A17 for SST32VF401/402

4. The device does not remain in Software Product ID Mode if powered down.

5. With AMS-A1 =0; SST Manufacturer’s ID= 00BFH, is read with A0 = 0,

SST32VF201/202 Device ID = 2789H, is read with A0 = 1,

SST32VF401/402 Device ID = 2780H, is read with A0 = 1.

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause pe r manent da mage to the device. This is a stres s rating only and funct ional operatio n

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to VDD+1.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Cur rent1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Extended -20°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 15 and 16

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

TABLE 5: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.6V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input = VIL/VIH, at f=1/TRC Min,

VDD=VDD Max, all DQs open

Read

Flash 20 mA OE#=VIL, WE#=VIH

BEF#=VIL, BES#=VIH

SRAM 20 mA BEF#=VIH, BES#=VIL

Concurrent Operation 45 mA BEF#=VIH, BES#=VIL

Write

Flash 25 mA WE#=VIL

BEF#=VIL, BES#=VIH, OE#=VIH

SRAM 20 mA BEF#=VIH, BES#=VIL

ISB Standby VDD Current 30 µA VDD=VDD Max, BEF#=BES#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOLF Flash Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOHF Flash Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

VOLS Output Low Vo ltage 0.4 V IOL=1 mA, VDD=VDD Min

VOHS Output High Voltage 2.2 V IOH=-500 µA, VDD=VDD Min

T5.1 541

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T6.0 541

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 24 pF

CIN1Input Capacitance VIN = 0V 12 pF

T7.0 541

TABLE 8: FLASH RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T8.0 541

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

AC CHARACTERISTICS

TABLE 9: SRAM READ CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TRCS Read Cycl e Time 70 ns

TAAS Address Access Time 70 ns

TBES Bank Enable Access Time 70 ns

TOES Output Enable Access Time 35 ns

TBYES UBS#, LBS# Access Time 70 ns

TBLZS1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output 0 ns

TOLZS1Output Enable to Active Output 0 ns

TBYLZS1UBS#, LBS# to Active Output 0 ns

TBHZS1BES# to High-Z Output 25 ns

TOHZS1Output Disable to High-Z Output 25 ns

TBYHZS1U BS#, LBS# to High-Z Output 35 ns

TOHS Output Hold from Address Change 10 ns

T9.1 541

TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TWCS Write Cycle Time 70 ns

TBWS Bank Enable to End-of-Write 60 ns

TAWS Address Valid to End-of-Write 60 ns

TASTS Address Set-up Time 0 ns

TWPS Write Pulse Width 60 ns

TWRS Write Recovery Time 0 ns

TBYWS UBS#, LBS# to En d-of-Write 60 ns

TODWS Output Disable from WE# Low 30 ns

TOEWS Output Enable from WE# High 0 ns

TDSS Data Set-up Time 30 ns

TDHS Data Hold from Write Time 0 ns

T10.0 541

TABLE 11: FLASH READ CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TBE Bank Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TBLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BEF# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TBHZ1BEF# High to High-Z Output 20 ns

TOHZ1OE# High to Hi gh-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

T11.0 541

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM

TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Word-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TBS WE# and BEF# Setup Time 0 ns

TBH WE# and BEF# Hold Time 0 ns

TOES OE# Hi gh Setup Ti me 0 ns

TOEH OE# High Hold Time 10 ns

TBPW BEF# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH WE# Pulse Width High 30 ns

TBPH BEF# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH Data Hold Time 0 ns

TIDA Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

T12.0 541

ADDRESSES AMSS-0

DQ15-0

UBS#, LBS#

Note: WE# remains High (VIH) for the Read cycle

AMSS = Most Significant SRAM Address

OE#

BES#

TRCS

TAAS

TBES

TOES

TBLZS

TOLZS

TBYES

TBYLZS TBYHZS

DATA VALID

TOHZS

TBHZS

TOHS

541 ILL F02.0

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# C ONTROLLED)1

TAWS

ADDRESSES AMSS-0

BES#

WE#

UBS#, LBS#

Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.

If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

TWPS TWRS

TWCS

TASTS

TBWS

TBYWS

TODWS TOEWS

TDSS TDHS

541 ILL F03.0

NOTE 2

DQ15-8, DQ7-0 VALID DATA IN

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1

ADDRESSES AMSS-0

WE#

BES#

TBWS

TAWS

TWCS

TWPS TWRS

TASTS TBYWS

DQ15-8, DQ7-0 VALID DATA IN

NOTE 2 NOTE 2

TDSS TDHS

UBS#, LBS#

Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

541 ILL F04.0

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SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM

FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

541 ILL F05.0

ADDRESSES AMSF-0

DQ15-0

WE#

OE#

BEF# TBE

TRC TAA

TOE

TOLZVIH

HIGH-Z TBLZ TOH TBHZ HIGH-Z

D ATA VALIDD ATA VALID

TOHZ

AMSF = Most Significant Flash Address

541 ILL F06.1

ADDRESSES AMSF-0

DQ15-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

BEF#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

AMSF = Most Significant Flash Address

Note: X can be VIL or VIH, but no other value

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SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM

FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM

541 ILL F07.1

ADDRESSES AMSF-0

DQ15-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

BEF#

TBP

AMSF = Most Significant Flash Address

Note: X can be VIL or VIH, but no other value

541 ILL F08.0

ADDRESSES AMSF-0

DQ7Data Data# Data# Data

WE#

OE#

BEF#

TOEH

TOE

TCE

TOES

AMSF = Most Significant Flash Address

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM

FIGURE 10: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM

541 ILL F09.0

ADDRESSES AMSF-0

DQ6

WE#

OE#

BEF#

TOETOEH

TBE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

AMSF = Most Significant Flash Address

541 ILL F10.1

ADDRESS AMSF-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 12)

X can be VIL or VIH, but no other value

AMSF = Most Significant Flash Address

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 11: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM

FIGURE 12: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM

541 ILL F11.1

ADDRESSES AMSF-0

DQ15-0

WE#

SW0

Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See Table 12)

X can be VIL or VIH, but no other value

SAX = Sector Address

AMSF = Most Significant Flash Address

SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

BEF#

SIX-WORD CODE FOR SECTOR-ERASE

TSE

TWP

541 ILL F12.1

ADDRESSES AMSF-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

BEF#

SIX-WORD CODE FOR BLOCK-ERASE

TSBE

TWP

Note: The device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See Table 12)

X can be VIL or VIH, but no other value

BAX = Block Address

AMSF = Most Significant Flash Address

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 13: SOFTWARE ID ENTRY AND READ

FIGURE 14: SOFTWARE ID EXIT AND RESET

541 ILL F13.1

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2 MFG ID

5555 2AAA 5555 0000 0001

OE#

BEF#

THREE-WORD SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

00BF

DEVICE ID

XX55XXAA XX90

Note: X can be VIL or VIH, but no other value

Device ID = 2789H for SST32VF201/202 and

2780H for SST32VF401/402

541 ILL F14.1

ADDRESS A14-0

DQ15-0

TIDA

TWP

T WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-WORD SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

BEF#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 16: A TEST LOAD EXAMPLE

541 ILL F15.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

A C test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) f or a lo gic “0”. Measurement reference points

f or inputs and outputs are VIT (0.5 VDD) and V OT (0.5 VDD). Input rise and f all times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

541 ILL F16.0

T O TESTER

TO DUT

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 17: WORD-PROGRAM ALGORITHM

541 ILL F17.1

Start

Write data: XXAAH

Address: 5555H

Write data: XX55H

Address: 2AAAH

Write data: XXA0H

Address: 5555H

Write Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

X can be VIL or VIH, but no other value.

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 18: WAIT OPTIONS

541 ILL F18.0

W ait TBP,

TSCE, or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS

541 ILL F19.1

Write data: XXAAH

Address: 5555H

Software Product ID Entry

Command Sequence

Write data: XX55H

Address: 2AAAH

Write data: XX90H

Address: 5555H

W ait TIDA

Read Software ID

Write data: XXAAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Write data: XX55H

Address: 2AAAH

Write data: XXF0H

Address: 5555H

Write data: XXF0H

Address: XXXXH

Return to normal

operation

W ait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value.

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 20: ERASE COMMAND SEQUENCE

541 ILL F20.1

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

W ait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

W ait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

W ait TBE

Block erased

to FFFFH

X can be VIL or VIH, but no other value.

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

FIGURE 21: CONCURRENT OPERATION FLOWCHART

541 ILL F21.0

Load SDP

Command

Sequence

Concurrent

Operation

Flash

Program/Erase

Initiated

Wait for End of

Write Indication

Flash Operation

Completed

End Concurrent

Operation

Read or Write

SRAM

End

Wait

Advance Information

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

PRODUCT ORDERING INFORMATION

Valid combinations for SST32VF201

SST32VF201-70-4C-L3K

SST32VF201-70-4E-L3K

Valid combinations for SST32VF202

SST32VF202-70-4C-L3K

SST32VF202-70-4E-L3K

Valid combinations for SST32VF401

SST32VF401-70-4C-L3K

SST32VF401-70-4E-L3K

Valid combinations for SST32VF402

SST32VF402-70-4C-L3K

SST32VF402-70-4E-L3K

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Device Speed Suffix1 Suffix2

SST32VFxxx -XXX -XX-XX

Package Modifier

K = 48 balls

Package Type

L3 = LFBGA (6mm x 8mm x 1.4mm)

Tempera ture Range

C = Commercial = 0°C to +70°C

E = Extended = -20 °C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Density

201 = 2 Mbit Flash + 1 Mbit SRAM

202 = 2 Mbit Flash + 2 Mbit SRAM

401 = 4 Mbit Flash + 1 Mbit SRAM

402 = 4 Mbit Flash + 2 Mbit SRAM

Function

Voltage

V = 2.7-3.6V

Device Family

32 = MPF + SRAM ComboMemory

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

PACKAGING DIAGRAMS

48-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 6MM X 8MM

SST PACKAGE CODE: L3K

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEW

TOP VIEW

SIDE VIEW

SEATING PLANE 0.35 ± 0.05

1.30 ± 0.10

0.15

6.00 ± 0.20

0.45 ± 0.05

(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48ba-LFBGA-L3K-6x8-450mic-ILL.1

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

1mm

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32VF201 / SST32VF202 / SST32VF401 / SST32VF402

Silicon Storage Technology, Inc. • 1171 Sonor a Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036