LTC1644
1
1644f
The LTC
®
1644 is a Hot Swap
TM
controller that allows a board
to be safely inserted and removed from a CompactPCI bus
slot. External N-channel transistors control the 3.3V/5V
supplies, while on-chip switches control the
–12V and 12V supplies. The 3.3V and 5V supplies can be
ramped up at a programmable rate. Electronic circuit break-
ers protect all four supplies against overcurrent faults. The
PWRGD output indicates when all of the supply voltages are
within tolerance. The OFF/ON pin is used to cycle the board
power or reset the circuit breaker. The PRECHARGE output
can be used to bias the bus I/O pins during card insertion
and extraction. PCI_RST# is combined on-chip with
HEALTHY# in order to generate LOCAL_PCI_RST#.
■
Hot Board Insertion into CompactPCI Bus
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Allows Safe Board Insertion and Removal from a
Live, CompactPCI
TM
Bus
■
Controls –12V, 3.3V, 5V and 12V Supplies
■
Adjustable Foldback Current Limit with Circuit
Breaker
■
Dual-Level Circuit Breakers Protect 5V and 3.3V
Supplies from Overcurrent and Short-Circuit Faults
■
LOCAL_PCI_RST# Logic On-Chip
■
PRECHARGE Output Biases I/O Pins During Card
Insertion and Extraction
■
Adjustable Supply Voltage Power-Up Rate
CompactPCI Bus
Hot Swap Controller
Hot Swap is a trademark of Linear Technology Corporation.
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
Figure 1
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
Z2
C5
0.01µF
C1
0.047µF
C4
0.01µF
GND
12V
IN
V
EEIN
OFF/ON
FAULT
PWRGD
RESETIN
3V
IN
3V
IN
*
5V
IN
*
3V
SENSE
17
3V
OUT
18
5V
IN
LTC1644
20-PIN SSOP
13
PRECHARGE
12
DRIVE
11
5V
OUT
3
5V
SENSE
1416
GATE
15
1
2
5
6
7
9
12V
OUT
V
EEOUT
TIMER
RESETOUT
20
19
4
10
R18
2k
R19
1k
R20 1.2k
EARLY V(I/O)
R3
10Ω
5V
IN
Z1
C6
0.01µFC7
0.01µF
Z1, Z2: SMAJ12CA Z3, Z4: 1PMT5.0AT3 *5V
IN
AND 3V
IN
MAY BE USED AS SOURCES OF EARLY POWER
R4
10Ω
R17
2k
5V
OUT
5V AT 5.7A
3V
OUT
3.3V AT 8A
12V
OUT
12V AT 500mA
V
EEOUT
–12V AT 100mA
I/O DATA LINE 1
I/O DATA LINE 128
I/O #1
1644 F01
Q3
MMBT2222A
1V
±10%
8
R11
51k
R10
18Ω 5% 3V
IN
3V
OUT
R13 10Ω
I/O #128
R14 10Ω
R12
51k
R6
2k
R5
1k
R8 1k
R7
12Ω
C3 4.7nF R9
24Ω
R1
0.005ΩQ1
IRF7413
Q2
IRF7413
R2
0.007Ω
C2
0.1µF
C
LOAD(5VOUT)
C
LOAD(3VOUT)
C
LOAD(VEEOUT)
C
LOAD(12VOUT)
RESET#
PCI
BRIDGE
CHIP
PCB EDGE
BACKPLANE
CONNECTOR
R15
1ΩR16
1Ω
• • •
• • •
• • •
BACKPLANE
CONNECTOR
5V
LONG 5V
3.3V
LONG 3.3V
12V
–12V
BD_SEL#
HEALTHY#
PCI_RST#
GROUND
I/O PIN 1
I/O PIN 128
Z3
R21 1.74Ω
R22 2.74Ω
Z4
C8
0.1µF
PER 10
POWER
PINS
C9
0.1µF
PER 10
POWER
PINS
+
+
+
+
LTC1644
2
1644f
Supply Voltages
12V
IN
................................................................ 13.2V
V
EEIN
.................................................................. –14V
Input Voltages (Pins 5, 9) .......................–0.3V to 13.5V
Output Voltages (Pins 6, 7, 10) ..............–0.3V to 13.5V
Analog Voltages and Currents
Pins 3, 11 to 14, 16 to 18 ...................–0.3V to 13.5V
Pins 4, 15 ............................. –0.3V to (12V
IN
+ 0.3V)
V
EEOUT
...................................................–14V to 0.3V
12V
OUT
...............................................–0.3V to 13.2V
Operating Temperature Range
LTC1644C ............................................... 0°C to 70°C
LTC1644I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
T
JMAX
= 140°C, θ
JA
= 135°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTC1644CGN
LTC1644IGN
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V12VIN = 12V, VEEIN = –12V, V3VIN = 3.3V, V5VIN = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
DD
V
12VIN
Supply Current OFF/ON = 0V ●38 mA
V
LKO
Undervoltage Lockout 12V
IN
, Ramping Down ●6.00 8.30 10.80 V
3V
IN
, 5V
IN
, Ramping Down ●2.25 2.48 2.75 V
V
FB
Foldback Current Limit Voltage V
FB
= (V
5VIN
– V
5VSENSE
), V
5VOUT
= 0V, TIMER = 0V ●81215 mV
V
FB
= (V
5VIN
– V
5VSENSE
), V
5VOUT
= 3V, TIMER = 0V ●40 51 70 mV
V
FB
= (V
3VIN
– V
3VSENSE
), V
3VOUT
= 0V, TIMER = 0V ●81215 mV
V
FB
= (V
3VIN
– V
3VSENSE
), V
3VOUT
= 2V, TIMER = 0V ●40 51 70 mV
V
CB
Circuit Breaker Trip Voltage V
CB
= (V
5VIN
– V
5VSENSE
), TIMER = FLOAT ●40 55 70 mV
V
CB
= (V
3VIN
– V
3VSENSE
), TIMER = FLOAT ●40 55 70 mV
t
OC
Overcurrent Fault Response Time (V
5VIN
– V
5VSENSE
) = 100mV, TIMER = FLOAT ●30 45 60 µs
(V
3VIN
– V
3VSENSE
) = 100mV, TIMER = FLOAT ●30 45 60 µs
t
SC
Short-Circuit Response Time (V
5VIN
– V
5VSENSE
) = 200mV, TIMER = FLOAT ●0.1 1.0 µs
(V
3VIN
– V
3VSENSE
) = 200mV, TIMER = FLOAT ●0.1 1.0 µs
I
CP
GATE Pin Output Current OFF/ON = 0V, V
GATE
= 0V, TIMER = 0V ●–20 –65 –100 µA
V
GATE
= 5V, OFF/ON = 4V 100 225 300 µA
OFF/ON = 0V, V
GATE
= 2V, TIMER = FLOAT, FAULT = 0V ●31020 mA
∆V
GATE
External Gate Voltage ∆V
GATE
= (V
12VIN
– V
GATE
), I
GATE
= –1µA●50 200 mV
V
DROP
Internal Switch Voltage Drop V
DROP
= (V
12VIN
– V
12VOUT
), I = 500mA ●200 600 mV
V
DROP
= (V
EEOUT
– V
EEIN
), I
EE
= 100mA ●110 250 mV
I
CL
Current Foldback 12V
IN
= 12V, 12V
OUT
= 0V, TIMER = 0V ●–50 –360 –600 mA
12V
IN
= 12V, 12V
OUT
= 10V, TIMER = 0V ●–525 –840 –1500 mA
V
EEIN
= –12V, V
EEOUT
= 0V, TIMER = 0V ●20 100 300 mA
V
EEIN
= –12V, V
EEOUT
= –10V, TIMER = 0V ●200 320 650 mA
T
TS
Thermal Shutdown Temperature 130 °C
1
2
3
4
5
6
7
8
9
10
TOP VIEW
GN PACKAGE
20-LEAD PLASTIC SSOP
20
19
18
17
16
15
14
13
12
11
12V
IN
V
EEIN
5V
OUT
TIMER
OFF/ON
FAULT
PWRGD
GND
RESETIN
RESETOUT
12V
OUT
V
EEOUT
3V
OUT
3V
IN
3V
SENSE
GATE
5V
SENSE
5V
IN
PRECHARGE
DRIVE
LTC1644
3
1644f
V
TH
Power Good Threshold Voltage 12V
OUT
●10.8 11.1 11.4 V
V
EEOUT
●– 10.4 – 10.5 – 11.1 V
3V
OUT
●2.8 2.9 3.0 V
5V
OUT
●4.50 4.62 4.75 V
V
3VONLY
3V Only Window Voltage V
3VONLY
= V
5VIN
– V
3VIN
, V
5VOUT
= V
3VOUT
= 3V ●50 107 200 mV
V
NOVEEIN
No V
EEIN
Threshold Voltage V
EEIN
●–4 –4.6 –6.3 V
V
IL
Input Low Voltage OFF/ON, RESETIN, FAULT ●0.8 V
V
IH
Input High Voltage OFF/ON, RESETIN, FAULT ●2V
I
IN
OFF/ON, RESETIN Input Current OFF/ON, RESETIN = 0V ●±0.08 ±10 µA
OFF/ON, RESETIN = 12V
IN
●±0.08 ±10 µA
RESETOUT, FAULT Output Current RESETOUT, FAULT = 5V, OFF/ON = 0V, RESETIN = 3.3V ●±0.08 ±10 µA
PWRGD Output Current PWRGD = 5V, OFF/ON = 4V ●±0.08 ±10 µA
5V
SENSE
Input Current 5V
SENSE
= 5V, 5V
OUT
= 0V ●55 100 µA
3V
SENSE
Input Current 3V
SENSE
= 3.3V, 3V
OUT
= 0V ●55 100 µA
5V
IN
Input Current 5V
IN
= 5V, TIMER = 0V ●1 1.5 mA
3V
IN
Input Current 3V
IN
= 3.3V, TIMER = FLOAT ●490 625 µA
3V
IN
= 3.3V, TIMER = 0V ●380 550 µA
5V
OUT
Input Current 5V
OUT
= 5V, OFF/ON = 0V, TIMER = 0V ●102 400 µA
3V
OUT
Input Current 3V
OUT
= 3.3V, OFF/ON = 0V, TIMER = 0V ●161 500 µA
I
TIMER
TIMER Pin Current OFF/ON = 0V, V
TIMER
= 0V ●–15 –21 –27 µA
V
TIMER
= 5V, OFF/ON = 4V ●30 45 70 mA
V
TIMER
TIMER Threshold Voltages (V
12VIN
– V
TIMER
), FAULT = 0V ●0.5 1 1.3 V
R
DIS
5V
OUT
Discharge Impedance OFF/ON = 4V ●45 100 Ω
3V
OUT
Discharge Impedance OFF/ON = 4V ●60 100 Ω
12V
OUT
Discharge Impedance OFF/ON = 4V ●430 1000 Ω
V
EEOUT
Discharge Impedance OFF/ON = 4V ●625 1000 Ω
V
OL
Output Low Voltage PWRGD, RESETOUT, FAULT, I = 3mA ●0.4 V
V
PXG
PRECHARGE Reference Voltage V
5VIN
= 5V ●0.95 1.00 1.05 V
V
5VIN
= V
3VIN
= 3.3V ●0.95 1.00 1.05 V
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V12VIN = 12V, VEEIN = –12V, V3VIN = 3.3V, V5VIN = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
LTC1644
4
1644f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
3.3V and 5V Current Foldback
Profile 12V Output Current –12V Output Current
OUTPUT VOLTAGE (V)
012345
OUTPUT CURRENT (A)
1644 G01
11
10
9
8
7
6
5
4
3
2
1
0
3V
OUT
5V
OUT
T
A
= 25°C
R
SENSE
= 0.005Ω
OUTPUT VOLTAGE (V)
024681012
OUTPUT CURRENT (A)
1644 G02
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = 25°C
12VIN = 12V
OUTPUT VOLTAGE (V)
0 –2–4–6–8–10–12
OUTPUT CURRENT (A)
1644 G03
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
TA = 25°C
VEEIN = –12V
12VIN Supply Current
vs Temperature 12VIN Undervoltage Lockout
vs Temperature 5VIN UVLO Threshold Voltage
vs Temperature
TEMPERATURE (°C)
–50
3.2
3.1
3.0
2.9
2.8 25 75
1644 G04
–25 0 50 100
12V
IN
SUPPLLY CURRENT (mA)
TEMPERATURE (°C)
–50
8.20
12V
IN
UNDERVOLTAGE LOCKOUT (V)
8.40
–25 025 50
1644 G05
75
8.45
8.50
8.25
8.30
8.35
100
RAMPING
UP
RAMPING
DOWN
TEMPERATURE (°C)
–50
5V
IN
UVLO THRESHOLD VOLTAGE (V)
2.49
2.50
2.51
25 75
1644 G06
2.48
2.47
2.46 –25 0 50
2.52
2.53
2.54
2.55
100
RAMPING
UP
RAMPING
DOWN
3VIN UVLO Threshold Voltage
vs Temperature 5V Foldback Current Limit Voltage
vs Temperature 3V Foldback Current Limit Voltage
vs Temperature
TEMPERATURE (°C)
–50
2.47
3V
IN
UVLO THRESHOLD VOLTAGE (V)
2.48
2.50
2.51
2.52
50
2.56
1644 G07
2.49
0
–25 75
25 100
2.53
2.54
2.55 RAMPING
UP
RAMPING
DOWN
TEMPERATURE (°C)
–50
0
5V FOLDBACK CURRENT LIMIT VOLTAGE (mV)
10
20
30
40
60
–25 02550
1644 G08
75 100
50
TIMER = 0V 5VOUT = 3V
5VOUT = 0V
TEMPERATURE (°C)
–50
0
3V FOLDBACK CURRENT LIMIT VOLTAGE (mV)
10
20
30
40
60
–25 02550
1644 G09
75 100
50
TIMER = 0V 3VOUT = 2V
3VOUT = 0V
LTC1644
5
1644f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
5V/3.3V Circuit Breaker Trip
Voltage vs Temperature
5V/3.3V Circuit Breaker Overcurrent
Fault Response Time
vs Temperature
5V/3.3V Circuit Breaker Short-
Circuit Response Time
vs Temperature
GATE Pin Current vs Temperature
(VGATE = 2V, FAULT = 0V) GATE Pin Current vs Temperature
(VGATE = 5V, OFF/ON = 4V)
GATE Pin Voltage vs Temperature 12V Internal Switch Voltage Drop
vs Temperature VEE Internal Switch Voltage Drop
vs Temperature
TEMPERATURE (°C)
–50
48.0
47.5
47.0
46.5
46.0
45.5
45.0
44.5 25 75
1644 G11
–25 0 50 100
5V/3.3V CIRCUIT BREAKER OVERCURRENT
FAULT RESPONSE TIME (µs)
TEMPERATURE (°C)
–50
0.100
5V/3.3V CIRCUIT BREAKER SHORT-CIRCUIT
RESPONSE TIME (µs)
0.105
0.110
0.115
0.120
0.125
–25 02550
1644 G12
75 100
GATE Pin Current vs Temperature
(VGATE = 0V, OFF/ON = 0V)
TEMPERATURE (°C)
–50
GATE PIN CURRENT (mA)
6
8
10
25 75
1644 G13
4
2
0–25 0 50
12
14
16
100
V
GATE
= 2V
FAULT = 0V
TEMPERATURE (°C)
–50
300
250
200
150
100
50
025 75
1644 G14
–25 0 50 100
GATE PIN CURRENT (µA)
V
GATE
= 5V
OFF/ON = 4V
TEMPERATURE (°C)
–50
–85
GATE PIN CURRENT (A)
–80
–70
–65
–60
50
–40
1644 G15
–75
0
–25 75
25 100
–55
–50
–45 V
GATE
= 5V
OFF/ON = 4V
TEMPERATURE (°C)
–50
11.97
11.96
11.95
11.94
11.93
11.92 25 75
1644 G16
–25 0 50 100
GATE PIN VOLTAGE (V)
I
GATE
= –1µA
TEMPERATURE (°C)
–50
0.35
0.30
0.25
0.20
0.15
0.10
0.05
025 75
1644 G17
–25 0 50 100
V
CC
INTERNAL SWITCH VOLTAGE DROP (V)
I = 500mA
TEMPERATURE (°C)
–50
0
V
EE
INTERNAL SWITCH VOLTAGE DROP (V)
0.02
0.06
0.08
0.10
50
0.18
1644 G18
0.04
0
–25 75
25 100
0.12
0.14
0.16 I
EE
= 100mA
TEMPERATURE (°C)
–50
56.2
56.0
55.8
55.6
55.4
55.2
55.0
54.8 25 75
1644 G10
–25 0 50 100
5V/3.3V CIRCUIT BREAKER TRIP VOLTAGE (mV)
TIMER PIN FLOATING
LTC1644
6
1644f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
12V Foldback Current Limit
vs Temperature VEE Foldback Current Limit
vs Temperature 12VOUT PWRGD Threshold
Voltage vs Temperature
VEEOUT PWRGD Threshold Voltage
vs Temperature 5VOUT PWRGD Threshold Voltage
vs Temperature 3VOUT PWRGD Threshold Voltage
vs Temperature
3V Only Window Voltage
vs Temperature No VEEIN Threshold Voltage vs
Temperature 5VSENSE Input Current vs
Temperature
TEMPERATURE (°C)
–50
0
12V FOLDBACK CURRENT LIMIT (A)
0.10
0.30
0.40
0.50
50
1.00
0.90
1644 G19
0.20
0
–25 75
25 100
0.60
0.70
0.80
12V
OUT
= 10V
12V
OUT
= 0V
TEMPERATURE (°C)
–50
0
V
EE
FOLDBACK CURRENT LIMIT (A)
0.05
0.15
0.20
0.25
50
0.45
1644 G20
0.10
0
–25 75
25 100
0.30
0.35
0.40
V
EEOUT
= –10V
V
EEOUT
= 0V
TEMPERATURE (°C)
–60
12V
OUT
PWRGD THRESHOLD VOLTAGE (V)
11.05
11.06
11.07
11.09
11.10
11.08
–40 –20 0 20
1644 G21
40 100
11.11
60 80
TEMPERATURE (°C)
–50
V
EEOUT
PWRGD THRESHOLD VOLTAGE (V)
25 75
1644 G22
–25 0 50
–10.46
–10.47
–10.48
–10.49
–10.50
–10.51
–10.52
–10.53
–10.54 100 TEMPERATURE (°C)
–50
4.610
5V
OUT
PWRGD THRESHOLD VOLTAGE (V)
–25 0 25 50
1644 G23
75 100
4.618
4.616
4.614
4.612
4.620
4.622
TEMPERATURE (°C)
–50
3V
OUT
PWRGD THRESHOLD VOLTAGE (V)
–25 0 25 50
1644 G24
75 100
2.905
2.903
2.901
2.899
2.897
2.895
TEMPERATURE (°C)
–50
3V ONLY WINDOW VOLTAGE (V)
0.09
0.10
0.11
25 75
1644 G25
0.08
0.07
0.06 –25 0 50
0.12
0.13
0.14
100
5V
IN
– 3V
IN
3V
IN
– 5V
IN
TEMPERATURE (°C)
–50
–4.20
–4.30
–4.40
–4.50
–4.60
–4.70
–4.80
–4.90 25 75
1644 G26
–25 0 50 100
V
EEIN
THRESHOLD VOLTAGE (V)
TEMPERATURE (°C)
–50
60
50
40
30
20
10
025 75
1644 G27
–25 0 50 100
5V
SENSE
INPUT CURRENT (µA)
5V
OUT
= 0V
5V
OUT
= 3V
LTC1644
7
1644f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
3VSENSE Input Current
vs Temperature 5VIN Input Current vs Temperature 3VIN Input Current vs Temperature
5VOUT Input Current
vs Temperature 3VOUT Input Current
vs Temperature TIMER Pin Current
vs Temperature (ON = 0V)
TIMER Pin Current
vs Temperature (OFF/ON = 4V) TIMER Threshold Voltage
vs Temperature 5VOUT Discharge Resistance
vs Temperature
TEMPERATURE (°C)
–50
60
50
40
30
20
10
025 75
1644 G28
–25 0 50 100
3V
SENSE
INPUT CURRENT (µA)
3V
OUT
= 0V
3V
OUT
= 2V
TEMPERATURE (°C)
–50
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96 25 75
1644 G29
–25 0 50 100
5V
IN
INPUT CURRENT (mA)
TIMER = 0V
TEMPERATURE (°C)
–50
300
3VIN INPUT CURRENT (µA)
350
400
450
550
–25 02550
1644 G30
75 100
500 TIMER PIN FLOATING
TIMER = 0V
TEMPERATURE (°C)
–50
100
5VOUT INPUT CURRENT (µA)
101
–25 025 50
1644 G31
75
103
104
102
100
TEMPERATURE (°C)
–50
157
158
3V
OUT
INPUT CURRENT (µA)
–25 025 50
1644 G32
75
163
164
160
159
161
162
100
TEMPERATURE (°C)
–50
20.4 –25 025 50
1644 G33
75
21.4
20.6
20.8
21.0
21.2
21.6
100
TIMER PIN CURRENT (µA)
VTIMER = 0V
ON = 0V
TEMPERATURE (°C)
–50
0
TIMER PIN CURRENT (mA)
10
20
30
40
70
60
–25 02550
1644 G34
75 100
50
VTIMER = 5V
OFF/ON = 4V
TEMPERATURE (°C)
–50
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80 25 75
1644 G35
–25 0 50 100
TIMER THRESHOLD VOLTAGE (V)
TEMPERATURE (°C)
–50
70
60
50
40
30
20
10
025 75
1644 G36
–25 0 50 100
5V
OUT
DISCHARGE RESISTANCE (Ω)
LTC1644
8
1644f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
3VOUT Discharge Resistance
vs Temperature 12VOUT Discharge Resistance
vs Temperature VEEOUT Discharge Resistance
vs Temperature
VOL vs Temperature Precharge Reference Voltage
vs Temperature
TEMPERATURE (°C)
–50
0
3V
OUT
DISCHARGE RESISTANCE (Ω)
10
30
40
50
50
90
1644 G37
20
0
–25 75
25 100
60
70
8O
TEMPERATURE (°C)
–50
0
V
EEOUT
DISCHARGE RESISTANCE (Ω)
100
300
400
500
50
900
1644 G39
200
0
–25 75
25 100
600
700
80O
TEMPERATURE (°C)
–50
700
600
500
400
300
200
100
025 75
1644 G38
–25 0 50 100
12V
OUT
DISCHARGE RESISTANCE (Ω)
TEMPERATURE (°C)
–50
0
V
OL
(V)
0.05
0.10
0.15
0.20
0.30
–25 02550
1644 G40
75 100
0.25
I = 3mA
FAULT
RESETOUT
PWRGD
TEMPERATURE (°C)
–50
1.002
PRECHARGE REFERENCE VOLTAGE (V)
1.003
1.004
1.005
–25 02550
1644 G41
75 100
V
5VIN
= 5V
12V
IN
(Pin 1): 12V Supply Input. A 0.5Ω switch is con-
nected between 12V
IN
and 12V
OUT
with a foldback current
limit. An undervoltage lockout circuit prevents the switches
from turning on while the 12V
IN
pin voltage is less than
8.3V. 12V
IN
also provides power to the LTC1644’s internal
circuitry.
V
EEIN
(Pin 2): –12V Supply Input. A 1Ω switch is con-
nected between V
EEIN
and V
EEOUT
with a foldback current
limit. If no V
EE
supply input is available, tie the V
EEIN
pin to
the GND pin in order to disable the V
EEOUT
power good
function.
PI FU CTIO S
UUU
5V
OUT
(Pin 3): 5V Output Sense. The PWRGD pin will not
pull low until the 5V
OUT
pin voltage exceeds 4.62V. If no 5V
input supply is available, tie the 5V
OUT
pin to the 3V
OUT
pin
in order to disable the 5V
OUT
power good function.
TIMER (Pin 4): Current Fault Inhibit Timing Input. Connect
a capacitor from TIMER to GND. With the chip turned off
(OFF/ON = HIGH), the TIMER pin is internally held at GND.
When the chip is turned on, a 21µA pull-up current source
is connected to TIMER. Current limit faults will be ignored
until the voltage at the TIMER pin rises to within 1V of
12V
IN
.
LTC1644
9
1644f
PI FU CTIO S
UUU
OFF/ON (Pin 5): Digital Input. Connect the CPCI BD_SEL#
signal to the OFF/ON pin. When the OFF/ON pin is pulled
low, the GATE pin is pulled high by a 65µA current source
and the internal 12V and –12V switches are turned on.
When the OFF/ON pin is pulled high, the GATE pin will be
pulled to ground by a 225µA current source and the 12V
and –12V switches turn off.
The OFF/ON pin is also used to reset the electronic circuit
breaker. If the OFF/ON pin is cycled high and low following
the trip of the circuit breaker, the circuit breaker is reset
and a normal power-up sequence will occur.
FAULT (Pin 6): Open-Drain Digital I/O. FAULT is pulled low
when a current limit fault is detected. Current limit faults
are ignored until the voltage at the TIMER pin is within 1V
of 12V
IN
. Once the TIMER cycle is complete, FAULT will
pull low and the chip latches off in the event of an
overcurrent fault. The chip will remain latched in the off
state until the OFF/ON pin is cycled high then low.
Forcing the FAULT pin low with an external pull-down will
cause the chip to be latched into the off state after a 45µs
deglitching time.
PWRGD (Pin 7): Open-Drain Digital Power Good Output.
Connect the CPCI HEALTHY# signal to the PWRGD pin.
PWRGD remains low while V
12VOUT
≥ 11.1V, V
3VOUT
≥
2.9V, V
5VOUT
≥ 4.62V and V
EEOUT
≤ –10.5V. When any of
the supplies falls below its power good threshold voltage,
PWRGD will go high after a 10µs deglitching time.
GND (Pin 8): Chip Ground.
RESETIN (Pin 9): Digital Input. Connect the CPCI PCI_RST#
signal to the RESETIN pin. Pulling RESETIN low will cause
RESETOUT to pull low.
RESETOUT (Pin 10): Open-Drain Digital Output. Connect
the CPCI LOCAL_PCI_RST# signal to the RESETOUT pin.
RESETOUT is the logical combination of RESETIN and
PWRGD.
DRIVE (Pin 11): Precharge Base Drive Output. Provides
base drive for an external NPN emitter-follower which in
turn biases the PRECHARGE node.
PRECHARGE (Pin 12): Precharge Monitor Input. An on-
chip error amplifier servos the DRIVE pin voltage to keep
the precharge node at 1V.
5V
IN
(Pin 13): 5V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 5V
IN
pin is less than 2.48V. If no
5V input supply is available, tie the 5V
IN
to the 3V
IN
pin.
5V
SENSE
(Pin 14): 5V Current Limit Sense. With a sense
resistor placed in the supply path between 5V
IN
and
5V
SENSE
, the GATE pin voltage will be adjusted to maintain
a constant 51mV across the sense resistor and a constant
current through the switch while the TIMER pin is low. A
foldback feature reduces the current limit as the voltage at
the 5V
OUT
pin approaches GND.
When the TIMER pin is high, the circuit breaker function is
enabled. If the voltage across the sense resistor exceeds
55mV but is less than 150mV, the circuit breaker is tripped
after a 45µs time delay. In the event the sense resistor
voltage exceeds 150mV, the circuit breaker trips immedi-
ately and the chip latches off. To disable the current limit,
5V
SENSE
and 5V
IN
can be shorted together.
GATE (Pin 15): High Side Gate Drive for the External 3.3V
and 5V N-Channels pass transistors. Requires an external
series RC network to compensate the current limit loop
and set the minimum ramp-up rate. During power up, the
slope of the voltage rise at the GATE is set by the 65µA
current source connected to 12V
IN
and the external ca-
pacitor connected to GND (C1, see Figure 1) or by the 3.3V
or 5V current limit and the bulk capacitance on the 3V
OUT
or 5V
OUT
supply lines (C
LOAD(5VOUT)
or C
LOAD(3VOUT)
, see
Figure␣ 1). During power down, the slew rate of the GATE
voltage is set by the 225µA current source connected to
GND and the external GATE capacitor (C1, see Figure 1).
The voltage at the GATE pin will be modulated to maintain
a constant current when either the 3V or 5V supplies go
into current limit while the TIMER pin is low. In the event
of a fault or an undervoltage condition, the GATE pin is
immediately pulled to GND.
3V
SENSE
(Pin 16): 3.3V Current Limit Set. With a sense
resistor placed in the supply path between 3V
IN
and
3V
SENSE
, the GATE pin voltage will be adjusted to maintain
a constant 51mV across the sense resistor and a constant
current through the switch while the TIMER pin is low. A
foldback feature reduces the current limit as the voltage at
the 3V
OUT
pin approaches GND.
LTC1644
10
1644f
BLOCK DIAGRA
W
When the TIMER pin is high, the circuit breaker function is
enabled. If the voltage across the sense resistor exceeds
55mV but is less than 150mV, the circuit breaker is tripped
after a 45µs time delay. In the event the sense resistor
voltage exceeds 150mV, the circuit breaker trips immedi-
ately and the chip latches off. To disable the current limit,
3V
SENSE
and 3V
IN
can be shorted together.
3V
IN
(Pin 17): 3.3V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 3V
IN
pin is less than 2.48V. If no
3.3V input supply is available, connect two series diodes
between 5V
IN
and 3V
IN
(tie anode of first diode to 5V
IN
and
cathode of second diode to 3V
IN
, see Figure 11).
PI FU CTIO S
UUU
3V
OUT
(Pin 18): Analog Input used to monitor the 3.3V
output supply voltage. The PWRGD pin cannot pull low
until the 3V
OUT
pin voltage exceeds 2.9V. If no 3.3V input
supply is available, tie the 3V
OUT
pin to the 5V
OUT
pin.
V
EEOUT
(Pin 19): –12V Supply Output. A 1Ω switch is
connected between V
EEIN
and V
EEOUT
. V
EEOUT
must ex-
ceed –10.5V before the PWRGD pin pulls low unless the
V
EE
PWRGD function is disabled by grounding the V
EEIN
pin.
12V
OUT
(Pin 20): 12V Supply Output. A 0.5Ω switch is
connected between 12V
IN
and 12V
OUT
. 12V
OUT
must
exceed 11.1V before the PWRGD pin can pull low.
Q6
V
EEIN
2
TIMER
4
V
EEOUT
19
3V
OUT
18
5V
OUT
3
–
+
+–
Q9
NOTE: V
12VIN
– V
TIMER
< 1V = TIMER HI, V
12VIN
– V
TIMER
> 1V = TIMER LOW
Q8
Q2
Q3
225µA
65µA
GATE
5V
OUT
TIMER
51mV, TIMER LO
150mV, TIMER HI
55mV
12V
IN
15
5V
SENSE
14
12V
IN
1
12V
OUT
20
5V
IN
13
–
+
+–
+–
2.5V
UVL
8.3V
UVL
–
+
+–
3V
OUT
55mV
CP3
REF
3V
SENSE
16
3V
IN
17
RESETOUT
10
–
+
–
+
+–
+–
2.5V
UVL
Q4
1V
Q12
CP4
REF
–
+
+
–
CP7
REF
–
+
CP5
REF
–
+
RESETIN 9
PWRGD 7
Q10
FAULT 6
Q11
OFF/ON 5
Q5Q7
21µA
12V
IN
GND
8
DRIVE
11
PRECHARGE
1644 BD
12
LOGIC
Q1
TIMER
51mV, TIMER LO
150mV, TIMER HI
CP1
A1
CP2
A2
A3
LTC1644
11
1644f
APPLICATIO S I FOR ATIO
WUUU
Hot Circuit Insertion
When a circuit board is inserted into a live CompactPCI
(CPCI) slot, the supply bypass capacitors on the board can
draw huge supply transient currents from the CPCI power
bus as they charge up. The transient currents can cause
glitches on the power bus, causing other boards in the
system to reset.
The LTC1644 is designed to turn a board’s supply voltages
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live CPCI slot without
glitching the system power supplies. The chip also protects
the supplies from shorts, precharges the bus I/O pins during
insertion and extraction and monitors the supply voltages.
The LTC1644 is specifically designed for CPCI applica-
tions where the chip resides on the plug-in board.
LTC1644 Feature Summary
• Allows safe board insertion and removal from a CPCI
backplane.
• Controls all four CPCI supplies: –12V, 12V, 3.3V and 5V.
• Adjustable foldback current limit: an adjustable analog
current limit with a value that depends on the output
voltage. If the output is shorted to ground, the current
limit drops to keep power dissipation and supply glitches
to a minimum.
• 12V and –12V circuit breakers: if either supply remains
in current limit too long, the circuit breaker will trip, the
supplies are turned off and the FAULT pin is pulled low.
• Dual-level, adjustable 5V and 3.3V circuit breakers: if
either supply exceeds current limit for too long, the
circuit breaker will trip, the supplies will be turned off
and the FAULT pin will be asserted. In the event that
either supply exceeds 3 times the nominal current level,
all supplies will be turned off and the FAULT pin will be
asserted immediately.
• Current limit during power up: the supplies are allowed
to power up in current limit. This allows the chip to
power up boards with widely varying capacitive loads
without tripping the circuit breaker. The maximum
allowable power-up time is adjustable using the TIMER
pin.
• 12V and –12V power switches on chip.
• PWRGD output: monitors the voltage status of the four
supply voltages.
• PCI_RST# combined on-chip with HEALTHY# to create
LOCAL_PCI_RST# output. If HEALTHY# deasserts,
LOCAL_PCI_RST# is asserted independent of
PCI_RST#.
• Precharge output: on-chip reference and amplifier pro-
vide 1V for biasing bus I/O connector pins during CPCI
card insertion and extraction.
• Space saving 20-pin SSOP package.
CPCI Power Requirements
CPCI systems usually require four power rails: 5V, 3.3V,
12V and –12V. The tolerance of the supplies as measured
at the components on the plug-in card is summarized in
Table 1.
Table 1. Compact PCI Power Specifications
SUPPLY TOLERANCE MAX RIPPLE (
P-P
)
5V +5%/–3% 50mV
3.3V +5%/–3% 50mV
12V ±5% 240mV
–12V ±5% 240mV
tOC Overcurrent Fault Detect tSC Short-Circuit Fault Detect
TI I G DIAGRA S
WUW
V5VSENSE OR
V3VSENSE
5V OR 3.3V FALL TIME ≤ 1µs
5VIN = 5V, 3VIN = 3.3V
FAULT
100mV
tOC
1644 TD01
1644 TD02
V
5VSENSE
OR
V
3VSENSE
5V OR 3.3V
FAULT
200mV
t
SC
FALL TIME ≤ 10ns
5V
IN
= 5V, 3V
IN
= 3.3V
LTC1644
12
1644f
Power-Up Sequence
The LTC1644 is specifically designed for live insertion and
removal of CPCI boards. The typical application is shown
in Figure 1. The 3.3V, 5V, 12V and –12V inputs to the
LTC1644 come from the medium length power pins. The
long 5V and 3.3V connector pins are connected through
decoupling resistors to the medium length 5V and 3.3V
connector pins on the CPCI plug-in card and provide early
power for the LTC1644’s precharge circuit, pull-up resis-
tors and the PCI bridge chip. The BD_SEL# signal is
connected to the OFF/ON pin while the PWRGD pin is
connected to the HEALTHY# signal. The HEALTHY# signal
is combined with the PCI_RST# signal on-chip to generate
the LOCAL_PCI_RST# signal which is available at the
RESETOUT pin.
The power supplies are controlled by placing external
N-channel pass transistors in the 3.3V and 5V power paths
and internal pass transistors for the 12V and –12V power
paths (Figure 1).
Resistors R1 and R2 provide current fault detection and
R5 and C1 provide current control loop compensation.
Resistors R3 and R4 prevent high frequency oscillations
in Q1 and Q2. Shunt RC snubbers R15-C4 and R16-C5 and
zener diodes Z1 and Z2 prevent the 12V
IN
and V
EEIN
pins,
respectively, from ringing beyond the absolute maximum
rated supply voltages during hot insertion.
When the CPCI card is inserted, the long 5V and 3.3V
connector pins and GND pins make contact first. The
LTC1644’s precharge circuit biases the bus I/O pins to 1V
during this stage of the insertion (Figure 2). The 12V, –12V
and 5V and 3.3V medium length pins make contact during
the next stage of insertion. At this point the LTC1644
powers on but slot power is disabled as long as the OFF/ON
pin is pulled high by the 1.2k pull-up resistor to 5V
IN
.
During the final stage of board insertion, the BD_SEL#
short connector pin makes contact and the OFF/ON pin can
APPLICATIO S I FOR ATIO
WUUU
be pulled low. This enables the pass transistors to turn on
and a 21µA current source is connected to TIMER (Pin␣ 4).
The current in each pass transistor increases until it
reaches the current limit for each supply. The 5V and 3.3V
supplies are then allowed to power up based on one of the
following rates:
Power-up rate: (1)
dV
dt
A
Cor I
Cor I
C
LIMIT V
LOAD VOUT
LIMIT V
LOAD VOUT
=µ==
65
1
5
5
3
3
,,
()
()
()
()
whichever is slower.
Current limit faults are ignored while the TIMER pin
voltage is ramping up and is less than 1V below 12V
IN
(Pin
1). Once all four supply voltages are within tolerance,
HEALTHY# (Pin 7) will pull low and LOCAL_PCI_RST# is
free to follow PCI_RST#.
Power-Down Sequence
When the BD_SEL# is pulled high, a power-down
sequence begins (Figure 3).
Internal switches are connected to each of the output
supply voltage pins to discharge the bypass capacitors to
ground. The TIMER pin is immediately pulled low. The
GATE pin (Pin 15) is pulled down by a 225µA current
source to prevent the load currents on the 3.3V and 5V
supplies from going to zero instantaneously and glitching
the power supply voltages. When any of the output volt-
ages dips below its threshold, the HEALTHY# signal pulls
high and LOCAL_PCI_RST# will be asserted low.
Once the power-down sequence is complete, the CPCI
card may be removed from the slot. During extraction, the
precharge circuit will continue to bias the bus I/O pins at
1V until the 5V and 3.3V long connector pin connections
are broken.
LTC1644
13
1644f
APPLICATIO S I FOR ATIO
WUUU
Figure 3. Normal Power-Down Sequence
Figure 2. Normal Power-Up Sequence
TIMER
During a power-up sequence, a 21µA current source is
connected to the TIMER pin (Pin 4) and current limit faults
are ignored until the voltage ramps to within 1V of 12V
IN
(Pin 1). This feature allows the chip to power up CPCI
boards with widely varying capacitive loads on the sup-
plies. The power-up time for any one of the four outputs is
given by Equation 2:
tXV CXV
II
ON OUT LOAD XVOUT OUT
LIMIT XVOUT LOAD XVOUT
()
=• •
−
2
()
() ()
(2)
where XV
OUT
= 5V
OUT
, 3V
OUT
, 12V
OUT
or V
EEOUT
(–12V).
For example, for C
LOAD(5VOUT)
= 2000µF, I
LIMIT(5VOUT)
=
7A and I
LOAD(5VOUT)
= 5A, the 5V
OUT
turn-on time will be
~10ms. By substituting the variables in Equation 2 with the
appropriate values, the turn-on time for the other three
outputs can be calculated.
The timer period should be set longer than the maximum
supply turn-on time but short enough to not exceed the
maximum safe operating area of the pass transistor during
a short circuit. The timer period for the LTC1644 is given
by:
tCV
A
TIMER TIMER
=•
µ11
21
(3)
As a design aid, the timer period as a function of the timing
capacitor using standard values from 0.01µF to 1µF is
shown in Table 2.
TIMER
10V/DIV
GATE
5V/DIV
12V
OUT
10V/DIV
V
EEOUT
10V/DIV
5V
OUT
10V/DIV
3V
OUT
10V/DIV
LOCAL_PCI_RST#
5V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
PRECHARGE
5V/DIV
10ms/DIV
1644 F02
TIMER
10V/DIV
GATE
5V/DIV
12VOUT
10V/DIV
VEEOUT
10V/DIV
5VOUT
10V/DIV
3VOUT
10V/DIV
LOCAL_PCI_RST#
5V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
PRECHARGE
5V/DIV
10ms/DIV
1644 F03
LTC1644
14
1644f
APPLICATIO S I FOR ATIO
WUUU
Table 2. tTIMER vs CTIMER
C
TIMER
t
TIMER
C
TIMER
t
TIMER
0.01µF 5.24ms 0.22µF 115ms
0.022µF 11.5ms 0.33µF 173ms
0.033µF 17.3ms 0.47µF 246ms
0.047µF 24.6ms 0.68µF 356ms
0.068µF 35.6ms 0.82µF 430ms
0.082µF 43.0ms 1µF 524ms
0.1µF 52.4ms
The TIMER pin is immediately pulled low when the BD_SEL#
signal goes high.
Thermal Shutdown
The internal switches for the 12V and –12V supplies are
protected by an internal current limit and a thermal shut-
down circuit. When the temperature of the chip reaches
130°C, all switches will be latched off and the FAULT pin
(Pin␣ 6) will be pulled low.
Short-Circuit Protection
During a normal power-up sequence, if the TIMER (Pin 4)
is done ramping and any supply is still in current limit, all
of the pass transistors will be immediately turned off and
FAULT (Pin 6) will be pulled low as shown in Figure 4.
In order to prevent excessive power dissipation in the pass
transistors and to prevent voltage spikes on the supplies
during short-circuit conditions, the current limit on each
supply is designed to be a function of the output voltage.
As the output voltage drops, the current limit decreases.
Unlike a traditional circuit breaker function where large
currents can flow before the breaker trips, the current
foldback feature assures that the supply current will be
kept at a safe level. In addition, current foldback prevents
voltage glitches when powering up into a short.
If either the 12V or –12V supply exceeds current limit after
power up, the shorted supply’s current will drop immedi-
ately to its I
LIMIT
value. If that supply remains in current
limit for more that 45µs, all of the supplies will be latched
off. The 45µs delay prevents quick current spikes—for
example, from a fan turning on—from causing false trips
of the circuit breaker.
After power-up, the 5V and 3.3V supplies are protected
from overcurrent and short-circuit conditions by dual-
level circuit breakers. In the event that either supply
current exceeds the nominal limit but is less than 3 times
the current limit, an internal timer is started. If the supply
is still overcurrent after 45µs, the circuit breaker trips and
all the supplies are turned off (Figure 5). If a short-circuit
occurs and the supply current exceeds 3 times the set
limit, the circuit breakers trip without any delay and the
chip latches off (Figure 6). The chip will stay in the latched
off state until OFF/ON (Pin 5) is cycled high then low or the
12V
IN
(Pin 1) power supply is cycled off then on.
The current limit and the foldback current level for the 5V
and 3.3V outputs are both a function of the external sense
resistor (R1 for 3V
OUT
and R2 for 5V
OUT
, see Figure 1). As
shown in Figure 1, a sense resistor is connected between
5V
IN
(Pin 13) and 5V
SENSE
(Pin 12) for the 5V supply. For
the 3V supply, a sense resistor is connected between 3V
IN
(Pin 9) and 3V
SENSE
(Pin 10). The current limit and the
foldback current level are given by Equations 4 and 5:
ImV
R
LIMIT XVOUT SENSE XVOUT
() ()
=51
(4)
ImV
R
FOLDBACK XVOUT SENSE XVOUT
() ()
=12
(5)
where XV
OUT
= 5V
OUT
or 3V
OUT
.
As a design aid, the current limit and foldback level for
commonly used values for R
SENSE
is shown in Table 3.
Table 3. ILIMIT(XVOUT) and IFOLDBACK(XVOUT) vs RSENSE
R
SENSE
(Ω)I
LIMIT(XVOUT)
I
FOLDBACK(XVOUT)
0.005 10.2A 2.4A
0.006 8.5A 2.0A
0.007 7.3A 1.7A
0.008 6.4A 1.5A
0.009 5.7A 1.3A
0.01 5.1A 1.2A
where XV
OUT
= 3V
OUT
or 5V
OUT
.
The current limit for the internal 12V switch is set at
840mA folding back to 360mA and the –12V switch at
320mA folding back to 100mA.
LTC1644
15
1644f
TIMER
10V/DIV
GATE
10V/DIV
5V
IN
– 5V
SENSE
100mV/DIV 50mV
FAULT
5V/DIV
20µs/DIV
1644 F05
TIMER
10V/DIV
GATE
10V/DIV
5V
IN
– 5V
SENSE
100mV/DIV
FAULT
5V/DIV
10µs/DIV
1644 F06
150mV
Figure 5. Overcurrent Fault on 5V Figure 6. Short-Circuit Fault on 5V
20ms/DIV
1644 F04
TIMER
10V/DIV
GATE
5V/DIV
12V
OUT
10V/DIV
V
EEOUT
10V/DIV
5V
OUT
5V/DIV
3V
OUT
5V/DIV
LOCAL_PCI_RST#
5V/DIV
BD_SEL#
5V/DIV
FAULT
5V/DIV
HEALTHY#
5V/DIV
PRECHARGE
5V/DIV
Figure 4. Power-Up into a Short on 3.3V Output
APPLICATIO S I FOR ATIO
WUUU
LTC1644
16
1644f
APPLICATIO S I FOR ATIO
WUUU
Calculating R
SENSE
An equivalent circuit for one of the LTC1644’s circuit
breakers useful in calculating the value of the sense
resistor is shown in Figure 7. To determine the most
appropriate value for the sense resistor first requires the
maximum current required by the load under worst-case
conditions.
–
+
14
LTC1644*
1644 F07
*ADDITIONAL DETAILS OMITTED FOR CLARITY
V
CB(MAX)
= 70mV
V
CB(NOM)
= 55mV
V
CB(MIN)
= 40mV
13
5V
SENSE
5V
IN
R
SENSE
I
LOAD(MAX)
5V
IN
V
CB
+
–
Two other parameters affect the value of the sense resis-
tor. First is the tolerance of the LTC1644’s circuit breaker
threshold. The LTC1644’s nominal circuit breaker thresh-
old is V
CB(NOM)
= 55mV; however, it exhibits ±15mV
tolerance over process and temperature. Second is the
tolerance (RTOL) in the sense resistor. Sense resistors are
available in RTOLs of ±1%, ±2% and ±5% and exhibit
temperature coefficients of resistance (TCRs) between
±75ppm/°C and ±100ppm/°C. How the sense resistor
changes as a function of temperature depends on the I
2
R
power being dissipated by it. The power rating of the sense
resistor should accommodate steady-state fault current
levels so that the component is not damaged before the
circuit breaker trips.
The first step in calculating the value of R
SENSE
is based on
I
LOAD(MAX)
and the lower limit for the circuit breaker
threshold, V
CB(MIN)
. The maximum value for R
SENSE
in this
case is expressed by Equation 6:
RV
I
SENSE CB MIN
LOAD MAX
=
()
()
(6)
Figure 7. Circuit Breaker Equivalent
Circuit for Calculating RSENSE
The second step is to determine the nominal value of
the sense resistor which is dependent on its tolerance
(RTOL␣ = ±1%, ±2%, or ±5%) and standard sense resistor
values. Equation 7 can be used to calculate the nominal
value from the maximum value found by Equation 6:
RR
RTOL
SENSE N M SENSE MAX
() ()
0
1100
=+
(7)
Often, the result of Equation 7 may not yield a standard
sense resistor value. In this case, two sense resistors with
the same RTOL can be connected in parallel to yield
R
SENSE(NOM)
.
The last step requires calculating a new value for I
TRIP(MAX)
(I
TRIP(MAX,NEW)
) based on a minimum value for R
SENSE
(R
SENSE(MIN)
) and the upper limit for the circuit breaker
threshold, V
CB(MAX)
. The new value for I
TRIP(MAX,NEW)
is
given by Equation 8:
IV
R
TRIP MAX NEW CB MAX
SENSE MIN
(,) ()
()
=
(8)
where R R RTOL
SENSE MIN SENSE NOM() ( )
=•−
1100
Table 4 lists I
TRIP(MIN)
and I
TRIP(MAX)
versus some sug-
gested values of R
SENSE
. Table 8 lists manufacturers and
part numbers for these resistor values.
Table 4. ITRIP vs RSENSE Table
R
SENSE
(1% RTOL) I
TRIP(MIN)
I
TRIP(MAX)
0.005Ω7.92A 14.14A
0.007Ω5.66A 10.10A
0.011Ω3.60A 6.43A
0.028Ω1.41A 2.53A
0.055Ω0.72A 1.29A
LTC1644
17
1644f
Output Voltage Monitor
The status of all four output voltages is monitored by the
power good function. In addition, the PCI_RST# signal is
logically combined on-chip with the HEALTHY# signal to
create LOCAL_PCI_RST# (see Table 5). As a result,
LOCAL_PCI_RST# will be pulled low whenever HEALTHY#
is pulled high independent of the state of the PCI_RST#
signal.
Table 5. LOCAL_PCI_RST# Truth Table
PCI_RST# HEALTHY# LOCAL_PCI_RST#
LO LO LO
LO HI LO
HI LO HI
HI HI LO
If any of the output voltages drop below the power good
threshold for more than 10µs, the PWRGD pin will be
pulled high and the LOCAL_PCI_RST# signal will be
asserted low.
Precharge
The PRECHARGE input and DRIVE output pins are in-
tended for use in generating the 1V precharge voltage that
is used to bias the bus I/O connector pins during board
insertion. The LTC1644 is also capable of generating
precharge voltages other than 1V. Figure 8 shows a circuit
that can be used in applications requiring a precharge
voltage less than 1V. The circuit in Figure 9 can be used for
applications that need precharge voltages greater than 1V.
Table 6 lists suggested resistor values for R10A and R10B
vs precharge voltage for the application circuits shown in
Figures 8 and 9.
Table 6. R10A and R10B Resistor Values vs Precharge Voltage
V
PRECHARGE
R10A R10B V
PRECHARGE
R10A R10B
1.5V 18Ω9.09Ω0.9V 16.2Ω1.78Ω
1.4V 18Ω7.15Ω0.8V 14.7Ω3.65Ω
1.3V 18Ω5.36Ω0.7V 12.1Ω5.11Ω
1.2V 18Ω3.65Ω0.6V 11Ω7.15Ω
1.1V 18Ω1.78Ω0.5V 9.09Ω9.09Ω
1V 18Ω0Ω
Due to leakage current constraints, precharge resistor
values of less than 50k are often required. In these
precharge applications, it may also be necessary to dis-
connect the individual resistors from the LTC1644’s
PRECHARGE pin when the plug-in board is completely
seated in the board slot. The circuit in Figure 10 uses a bus
switch to connect the individual precharge resistors to the
LTC1644’s PRECHARGE pin while the BD_SEL# pin volt-
age is pulled up to 5V
IN
, i.e., when the BD_SEL# short
connector pin is still unconnected. After the plug-in board
is completely seated, the BD_SEL# pin voltage will drop to
approximately 3.8V (assuming BD_SEL# isn’t asserted
low), and the bus switch OE pin is pulled high by Q2. When
the plug-in card is removed from the connector, the
BD_SEL# connection is broken first and the BD_SEL# pin
voltage pulls up to 5V. This causes Q2 to turn off, which re-
enables the bus switch and the precharge resistors are
reconnected to the LTC1644’s PRECHARGE pin for the
remainder of the board extraction process.
Other CompactPCI Applications
The LTC1644 can be easily configured for applications
where no V
EE
supply is present by simply connecting the
V
EEIN
pin to GND and floating the V
EEOUT
pin (Figure␣ 11).
For CPCI applications where no 5V supply input is re-
quired, short both the 5V
IN
and 5V
SENSE
pins to the 3V
IN
pin and short the 5V
OUT
pin to the 3V
OUT
pin (Figure␣ 12).
If no 3.3V supply input is required, Figure 13 illustrates
how the LTC1644 should be configured. First, 3V
SENSE
(Pin 16) is connected to 3V
IN
(Pin 17), 3V
OUT
(Pin 18) is
connected to 5V
OUT
(Pin 3) and the LTC1644’s 3V
IN
pin is
connected through a pair of signal diodes (BAV99) to 5V
IN
.
For applications where the BD_SEL# connector pin is
typically grounded on the backplane, the circuit in
Figure␣ 14 allows the LTC1644 to be reset simply by
pressing a pushbutton switch on the CPCI plugin board.
This arrangement eliminates the requirement to extract
and reinsert the CPCI board in order to reset the LTC1644’s
circuit breakers.
Power MOSFET Selection Criteria
Three device parameters are key in selecting the optimal
power MOSFET for Hot Swap applications. The three
parameters are: (1) device power dissipation (P
D
); (2)
device drain-source channel ON resistance, R
DS(ON)
; and
APPLICATIO S I FOR ATIO
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LTC1644
18
1644f
APPLICATIO S I FOR ATIO
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OFF/ON
5V
IN
5V
IN
5
13
LTC1644*
1644 F10
R13
10Ω 5%
R14
10Ω 5%
I/O
I/O
PCI
BRIDGE
CHIP
UP TO 128 I/O LINESDATA BUS
3V
IN
GND PRECHARGE
12
DRIVE
11
Q1
MMBT2222A
8
R11
10k
5%
R12
10k
5%
PRECHARGE OUT
1V ±10%
I
OUT
= ±55mA
R10
18Ω 5%
Q2
MMBT3906
R24
75k
5%
R19
1k 5%
R20
1.2k
5%
R22 2.74Ω
R23
51k 5%
R8
1k 5%
R7
12Ω 5%
C3 4.7nF R9
24Ω
Z4: 1PMT5.0AT3
*ADDITIONAL PINS OMITTED FOR CLARITY
PCB EDGE
BACKPLANE
CONNECTOR
BACKPLANE
CONNECTOR
5V
LONG 5V
BD_SEL#
GROUND
I/O PIN 1
I/O PIN 128
• • •
• • •
• • •
Z4
C7
0.01µF
C9 0.1µF
PER 10
POWER PINS
BUS SWITCH
OE
Figure 10. Precharge Circuit with Bus Switch
MMBT2222A
C3 4.7nF R9
18Ω
R10A R10B
R8
1k
R7
12Ω
3V
IN
PRECHARGE OUT
1644 F08
GND PRECHARGE DRIVE
LTC1644*
81211
*ADDITIONAL DETAILS OMITTED FOR CLARITY
V
PRECHARGE
= • 1V
R10A
R10A + R10B
Figure 8. Precharge Voltage <1V Application Circuit Figure 9. Precharge Voltage >1V Application Circuit
MMBT2222A
C3 4.7nF R9
18Ω
R10A R10B
R8
1k
R7
12Ω
3V
IN
PRECHARGE OUT
1644 F09
GND PRECHARGE DRIVE
LTC1644*
812 11
*ADDITIONAL DETAILS OMITTED FOR CLARITY
V
PRECHARGE
= • 1V
R10A + R10B
R10A
(3) the gate-source (V
GS
) voltage drive for the specified
R
DS(ON)
. Power MOSFET power dissipation is dependent
on four parameters: current delivered to the load, I
LOAD
;
device R
DS(ON)
; device thermal resistance, junction-to-
ambient, θ
JA
; and the maximum ambient temperature to
which the circuit will be exposed, T
A(MAX)
. All four of these
parameters determine the junction temperature of the
MOSFET. For reliable circuit operation, the maximum
junction temperature (T
J(MAX)
) for a power MOSFET should
not exceed the manufacturer’s recommended value. For a
given set of conditions, the junction temperature of a
power MOSFET is given by Equation 9:
MOSFET Junction Temperature, (9)
T
J(MAX)
≤ T
A(MAX)
+ θ
JA
• P
D
where P
D
= I
LOAD
• R
DS(ON)
PCB layout techniques for optimal thermal management
of power MOSFET power dissipation help to keep device
θ
JA
as low as possible. See PCB Layout Considerations
section for more information.
The R
DS(ON)
of the external pass transistor should be low
to make its drain-source voltage (V
DS
) a small percentage
of 3V
IN
or 5V
IN
. For example, at 3V
IN
= 3.3V, V
DS
+ V
CB
=
0.1V yields a 3% error at maximum load current. This
LTC1644
19
1644f
APPLICATIO S I FOR ATIO
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Figure 12. No 5V Supply Application Circuit
C1
0.047µF
GND
3V
IN
3V
IN
R21 1.74Ω
3V
SENSE
17
3V
OUT
18
5V
IN
LTC1644*
13
C6
0.01µF
5V
OUT
3
5V
SENSE
14 16
GATE
15
8
R3
10Ω
3V
OUT
1644 F12
R5
1k
R1
0.005ΩQ1
IRF7413
Z3: 1PMT5.0AT3
*ADDITIONAL PINS OMITTED FOR CLARITY
PCB EDGE
BACKPLANE
CONNECTOR
BACKPLANE
CONNECTOR
3.3V
LONG 3.3V
GROUND
Z3
C8 0.1µF
PER 10
POWER PINS
C1
0.047µF
C4
0.01µF
GND
12VIN
VEEIN
OFF/ON
FAULT
PWRGD
RESETIN
3VIN
3VIN*
R22 2.74Ω
5VIN*
3VSENSE
17
3VOUT
18
5VIN
LTC1644
13
PRECHARGE DRIVE
5VOUT
3
5VSENSE
1416
GATE
15
1
2
5
6
7
9
12VOUT
VEEOUT
TIMER
RESETOUT
20
19
4
EARLY V(I/O)
R18
2k
R19
1k
R20 1.2k
R3
10Ω
5VIN
R21 1.74Ω
R4
10Ω
R17
2k
5VOUT
3VOUT
12VOUT
VEEOUT
NC
R5
1k
R1
0.005ΩQ1
IRF7413
Q2
IRF7413
R2
0.007Ω
C2
0.1µF
R15
1Ω12 11
10
Z1
Z1: SMAJ12CA Z3, Z4: 1PMT5.0AT3
*5VIN AND 3VIN MAY BE USED AS SOURCES OF EARLY POWER
I/O DATA LINE 1
I/O DATA LINE 128
I/O #1
1644 F11
Q3
MMBT2222A
8
R11
51k
R10
18Ω 5% 3VIN
3VOUT
R13
10Ω
I/O #128
R14
10Ω
R12
51k 1V
±10%
R6
2k
R8 1k
R7
12Ω
C3 4.7nF R9
24Ω
RESET#
PCI
BRIDGE
(21154)
PCB EDGE
BACKPLANE
CONNECTOR
C8 0.1µF
PER 10
POWER
PINS
Z3
C7
0.01µF
C6
0.01µF
BACKPLANE
CONNECTOR
5V
LONG 5V
3.3V
LONG 3.3V
12V
BD_SEL#
HEALTHY#
PCI_RST#
GROUND
I/O PIN 1
I/O PIN 128
• • •
I/O #1
I/O #128
• • •
• • •
CLOAD(5VOUT)
CLOAD(3VOUT)
CLOAD(12VOUT)
Z4
C9 0.1µF
PER 10
POWER
PINS
+
+
+
Figure 11. No VEE (–12V) Supply Application Circuit
LTC1644
20
1644f
C1
0.047µF
GND
5V
IN
5V
IN
D1
5V
SENSE
13
5V
OUT
3
3V
IN
LTC1644*
17
3V
OUT
18
3V
SENSE
16 14
GATE
15
8
R4
10Ω
5V
OUT
1644 F13
R5
1k
R2
0.007ΩQ2
IRF7413
D2
NCZ4
D1, D2: BAV99
Z4: 1PMT5.0AT3
*ADDITIONAL PINS OMITTED FOR CLARITY
PCB EDGE
BACKPLANE
CONNECTOR
BACKPLANE
CONNECTOR
5V
LONG 5V
GROUND
R22 2.74Ω
C6
0.01µF
C9 0.1µF
PER 10
POWER PINS
Figure 13. No 3.3V Supply Application Circuit
APPLICATIO S I FOR ATIO
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Figure 14. BD_SEL# Pushbutton Toggle Switch
GND
LTC1644*
8
1.2k
PUSHBUTTON
SWITICH
100Ω
5V
IN
1k
GROUND
OFF/ON
5
BD_SEL#
1644 F14
*ADDITIONAL PINS OMITTED FOR CLARITY
PCB EDGE
BACKPLANE
CONNECTOR
BACKPLANE
CONNECTOR
restricts the choice of power MOSFETs to those devices
with very low R
DS(ON)
. Table 9 lists some power MOSFETs
that can be used with the LTC1644.
Power MOSFETs are classified into two categories: stan-
dard MOSFETs (R
DS(ON)
specified at V
GS
= 10V) and logic-
level MOSFETs (R
DS(ON)
specified at V
GS
= 5V). Since
external pass transistors are required for the 3.3V and 5V
supply rails, logic-level power MOSFETs should be used
with the LTC1644.
Overvoltage Transient Protection
Good engineering practice calls for bypassing the supply
rail of any analog circuit. Bypass capacitors are often
placed at the supply connection of every active device, in
addition to one or more large-value bulk bypass capacitors
per supply rail. If power is connected abruptly, the large
bypass capacitors slow the rate of rise of the supply
voltage and heavily damp any parasitic resonance of lead
or PC track inductance working against the supply bypass
capacitors.
The opposite is true for LTC1644 Hot Swap circuits
mounted on plug-in cards. In most cases, there is no
supply bypass capacitor present on the powered 12V
(12V
IN
), –12V (V
EEIN
) of the PCB edge connector or on the
3.3V (3V
IN
) or the 5V (5V
IN
) side of the MOSFET switch. An
abrupt connection, produced by inserting the board into a
backplane connector, results in a fast rising edge applied
on these input supply lines of the LTC1644.
Since there is no bulk capacitance to damp the parasitic
track inductance, supply voltage transients excite para-
sitic resonant circuits formed by the power MOSFET
capacitance and the combined parasitic inductance from
the wiring harness, the backplane and the circuit board
traces. These ringing transients appear as a fast edge on
the input supply lines, exhibiting a peak overshoot up to
2.5 times the steady-state value followed by a damped
LTC1644
21
1644f
APPLICATIO S I FOR ATIO
WUUU
that in all LTC1644 circuit schematics, zener diodes and
snubber networks have been added to the 12V
IN
and V
EEIN
(–12V) supply rail and should be used always. Since the
absolute maximum supply voltage of the LTC1644 is
13.2V, snubber networks are not necessary on the 3V
IN
or
the 5V
IN
supply lines. Zener diodes, however, are recom-
mended as these devices provide large-scale transient
protection for the LTC1644 against PCI backplane fault
occurrences. All protection networks should be mounted
very close to the LTC1644’s supply voltage using short
lead lengths to minimize lead inductance. This is shown
schematically in Figures 15 and 16 and a recommended
layout of the transient protection devices around the
LTC1644 is shown in Figure 17.
sinusoidal response whose duration and period is depen-
dent on the resonant circuit parameters. Since the abso-
lute maximum supply voltage of the LTC1644 is 13.2V,
transient protection against 12VIN and VEEIN supply volt-
age spikes and ringing is highly recommended.
In these applications, there are two methods for eliminat-
ing these supply voltage transients: using Zener diodes to
clip the transient to a safe level and snubber networks.
Snubber networks are series RC networks whose time
constants are experimentally determined based on the
board’s parasitic resonant circuits. As a starting point, the
capacitors in these networks are chosen to be 10× to 100×
the power MOSFET’s C
OSS
under bias. The series resistor
is a value determined experimentally and ranges from 1Ω
to 50Ω, depending on the parasitic resonant circuit. Note
Figure 15. Place Transient Protection Devices Close to LTC1644’s 5VIN and 3VIN Pins
C1
0.047µF
3V
IN
3V
IN
3.3V
5V
IN
5V
3V
SENSE
17
3V
OUT
18
5V
IN
13
5V
OUT
3
5V
SENSE
1416
GATE
15
R3
10ΩR4
10Ω
5V
OUT
5V
3V
OUT
3.3V
R5
1k
R1
0.005ΩQ1
IRF7413
Q2
IRF7413
R2
0.007Ω
Z3 Z4
LTC1644*
1644 F15
GND
8
Z3, Z4: 1PMT5.0AT3
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 16. Place Transient Protection Devices
Close to LTC1644’s 12VIN and VEEIN Pins Figure 17. Recommended Layout for Transient Protection Components
12V
IN
1
V
EEIN
12V
IN
–12V
IN
2
Z1 Z2
R16
1Ω
C5
0.01µF
LTC1644*
1644 F16
GND
8
Z1, Z2: SMAJ12CA
*ADDITIONAL DETAILS OMITTED FOR CLARITY
R15
1Ω
C4
0.01µF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VIAS TO
GND PLANE
C4
R13
GND
5V
IN
LTC1644*
*ADDITIONAL DETAILS OMITTED FOR CLARITY
DRAWING IS NOT TO SCALE!
1644 F17
3V
IN
V
EEIN
12V
IN
Z1
Z2
Z3 Z4
C5
R14
LTC1644
22
1644f
APPLICATIO S I FOR ATIO
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Table 7. Manufacturers’ Web Site
MANUFACTURER WEB SITE
International Rectifier www.irf.com
ON Semiconductor www.onsemi.com
IRC-TT www.irctt.com
Vishay-Dale www.vishay.com
Vishay-Siliconix www.vishay.com
Diodes, Inc. www.diodes.com
Obtaining Information on Specific Parts
For more information regarding or to request a copy of the
CompactPCI specification, contact the PCI Industrial Com-
puter Manufacturers Group at:
PCI Industrial Computer Manufacturers Group
Wakefield, MA 01880 USA
Phone: 01 (617) 224-1100
Web Site: http://www.picmg.com
TransZorb SMAJ12CA and diodes BAV99 are supplied by:
Diodes, Incorporated
Westlake Village, CA 91362 USA
Phone: 01 (805) 446-4800
Web Site: http://www.vishay-liteon.com or
http://www.diodes.com
Transistors MMBT2222A and TVS 1PMT5.0AT3 are
supplied by:
Semiconductor Components Industries, LLC
Phoenix, AZ 85008 USA
Phone: 01 (602) 244-6600
Web Site: http://www.onsemi.com
PCB Layout Considerations
For proper operation of the LTC1644’s circuit breaker
operation, 4-wire Kelvin-sense connections between the
sense resistor and the LTC1644’s 5V
IN
and 5V
SENSE
pins
and 3V
IN
and 3V
SENSE
pins are strongly recommended.
The PCB layout should be balanced and symmetrical to
minimize wiring errors. In addition, the PCB layout for the
sense resistors and the power MOSFETs should include
good thermal management techniques for optimal device
power dissipation.
A recommended PCB layout for the sense resistor, the
power MOSFET and the GATE drive components around
the LTC1644 is illustrated in Figure 18. In Hot Swap
applications where load currents can be 10A, narrow PCB
tracks exhibit more resistance than wider tracks and
operate at more elevated temperatures. Since the sheet
resistance of 1 ounce copper foil is approximately
0.45mΩ/■■, track resistances add up quickly in high
current applications. Thus, to keep PCB track resistance
and temperature rise to a minimum, the suggested trace
width in these applications for 1 ounce copper foil is 0.03"
for each ampere of DC current.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
the PC board. For 1 ounce copper foil plating, a general rule
is 1 ampere of DC current per via, making sure the via is
properly dimensioned so that solder completely fills any
void. For other plating thicknesses, check with your PCB
fabrication facility.
Power MOSFET and Sense Resistor Selection
Table 8 lists some current sense resistors that can be used
the LTC1644’s circuit breakers and Table 9 list some
power MOSFET transistors that are available. Table 7 lists
supplier web site addresses for discrete component men-
tioned throughout the LTC1644 data sheet.
LTC1644
23
1644f
Table 8. Sense Resistor Selection Guide
CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER
1A LR120601R055F 0.055Ω, 0.5W, 1% Resistor IRC-TT
WSL1206R055 Vishay-Dale
2A LR120601R028F 0.028Ω, 0.5W, 1% Resistor IRC-TT
WSL1206R028 Vishay-Dale
5A LR120601R011F 0.011Ω, 0.5W, 1% Resistor IRC-TT
WSL2010R011 Vishay-Dale
7.6A WSL2512R007 0.007Ω, 1W, 1% Resistor Vishay-Dale
10A WSL2512R005 0.005Ω, 1W, 1% Resistor Vishay-Dale
Table 9. N-Channel Power MOSFET Selection Guide
CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER
0 to 2 MMDF3N02HD Dual N-Channel SO-8 ON Semiconductor
R
DS(ON)
= 0.1Ω
2 to 5 MMSF5N02HD Single N-Channel SO-8 ON Semiconductor
R
DS(ON)
= 0.025Ω
5 to 10 MTB50N06V Single N-Channel DD Pak ON Semiconductor
R
DS(ON)
= 0.028Ω
5 to 10 IRF7413 Single N-Channel SO-8 International Rectifier
R
DS(ON)
= 0.01Ω
5 to 10 Si4410DY Single N-Channel SO-8 Vishay-Siliconix
R
DS(ON)
= 0.01Ω
APPLICATIO S I FOR ATIO
WUUU
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
.337 – .344*
(8.560 – 8.737)
GN20 (SSOP) 0502
12
345678910
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
1617181920 15 14 13 12 11
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
.008 – .012
(0.203 – 0.305)
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.058
(1.473)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 TYP.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
GN Package
20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
LTC1644
24
1644f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
LT/TP 0203 2K • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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Fast Circuit Breaker
Figure 18. Recommended Layout for Power MOSFET, Sense Resistor and GATE Components for the 3.3V Rail
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LTC1644*
CURRENT FLOW
TO SOURCE
*ADDITIONAL DETAILS OMITTED FOR CLARITY
DRAWING IS NOT TO SCALE!
1644 F18
TRACK WIDTH W:
0.03" PER AMPERE
ON 1OZ Cu FOIL
D
D
D
D
G
S
S
S
CURRENT FLOW
TO LOAD CURRENT FLOW
TO LOAD
SENSE
RESISTOR SO-8
VIA TO
GND PLANE
GNDGND
3V
OUT
3.3V
3V
IN
3.3V
VIA/PATH
TO GND
GATE
R3
R5
C1
C
TIMER
WW
W
APPLICATIO S I FOR ATIO
WUUU
