2012-2013 Microchip Technology Inc. DS20005155B-page 1
23A512/23LC512
Device Selection Table
Features:
• SPI-Compatible Bus Interface:
- 20 MHz Clock rate
- SPI/SDI/SQI mode
• Low-Power CMOS Technology:
- Read Current: 3 mA at 5.5V, 20 MHz
- Standby Current: 4 A at +85°C
• Unlimited Read and Write Cycles
• Zero Write Time
• 64K x 8-bit Organization:
- 32-byte page
• Byte, Page and Sequential mode for Reads and
Writes
• High Reliability
• Temperature Ranges Supported:
• RoHS Compliant
• 8-Lead SOIC, TSSOP and PDIP Packages
Pin Function Table
Description:
The Microchip Technology Inc. 23A512/23LC512 are
512Kbit Serial SRAM devices. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK) plus separate data in (SI) and data
out (SO) lines. Access to the device is controlled
through a Chip Select (CS) input. Additionally, SDI
(Serial Dual Interface) and SQI (Serial Quad Interface)
is supported if your application needs faster data rates.
This device also supports unlimited reads and writes to
the memory array.
The 23A512/23LC512 is available in standard
packages including 8-lead SOIC, PDIP and advanced
8-lead TSSOP.
Package Types (not to scale)
Part
Number VCC Range Temp.
Ranges
Dual I/O
(SDI)
Quad I/O
(SQI)
Max. Clock
Frequency Packages
23A512 1.7-2.2V I, E Yes Yes 20 MHz(1) SN, ST, P
23LC512 2.5-5.5V I, E Yes Yes 20 MHz(1) SN, ST, P
Note 1: 16 MHz for E-temp.
- Industrial (I): -40Cto +85C
- Automotive (E): -40C to +125C
Name Function
CS Chip Select Input
SO/SIO1 Serial Output/SDI/SQI Pin
SIO2 SQI Pin
VSS Ground
SI/SIO0 Serial Input/SDI/SQI Pin
SCK Serial Clock
HOLD/SIO3 Hold/SQI Pin
VCC Power Supply
CS
SO/SIO1
SIO2
VSS
VCC
HOLD/SIO3
SCK
SI/SIO0
1
2
3
4
8
7
6
5
SOIC/TSSOP/PDIP
512Kbit SPI Serial SRAM with SDI and SQI Interface
23A512/23LC512
DS20005155B-page 2 2012-2013 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +0.3V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias.............................................................................................................-40°C to +125°C
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C
Automotive (E): T
A = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Typ. Max. Units Test Conditions
D001 VCC Supply voltage 1.7
2.5
—2.2
5.5
V 23A512
23LC512
D002 VIH High-level input
voltage
0.7 VCC —VCC + 0.3 V —
D003 VIL Low-level input
voltage
-0.3 —
0.2 V
CC
0.1 V
CC
V 23A512
23LC512
D004 VOL Low-level output
voltage
——0.2VIOL = 1 mA
D005 VOH High-level output
voltage
VCC - 0.5 — — V IOH = -400 A
D006 ILI Input leakage
current
—— ±1ACS = VCC, VIN = VSS OR VCC
D007 ILO Output leakage
current
—— ±1ACS = VCC, VOUT = VSS OR VCC
D008 ICC Read Operating current —
—
1
3
10
10
mA
mA
FCLK = 20 MHz; SO = O, 2.2V
FCLK = 20 MHz; SO = O, 5.5V
D009 ICCS Standby current —
—
—
—
1
—
4
—
4
12
10
20
A
A
A
A
CS = VCC = 2.2V, Inputs tied to
VCC or VSS, I-Temp
CS = VCC = 2.2V, Inputs tied to
VCC or VSS, E-Temp
CS = VCC = 5.5V, Inputs tied to
VCC or VSS, I-Temp
CS = VCC = 5.5V, Inputs tied to
VCC or VSS, E-Temp
D010 CINT Input capacitance — — 7 pF VCC = 5.0V, f = 1 MHz, TA = 25°C
(Note 1)
D011 VDR RAM data retention
voltage
—1.0 — V(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This is the limit to which VCC can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
3: Typical measurements taken at room temperature.
2012-2013 Microchip Technology Inc. DS20005155B-page 3
23A512/23LC512
TABLE 1-3: AC TEST CONDITIONS
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
1FCLK Clock frequency — 20
16
MHz I-Temp
E-Temp
2TCSS CS setup time 25
32
—ns
I-Temp
E-Temp
3T
CSH CS hold time 50 — ns —
4T
CSD CS disable time 25
32
—ns
I-Temp
E-Temp
5 Tsu Data setup time 10 — ns —
6T
HD Data hold time 10 — ns —
7TRCLK rise time — 20 ns (Note 1)
8T
FCLK fall time — 20 ns (Note 1)
9THI Clock high time 25
32
—ns
I-Temp
E-Temp
10 TLO Clock low time 25
32
—ns
I-Temp
E-Temp
11 TCLD Clock delay time 25
32
—ns
I-Temp
E-Temp
12 TVOutput valid from clock low —25
32
ns I-Temp
E-Temp
13 THO Output hold time 0 — ns (Note 1)
14 TDIS Output disable time —20ns
—
15 THS HOLD setup time 10 — ns —
16 THH HOLD hold time 10 — ns —
17 THZ HOLD low to output High-Z 10 — ns —
18 THV HOLD high to output valid — 50 ns —
Note 1: This parameter is periodically sampled and not 100% tested.
AC Waveform:
Input pulse level 0.1 VCC to 0.9 VCC
Input rise/fall time 5 ns
CL = 30 pF —
Timing Measurement Reference Level:
Input 0.5 VCC
Output 0.5 VCC
23A512/23LC512
DS20005155B-page 4 2012-2013 Microchip Technology Inc.
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING (SPI MODE)
FIGURE 1-3: SERIAL OUTPUT TIMING (SPI MODE)
CS
SCK
SO
SI
HOLD
16
15 15 16
18
17
Don’t Care 5
High-Impedance
n + 2 n + 1 n n - 1
n
n + 2 n + 1 n nn - 1
CS
SCK
SI
SO
65
8
711
3
LSB in
MSB in
High-Impedance
2
4
CS
SCK
SO
10
9
12
MSB out LSB out
3
14
Don’t Care
SI
13
2012-2013 Microchip Technology Inc. DS20005155B-page 5
23A512/23LC512
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 23A512/23LC512 is an 512Kbit Serial SRAM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol. In addition, the 23A512/
23LC512 is also capable of operating in SDI/SQI high
speed SPI mode.
The 23A512/23LC512 contains an 8-bit instruction reg-
ister. The device is accessed via the SI pin, with data
being clocked in on the rising edge of SCK. The CS pin
must be low for the entire operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
2.2 Modes of Operation
The 23x512 has three modes of operation that are
selected by setting bits 7 and 6 in the MODE register.
The modes of operation are Byte, Page and Burst.
Byte Operation
– is selected when bits 7 and 6 in the
MODE register are set to
00
. In this mode, the read/
write operations are limited to only one byte. The
Command followed by the 16-bit address is clocked into
the device and the data to/from the device is transferred
on the next eight clocks (Figure 2-1, Figure 2-2).
Page Operation
– is selected when bits 7 and 6 in the
MODE register are set to
10
. The 23x512 has 2048
pages of 32 bytes. In this mode, the read and write oper-
ations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (Figure 2-3, Figure 2-4).
Sequential Operation
– is selected when bits 7 and 6
in the MODE register are set to
01
. Sequential opera-
tion allows the entire array to be written to and read
from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to
0x0000
(Figure 2-5, Figure 2-6).
2.3 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 23A512/23LC512
followed by the 16-bit address. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (FFFFh),
the address counter rolls over to address 0000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS
pin.
2.4 Write Sequence
Prior to any attempt to write data to the 23A512/
23LC512, the device must be selected by bringing CS
low.
Once the device is selected, the Write command can
be started by issuing a WRITE instruction, followed by
the 16-bit address, and then the data to be written. A
write is terminated by the CS being brought high.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is automati-
cally incremented. When the Address Pointer reaches
the highest address (FFFFh), the address counter rolls
over to (0000h). This allows the operation to continue
indefinitely, however, previous data will be overwritten.
23A512/23LC512
DS20005155B-page 6 2012-2013 Microchip Technology Inc.
FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE)
FIGURE 2-2: BYTE WRITE SEQUENCE (SPI MODE)
TABLE 2-1: INSTRUCTION SET
Instruction Name Instruction Format Hex
Code Description
READ 0000 0011 0x03 Read data from memory array beginning at selected address
WRITE 0000 0010 0x02 Write data to memory array beginning at selected address
EDIO 0011 1011 0x3B Enter Dual I/O access
EQIO 0011 1000 0x38 Enter Quad I/O access
RSTIO 1111 1111 0xFF Reset Dual and Quad I/O access
RDMR 0000 0101 0x05 Read Mode Register
WRMR 0000 0001 0x01 Write Mode Register
SO
SI
SCK
CS
0 234567891011 21222324252627282930311
0100000115 14 13 12 210
76543210
Instruction 16-bit Address
Data Out
High-Impedance
SO
SI
CS
9 1011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte
High-Impedance
SCK
0 23456718
2012-2013 Microchip Technology Inc. DS20005155B-page 7
23A512/23LC512
FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE)
FIGURE 2-4: PAGE WRITE SEQUENCE (SPI MODE)
76543210
Page X, Word Y
SI
CS
9 1011 2122232425262728293031
15 14 13 12 210
16-bit Address
SCK
0 23456718
SO
CS
76543210
Page X, Word 0
SCK
32 34 35 36 37 38 3933
76543210
Page X, Word 31
76543210
Page X, Word Y+1
Page X, Word Y
SO
High-Impedance
SI
01000001
Instruction
SI
CS
9 1011 2122232425262728293031
15 14 13 12 21076543210
16-bit Address
SCK
0 23456718
CS
SI 76543210
Page X, Word 0
76543210
Page X, Word 31
76543210
Page X, Word Y+1
Page X, Word Y
Page X, Word Y
SCK
32 34 35 36 37 38 3933
00000001
Instruction
23A512/23LC512
DS20005155B-page 8 2012-2013 Microchip Technology Inc.
FIGURE 2-5: SEQUENTIAL READ SEQUENCE (SPI MODE)
SI
CS
9 1011 2122232425262728293031
15 14 13 12 210
76543210
Instruction 16-bit Address
Page X, Word Y
SCK
0 23456718
SO
CS
76543210
Page X+1, Word 1
SCK
76543210
Page X+1, Word 0
76543210
Page X, Word 31
SO
CS
76543210
Page X+n, Word 31
SCK
76543210
Page X+n, Word 1
76543210
Page X+1, Word 31
SO
SI
SI
01000001
2012-2013 Microchip Technology Inc. DS20005155B-page 9
23A512/23LC512
FIGURE 2-6: SEQUENTIAL WRITE SEQUENCE (SPI MODE)
SI
CS
9 1011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte 1
SCK
0 23456718
SI
CS
41 42 43 46 47
76543210
Data Byte n
SCK
32 34 35 36 37 38 3933 40
76543210
Data Byte 3
76543210
Data Byte 2
44 45
23A512/23LC512
DS20005155B-page 10 2012-2013 Microchip Technology Inc.
2.5 Read Mode Register Instruction
(RDMR)
The Read Mode Register instruction (RDMR) provides
access to the MODE register. The MODE register may
be read at any time. The MODE register is formatted as
follows:
TABLE 2-2: MODE REGISTER
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
0 0 = Byte mode
1 0 = Page mode
0 1 = Sequential mode (default operation)
1 1 = Reserved
Bits 0 through 5 are reserved and should always be set
to ‘0’.
See Figure 2-7 for the RDMR timing sequence.
FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE (RDMR)
76543210
W/R W/R – – – – – –
MODE MODE 00000 0
W/R = writable/readable
SO
SI
CS
9101112131415
11000000
7654 2 10
Instruction
Data from MODE Register
High-Impedance
SCK
0 23456718
3
2012-2013 Microchip Technology Inc. DS20005155B-page 11
23A512/23LC512
2.6 Write Mode Register Instruction
(WRMR)
The Write Mode Register instruction (WRMR) allows the
user to write to the bits in the MODE register as shown
in Table 2-2. This allows for setting of the Device
Operating mode. Several of the bits in the MODE
register must be cleared to ‘0’. See Figure 2-8 for the
WRMR timing sequence.
FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE (WRMR)
2.7 Power-On State
The 23A512/23LC512 powers on in the following state:
• The device is in low-power Standby mode
(CS =1)
• A high-to-low-level transition on CS is required to
enter active state
SO
SI
CS
9101112131415
01000000
7654 210
Instruction Data to MODE Register
High-Impedance
SCK
0 23456718
3
23A512/23LC512
DS20005155B-page 12 2012-2013 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3 - 1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
When the device is deselected, SO goes to the high-
impedance state, allowing multiple parts to share the
same SPI bus. After power-up, a low level on CS is
required, prior to any sequence being initiated.
3.2 Serial Output (SO)
The SO pin is used to transfer data out of the 23A512/
23LC512. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
3.3 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
3.4 Serial Dual Interface Pins(SIO0,
SIO1)
The SIO0 and SIO1 pins are used for SDI mode of
operation. Functionality of these I/O pins is shared with
SO and SI.
3.5 Serial Quad Interface Pins (SIO0 –
SIO3)
The SIO0 through SIO3 pins are used for SQI mode of
operation. Because of the shared functionality of these
pins the HOLD feature is not available when using SQI
mode.
3.6 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 23A512/23LC512. Instruc-
tions, addresses or data present on the SI pin are
latched on the rising edge of the clock input, while data
on the SO pin is updated after the falling edge of the
clock input.
3.7 Hold Function (HOLD)
The HOLD pin is used to suspend transmission to the
23A512/23LC512 while in the middle of a serial
sequence without having to re-transmit the entire
sequence over again. It must be held high any time
this function is not being used. Once the device is
selected and a serial sequence is underway, the
HOLD pin may be pulled low to pause further serial
communication without resetting the serial sequence.
The HOLD pin should be brought low while SCK is
low, otherwise the HOLD function will not be invoked
until the next SCK high-to-low transition. The 23A512/
23LC512 must remain selected during this sequence.
The SI and SCK levels are “don’t cares” during the
time the device is paused and any transitions on these
pins will be ignored. To resume serial communication,
HOLD should be brought high while the SCK pin is
low, otherwise serial communication will not be
resumed until the next SCK high-to-low transition.
The SO line will tri-state immediately upon a high-to
low transition of the HOLD pin, and will begin
outputting again immediately upon a subsequent low-
to-high transition of the HOLD pin, independent of the
state of SCK.
Hold functionality is not available when operating in
SQI mode.
Name
SOIC/
PDIP
TSSOP
Function
CS 1 Chip Select Input
SO/SIO1 2 Serial Data Output/SDI/SQI
Pin
SIO2 3 SQI Pin
VSS 4Ground
SI/SIO0 5 Serial Data Input/SDI/SQI Pin
SCK 6Serial Clock Input
HOLD/SIO3 7 Hold/SQI Pin
VCC 8 Power Supply
2012-2013 Microchip Technology Inc. DS20005155B-page 13
23A512/23LC512
3.8 SPI/SDI and SQI Pin Designations
CS
SIO1
NC
Vss
Vcc
HOLD
SCK
SIO0
1
2
3
4
8
7
6
5
SDI Mode:
CS
SIO1
SIO2
Vss
Vcc
SIO3
SCK
SIO0
1
2
3
4
8
7
6
5
SQI Mode:
CS
SO
NC
Vss
Vcc
HOLD
SCK
SI
1
2
3
4
8
7
6
5
SPI Mode:
Note: Pin 3 should not be left floating when
using SPI/SDI mode.
23A512/23LC512
DS20005155B-page 14 2012-2013 Microchip Technology Inc.
4.0 DUAL AND QUAD SERIAL
MODE
The 23A512/23LC512 also supports SDI (Serial Dual)
and SQI (Serial Quad) mode of operation when used
with compatible master devices. As a convention for
SDI mode of operation, two bits are entered per clock
using the SIO0 and SIO1 pins. Bits are clocked MSB
first.
For SQI mode of operation, four bits of data are entered
per clock, or one nibble per clock. The nibbles are
clocked MSB first.
4.1 Dual Interface Mode
The 23A512/23LC512 supports Serial Dual Input (SDI)
mode of operation. To enter SDI mode the EDIO com-
mand must be clocked in (Figure 4-1). It should be
noted that if the MCU resets before the SRAM, the user
will need to determine the serial mode of operation of
the SRAM and reset it accordingly. Byte read and write
sequence in SDI mode is shown in Figure 4-2 and
Figure 4-3.
FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE
4.2 Quad Interface Mode
In addition to the Serial Dual Interface (SDI) mode of
operation Serial Quad Interface (SQI) is also
supported. In this mode the HOLD functionality is not
available. To enter SQI mode the EQIO command must
be clocked in (Figure 4-4).
SCK
0 2345671
SI
High-Impedance
SO
CS
000111 11
2012-2013 Microchip Technology Inc. DS20005155B-page 15
23A512/23LC512
FIGURE 4-2: BYTE READ MODE SDI
FIGURE 4-3: BYTE WRITE MODE SDI
Note: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high.
Note: The first byte read after the address will be a dummy byte.
CS
91011
12 13 14 15 16 17 18 19
02
345 67
18
642014 12 10 8
753115 13 11 9
16-Bit Address
Instruction Dummy Byte
6420
7531
Data Out
SCK
SIO0
SIO1
1000
00 0 1
Note: Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high.
CS
9101112
13 14 15
0234
567
18
642014 12 10 8
753115 13 11 9
16-Bit Address
Instruction Data In
6420
7531
SCK
SIO1
0000
00 0 1
SIO0
23A512/23LC512
DS20005155B-page 16 2012-2013 Microchip Technology Inc.
FIGURE 4-4: ENTER SQI MODE (EQIO) FROM SPI MODE
4.3 Exit SDI or SQI Mode
To exit from SDI mode, the RSTIO command must be
issued. The command must be entered in the current
device configuration, either SDI or SQI, see Figure 4-7
and Figure 4-8.
FIGURE 4-5: BYTE READ MODE SQI
SCK
0 2345671
SI
High-Impedance
SO
CS
00
0111 00
Note: Page and Sequential mode is similar in that additional bytes can be clocked out before CS is brought high.
Note: The first byte read after the address will be a dummy byte.
CS
SCK
023
4567
189
1
012 8 4 0
SIO0
1
013 9 5 1
0
0
0
0
SIO1
SIO2
SIO3
Instruction 16-Bit Address
Dummy
Byte
Data Out
14 10 6 2
15 11 7 3 73
62
51
40
2012-2013 Microchip Technology Inc. DS20005155B-page 17
23A512/23LC512
FIGURE 4-6: BYTE WRITE MODE SQI
FIGURE 4-7: RESET SDI MODE (RSTIO) – FROM SDI MODE
Note: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high.
CS
SCK
023
4567
189
1
012 8 4 0
SIO0
1
013 9 5 1
0
0
0
0
SIO1
SIO2
SIO3
Instruction 16-Bit Address
Data
N
Data N+1
14 10 6 2
15 11 7 3 73
62
51
40
73
62
51
40
SCK
023
1
SIO0
CS
1111
SIO1 11 1 1
23A512/23LC512
DS20005155B-page 18 2012-2013 Microchip Technology Inc.
FIGURE 4-8: RESET SDI/SQI MODE (RSTIO) – FROM SQI MODE
SCK
0 1
SIO0
CS
11
SIO1 11
SIO2 11
SIO3 11
2012-2013 Microchip Technology Inc. DS20005155B-page 19
23A512/23LC512
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
8-Lead SOIC (3.90 mm)
XXXXYYWW
XXXXXXXT
NNN
Example:
SN 1343
23A512I
1L7
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC® designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
8-Lead TSSOP Example:
XXXT
YYWW
NNN
3LAI
1343
1L7
T/XXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
I/P 1L7
23A512
1343
Example:
3
e
Part Number
1st Line Marking Codes
PDIP SOIC TSSOP
23A512 23A512 23A512 3AAT
23LC512 23LC512 23LC512T 3LAT
Note: T = Temperature grade (I, E)
23A512/23LC512
DS20005155B-page 20 2012-2013 Microchip Technology Inc.
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
2012-2013 Microchip Technology Inc. DS20005155B-page 21
23A512/23LC512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
23A512/23LC512
DS20005155B-page 22 2012-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2013 Microchip Technology Inc. DS20005155B-page 23
23A512/23LC512
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23A512/23LC512
DS20005155B-page 24 2012-2013 Microchip Technology Inc.
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2012-2013 Microchip Technology Inc. DS20005155B-page 25
23A512/23LC512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
23A512/23LC512
DS20005155B-page 26 2012-2013 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision A (September 2012)
Initial release.
Revision B (November 2013)
Added E-Temp specs.
2013 Microchip Technology Inc. DS20005155B-page 27
23A512/23LC512
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
23A512/23LC512
DS20005155B-page 28 2013 Microchip Technology Inc.
NOTES:
2012-2013 Microchip Technology Inc. DS20005155B-page 29
23A512/23LC512
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not all possible ordering options
are shown below..
PART NO. X/XX
PackageTape & Reel
Device
Device: 23A512 =
23LC512 =
512 Kbit, 1.7 - 2.2V, SPI Serial SRAM
512 Kbit, 2.5 - 5.5V, SPI Serial SRAM
Tape & Reel: Blank =
T=
Standard packaging (tube)
Ta pe & Re e l
Temperature
Range:
I=
E=
-40C to +85C
-40C to +125C
Package: SN =
ST =
P=
Plastic SOIC (3.90 mm body), 8-lead
Plastic TSSOP (4.4 mm body), 8-lead
Plastic PDIP (300 mil body), 8-lead
Examples:
a) 23A512-I/ST = 512 Kbit, 1.7-2.2V Serial
SRAM, Industrial temp., TSSOP package
b) 23LC512T-I/SN = 512 Kbit, 2.5-5.5V Serial
SRAM, Industrial temp., Tape & Reel, SOIC
package
c) 23LC512-I/P = 512 Kbit, 2.5-5.5V Serial
SRAM, Industrial temp., PDIP package
d) 23A512-E/ST = 512 Kbit, 1.7-2.2V Serial
SRAM, Extended temp., TSSOP package
e) 23LC512T-E/SN = 512 Kbit, 2.5-5.5V Serial
SRAM, Extended temp., Tape & Reel, SOIC
package
f) 23LC512-E/P = 512 Kbit, 2.5-5.5V Serial
SRAM, Extended temp., PDIP package
–X
Temp Ran ge
23A512/23LC512
DS20005155B-page 30 2012-2013 Microchip Technology Inc.
NOTES:
2012-2013 Microchip Technology Inc. DS20005155B-page 31
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620776179
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005155B-page 32 2012-2013 Microchip Technology Inc.
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10/28/13
