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Old Company Name in Catalogs and Other Documents
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Renesas Electronics document. We appreciate your understanding.
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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
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MOS INTEGRATED CIRCUIT
4 BIT SINGLE-CHIP MICROCONTROLLER
The
µ
PD750108 is one of the 75XL series 4-bit single-chip microcontrollers, which provide data processing
capability equal to that of an 8-bit microcontroller.
The
µ
PD750108 is produced by replacing the main system clock oscillator of the
µ
PD750008 with an RC oscillator,
enabling operation at a relatively low voltage of 1.8 V. In addition, it is best suited to applications using batteries.
The
µ
PD750108(A) has a higher reliability than the
µ
PD750108.
A built-in one-time PROM product,
µ
PD75P0116, is also available. It is suitable for small-scale production and
evaluation of application systems.
The following user’s manual describes the details of the functions of the
µ
PD750108. Be sure to read it
before designing application systems.
µ
PD750108 User’s Manual: U11330E
FEATURES
Built-in RC oscillator
Enables the immediate start of processing after the
release of standby mode
Capable of low-voltage operation: VDD = 1.8 to 5.5 V
Internal memory
Program memory (ROM)
: 4,096 × 8 bits (
µ
PD750104 and
µ
PD750104(A))
: 6,144 × 8 bits (
µ
PD750106 and
µ
PD750106(A))
: 8,192 × 8 bits (
µ
PD750108 and
µ
PD750108(A))
Data memory (RAM)
: 512 × 4 bits
APPLICATIONS
µ
PD750104,
µ
PD750106, and
µ
PD750108
Cameras, meters, and pagers
µ
PD750104(A),
µ
PD750106(A), and
µ
PD750108(A)
Electrical equipment for automobiles
µ
PD750104,750106,750108,750104(A),750106(A),750108(A)
Function for specifying the instruction execution time
(useful for saving power)
4
µ
s, 8
µ
s, 16
µ
s, 64
µ
s (when operating at 1.0 MHz)
2
µ
s, 4
µ
s, 8
µ
s, 32
µ
s (when operating at 2.0 MHz)
122
µ
s (when operating at 32.768 kHz)
Enhanced timer function (4 channels)
Can be easily substituted for the
µ
PD750008 because
this product succeeds to the functions and instructions
of the
µ
PD750008.
DATA SHEET
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
The mark shows major revised points.
Document No. U12301EJ1V1DS00 (1st edition)
Date Published August 2005 N CP (K)
Printed in Japan
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
2Data Sheet U12301EJ1V1DS
The
µ
PD750104,
µ
PD750106,
µ
PD750108,
µ
PD750104(A),
µ
PD750106(A), and
µ
PD750108(A) differ only in
quality grade. In this manual, the
µ
PD750108 is described unless otherwise specified. Users of other than the
µ
PD750108 should read
µ
PD750108 as referring to the pertinent product.
When the description differs among
µ
PD750104,
µ
PD750106, and
µ
PD750108, they also refer to the pertinent (A)
products.
µ
PD750104
µ
PD750104(A),
µ
PD750106
µ
PD750106(A),
µ
PD750108
µ
PD750108(A)
ORDERING INFORMATION
Part number Package Quality grade
µ
PD750104CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard
µ
PD750104CU-×××-A 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard
µ
PD750104GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard
µ
PD750104GB-×××-3BS-MTX-A 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard
µ
PD750106CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard
µ
PD750106CU-×××-A 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard
µ
PD750106GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard
µ
PD750106GB-×××-3BS-MTX-A 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard
µ
PD750108CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard
µ
PD750108CU-×××-A 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard
µ
PD750108GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard
µ
PD750108GB-×××-3BS-MTX-A 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Standard
µ
PD750104CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special
µ
PD750104GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm-pitch) Special
µ
PD750106CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special
µ
PD750106GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Special
µ
PD750108CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special
µ
PD750108GB(A)-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Special
Remarks 1. Products with “-A” at the end of the part number are lead-free products.
2. ××× is a mask ROM code number.
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Electronics Corporation to know the specification of quality grade on the devices and its recommended applications.
DIFFERENCES BETWEEN
µ
PD75010× AND
µ
PD75010×(A)
Product number
Item
Quality grade Standard Special
µ
PD750104
µ
PD750106
µ
PD750108
µ
PD750104(A)
µ
PD750106(A)
µ
PD750108(A)
3
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
ROM
RAM
FUNCTIONS
CMOS input
CMOS I/O
N-ch open
drain I/O
Total
8
18
8
34
Can incorporate 7 pull-up resistors that are specified with the software.
Can directly drive the LED.
Can incorporate 18 pull-up resistors that are specified with the software.
Can directly drive the LED.
Can withstand 13 V.
Can incorporate pull-up resistors that are specified with the mask option.
Serial interface
Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupt
Test input
System clock oscillator
Standby
Operating ambient
temperature range
Supply voltage
Package
Item
Command execution
time
Internal memory
General-purpose
register
I/O port
Timer
Bit sequential buffer (BSB)
4 channels
8-bit timer/event counter: 1 channel
8-bit timer counter: 1 channel
Basic interval timer/watchdog timer: 1 channel
lock timer: 1 channel
Three-wire serial I/O mode ... switchable between the start LSB and the start MSB
Two-wire serial I/O mode
SBI mode
16 bits
Φ
, 125, 62.5, or 15.6 kHz (when the main system clock operates at 1.0 MHz)
Φ
, 250, 125, or 31.3 kHz (when the main system clock operates at 2.0 MHz)
2, 4, or 32 kHz (when the subsystem clock operates at 32.768 kHz)
0.488, 0.977, or 7.813 kHz (when the main system clock operates at 1.0 MHz)
0.977, 1.953, or 15.625 kHz (when the main system clock operates at 2.0 MHz)
External : 3
Internal : 4
External : 1
Internal : 1
RC oscillator for main system clock (with external resistor and capacitor)
Crystal oscillator for subsystem clock
STOP/HALT mode
TA = -40 to +85 °C
VDD = 1.8 to 5.5 V
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
Function
4, 8, 16, or 64
µ
s (when the main system clock operates at 1.0 MHz)
2, 4, 8, or 32
µ
s (when the main system clock operates at 2.0 MHz)
122
µ
s (when the subsystem clock operates at 32.768 kHz)
4,096 × 8 bits (
µ
PD750104)
6,144 × 8 bits (
µ
PD750106)
8,192 × 8 bits (
µ
PD750108)
512 × 4 bits
When operating in 4 bits: 8 × 4 banks
When operating in 8 bits: 4 × 4 banks
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
4Data Sheet U12301EJ1V1DS
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 6
2. BLOCK DIAGRAM ..................................................................................................................... 8
3. PIN FUNCTIONS ........................................................................................................................ 9
3.1 Port Pins ......................................................................................................................................... 9
3.2 Non-Port Pins ................................................................................................................................. 10
3.3 Pin Input/Output Circuits .............................................................................................................. 11
3.4 Connection of Unused Pins ......................................................................................................... 13
4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION ........................................................................ 14
4.1 Differences between Mk Ι Mode and Mk ΙΙ Mode ...................................................................... 14
4.2 Setting of the Stack Bank Selection Register (SBS) ................................................................ 15
5. MEMORY CONFIGURATION .................................................................................................... 16
6. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 21
6.1 Digital I/O Ports .............................................................................................................................. 21
6.2 Clock Generator ............................................................................................................................. 21
6.3 Control Functions of Subsystem Clock Oscillator ................................................................... 23
6.4 Clock Output Circuit...................................................................................................................... 24
6.5 Basic Interval Timer/Watchdog Timer ........................................................................................ 25
6.6 Clock Timer..................................................................................................................................... 26
6.7 Timer/Event Counter ..................................................................................................................... 27
6.8 Serial Interface ............................................................................................................................... 30
6.9 Bit Sequential Buffer ..................................................................................................................... 32
7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ............................................................... 33
8. STANDBY FUNCTION ............................................................................................................... 35
9. RESET FUNCTION ..................................................................................................................... 36
10. MASK OPTION ........................................................................................................................... 39
11. INSTRUCTION SET.................................................................................................................... 40
12. ELECTRICAL CHARACTERISTICS ......................................................................................... 53
13. CHARACTERISTIC CURVE (REFERENCE VALUES) ............................................................ 65
5
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
14. EXAMPLES OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE
VALUES) ..................................................................................................................................... 66
15. PACKAGE DRAWINGS ............................................................................................................. 68
16. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 70
APPENDIX A FUNCTIONS OF THE
µ
PD750008,
µ
PD750108, AND
µ
PD75P0116 .................. 72
APPENDIX B DEVELOPMENT TOOLS ........................................................................................ 74
APPENDIX C RELATED DOCUMENTS........................................................................................ 78
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
6Data Sheet U12301EJ1V1DS
1. PIN CONFIGURATION (TOP VIEW)
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µ
PD750104CU-×××,
µ
PD750104CU-×××-A,
µ
PD750104CU(A)-×××
µ
PD750106CU-×××,
µ
PD750106CU-×××-A,
µ
PD750106CU(A)-×××
µ
PD750108CU-×××,
µ
PD750108CU-×××-A,
µ
PD750108CU(A)-×××
IC : Internally connected (Connect directly to VDD.)
V
SS
P40
P41
P42
P43
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
XT1
XT2
RESET
CL1
CL2
P33
P32
P31
P30
P81
P80
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
P13/TI0
P12/INT2
P11/INT1
P10/INT0
IC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
7
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
µ
PD750104GB-×××-3BS-MTX,
µ
PD750104GB-×××-3BS-MTX-A,
µ
PD750104GB(A)-×××-3BS-MTX
µ
PD750106GB-×××-3BS-MTX,
µ
PD750106GB-×××-3BS-MTX-A,
µ
PD750106GB(A)-×××-3BS-MTX
µ
PD750108GB-×××-3BS-MTX,
µ
PD750108GB-×××-3BS-MTX-A,
µ
PD750108GB(A)-×××-3BS-MTX
IC : Internally connected (Connect directly to VDD.)
PIN NAMES
BUZ : Buzzer Clock P70-P73 : Port 7
CL1, CL2 : Main System Clock (RC) P80, P81 : Port 8
IC : Internally Connected PCL : Programmable Clock
INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 PTO0, PTO1 : Programmable Timer Output 0, 1
INT2 : External Test Input 2 RESET : Reset
KR0-KR7 : Key Return 0-7 SB0, SB1 : Serial Bus 0, 1
NC : No connection SCK : Serial Clock
P00-P03 : Port 0 SI : Serial Input
P10-P13 : Port 1 SO : Serial Output
P20-P23 : Port 2 TI0 : Timer Input 0
P30-P33 : Port 3 VDD :Positive Power Supply
P40-P43 : Port 4 VSS :Ground
P50-P53 : Port 5 XT1, XT2 : Subsystem Clock (Crystal)
P60-P63 : Port 6
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
P53
P52
P51
P50
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P13/TI0
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P80
P81
P30
P31
P32
P33
NC
P43
P42
P41
P40
V
SS
XT1
XT2
RESET
CL1
CL2
P73/KR7
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
V
DD
IC
P10/INT0
P11/INT1
P12/INT2
NC
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
8Data Sheet U12301EJ1V1DS
2. BLOCK DIAGRAM
Note The ROM capacity depends on the product.
BIT SEQ.
BUFFER (16)
PORT 0 P00 - P034
PORT 1
PORT 2 4
PORT 3 P30 - P334
PORT 4 P40 - P434
PORT 5 P50 - P534
PORT 6 P60 - P634
VSSVDD RESET
IC
CPU CLOCK
Φ
STAND BY
CONTROL
CL2CL1XT2XT1
SYSTEM CLOCK
GENERATOR
MAINSUB
CLOCK
DIVIDER
CLOCK
OUTPUT
CONTROL
fx/2N
PCL/P22
GENERAL
REGISTER
DATA
MEMORY
(RAM)
512 × 4 BITS
BANK
SBS
SP (8)
CY
ALU
PROGRAM
COUNTER
PROGRAM
MEMORYNote
(ROM) DECODE
AND
CONTROL
BASIC INTERVAL
TIMER/
WATCHDOG
TIMER
TI0/P13
INTBT RESET
8-BIT
TIMER/EVENT
COUNTER #0
PTO0/P20
INTT0 TOUT0
8-BIT TIMER
COUNTER #1
INTT1
TOUT0
CLOCKED
SERIAL
INTERFACE
SI/SB1/P03
INTERRUPT
CONTROL
INT0/P10
SO/SB0/P02
SCK/P01
INT1/P11
INT2/P12
INT4/P00
KR0/P60-
KR7/P73
WATCH
TIMER
8PORT 7 P70 - P734
PORT 8 P80, P812
P10 - P134
P20 - P23
PTO1/P21
INTCSI
INTW
BUZ/P23
9
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
3. PIN FUNCTIONS
3.1 Port Pins
Notes 1. The circle ( ) indicates the Schmitt trigger input.
2. When pull-up resistors that can be specified with the mask option are not incorporated (when pins are
used as N-ch open-drain input ports), the input leak low current increases when an input instruction or
bit operation instruction is executed.
I/O circuit
type
Note 1
-A
-B
-C
-C
E-B
E-B
M-D
M-D
-A
-A
E-B
When reset
Input
Input
Input
Input
High level (when
pull-up resistors
are provided) or
high impedance
High level (when
pull-up resistors
are provided) or
high impedance
Input
Input
Input
8-bit
I/O
×
×
×
×
×
Function
4-bit input port (PORT0).
For P01 - P03, built-in pull-up resistors
can be connected by software in units
of 3 bits.
4-bit input port (PORT1).
Built-in pull-up resistors can be
connected by software in units of 4 bits.
A noise eliminator can be selected only
when the P10/INT0 pin is used.
4-bit I/O port (PORT2).
Built-in pull-up resistors can be
connected by software in units of 4 bits.
Programmable 4-bit I/O port (PORT3).
I/O can be specified bit by bit. Built-in
pull-up resistors can be connected by
software in units of 4 bits.
N-ch open-drain 4-bit I/O port (PORT4).
A pull-up resistor can be provided bit by
bit (mask option). Withstand voltage is
13 V in open-drain mode.
N-ch open-drain 4-bit I/O port (PORT5).
A pull-up resistor can be provided bit by
bit (mask option). Withstand voltage is
13 V in open-drain mode.
Programmable 4-bit I/O port (PORT6).
I/O can be specified bit by bit. Built-in
pull-up resistors can be connected by
software in units of 4 bits.
4-bit I/O port (PORT7).
Built-in pull-up resistors can be
connected by software in units of 4 bits.
2-bit I/O port (PORT8).
Built-in pull-up resistors can be
connected by software in units of 2
bits.
B
F
F
M
B
Pin name
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30 - P33
P40 - P43
Note 2
P50 - P53
Note 2
P60
P61
P62
P63
P70
P71
P72
P73
P80
P81
Input/
output
Input
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
F
F
Shared
pin
INT4
SCK
SO/SB0
SI/SB1
INT0
INT1
INT2
TI0
PTO0
PTO1
PCL
BUZ
-
-
-
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
-
-
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
10 Data Sheet U12301EJ1V1DS
3.2 Non-Port Pins
Notes 1. The circle ( ) indicates the Schmitt trigger input.
2. With a noise eliminator/asynchronously selectable
3. Asynchronous
B
B
F
F
M
B
Function
Inputs external event pulse to the timer/event
counter
Timer/event counter output
Timer counter output
Clock output
Arbitrary frequency output (for buzzer output or
system clock trimming)
Serial clock I/O
Serial data output
Serial data bus I/O
Serial data input
Serial data bus I/O
Edge detection vectored interrupt input (both
rising and falling edges are detected)
Rising edge detection testable input
Falling edge detection testable input
Falling edge detection testable input
Pin for connecting a resistor (R) or capacitor (C)
for main system clock oscillation. An external
clock cannot be input.
Crystal connection pin for subsystem clock
generation. When external clock signal is used, it
is applied to XT1, and it reverse phase signal is
applied to XT2.
XT1 can be used as a 1-bit input (test).
System reset input (active low)
Internally connected. (To be connected directly to
VDD)
Positive power supply
Ground potential
Input/
output
Input
Output
I/O
Input
Input
Input
Input
Input
-
-
Input
-
Input
-
-
-
When reset
Input
Input
Input
Input
Input
Input
-
-
-
-
-
-
Edge detection vectored interrupt input
(detection edge selectable). A noise eliminator
can be selected when INT0/P10 is used.
Shared
pin
P13
P20
P21
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60 - P63
P70 - P73
-
-
-
-
-
-
Note 3
Note 2
Note 3
I/O circuit
type
Note 1
-C
E-B
-A
-B
-C
-C
-A
-A
-
-
-
-
-
B
Pin name
TI0
PTO0
PTO1
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 - KR3
KR4 - KR7
CL1
CL2
XT1
XT2
RESET
IC
VDD
VSS
F
F
11
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
3.3 Pin Input/Output Circuits
The input/output circuit of each
µ
PD750108 pin is shown below in a simplified manner.
Type A Type D
Type B Type E-B
Type B-C Type F-A
(1/2)
CMOS input buffer
V
DD
IN
P-ch
N-ch
Schmitt trigger input with hysteresis
IN
P.U.R.: Pull-Up Resistor
IN
P-ch P.U.R.
enable
P.U.R.
V
DD
P.U.R.: Pull-Up Resistor
P.U.R.
VDD
P.U.R.
enable P-ch
IN/OUT
Data
Output
disable
Type D
Type A
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
V
DD
P-ch
N-ch
OUT
Data
Output
disable
P.U.R.
V
DD
P.U.R.
enable P-ch
IN/OUT
Data
Output
disable
Type D
Type B
P.U.R.: Pull-Up Resistor
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
12 Data Sheet U12301EJ1V1DS
Type F-B Type M-C
Type M-D
(2/2)
P.U.R.: Pull-U
p
Resistor
VDD
P-ch
N-ch
IN/OUT
VDD
P-ch
P.U.R.
P.U.R.
enable
Output
disable
(P)
Data
Output
disable
Output
disable
(N)
P.U.R.: Pull-U
p
Resistor
N-ch
P.U.R.
Data
Output
disable
P.U.R.
enable
V
DD
P-ch
IN/OUT
P.U.R.: Pull-Up Resistor
N-ch
(Withstand
voltage:
+13 V)
IN/OUT
Data
V
DD
Output
disable
P.U.R.
(Mask option)
Note
P.U.R
Note
V
DD
P-ch
Input
instruction
Pull-up resistor that operates only when pull-up resistors
that can be specified with the mask option are not
incorporated and an input instruction is executed.
(When the pin is low, the current flows from V
DD
to the pin.)
Voltage
restriction
circuit
(Withstand voltage: +13 V)
13
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Input state : To be connected to VSS or VDD
through a separate resistor
Output state : To be left open
Input state : To be connected to VSS or VDD
through a separate resistor
Output state : To be left open
Input state : To be connected to VSS
Output state : To be connected to VSS
(Do not connect to a pull-up
resistor specified with a mask
option.)
3.4 Connection of Unused Pins
Table 3-1. Connection of Unused Pins
Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-
in feedback resistor).
Pin name Recommended connection
P00/INT4 To be connected to VSS or VDD
P01/SCK
P02/SO/SB0
P03/SI/SB1 To be connected to VSS
P10/INT0 - P12/INT2 To be connected to VSS or VDD
P13/TI0
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
P30 - P33
P40 - P43
P50 - P53
P60/KR0 - P63/KR3
P70/KR4 - P73/KR7
P80, P81
XT1Note To be connected to VSS or VDD
XT2Note To be left open
IC To be connected directly to VDD
To be connected to VSS or VDD through a
separate resistor
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
14 Data Sheet U12301EJ1V1DS
4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION
4.1 Differences between Mk Ι Mode and Mk ΙΙ Mode
The CPU of the
µ
PD750108 has two modes (Mk Ι mode and Mk ΙΙ mode) and which mode is used is selectable.
Bit 3 of the stack bank selection register (SBS) determines the mode.
Mk Ι mode: This mode has the upward compatibility with the 75X series.
It can be used in the 75XL CPUs having a ROM of up to 16 KB.
Mk ΙΙ mode: This mode is not compatible with the 75X series.
It can be used in all 75XL CPUs, including those having a ROM of 16 KB or more.
Table 4-1 shows the differences between Mk Ι mode and Mk ΙΙ mode.
Table 4-1. Differences between Mk Ι Mode and Mk ΙΙ Mode
Caution Mk ΙΙ mode can be used to support a program area larger than 16K bytes in the 75X series or 75XL
series. This mode enhances a software compatibility with products whose program area is larger
than 16K bytes. If Mk ΙΙ mode is selected, when the subroutine call instruction is executed, the
number of stack bytes (use area) will be increased by one byte for each stack, compared to Mk
Ι mode. When a CALL !addr or CALLF !faddr instruction is executed, it takes one more machine
cycle. Therefore, Mk Ι mode should be used for applications for which RAM efficiency or
processing capabilities is more critical than a software compatibility.
Number of stack bytes in a
subroutine instruction
BRA !addr1 instruction
CALLA !addr1 instruction
CALL !addr instruction
CALLF !faddr instruction
2 bytes
None
3 machine cycles
2 machine cycles
3 bytes
Available
4 machine cycles
3 machine cycles
Mk Ι mode Mk ΙΙ mode
15
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
4.2 Setting of the Stack Bank Selection Register (SBS)
The Mk Ι mode and Mk ΙΙ mode are switched by stack bank selection register. Figure 4-1 shows the register
configuration.
The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk Ι mode,
initialize the register to 100×BNote at the beginning of the program. To use the CPU in Mk ΙΙ mode, initialize it to
000×BNote.
Note Specify the desired value in ×.
Figure 4-1. Stack Bank Selection Register Format
Caution The CPU operates in Mk Ι mode after the RESET signal is issued, because bit 3 of SBS is set to
1. Set bit 3 of SBS to 0 (Mk ΙΙ mode) to use the CPU in Mk ΙΙ mode.
SBS0SBS1SBS2SBS3
0123
F84H
Address
SBS
Symbol
0
0
0
1
Memory bank 0
Memory bank 1
Other settings are inhibited.
0
1
Mk ΙΙ mode
Mk Ι mode
Mode switching designation
Bit 2 must be set to 0.
Stack area designation
0
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
16 Data Sheet U12301EJ1V1DS
5. MEMORY CONFIGURATION
Program memory (ROM) : 4,096 × 8 bits (0000H-0FFFH):
µ
PD750104
6,144 × 8 bits (0000H-17FFH):
µ
PD750106
8,192 × 8 bits (0000H-1FFFH):
µ
PD750108
0000H to 0001H
Vector address table for holding the RBE and MBE values and program start address when a RESET signal is
issued (allowing a reset start at an arbitrary address)
0002H to 000DH
Vector address table for holding the RBE and MBE values and program start address for each vectored interrupt
(allowing interrupt processing to be started at an arbitrary address)
0020H to 007FH
Table area referenced by the GETI instructionNote
Note The GETI instruction requires only one byte to represent an arbitrary two-byte or three-byte instruction or
two one-byte instructions, reducing the number of program bytes.
Data memory (RAM)
Data area : 512 × 4 bits (000H to 1FFH)
Peripheral hardware area: 128 × 4 bits (F80H to FFFH)
17
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Figure 5-1. Program Memory Map (in
µ
PD750104)
Note Can be used only in the Mk ΙΙ mode.
Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address
with only the 8 low-order bits of the PC changed.
000H
Address 7654
MBE RBE 0 0 Internal reset start address (high-order 4 bits)
0
002H MBE RBE 0 0 INTBT/INT4 (high-order 4 bits)start address
004H MBE RBE 0 0 INT0 (high-order 4 bits)start address
006H MBE RBE 0 0 INT1 (high-order 4 bits)start address
008H MBE RBE 0 0 INTCSI (high-order 4 bits)start address
00AH MBE RBE 0 0 INTT0 (high-order 4 bits)start address
00CH MBE RBE 0 0 INTT1 (high-order 4 bits)start address
020H
07FH
080H
7FFH
800H
FFFH
GETI instruction reference table
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
CALLF
! faddr
instruction
entry
address Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1
Note
or
CALLA !addr1
Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
BRCB
!caddr
instruction
branch
address
-15 to -1,
+2 to +16
Branch destination
address and
subroutine entry
address when
GETI instruction
is executed
Internal reset start address
INTBT/INT4 start address
INT0 start address
INT1 start address
INTCSI start address
INTT0 start address
INTT1 start address
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
18 Data Sheet U12301EJ1V1DS
Figure 5-2. Program Memory Map (in
µ
PD750106)
Note Can be used only in the Mk ΙΙ mode.
Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address
with only the 8 low-order bits of the PC changed.
0000H
Address
0002H MBE RBE 0 INTBT/INT4 (high-order 5 bits)start address
0004H MBE RBE 0 INT0 (high-order 5 bits)start address
0006H MBE RBE 0 INT1 (high-order 5 bits)start address
0008H MBE RBE 0 INTCSI (high-order 5 bits)start address
000AH MBE RBE 0 INTT0 (high-order 5 bits)start address
0020H
007FH
0080H
07FFH
0800H
MBE RBE 0 Internal reset start address (high-order 5 bits)
0FFFH
1000H
17FFH
GETI instruction reference table
000CH MBE RBE 0 INTT1 (high-order 5 bits)start address
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
CALLF
!faddr
instruction
entry
address
BRCB !caddr
instruction
branch
address
Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1Note or
CALLA !addr1Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
-15 to -1,
+2 to +16
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
BRCB !caddr
instruction
branch
address
765 0
Internal reset start address
INTBT/INT4
INT0
INT1
INTCSI
INTT0
INTT1
start address
start address
start address
start address
start address
start address
19
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Figure 5-3. Program Memory Map (in
µ
PD750108)
Note Can be used only in the Mk ΙΙ mode.
Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address
with only the 8 low-order bits of the PC changed.
0000H
Address
0002H MBE RBE 0 INTBT/INT4 (high-order 5 bits)start address
0004H MBE RBE 0 INT0 (high-order 5 bits)start address
0006H MBE RBE 0 INT1 (high-order 5 bits)start address
0008H MBE RBE 0 INTCSI (high-order 5 bits)start address
000AH MBE RBE 0 INTT0 (high-order 5 bits)start address
0020H
007FH
0080H
07FFH
0800H
MBE RBE 0 Internal reset start address (high-order 5 bits)
0FFFH
1000H
1FFFH
GETI instruction reference table
000CH MBE RBE 0 INTT1 (high-order 5 bits)start address
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
CALLF
!faddr
instruction
entry
address
BRCB !caddr
instruction
branch
address
Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1
Note
or
CALLA !addr1
Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
-15 to -1,
+2 to +16
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
BRCB !caddr
instruction
branch
address
765 0
Internal reset start address
INTBT/INT4
INT0
INT1
INTCSI
INTT0
INTT1
start address
start address
start address
start address
start address
start address
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
20 Data Sheet U12301EJ1V1DS
Figure 5-4. Data Memory Map
Note Memory bank 0 or 1 can be selected as the stack area.
(32 × 4)
Data memory
000H
01FH
020H
0FFH
100H
1FFH
F80H
FFFH
256 × 4
(224 × 4)
256 × 4
128 × 4
0
1
15
Stack
areaNote
Area for
general-purpose
register
Data area
Static RAM
(512 × 4)
Peripheral
hardware area
Not contained
Memory bank
21
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
When the serial interface function is used, dual-function pins
function as output pins in some operation modes.
4-bit input port
Allows input or output mode setting in units of 4 bits.
Allows input or output mode setting in units of 1 bit.
Operation and feature
Port name
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
6. PERIPHERAL HARDWARE FUNCTIONS
6.1 Digital I/O Ports
The
µ
PD750108 has the following three types of I/O port:
•8 CMOS input pins (PORT0 and PORT1)
18 CMOS I/O pins (PORT2, PORT3, and PORT6 to PORT8)
•8 N-ch open-drain I/O pins (PORT4 and PORT5)
Total: 34 pins
Table 6-1. Digital Ports and Their Features
6.2 Clock Generator
The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Figure 6-1 shows
the configuration of the clock generator.
Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control
register (SCC).
The main system clock and subsystem clock are used.
The instruction execution time can be made variable.
• 4, 8, 16, or 64
µ
s (when the main system clock is at 1.0 MHz)
• 2, 4, 8, or 32
µ
s (when the main system clock is at 2.0 MHz)
• 122
µ
s (when the subsystem clock is at 32.768 kHz)
Allows input or output mode setting in
units of 4 bits. Whether to use pull-up
resistors can be specified bit by bit with
the mask option.
Allows input or output mode setting in
units of 1 bit.
Allows input or output mode setting in
units of 4 bits.
Ports 4 and 5 can be
paired, allowing data
I/O in units of 8 bits.
Ports 6 and 7 can be
paired, allowing data
I/O in units of 8 bits.
4-bit input
4-bit I/O
4-bit I/O (N-ch
open-drain can
withstand 13 V)
4-bit I/O
2-bit I/O
Also used as INT4, SCK,
SO/SB0, or SI/SB1.
Also used as INT0, INTI,
INT2 or TI0.
Also used as PTO0,
PTO1, PCL, or BUZ.
-
Also used as one of KR0
to KR3.
Also used as one of KR4
to KR7.
-
Allows input or output mode setting in units of 2 bits.
Function Remarks
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
22 Data Sheet U12301EJ1V1DS
Figure 6-1. Clock Generator Block Diagram
Note Instruction execution
Remarks 1. fCC = Main system clock frequency
2. fXT = Subsystem clock frequency
3.
Φ
= CPU clock
4. PCC: Processor clock control register
5. SCC: System clock control register
6. One clock cycle (tCY) of the CPU clock (
Φ
) is equal to one machine cycle of an instruction.
Subsystem
clock generator
Main system
clock generator
RC oscillation
Clock timer
Basic interval timer (BT)
Timer/event counter
Timer counter
Serial interface
Clock timer
INT0 noise eliminator
Clock output circuit
1/1 to 1/4096
Frequency divider
Selec-
tor
Selec-
tor
Frequency
divider
Φ
Oscillator
disable
signal
Internal bus
HALTNote
STOPNote
PCC2, PCC3
clear signal Wait release signal from BT
Standby release signal from
interrupt control circuit
RESET signal
XT1
XT2
CL1
CL2
4
SCC
SCC3
SCC0
PCC
PCC0
PCC1
PCC2
PCC3
STOP flip-flop
QS
R
HALT flip-flop
S
Q
R
f
XT
f
CC
1/2 1/16
1/4
1/4
WM.3
CPU
INT0 noise
eliminator
Clock
output
circuit
23
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
6.3 Control Functions of Subsystem Clock Oscillator
The subsystem clock oscillator of the
µ
PD750108 has two control functions to decrease the supply current.
The function to select with the software whether to use the built-in feedback resistorNote
The function to suppress the supply current by reducing the drive current of the built-in inverter when the supply
voltage is high (VDD 2.7 V)
Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-in feedback resistor), connect
XT1 to VSS or VDD, and open XT2. This makes it possible to reduce the supply current required by the
subsystem clock oscillator.
Each function can be used by switching bits 0 and 1 in the sub-oscillator control register (SOS). (See Figure 6-
2.)
Figure 6-2. Subsystem Clock Oscillator
SOS.0
SOS.1
XT1 XT2
Inverter
Feedback resistor
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
24 Data Sheet U12301EJ1V1DS
6.4 Clock Output Circuit
The clock output circuit outputs a clock pulse from the P22/PCL pin. This clock pulse is used for remote control
waveform output, peripheral LSIs, etc.
Clock output (PCL):
Φ
, 125, 62.5, or 15.6 kHz (at 1.0 MHz)
Φ
, 250, 125, or 31.3 kHz (at 2.0 MHz)
Figure 6-3. Clock Output Circuit Configuration
Remark Measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable.
From the clock
generator
CLOM
Selector
Output
buffer
Port 2 input/
output mode
specification bit
P22 output
latch
PCL/P22
Internal bus
4
PORT2.2 Bit 2 of PMGB
CLOM0CLOM10CLOM3
Φ
f
CC
/2
3
f
CC
/2
4
f
CC
/2
6
25
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
6.5 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has these functions:
Interval timer operation which generates a reference timer interrupt
Operation as a watchdog timer for detecting program crashes and resetting the CPU
Selection of wait time for releasing the standby mode and counting the wait time
Reading out the count value
Figure 6-4. Block Diagram of the Basic Interval Timer/Watchdog Timer
Note Instruction execution
From the clock
generator
Internal bus
4
fCC/2
5
fCC/2
7
fCC/2
9
fCC/2
12
MPX Basic interval timer
(8-bit frequency divider)
Clear signal Clear signal
BT interrupt
request flag Vectored
interrupt
request
signal
IRQBT
Wait release
signal for standby
release
Set
signal
BT
8
BTM3 BTM2 BTM1 BTM0 BTM
SET1
Note
3
1
WDTM
Internal
reset signal
SET1
Note
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
26 Data Sheet U12301EJ1V1DS
6.6 Clock Timer
The
µ
PD750108 contains one channel for a clock timer. The clock timer provides the following functions:
Sets the test flag (IRQW) with a 0.5 sec interval (when WM0 = 1).
The standby mode can be released by IRQW.
The 0.5 second interval can be generated from the subsystem clock (32.768 kHz).
The time interval can be made 128 times faster by selecting the fast mode. This is convenient for program
debugging, testing, etc.
Any of the frequencies (fW/24, fW/23, or fW can be output to the P23/BUZ pin. This can be used for beep and
system clock frequency trimming.
The clock can be started from zero seconds by clearing the frequency divider.
Figure 6-5. Clock Timer Block Diagram
Note When a frequency-divided main system clock is used, 32.768 kHz cannot be selected as the source clock
frequency.
Remark The values in parentheses in the figure above are for fCC = 1.0 MHz, fXT = 32.768 kHz.
P23/BUZ
Internal bus
8
Selector
From the
clock
generator
f
CC
128
(7.8125 kHz)
f
XT
(32.768 kHz)
Selector Frequency divider
Selector INTW
IRQW
set signal
WM7 0 WM5 WM4 WM3 WM2 WM1 WM0 P23 output
latch
Bit 2 of PMGBPORT2.3
Output buffer
Clear
f
W
32.768 kHz
or
7.8125 kHz
Bit test instruction
Port 2 input/
output mode
WM
f
w
2
7
f
w
2
14
f
w
2
3
f
w
2
4
Note
27
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
6.7 Timer/Event Counter
The
µ
PD750108 contains one channel for a timer/event counter and one channel for a timer counter. Figures
6-6 and 6-7 show their configurations.
The timer/event counter provides the following functions:
Programmable interval timer operation
Outputs square-wave signal of an arbitrary frequency to the PTOn pin (n = 0, 1)
Event counter operation (channel 0 only)
Divides the TI0 pin input by N and outputs to the PTO0 pin (frequency divider operation) (channel 0 only)
Supplies serial shift clock to the serial interface circuit (channel 0 only)
Count read function
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
28 Data Sheet U12301EJ1V1DS
Figure 6-6. Timer/Event Counter Block Diagram
Count register (8)
TI0/P13
MPX
Timer operation start signal
888
From the clock
generator
Internal bus
TM06 TM05 TM04 TM03 TM02
Port input
buffer
Comparator (8)
Modulo register (8) T0 enable
flag
P20
output
latch
signal
Port 2
input/
output
mode
Clear signal
T0
TMOD0 Bit 2 of PMGB
PTO0/P20
Output
buffer
Reset
RESET
IRQT0 clear
signal
TOUT
flip-flop
TM0
Input buffer
IRQT0
set signal
INTT0
PORT2.0
TOUT0
To serial
interface
CP
Match
8
8
TOE0
SET1
Note
f
CC
/2
4
f
CC
/2
6
f
CC
/2
8
f
CC
/2
10
Note Instruction execution
29
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Figure 6-7. Timer Counter Block Diagram
Count register (8)
MPX
Timer operation start signal
888
From the clock
generator
Internal bus
TM16 TM15 TM14 TM13 TM12
Comparator (8)
Modulo register (8) T1 enable
flag
P21
output
latch
Port 2
input/
output
mode
Clear signal
T1
TMOD1 Bit 2 of PMGB
PTO1/P21
Output
buffer
Reset
RESET
IRQT1 clear
signal
TOUT
flip-flop
TM1
SET1
Note
IRQT1
set signal
INTT1
PORT2.1TOE1
CP
Match
8
8
f
CC
/2
6
f
CC
/2
8
f
CC
/2
10
f
CC
/2
12
Note Instruction execution
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
30 Data Sheet U12301EJ1V1DS
6.8 Serial Interface
µ
PD750108 has an 8-bit synchronous serial interface. The serial interface has the following four types of mode.
Operation stop mode
Three-wire serial I/O mode
Two-wire serial I/O mode
SBI mode
31
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Figure 6-8. Serial Interface Block Diagram
Internal bus
88
8
8/4
P03/SI/SB1
P02/SO/SB0
P01/SCK
(8)
f
CC
/2
3
f
CC
/2
4
f
CC
/2
6
TOUT0
(from timer/event counter)
CSIM
RELD
CMDD
ACKD
ACKT
ACKE
BSYE
RELT
CMDT
DQ
SET CLR
(8)
(8)
SBIC
Bit
test
Slave address register (SVA)
Address comparator
Coincidence
signal
Bit manipulation
SO latch
Bit test
Selec-
tor
Selec-
tor
Busy/
acknowledge
output circuit
Bus release/
command/
acknowledge
detection circuit
Serial clock
counter
Serial clock
control circuit
INTCSI
control circuit
IRQCSI
set signal
INTCSI
P01
output latch Serial clock
selector
External SCK
Shift register (SIO)
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
32 Data Sheet U12301EJ1V1DS
6.9 Bit Sequential Buffer: 16 Bits
The bit sequential buffer (BSB) is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially updated by bit manipulation operation. Therefore, this buffer
is very useful for processing long data in bit units.
Figure 6-9. Bit Sequential Buffer Format
Remarks 1. In pmem.@L addressing, bit specification is shifted according to the L register.
2. In pmem.@L addressing, the bit sequential buffer can be manipulated at any time regardless of MBE/
MBS specification.
3210321032103210
BSB3 BSB2 BSB1 BSB0
FC3H FC2H FC1H FC0H
L = FH L = CH L = BH L = 8H L = 7H L = 4H L = 3H L = 0H
DECS L
INCS L
Address
Bit
L register
Symbol
33
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
The
µ
PD750108 has seven interrupt sources and two test sources. One test source, INT2, has two types of edge
detection testable input pins.
The interrupt control circuit of the
µ
PD750108 has the following functions.
(1) Interrupt functions
Hardware controlled vectored interrupt function which can control whether or not to accept an interrupt using
the interrupt flag (IE×××) and interrupt master enable flag (IME).
The interrupt start address can be set arbitrarily.
Multiple interrupt function which can specify the priority by the interrupt priority specification register (IPS)
Test function of an interrupt request flag (IRQ×××)
(The software can confirm that an interrupt occurred.)
Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.)
(2) Test functions
Whether test request flags (IRQ×××) are issued can be checked with software.
Release of the standby mode (A test source to be released can be selected with test enable flags.)
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
34 Data Sheet U12301EJ1V1DS
Figure 7-1. Interrupt Control Circuit Block Diagram
Note Noise eliminator (Standby release is not possible when the noise eliminator is selected.)
2
IM2
14
IRQBT
IRQ4
IRQ0
IRQ1
IRQCSI
IRQT0
IRQT1
IRQW
IRQ2
INTBT
INT4/P00
INT0/P10
INT1/P11
INTCSI
INTT0
INTT1
INTW
INT2/P12
Both-edge
detector
IM0
Edge
detector
Edge
detector
Rising edge
detector
Falling edge
detector
KR0/P60
KR7/P73
Selec-
tor
IM2
Interrupt enable flag (IE×××)IPS IST0
IME
Priority control circuit
Decoder
VRQn
Vector table
address
generator
Standby release signal
Internal bus
Selector
Note
IM1 IST1
35
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
8. STANDBY FUNCTION
The
µ
PD750108 has two different standby modes (STOP mode and HALT mode) to reduce power dissipation while
waiting for program execution.
Table 8-1. Standby Mode Statuses
Notes 1. Operation is possible only when the main system clock operates.
2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode
register (IM0) (when IM02 = 1).
Instruction for setting
System clock for setting
Clock oscillator
Basic interval
timer/watchdog
timer
Serial interface
Timer/event
counter
Timer counter
Clock timer
External interrupt
CPU
Release signal
STOP mode
STOP instruction
Can be set only when operating on the
main system clock.
The main system clock stops its operation.
Does not operate.
Can operate only when the external SCK
input is selected for the serial clock.
Can operate only when the TI0 pin input is
selected for the count clock.
Does not operate.
Can operate when fXT is selected as the
count clock.
INT1, INT2, and INT4 can operate.
Only INT0 cannot operate.Note 2
Does not operate.
Opera-
tion
status
Item Mode
An interrupt request signal from hardware whose operation is enabled by the interrupt
enable flag or the generation of a RESET signal
HALT mode
HALT instruction
Can be set either with the main system
clock or the subsystem clock.
Only the CPU clock Φ stops its operation
(oscillation continues).
Can operate only at main system clock
oscillation.
BT mode : IRQBT is set at the reference
interval.
WT mode : A reset signal is generated
when the BT overflows.
Can operate only when external SCK input
is selected as the serial clock or at main
system clock oscillation.
Can operate only when TI0 pin input is
specified as the count clock or at main
system clock oscillation.
Can operate.Note 1
Can operate.
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
36 Data Sheet U12301EJ1V1DS
9. RESET FUNCTION
The
µ
PD750108 is reset with the external reset signal (RESET) or the reset signal received from the basic interval
timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure 9-1 shows the
configuration of the reset circuit.
Figure 9-1. Configuration of Reset Functions
When the RESET signal is generated, all hardware is initialized as indicated in Table 9-1. Figure 9-2 shows the
reset operation timing.
Figure 9-2. Reset Operation by Generation of RESET Signal
Note 56/fCC (28
µ
s at 2.0 MHz, 56
µ
s at 1.0 MHz)
WDTM
RESET Internal reset signal
Reset signal from basic
interval timer/watchdog timer
Internal bus
RESET signal is generated
Operating mode or
standby mode HALT mode Operating mode
Internal reset o
p
eration
Wait
Note
37
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Table 9-1. Status of the Hardware after a Reset (1/2)
Program counter (PC)
PSW
Stack pointer (SP)
Stack bank selection register (SBS)
Data memory (RAM)
General-purpose registers (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
Timer/event
counter
Timer counter
Clock timer
Serial interface
4 low-order bits at address 0000H
in program memory are set in PC
bits 11 to 8, and the data at address
0001H are set in PC bits 7 to 0.
5 low-order bits at address 0000H
in program memory are set in PC
bits 12 to 8, and the data at address
0001H are set in PC bits 7 to 0.
Held
0
0
Bit 6 at address 0000H in
program memory is set in RBE,
and bit 7 is set in MBE.
Undefined
1000B
Held
Held
0, 0
Undefined
0
0
0
FFH
0
0, 0
0
FFH
0
0, 0
0
Held
0
0
Held
4 low-order bits at address 0000H
in program memory are set in PC
bits 11 to 8, and the data at address
0001H are set in PC bits 7 to 0.
5 low-order bits at address 0000H
in program memory are set in PC
bits 12 to 8, and the data at address
0001H are set in PC bits 7 to 0.
Undefined
0
0
Bit 6 at address 0000H in program
memory is set in RBE, and bit 7 is
set in MBE.
Undefined
1000B
Undefined
Undefined
0, 0
Undefined
0
0
0
FFH
0
0, 0
0
FFH
0
0, 0
0
Undefined
0
0
Undefined
Generation of a RESET signal
during operation
Generation of a RESET signal in
a standby mode
Hardware
Carry flag (CY)
Skip flags (SK0 to SK2)
Interrupt status flags (IST0, IST1)
Bank enable flags (MBE, RBE)
µ
PD750104
µ
PD750106, 750108
Counter (BT)
Mode register (BTM)
Watchdog timer enable flag
(WDTM)
Counter (T0)
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT flip-flop
Counter (T1)
Modulo register (TMOD1)
Mode register (TM1)
TOE1, TOUT flip-flop
Mode register (WM)
Shift register (SIO)
Operation mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Basic interval
timer/ watchdog
timer
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
38 Data Sheet U12301EJ1V1DS
Table 9-1. Status of the Hardware after a Reset (2/2)
0
0
0
0
Reset (0)
0
0
0, 0, 0
Off
Clear (0)
0
0
Undefined
Generation of a RESET signal
during operation
Clock generator,
clock output cir-
cuit
Interrupt
Digital ports
Processor clock control register (PCC)
System clock control register (SCC)
Clock output mode register (CLOM)
Interrupt request flag (IRQ×××)
Interrupt enable flag (IE×××)
Priority selection register (IPS)
INT0, INT1, and INT2 mode registers
(IM0, IM1, IM2)
Output buffer
Output latch
I/O mode registers (PMGA, PMGB,
PMGC)
Pull-up resistor specification registers
(POGA, POGB)
Generation of a RESET signal in
a standby mode
Hardware
Sub-oscillator control register (SOS)
0
0
0
0
Reset (0)
0
0
0, 0, 0
Off
Clear (0)
0
0
Held
Bit sequential buffers (BSB0 to BSB3)
39
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
10. MASK OPTION
The
µ
PD750108 has the following mask options:
Mask option of P40 to P43 and P50 to P53
Can specify whether to incorporate the pull-up resistor.
The pull-up resistor is incorporated bit by bit.
The pull-up resistor is not incorporated.
Mask option of standby function
Can specify the wait time when STOP mode was released by an interrupt.
29/fCC (256
µ
s at 2.0 MHz, 512
µ
s at 1.0 MHz)
No wait
Mask option of subsystem clock
Can specify whether to enable the built-in feedback resistor.
The built-in feedback resistor is enabled (it is turned on or off by software).
The built-in feedback resistor is disabled (it is cut by hardware).
1
2
2
1
2
1
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
40 Data Sheet U12301EJ1V1DS
Description
Representation
format
11. INSTRUCTION SET
(1) Operand identifier and its descriptive method
The operands are described in the operand column of each instruction according to the descriptive method for
the operand format of the appropriate instructions. (For details, refer to the RA75X Assembler Package User's
Manual: Language (EEU-1363).) For descriptions in which alternatives exist, one element should be selected.
Capital letters and plus and minus signs are keywords; therefore, they should be described as they are.
For immediate data, the appropriate numerical values or labels should be described.
The symbols of register flags can be used as a label instead of mem, fmem, pmem, and bit. (For details, refer
to the
µ
PD750108 User’s Manual (U11330E).) However, there are some restrictions on usable labels for fmem
and pmem.
Note Only even address can be specified for 8-bit data processing.
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
XA, BC, DE, HL
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA', BC', DE', HL'
BC, DE, HL, XA', BC', DE', HL'
HL, HL+, HL-, DE, DL
DE, DL
4-bit immediate data or label
8-bit immediate data or label
8-bit immediate data or labelNote
2-bit immediate data or label
FB0H - FBFH, FF0H - FFFH immediate data or label
FC0H - FFFH immediate data or label
0000H - 0FFFH immediate data or label (
µ
PD750104)
0000H - 17FFH immediate data or label (
µ
PD750106)
0000H - 1FFFH immediate data or label (
µ
PD750108)
0000H - 0FFFH immediate data or label (
µ
PD750104)
0000H - 17FFH immediate data or label (
µ
PD750106)
0000H - 1FFFH immediate data or label (
µ
PD750108)
12-bit immediate data or label
11-bit immediate data or label
20H - 7FH immediate data (however, bit 0 = 0) or label
PORT0 - PORT8
IEBT, IET0, IET1, IE0 - IE2, IE4, IECSI, IEW
RB0 - RB3
MB0, MB1, MB15
reg
reg1
rp
rp1
rp2
rp'
rp'1
rpa
rpa1
n4
n8
mem
bit
fmem
pmem
addr
addr1(for Mk ΙΙ
mode only)
caddr
faddr
taddr
PORTn
IE×××
RBn
MBn
41
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
(2) Symbol definitions in operation description
A:A register; 4-bit accumulator
B:B register
C:C register
D:D register
E:E register
H:H register
L:L register
X:X register
XA : Register pair (XA); 8-bit accumulator
BC : Register pair (BC)
DE : Register pair (DE)
HL : Register pair (HL)
XA' : Extended register pair (XA')
BC' : Extended register pair (BC')
DE' : Extended register pair (DE')
HL' : Extended register pair (HL')
PC : Program counter
SP : Stack pointer
CY : Carry flag; Bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn : Port n (n = 0 to 8)
IME : Interrupt master enable flag
IPS : Interrupt priority specification register
IE××× :Interrupt enable flag
RBS : Register bank selection register
MBS : Memory bank selection register
PCC : Processor clock control register
.:Address bit delimiter
(××):Contents addressed by ××
××H:Hexadecimal data
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
42 Data Sheet U12301EJ1V1DS
(3) Symbols used for the addressing area column
Remarks 1. MB indicates the memory bank that can be accessed.
2. For *2, MB = 0 regardless of MBE and MBS settings.
3. For *4 and *5, MB = 15 regardless of MBE and MBS settings.
4. For *6 to *11, each addressable area is indicated.
(4) Description of machine cycle column
S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S changes
as follows:
When no skip is performed : S = 0
When a 1-byte or 2-byte instruction is skipped : S = 1
When a 3-byte instructionNote is skipped : S = 2
Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 instructions.
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle (= tCY) of the CPU clock (
Φ
), and four types of times are available for
selection according to the PCC setting.
* 1 MB = MBE • MBS (MBS = 0, 1, 15)
* 2 MB = 0
* 3 MBE = 0
MBE = 1
:
:
MB = 0 (000H - 07FH), MB = 15 (F80H - FFFH)
MB = MBS (MBS = 0, 1, 15)
* 4 MB = 15, fmem = FB0H - FBFH, FF0H - FFFH
* 5 MB = 15, pmem = FC0H - FFFH
* 6 addr = 0000H - 0FFFH ( PD750104), 0000H - 17FFH ( PD750106)
0000H - 1FFFH ( PD750108)
µ
µ
µ
* 7 addr, addr1 = (Current PC) - 15 to (Current PC) - 1
(Current PC) + 2 to (Current PC) + 16
* 8 caddr = 0000H - 0FFFH ( PD750104)
0000H - 0FFFH (PC12 = 0: PD750106, 750108)
1000H - 17FFH (PC12 = 1: PD750106)
1000H - 1FFFH (PC12 = 1: PD750108)
µ
µ
µ
* 9 faddr = 0000H - 07FFH
* 10 taddr = 0020H - 007FH
Data memory
addressing
Program memory
addressing
µ
Mk ΙΙ mode only
addr1 =
µ
µ
µ
0000H - 0FFFH ( PD750104)
0000H - 17FFH ( PD750106)
0000H - 1FFFH ( PD750108)
* 11
43
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Group
Transfer
Table
reference
Mne-
monic
MOV
XCH
MOVT
Operand
A, #n4
reg1, #n4
XA, #n8
HL, #n8
rp2, #n8
A, @HL
A, @HL+
A, @HL-
A, @rpa1
XA, @HL
@HL, A
@HL, XA
A, mem
XA, mem
mem, A
mem, XA
A, reg
XA, rp'
reg1, A
rp'1, XA
A, @HL
A, @HL+
A, @HL-
A, @rpa1
XA, @HL
A, mem
XA, mem
A, reg1
XA, rp'
XA, @PCDE
XA, @PCXA
XA, @BCDE
XA, @BCXA
Bytes
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
1
1
1
Machin-
ing
cycle
1
2
2
2
2
1
2 + S
2 + S
1
2
1
2
2
2
2
2
2
2
2
2
1
2 + S
2 + S
1
2
2
2
1
2
3
3
3
3
Skip
condition
String A
String A
String B
L = 0
L = FH
L = 0
L = FH
Address-
ing area
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
*1
*1
*1
*2
*1
*3
*3
*6
*6
Operation
A n4
reg1 n4
XA n8
HL n8
rp2 n8
A (HL)
A (HL), then L L + 1
A (HL), then L L - 1
A (rpa1)
XA (HL)
(HL) A
(HL) XA
A (mem)
XA (mem)
(mem) A
(mem) XA
A reg
XA rp'
reg1 A
rp'1 XA
A (HL)
A (HL), then L L + 1
A (HL), then L L - 1
A (rpa1)
XA (HL)
A (mem)
XA (mem)
A reg1
XA rp'
µ
PD750104
XA (PC11-8 + DE) ROM
µ
PD750106, 750108
XA (PC12-8 + DE) ROM
µ
PD750104
XA (PC11-8 + XA) ROM
µ
PD750106, 750108
XA (PC12-8 + XA) ROM
XA (BCDE) ROMNote
XA (BCXA) ROMNote
Note Set register B to 0 in the
µ
PD750104. Only the LSB is valid in register B in the
µ
PD750106 and
µ
PD750108.
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
44 Data Sheet U12301EJ1V1DS
Group
Bit transfer
Arithme-
tic
Accumulator
manipulation
Increment/
decrement
Mne-
monic
MOV1
ADDS
ADDC
SUBS
SUBC
AND
OR
XOR
RORC
NOT
INCS
DECS
Operand
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
A, #n4
XA, #n8
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A
A
reg
rp1
@HL
mem
reg
rp'
Bytes
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
1
1
2
2
1
2
Machin-
ing
cycle
2
2
2
2
2
2
1 + S
2 + S
1 + S
2 + S
2 + S
1
2
2
1 + S
2 + S
2 + S
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
1 + S
1 + S
2 + S
2 + S
1 + S
2 + S
Skip
condition
carry
carry
carry
carry
carry
borrow
borrow
borrow
reg = 0
rp1 = 00H
(HL) = 0
(mem) = 0
reg = FH
rp' = FFH
Address-
ing area
*4
*5
*1
*4
*5
*1
*1
*1
*1
*1
*1
*1
*1
*1
*3
Operation
CY (fmem.bit)
CY (pmem7-2 + L3-2.bit(L1-0))
CY (H + mem3-0.bit)
(fmem.bit) CY
(pmem7-2 + L3-2.bit(L1-0)) CY
(H + mem3-0.bit) CY
A A + n4
XA XA + n8
A A + (HL)
XA XA + rp'
rp'1 rp'1 + XA
A, CY A + (HL) + CY
XA, CY XA + rp' + CY
rp'1, CY rp'1 + XA + CY
A A - (HL)
XA XA - rp'
rp'1 rp'1 - XA
A, CY A - (HL) - CY
XA, CY XA - rp' - CY
rp'1, CY rp'1 - XA - CY
A A
n4
A A
(HL)
XA XA
rp'
rp'1 rp'1
XA
A A
n4
A A
(HL)
XA XA
rp'
rp'1 rp'1
XA
A A n4
A A (HL)
XA XA rp'
rp'1 rp'1 XA
CY A0, A3 CY, An-1 An
A A
reg reg + 1
rp1 rp1 + 1
(HL) (HL) + 1
(mem) (mem) + 1
reg reg - 1
rp' rp' - 1
45
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Group
Compari-
son
Carry flag
manipula-
tion
Memory
bit
manipula-
tion
Mne-
monic
SKE
SET1
CLR1
SKT
NOT1
SET1
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
Operand
reg, #n4
@HL, #n4
A, @HL
XA, @HL
A, reg
XA, rp'
CY
CY
CY
CY
mem.bit
fmem.bit
pmem.@L
@H+mem.bit
mem.bit
fmem.bit
pmem.@L
@H+mem.bit
mem.bit
fmem.bit
pmem.@L
@H+mem.bit
mem.bit
fmem.bit
pmem.@L
@H+mem.bit
fmem.bit
pmem.@L
@H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
Bytes
2
2
1
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Machin-
ing
cycle
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1
1
1 + S
1
2
2
2
2
2
2
2
2
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2
2
2
2
2
2
2
2
2
Skip
condition
reg = n4
(HL) = n4
A = (HL)
XA = (HL)
A = reg
XA = rp'
CY = 1
(mem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H + mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
Address-
ing area
*1
*1
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
Operation
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if XA = (HL)
Skip if A = reg
Skip if XA = rp'
CY 1
CY 0
Skip if CY = 1
CY CY
(mem.bit) 1
(fmem.bit) 1
(pmem7-2 + L3-2.bit(L1-0)) 1
(H + mem3-0.bit) 1
(mem.bit) 0
(fmem.bit) 0
(pmem7-2 + L3-2.bit(L1-0)) 0
(H + mem3-0.bit) 0
Skip if (mem.bit) = 1
Skip if (fmem.bit) = 1
Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1
Skip if (H + mem3-0.bit) = 1
Skip if (mem.bit) = 0
Skip if (fmem.bit) = 0
Skip if (pmem7-2 + L3-2.bit(L1-0)) = 0
Skip if (H + mem3-0.bit) = 0
Skip if (fmem.bit) = 1 and clear
Skip if (pmem
7-2
+ L
3-2
.bit(L
1-0
)) = 1 and clear
Skip if (H + mem
3-0
.bit) = 1 and clear
CY CY (fmem.bit)
CY CY
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
CY CY (H + mem3-0.bit)
CY CY (fmem.bit)
CY CY
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
CY CY (H + mem3-0.bit)
CY CY (fmem.bit)
CY CY
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
CY CY (H + mem3-0.bit)
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
46 Data Sheet U12301EJ1V1DS
Group
Branch
Mne-
monic
BRNote
Operand
addr
addr1
!addr
$addr
$addr1
Skip
condition
Address-
ing area
*6
*11
*6
*7
Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.
Bytes
-
-
3
1
1
Machin-
ing
cycle
-
-
3
2
2
Operation
µ
PD750104
PC11-0 addr
The assembler selects the most
adequate instruction from BR !addr,
BRCB !caddr, or BR $addr.
µ
PD750106, 750108
PC12-0 addr
The assembler selects the most
adequate instruction from BR !addr,
BRCB !caddr, or BR $addr.
µ
PD750104
PC11-0 addr1
The assembler selects the most
adequate instruction from
instructions below.
• BR !addr
• BRA !addr1
• BRCB !caddr
• BR $addr1
µ
PD750106, 750108
PC12-0 addr1
The assembler selects the most
adequate instruction from
instructions below.
• BR !addr
• BRA !addr1
• BRCB !caddr
• BR $addr1
µ
PD750104
PC11-0 addr
µ
PD750106, 750108
PC12-0 addr
µ
PD750104
PC11-0 addr
µ
PD750106, 750108
PC12-0 addr
µ
PD750104
PC11-0 addr1
µ
PD750106, 750108
PC12-0 addr1
47
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Group
Branch
Subrou-
tine stack
control
Mne-
monic
BR
BRA
Note 3
BRCB
CALLA
Note 3
Operand
PCDE
PCXA
BCDE
BCXA
!addr1
!caddr
!addr1
Bytes
2
2
2
2
3
2
3
Machin-
ing
cycle
3
3
3
3
3
2
3
Skip
condition
Address-
ing area
*6
*6
*11
*8
*11
Operation
µ
PD750104
PC11-0 PC11-8 + DE
µ
PD750106, 750108
PC12-0 PC12-8 + DE
µ
PD750104
PC11-0 PC11-8 + XA
µ
PD750106, 750108
PC12-0 PC12-8 + XA
µ
PD750104
PC11-0 BCDENote 1
µ
PD750106, 750108
PC12-0 BCDENote 2
µ
PD750104
PC11-0 BCXANote 1
µ
PD750106, 750108
PC12-0 BCXANote 2
µ
PD750104
PC11-0 addr1
µ
PD750106, 750108
PC12-0 addr1
µ
PD750104
PC11-0 caddr11-0
µ
PD750106, 750108
PC12-0 PC12 + caddr11-0
µ
PD750104
(SP - 2) ×, ×, MBE, RBE
(SP - 6) (SP - 3) (SP - 4) PC11-0
(SP - 5) 0, 0, 0, 0
PC11-0 addr1, SP SP - 6
µ
PD750106, 750108
(SP - 2) ×, ×, MBE, RBE
(SP - 6) (SP - 3) (SP - 4) PC11-0
(SP - 5) 0, 0, 0, PC12
PC12-0 addr1, SP SP - 6
Notes 1. Set register B to 0.
2. Only the LSB is valid in register B.
3. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode
only.
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
48 Data Sheet U12301EJ1V1DS
Group
Subrou-
tine stack
control
Mne-
monic
CALL
Note
CALLF
Note
Operand
!addr
!faddr
Bytes
3
2
Machin-
ing
cycle
3
4
2
3
Skip
condition
Address-
ing area
*6
*9
Operation
µ
PD750104
(SP - 3) MBE, RBE, 0, 0
(SP - 4) (SP - 1) (SP - 2) PC11-0
PC11-0 addr, SP SP - 4
µ
PD750106, 750108
(SP - 3) MBE, RBE, 0, PC12
(SP - 4) (SP - 1) (SP - 2) PC11-0
PC12-0 addr, SP SP - 4
µ
PD750104
(SP - 2) ×, ×, MBE, RBE
(SP - 6) (SP - 3) (SP - 4) PC11-0
(SP - 5) 0, 0, 0, 0
PC11-0 addr, SP SP - 6
µ
PD750106, 750108
(SP - 2) ×, ×, MBE, RBE
(SP - 6) (SP - 3) (SP - 4) PC11-0
(SP - 5) 0, 0, 0, PC12
PC12-0 addr, SP SP - 6
µ
PD750104
(SP - 3) MBE, RBE, 0, 0
(SP - 4) (SP - 1) (SP - 2) PC11-0
PC11-0 0 + faddr, SP SP - 4
µ
PD750106, 750108
(SP - 3) MBE, RBE, 0, PC12
(SP - 4) (SP - 1) (SP - 2) PC11-0
PC12-0 00 + faddr, SP SP - 4
µ
PD750104
(SP - 2) ×, ×, MBE, RBE
(SP - 6) (SP - 3) (SP - 4) PC11-0
(SP - 5) 0, 0, 0, 0
PC11-0 0 + faddr, SP SP - 6
µ
PD750106, 750108
(SP - 2) ×, ×, MBE, RBE
(SP - 6) (SP - 3) (SP - 4) PC11-0
(SP - 5) 0, 0, 0, PC12
PC12-0 00 + faddr, SP SP - 6
Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.
49
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Group
Subrou-
tine stack
control
Mne-
monic
RET
Note
RETSNote
Operand Bytes
1
1
Machin-
ing
cycle
3
3
3 + S
3 + S
Skip
condition
Uncondition
Address-
ing area
Operation
µ
PD750104
PC11-0 (SP) (SP + 3) (SP + 2)
MBE, RBE, 0, 0 (SP + 1), SP SP + 4
µ
PD750106, 750108
PC11-0 (SP) (SP + 3) (SP + 2)
MBE, RBE, 0, PC12 (SP + 1)
SP SP + 4
µ
PD750104
×, ×, MBE, RBE (SP + 4)
0, 0, 0, 0 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
SP SP + 6
µ
PD750106, 750108
×, ×, MBE, RBE (SP + 4)
MBE, 0, 0, PC12 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
SP SP + 6
µ
PD750104
MBE, RBE, 0, 0 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
SP SP + 4
then skip unconditionally
µ
PD750106, 750108
MBE, RBE, 0 PC12 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
SP SP + 4
then skip unconditionally
µ
PD750104
0, 0, 0, 0 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
×, ×, MBE, RBE (SP + 4)
SP SP + 6
then skip unconditionally
µ
PD750106, 750108
0, 0, 0, PC12 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
×, ×, MBE, RBE (SP + 4)
SP SP + 4
then skip unconditionally
Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
50 Data Sheet U12301EJ1V1DS
Group
Subrou-
tine stack
control
Interrupt
control
Input/
output
CPU
control
Mne-
monic
RETI
Note 1
PUSH
POP
EI
DI
INNote 2
OUT
Note 2
HALT
STOP
NOP
Operand
rp
BS
rp
BS
IE×××
IE×××
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
Bytes
1
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
Machin-
ing
cycle
3
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
Skip
condition
Address-
ing area
Operation
µ
PD750104
MBE, RBE, 0, 0 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
PSW (SP + 4) (SP + 5), SP SP + 6
µ
PD750106, 750108
MBE, RBE, 0, PC12 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
PSW (SP + 4) (SP + 5), SP SP + 6
µ
PD750104
0, 0, 0, 0 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
PSW (SP + 4) (SP + 5), SP SP + 6
µ
PD750106, 750108
0, 0, 0, PC12 (SP + 1)
PC11-0 (SP) (SP + 3) (SP + 2)
PSW (SP + 4) (SP + 5), SP SP + 6
(SP - 1)(SP - 2) rp, SP SP - 2
(SP - 1) MBS, (SP - 2) RBS,
SP SP - 2
rp (SP + 1)(SP), SP SP + 2
MBS (SP + 1), RBS (SP),
SP SP + 2
IME (IPS.3) 1
IE××× 1
IME (IPS.3) 0
IE××× 0
A PORTn (n = 0 - 8)
XA PORTn+1,PORTn (n = 4, 6)
PORTn A (n = 2 - 8)
PORTn+1,PORTn XA (n = 4, 6)
Set HALT Mode (PCC.2 1)
Set STOP Mode (PCC.3 1)
No Operation
Notes 1. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode
only.
2. When executing the IN/OUT instruction, MBE must be set to 0 or MBE and MBS must be set to 1 and
15, respectively.
51
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Group
Special
Mne-
monic
SEL
GETI
Notes 1, 2
Operand
RBn
MBn
taddr
Bytes
2
2
1
Machin-
ing
cycle
2
2
3
3
4
3
Skip
condition
Depends
on the
referenced
instruction.
Depends
on the
referenced
instruction.
Depends
on the
referenced
instruction.
Address-
ing area
*10
*10
Operation
RBS n (n = 0 - 3)
MBS n (n = 0, 1, 15)
µ
PD750104
When the TBR instruction is used
PC11-0 (taddr)3-0 + (taddr + 1)
When the TCALL instruction is used
(SP - 4) (SP - 1) (SP - 2) PC11-0
(SP - 3) MBE, RBE, 0, 0
PC11-0 (taddr)3-0 + (taddr + 1)
SP SP - 4
When an instruction other than the
TBR and TCALL instructions is used
Execution of (taddr)(taddr + 1)
instruction
µ
PD750106, 750108
When the TBR instruction is used
PC12-0 (taddr)4-0 + (taddr + 1)
When the TCALL instruction is used
(SP - 4) (SP - 1) (SP - 2) PC11-0
(SP - 3) MBE, RBE, 0, PC12
PC12-0 (taddr)4-0 + (taddr + 1)
SP SP - 4
When an instruction other than the
TBR and TCALL instructions is used
Execution of (taddr)(taddr + 1)
instruction
µ
PD750104
When the TBR instruction is used
PC11-0 (taddr)3-0 + (taddr + 1)
When the TCALL instruction is used
(SP - 6) (SP - 3) (SP - 4) PC11-0
(SP - 5) 0, 0, 0, 0
(SP - 2) ×, ×, MBE, RBE
PC11-0 (taddr)3-0 + (taddr + 1)
SP SP - 6
When an instruction other than the TBR
and TCALL instructions is used
Execution of (taddr)(taddr + 1)
instruction
Notes 1. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode
only.
2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI
instructions.
........................................................
........................................................
........................................................
........................................................ .....................
.....................
.......................................................................
....................................................................... .....................
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
52 Data Sheet U12301EJ1V1DS
Group
Special
Mne-
monic
GETI
Notes 1, 2
Operand
taddr
Bytes
1
Machin-
ing
cycle
3
4
3
Skip
condition
Depends
on the
referenced
instruction.
Address-
ing area
*10
Operation
µ
PD750106, 750108
When the TBR instruction is used
PC12-0 (taddr)4-0 + (taddr + 1)
When the TCALL instruction is used
(SP - 6) (SP - 3) (SP - 4) PC11-0
(SP - 5) 0, 0, 0, PC12
(SP - 2) ×, ×, MBE, RBE
PC12-0 (taddr)4-0 + (taddr + 1)
SP SP - 6
When an instruction other than the TBR
and TCALL instructions is used
Execution of (taddr)(taddr + 1)
instruction
Notes 1. The shaded portion is supported in Mk ΙΙ mode only.
2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI
instructions.
.......................................................................
....................................................................... .....................
53
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
12. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the
product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.
CAPACITANCE (TA = 25 °C, VDD = 0 V)
Unit
V
V
V
V
V
mA
mA
mA
mA
°C
°C
Rated value
-0.3 to +7.0
-0.3 to VDD + 0.3
-0.3 to VDD + 0.3
-0.3 to +14.0
-0.3 to VDD + 0.3
-10
-30
30
220
-40 to +85
-65 to +150
Conditions
Other than ports 4 and 5
Ports With a built-in pull-up resistor
4 and 5 With N-ch open drain
Each pin
Total of all pins
Each pin
Total of all pins
Parameter
Supply voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Operating ambient temperature
Storage temperature
Symbol
VDD
VI1
VI2
VO
IOH
IOL
TA
Tstg
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CIN
COUT
CIO
MAX.
15
15
15
Unit
pF
pF
pF
TYP.
Conditions
f = 1 MHz
0 V for pins other than pins to be
measured
MIN.
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
54 Data Sheet U12301EJ1V1DS
Recommended
constant
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
Note The oscillator frequency indicates only the oscillator characteristics. See AC characteristics for the
instruction execution time and oscillator frequency characteristics.
Caution When the main system clock oscillator is used, conform to the following guidelines when wiring
at the portions surrounded by dotted lines in the figures above to eliminate the influence of the
wiring capacity.
The wiring must be as short as possible.
Other signal lines must not run in these areas.
Any line carrying a high fluctuating current must be kept away as far as possible.
The grounding point of the capacitor of the oscillator must have the same potential as that
of VSS.
It must not be grounded to ground patterns carrying a large current.
No signal must be taken from the oscillator.
TYP.Parameter
Oscillator frequency (fCC)Note
MIN.
0.4
MAX.
2.0
Unit
MHz
ConditionsResonator
RC
oscillator
CL1 CL2
55
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Recommended
constant
Resonator Parameter
kHz
s
s
kHz
µ
s
Unit
35
2
10
100
15
32.768
1.0
32
32
5
Conditions
Crystal
External
clock
Oscillator frequency (fXT)Note 1
Oscillation settling timeNote 2
XT1 input frequency (fXT)Note 1
XT1 input high/low level width
(tXTH, tXTL)
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item
of AC characteristics for the instruction execution time.
2. The oscillation settling time means the time required for the oscillation to settle after VDD is applied.
Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring
at the portions of surrounded by dotted lines in the figures above to eliminate the influence of
the wiring capacity.
The wiring must be as short as possible.
Other signal lines must not run in these areas.
Any line carrying a high fluctuating current must be kept away as far as possible.
The grounding point of the capacitor of the oscillator must have the same potential as that of
VSS
It must not be grounded to ground patterns carrying a large current.
No signal must be taken from the oscillator.
When the subsystem clock is used, pay special attention to its wiring; the subsystem clock
oscillator has low amplification to minimize current consumption and is more likely to malfunc-
tion due to noise than the main system clock oscillator.
MIN. TYP. MAX.
C3 C4
R
XT1 XT2
XT1 XT2
VDD = 4.5 to 5.5 V
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
56 Data Sheet U12301EJ1V1DS
DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter Symbol
mA
mA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
k
k
IOL
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
VOH
VOL1
VOL2
ILIH1
ILIH2
ILIH3
ILIL1
ILIL2
ILIL3
ILOH1
ILOH2
ILOL
RL1
RL2
0.7VDD
0.9VDD
0.8VDD
0.9VDD
0.7VDD
0.9VDD
0.7VDD
0.9VDD
VDD - 0.1
0
0
0
0
0
VDD - 0.5
50
15
SCK, SO,
and ports
2 to 8
VDD = 5.0 V
VDD = 3.0 V
0.2
-10
-3
100
30
15
150
VDD
VDD
VDD
VDD
VDD
VDD
13
13
VDD
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.1
2.0
0.4
0.2VDD
3
20
20
-3
-20
-3
-30
-27
-8
3
20
-3
200
60
MIN. TYP. MAX. Unit
Low-level output
current
High-level input
voltage
Low-level input
voltage
High-level output voltage
Low-level output
voltage
High-level input
leakage current
Low-level input
leakage current
High-level output
leakage current
Low-level output
leakage current
Built-in pull-up
resistor
Ports 4 and 5 (With N-ch
open drain)
When the input instruction
is executed
With a Built-in pull-up
resistor
With N-ch open drain
Each pin
Total of all pins
Ports 2, 3, and 8
Ports 0, 1, 6, and 7 and RESET
Ports 4 and
5
XT1
Ports 2 to 5, and 8
Ports 0, 1, 6, and 7 and RESET
XT1
SCK, SO, and ports 2, 3, and 6 to 8 IOH = -1.0 mA
SB0, SB1 N-ch open drain Pull-up resistor 1 k
VIN = VDD Other than XT1
XT1
VIN = 13 V Ports 4 and 5 (With N-ch open drain)
VIN = 0 V Other than XT1 and ports 4 and 5
XT1
Ports 4 and 5 (With N-ch open drain)
At other than input instruction execution
VOUT = VDD SCK, SO/SB0, SB1, and ports 2, 3, and 6
to 8
Ports 4 and 5 (With a built-in pull-up resistor)
VOUT = 13 V Ports 4 and 5 (With N-ch open drain)
VOUT = 0 V
VIN = 0 V Ports 0 to 3 and 6 to 8 (except P00 pin)
Ports 4 and 5 (mask option)
Conditions
2.7 V VDD 5.5 V
1.8 V VDD < 2.7 V
2.7 V VDD 5.5 V
1.8 V VDD < 2.7 V
2.7 V VDD 5.5 V
1.8 V VDD < 2.7 V
2.7 V VDD 5.5 V
1.8 V VDD < 2.7 V
2.7 V VDD 5.5 V
1.8 V VDD < 2.7 V
2.7 V VDD 5.5 V
1.8 V VDD < 2.7 V
IOL = 15 mA, VDD = 5.0 V ± 10%
IOL = 1.6 mA
57
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Parameter
Power supply
currentNote 1
Conditions
Low-current-
drain
modeNote 7
DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
Notes 1. This current excludes the current which flows through the built-in pull-up resistors.
2. This value applies also when the subsystem clock oscillates.
3. Value when the processor clock control register (PCC) is set to 0011 and the
µ
PD750108 is operated
in the high-speed mode.
4. Value when the PCC is set to 0000 and the
µ
PD750108 is operated in the low-speed mode.
5. This value applies when the system clock control register (SCC) is set to 1001 to stop the main system
clock pulse and to start the subsystem clock pulse.
6. Mode when the sub-oscillator control register (SOS) is set to 0000.
7. Mode when the SOS is set to 0010.
8. This value applies when the SOS is set to 00×1 and the sub-oscillator feedback resistor is not used (×
= don’t care).
Symbol
IDD1
IDD2
IDD3
IDD4
IDD5
Unit
mA
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
VDD = 5.0 V ± 10%Note 3
VDD = 3.0 V ± 10%Note 4
HALT mode
Low-voltage
modeNote 6
HALT mode Low-vol-
tage
modeNote 6
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
Low-cur-
rent-drain
modeNote 7
XT1 =
0 VNote 8
STOP
mode
VDD = 3.0 V ± 10%
VDD = 3.0 V,
TA = -40 to +50 °C
VDD = 2.0 V ± 10%
VDD = 3.0 V, TA = 25 °C
VDD = 3.0 V ± 10%
VDD = 3.0 V,
TA = -40 to +50 °C
VDD = 3.0 V, TA = 25 °C
TA = 25 °C
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
VDD = 3.0 V, TA = 25 °C
VDD = 3.0 V ± 10%
VDD = 3.0 V, TA = 25 °C
1.0
MHzNote 2
RC
oscillation
R = 22 k,
C = 22 pF
32.768
kHzNote 5
crystal
oscillation
MIN. TYP.
0.65
180
370
170
11.0
5.5
11.0
8.0
8.0
5.0
5.0
2.5
5.0
4.0
4.0
4.0
0.05
0.02
0.02
MAX.
1.6
360
920
340
40.0
18.0
18.0
24.0
14.0
30.0
12.0
10.0
10.0
15.0
8.0
7.0
5.0
2.5
0.2
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
58 Data Sheet U12301EJ1V1DS
AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
CPU clock cycle
timeNote 1 (minimum
instruction execution time
= 1 machine cycle)
TI0 input frequency
TI0 input high/low level
width
Interrupt input high/low
level width
RESET low level width
RC oscillator frequency
IM02 = 0
IM02 = 1
Notes 1. When the main system clock is used, the
cycle time of the CPU clock (
Φ
) (minimum
instruction execution time) depends on the
time constants of connected resistors (R)
and capacitors (C) and the processor clock
control register (PCC).
When the subsystem clock is used, the cycle
time of the CPU clock (
Φ
) (minimum instruc-
tion execution time) depends on the fre-
quency of the connected resonator (and ex-
ternal clock), the system clock control regis-
ter (SCC), and the processor clock control
register (PCC).
The figure on the right side shows the cycle
time tCY characteristics for the supply voltage
VDD during main system clock operation.
2. This value becomes 2tCY or 128/fCC accord-
ing to the setting of the interrupt mode reg-
ister (IM0).
tCY
fTI
tTIH,
tTIL
tINTH,
tINTL
tRSL
fCC
Conditions MIN. TYP. MAX. Unit
Operated by main system clock pulse 2.0 128
µ
s
Operated by subsystem clock pulse 114 122 125
µ
s
VDD = 2.7 to 5.5 V 0 1 MHz
0275 kHz
VDD = 2.7 to 5.5 V 0.48
µ
s
1.8
µ
s
INT0 Note 2
µ
s
10
µ
s
INT1, INT2, and INT4 10
µ
s
KR0 to KR7 10
µ
s
10
µ
s
MHz
MHz
Parameter Symbol
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
1.00
1.00
1.30
1.30
0.90
0.55
R = 22 k,
C = 22 pF
11.8 2 3 4 5 5.5 60
0.5
1
2
3
4
5
6
128
t
CY
vs. V
DD
(Main system clock in operation)
Cycle time t
CY
[ s]
µ
Power supply voltage V
DD
[V]
Operation guaranteed
range
59
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
SCK cycle time
SCK high/low level
width
SINote 1 setup time
(referred to SCK)
SINote 1 hold time
(referred to SCK)
Delay time from SCK
to SONote 1 output
SERIAL TRANSFER OPERATION
Two-wire and three-wire serial I/O modes (SCK: Internal clock output): (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1.
2. RL is the resistance of the SO output line load, while CL is the capacitance.
Two-wire and three-wire serial I/O modes (SCK: External clock input): (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1.
2. RL is the resistance of the SO output line load, while CL is the capacitance.
TYP. MAX.
300
1,000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
800
3,200
400
1,600
100
150
400
600
0
0
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
RL = 1 kNote 2 VDD = 2.7 to 5.5 V
CL = 100 pF
Symbol
tKCY2
tKL2,
tKH2
tSIK2
tKSI2
tKSO2
Parameter
SCK cycle time
SCK high/low level
width
SINote 1 setup time
(referred to SCK)
SINote 1 hold time
(referred to SCK)
Delay time from SCK
to SONote 1 output
MIN.
1,300
3,800
tKCY1/2 - 50
tKCY1/2 - 150
150
500
400
600
0
0
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
RL = 1 kNote 2 VDD = 2.7 to 5.5 V
CL = 100 pF
Symbol
tKCY1
tKL1,
tKH1
tSIK1
tKSI1
tKSO1
TYP. MAX.
250
1,000
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
60 Data Sheet U12301EJ1V1DS
SBI mode (SCK: Internal clock output (master)): (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance.
SBI mode (SCK: External clock input (slave)): (TA = -40 to +85 °C, VDD = 1.8 to 5.5 V)
Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance.
TYP. MAX.
250
1,000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
1,300
3,800
tKCY3/2 - 50
tKCY3/2 - 150
150
500
tKCY3/2
0
0
tKCY3
tKCY3
tKCY3
tKCY3
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
RL = 1 kNote VDD = 2.7 to 5.5 V
CL = 100 pF
Symbol
tKCY3
tKL3,
tKH3
tSIK3
tKSI3
tKSO3
tKSB
tSBK
tSBL
tSBH
Parameter
SCK cycle time
SCK high/low level
width
SB0/SB1 setup time
(referred to SCK)
SB0/SB1 hold time
(referred to SCK)
Delay time from SCK
to SB0/SB1 output
From SCK to SB0/SB1
From SB0/SB1 to SCK
SB0/SB1 low level width
SB0/SB1 high level
width
TYP. MAX.
300
1,000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
800
3,200
400
1,600
100
150
tKCY4/2
0
0
tKCY4
tKCY4
tKCY4
tKCY4
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
RL = 1 kNote VDD = 2.7 to 5.5 V
CL = 100 pF
Symbol
tKCY4
tKL4,
tKH4
tSIK4
tKSI4
tKSO4
tKSB
tSBK
tSBL
tSBH
Parameter
SCK cycle time
SCK high/low level
width
SB0/SB1 setup time
(referred to SCK)
SB0/SB1 hold time
(referred to SCK)
Delay time from SCK
to SB0/SB1 output
From SCK to SB0/SB1
From SB0/SB1 to SCK
SB0/SB1 low level width
SB0/SB1 high level
width
61
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
AC timing measurement points (excluding XT1 input)
Clock timing
TI0 timing
t
XTL
t
XTH
1/f
XT
XT1 input
V
DD
- 0.1 V
0.1 V
tTIL tTIH
1/fTI
TI0
VIL (MAX.)
VIH (MIN.)
VIL (MAX.)
VIH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
62 Data Sheet U12301EJ1V1DS
Serial transfer timing
Three-wire serial I/O mode:
Two-wire serial I/O mode:
Input data
Output data
SCK
SI
SO
tKCY1
tKCY2
tSIK1
tSIK2
tKSI1
tKSI2
tKL1
tKL2
tKH1
tKH2
t
KSO1
t
KSO2
tKCY1
tKCY2
tKL1
tKL2
tKH1
tKH2
tSIK1
tSIK2
tKSI1
tKSI2
tKSO1
tKSO2
SCK
SB0 and SB1
63
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Serial transfer timing
Bus release signal transfer:
Command signal transfer:
Interrupt input timing
RESET input timing
SCK
SB0 and SB1
t
KSB
t
SBL
t
SBH
t
SBK
t
KCY3
t
KCY4
t
KSO3
t
KSO4
t
KL3
t
KL4
t
KH3
t
KH4
t
KSI3
t
KSI4
t
SIK3
t
SIK4
SCK
SB0 and SB1
t
KSB
t
KL3
t
KL4
t
KCY3
t
KCY4
t
KSO3
t
KSO4
t
SBK
t
KH3
t
KH4
t
SIK3
t
SIK4
t
KSI3
t
KSI4
INT0, INT1, INT2,
and INT4
KR0 - KR7
t
INTL
t
INTH
RESET
tRSL
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
64 Data Sheet U12301EJ1V1DS
Parameter Symbol
Release signal setting time
Oscillation settling timeNote 1
tSREL
tWAIT Release by RESET
Release by interrupt request
Conditions
DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE
(TA = -40 to +85 °C)
Notes 1. CPU operation stop time for preventing unstable operation at the beginning of oscillation.
2. Select either 512/fCC or no wait with the mask option.
Data hold timing (STOP mode release by RESET)
Data hold timing (standby release signal: STOP mode release by interrupt signal)
0
MIN. TYP. MAX. Unit
µ
s
µ
s
µ
s
56/fCC
Note 2
RESET
V
DD
t
SREL
t
WAIT
Internal reset operation
HALT mode
Operation
mode
STOP instruction execution
Data hold mode
STOP mode
Standby release signal
(Interrupt request)
V
DD
t
SREL
t
WAIT
HALT mode
Operation
mode
STOP instruction execution
Data hold mode
STOP mode
65
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
13. CHARACTERISTIC CURVE (REFERENCE VALUES)
CL1 CL2 XT1 XT2
RC
oscillation
22 k
Crystal
32.768 kHz 220 k
22 pF 33 pF 33 pF
0
0.001
0.005
0.01
0.05
Supply current I
DD
(mA)
0.1
0.5
1.0
5.0
10
1234
Su
l
volta
e V
DD
V
5678
I
DD
vs. V
DD
(When the main system clock is operating at 1.0 MHz with an RC oscillation)
(T
A
= 25 ˚C)
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
Main system clock HALT
mode + 32 kHz oscillation
Subsystem clock operating
mode (SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 0) and main system
clock STOP mode + 32 kHz
oscillation (SOS.1 =0)
Subsystem clock HALT mode
(SOS.1 = 1) and main system
clock STOP mode + 32 kHz
oscillation (SOS.1 =1)
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
66 Data Sheet U12301EJ1V1DS
14. EXAMPLES OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES)
0
0.5
1.0
Main system clock frequency f
CC
(MHz)
Sample A
Sample B
Sample C
2.0
1234
Supply voltage V
DD
(V)
5678
CL1 CL2
22 k
22 pF
f
CC
vs. V
DD
(RC oscillation , R = 22 k, C = 22 pF)
(T
A
= -40 ˚C)
0
0.5
1.0
Main system clock frequency f
CC
(MHz)
Sample A
Sample B
Sample C
2.0
1234
Supply voltage VDD (V)
5678
CL1 CL2
22 k
22 pF
(TA = 25 ˚C)
0
0.5
1.0
Main system clock frequency f
CC
(MHz)
Sample A
Sample B
Sample C
2.0
1234
Supply voltage VDD (V)
5678
CL1 CL2
22 k
22 pF
(TA = 85 ˚C)
67
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
-60
0.5
1.0
Main system clock frequency f
CC
(MHz)
2.0
-40 -20 0 +20
O
p
eratin
g
ambient tem
p
erature T
A
(
˚C
)
+40 +60 +80 +100
CL1 CL2
22 k
22 pF
(Sample A)
f
CC
vs. T
A
(RC oscillation, R = 22 k, C = 22 pF)
VDD = 5.0 V
VDD = 3.0 V
VDD = 2.2 V
VDD = 1.8 V
-60
0.5
1.0
Main system clock frequency f
CC
(MHz)
2.0
-40 -20 0 +20
Operating ambient temperature T
A
(˚C)
+40 +60 +80 +100
CL1 CL2
22 k
22 pF
(Sample B)
V
DD
= 5.0 V
V
DD
= 3.0 V
V
DD
= 2.2 V
V
DD
= 1.8 V
-60
0.5
1.0
Main system clock frequency f
CC
(MHz)
2.0
-40 -20 0 +20
Operating ambient temperature T
A
(˚C)
+40 +60 +80 +100
CL1 CL2
22 k
22 pF
(Sample C)
V
DD
= 5.0 V
V
DD
= 3.0 V
V
DD
= 2.2 V
V
DD
= 1.8 V
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
68 Data Sheet U12301EJ1V1DS
15. PACKAGE DRAWINGS
44 PIN PLASTIC QFP ( 10)
S44GB-80-3BS
ITEM MILLIMETERS INCHES
N
P
Q0.125±0.075
0.10
2.7
0.004
0.106
0.005±0.003
NOTE
Each lead centerline is located within 0.16 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
J
I
H
N
A13.2±0.2 0.520+0.008
–0.009
B10.0±0.2 0.394+0.008
–0.009
C10.0±0.2 0.394+0.008
–0.009
D13.2±0.2 0.520+0.008
–0.009
F
G
H
1.0
0.37
1.0 0.039
0.039
0.015+0.003
–0.004
I
J
K
0.8 (T.P.)
1.6±0.2
0.16 0.007
0.031 (T.P.)
0.063±0.008
L0.8±0.2 0.031+0.009
–0.008
M0.17 0.007+0.002
–0.003
S3.0 MAX. 0.119 MAX.
R3°3°+7°
–3°
+0.08
–0.07
+0.06
–0.05
+7°
–3°
detail of lead end
Q
F
G
K
M
L
R
M
33
34 22
44
112
11
23
S
P
CD
A
B
69
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
42PIN PLASTIC SHRINK DIP (600 mil)
ITEM MILLIMETERS INCHES
A
B
C
F
G
H
I
J
K
39.13 MAX.
1.778 (T.P.)
3.2±0.3
0.51 MIN.
4.31 MAX.
1.78 MAX.
0.17
15.24 (T.P.)
5.08 MAX.
N
0.9 MIN.
R
1.541 MAX.
0.070 MAX.
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.600 (T.P.)
0.007
0.070 (T.P.)
P42C-70-600A-1
A
C
D
G
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
D0.50±0.10 0.020
M0.25 0.010
+0.10
–0.05
0~15°0~15°
+0.004
–0.003
+0.004
–0.005
M
K
N
L13.2 0.520
2) Item "K" to center of leads when formed parallel.
42
1
22
21
L
MR
B
F
H
J
I
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
70 Data Sheet U12301EJ1V1DS
16. RECOMMENDED SOLDERING CONDITIONS
The
µ
PD750104,
µ
PD750106, and
µ
PD750108 should be soldered and mounted under the following recommended
conditions.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 16-1. Surface Mounting Type Soldering Conditions
(1)
µ
PD750104GB-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
µ
PD750106GB-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
µ
PD750108GB-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
µ
PD750104GB(A)-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
µ
PD750106GB(A)-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
µ
PD750108GB(A)-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times or less
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once
Preheating temperature: 120°C max. (package surface temperature)
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
IR35-00-3
VP15-00-3
WS60-00-1
Infrared reflow
VPS
Wave soldering
Partial heating
Soldering Method Soldering Conditions Recommended
Condition Symbol
Caution Do not use different soldering methods together (except for partial heating).
Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics
sales representative.
(2)
µ
PD750104GB-×××-3BS-MTX-A: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
µ
PD750106GB-×××-3BS-MTX-A: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
µ
PD750108GB-×××-3BS-MTX-A: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)
Undefined
Remark Products with “-A” at the end of the part number are lead-free products.
71
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
Table 16-2. Insertion Type Soldering Conditions
µ
PD750104CU-×××:42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
µ
PD750106CU-×××:42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
µ
PD750108CU-×××:42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
µ
PD750104CU-×××-A: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
µ
PD750106CU-×××-A: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
µ
PD750108CU-×××-A: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
µ
PD750104CU(A)-×××:42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
µ
PD750106CU(A)-×××:42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
µ
PD750108CU(A)-×××:42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
Soldering method Soldering conditions
Wave soldering (pin only)
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max.
Pin temperature: 300°C max., Time: 3 seconds max. (for each pin)
Caution Apply wave soldering to pins only. See to it that the jet solder does not contact with the chip directly.
Remarks 1. Products with “-A” at the end of the part number are lead-free products.
2. For soldering methods and conditions other than those recommended above, contact an NEC
Electronics sales representative.
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
72 Data Sheet U12301EJ1V1DS
APPENDIX A FUNCTIONS OF THE
µ
PD750008,
µ
PD750108, AND
µ
PD75P0116
Instruction
execution time
(1/2)
Item
µ
PD750008
µ
PD750108
µ
PD75P0116
Program memory Masked ROM One-time PROM
0000H - 1FFFH 0000H - 3FFFH
(8,192 × 8 bits) (16,384 × 8 bits)
Data memory 000H - 1FFH
(512 × 4 bits)
CPU 75XL CPU
General-purpose register (4 bits × 8 or 8 bits × 4) × 4 banks
Main system clock oscillator Crystal/ceramic RC oscillator (with external resistor and
oscillator capacitor)
Time required for start after reset 217/fX, 215/fXFixed to 56/fCC
(selected using a mask
option)
Wait time applied when STOP 220/fX, 217/fX, 215/fX,29/fCC or no wait Fixed to 29/fCC
mode is released by an interrupt 213/fX (selected accord- (selected using a mask
ing to BTM setting) option)
Subsystem clock oscillator Crystal oscillator
When selecting the main 0.95, 1.91, 3.81, or 15.3 4, 8, 16, or 64
µ
s (when operating at fCC = 1.0 MHz)
system clock
µ
s (when operating at
fX =4.19 MHz) 2, 4, 8, or 32
µ
s (when operating at fCC = 2.0 MHz)
0.67, 1.33, 2.67, or 10.7
µ
s (when operating at
fX = 6.0 MHz)
When selecting the 122
µ
s (when operating at 32.768 kHz)
subsystem clock
CMOS input 8 (Built-in pull-up resistors that can be connected by software: 7)
CMOS I/O 18 (Built-in pull-up resistors that can be connected by software)
N-ch open-drain I/O 8 (Pull-up resistors that can be incorporated by 8 (No mask option)
mask option) Withstand voltage of
Withstand voltage of 13 V 13 V
Total 34
Timer 4 channels 4 channels
8-bit timer counter: 1 8-bit timer counter (clock timer output function
8-bit timer/event provided): 1
counter: 1 8-bit timer/event counter: 1
Basic interval timer/ Basic interval timer/watchdog timer: 1
watchdog timer: 1 Clock timer: 1
Clock timer: 1
I/O port
73
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
(2/2)
Item
µ
PD750008
µ
PD750108
µ
PD75P0116
Serial interface 3 modes supported
Three-wire serial I/O mode: First transferred bit switchable between
LSB and MSB
Two-wire serial I/O mode
SBI mode
Clock output (PCL)
Φ
, 524, 262, or 65.5 kHz
Φ
, 125, 62.5, or 15.6 kHz (when the main system
(when the main system clock operates at 1.0 MHz)
clock operates at 4.19
MHz)
Φ
, 750, 375, or 93.8 kHz
Φ
, 250, 125, or 31.3 kHz (when the main system
(when the main system clock operates at 2.0 MHz)
clock operates at 6.0
MHz)
Buzzer output (BUZ) 2, 4, or 32 kHz (when the 2, 4, or 32 kHz (when the subsystem clock
main system clock operates at 32.768 kHz)
operates at 4.19 MHz 0.488, 0.977, or 7.813 kHz (when the main
or the subsystem clock system clock operates at 1.0 MHz)
operates at 32.768 kHz) 0.977, 1.953, or 15.625 kHz (when the main
2.93, 5.86, or 46.9 kHz system clock operates at 2.0 MHz)
(when the main system
clock operates at 6.0
MHz)
Vectored interrupt External: 3, internal: 4
Test input External: 1, internal: 1
Supply voltage VDD = 2.2 to 5.5 V VDD = 1.8 to 5.5 V
Operating ambient temperature TA = -40 to +85 °C
Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
74 Data Sheet U12301EJ1V1DS
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for the development of a system which employs the
µ
PD750108.
In the 75XL series, use the common relocatable assembler together with a device file of each model.
Language processors
Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later.
Remark The operations of the assembler and device file are guaranteed only on the above host machines and
OSs.
OS
MS-DOSTM
Ver. 3.30
to
Ver. 6.2Note
See "OS for IBM PC."
OS
MS-DOS
Ver. 3.30
to
Ver. 6.2Note
See "OS for IBM PC."
Part number
µ
S5A13DF750008
µ
S5A10DF750008
µ
S7B13DF750008
µ
S7B10DF750008
Host machine
PC-9800 series
IBM PC/AT and
compatibles
Host machine
PC-9800 series
IBM PC/ATTM and
compatibles
Device file
RA75X relocatable assembler Part number
µ
S5A13RA75X
µ
S5A10RA75X
µ
S7B13RA75X
µ
S7B10RA75X
Distribution media
3.5-inch 2HD
5.25-inch 2HD
3.5-inch 2HC
5.25-inch 2HC
Distribution media
3.5-inch 2HD
5.25-inch 2HD
3.5-inch 2HC
5.25-inch 2HC
75
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
PROM programming tools
Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or
later.
Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.
Hardware
Software
PG-1500
PA-75P008CU
PG-1500 controller
OS
MS-DOS
Ver. 3.30
to
Ver. 6.2Note
See "OS for IBM PC."
Host machine
PC-9800 series
IBM PC/AT and
compatibles
Distribution media
3.5-inch 2HD
5.25-inch 2HD
3.5-inch 2HD
5.25-inch 2HC
Part number
µ
S5A13PG1500
µ
S5A10PG1500
µ
S7B13PG1500
µ
S7B10PG1500
The PG-1500 PROM programmer is used together with an accessory board and optional
program adapter. It allows the user to program a single chip microcontroller containing
PROM from a standalone terminal or a host machine. The PG-1500 can be used to
program typical 256K-bit to 4M-bit PROMs.
The PA-75P008CU is a PROM programmer adapter provided for the
µ
PD75P0116CU/GB.
It is used in conjunction with the PG-1500.
This program enables the host machine to control the PG-1500 through the serial and
parallel interfaces.
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
76 Data Sheet U12301EJ1V1DS
Hardware
Part number
µ
S5A13IE75X
µ
S5A10IE75X
µ
S7B13IE75X
µ
S7B10IE75X
Distribution media
3.5-inch 2HD
5.25-inch 2HD
3.5-inch 2HC
5.25-inch 2HC
Debugging tools
The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the
µ
PD750108.
The system configuration is shown below.
Notes 1. Maintenance service only
2. These software products cannot use the task swap function, which is available in MS DOS Ver. 5.00
or later.
Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs.
2. The
µ
PD750104,
µ
PD750106,
µ
PD750108, and
µ
PD75P0116 are collectively called the
µ
PD750108
subseries.
OS
MS-DOS
Ver. 3.30
to
Ver. 6.2Note 2
See "OS for IBM PC."
The IE-75000-R is an in-circuit emulator used to debug hardware and software when
developing an application system using the 75X series and 75XL series. Use this
emulator together with optional emulation board IE-75300-R-EM and emulation probe
EP-75008CU-R or EP-75008GB-R to develop application systems of the
µ
PD750108
subseries.
For efficient debugging, connect the emulator to the host machine and a PROM
programmer.
The IE-75000-R contains emulation board IE-75000-R-EM. The board is connected
to the IE-75000-R.
The IE-75001-R is an in-circuit emulator used to debug hardware and software when
developing an application system using the 75X series and 75XL series. Use this
emulator together with optional emulation board IE-75300-R-EM and emulation probe
EP-75008CU-R or EP-75008GB-R to develop application systems of the
µ
PD750108
subseries.
For efficient debugging, connect the emulator to the host machine and a PROM
programmer.
The IE-75300-R-EM is an emulation board used to evaluate an application system
using the
µ
PD750108 subseries.
Use this board together with the IE-75000-R or IE-75001-R.
The EP-75008CU-R is an emulation probe for the
µ
PD750108CU.
Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-R-
EM.
The EP-75008GB-R is an emulation probe for the
µ
PD750108GB.
Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-R-
EM.
A 44-pin conversion socket, the EV-9200G-44, supplied with this probe facilitates the
connection of the probe to the target system.
This program enables the host machine to control the IE-75000-R or IE-75001-R
through the RS-232-C and Centronics interface.
IE-75000-RNote 1
IE-75001-R
IE-75300-R-EM
EP-75008CU-R
EP-75008GB-R
IE control program
Software
EV-9200G-44
Host machine
PC-9800 series
IBM PC/AT and
compatibles
77
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
OS for IBM PC
The following IBM PC OSs are supported.
OS Version
PC DOSTM Ver. 5.02 to Ver. 6.3
J6.1/VNote to J6.3/VNote
MS-DOS Ver. 5.0 to Ver. 6.22
5.0/VNote to 6.2/VNote
IBM DOSTM J5.02/VNote
Note Only English version is supported.
Caution These software products cannot use the task swap function, which is available in MS-DOS
Ver. 5.0 or later.
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
78 Data Sheet U12301EJ1V1DS
Document number
Japanese English
Document number
Japanese English
Hardware
Software
IE-75000-R/IE-75001-R User's Manual
IE-75300-R-EM User's Manual
EP-75008CU-R User's Manual
EP-75008GB-R User's Manual
PG-1500 User's Manual
RA75X Assembler Package User's
Manual
PG-1500 Controller
User's Manual
PC-9800 series (MS-DOS) base
IBM PC series (PC DOS) base
Operation
Language
Document number
Japanese English
C10535E
C11531E
C10983E
-
MEI-1202
-
IC Package Manual
Semiconductor Device Mounting Technology Manual
Quality Grade on NEC Semiconductor Devices
Reliability and Quality Control of NEC Semiconductor Devices
Electrostatic Discharge (ESD) Test
Semiconductor Device Quality Guarantee Guide
Microcontroller-Related Products Guide - by third parties
Document name
Document name
Document name
APPENDIX C RELATED DOCUMENTS
Some documents are preliminary editions, but they are not so specified in the tables below.
Documents related to devices
Documents related to development tools
Other related documents
Caution The above related documents are subject to change without notice. Be sure to use the latest
edition when you design your system.
U12301J
U12603J
U11330J
U11456J
U10453J
EEU-846
U11354J
EEU-699
EEU-698
U11940J
EEU-731
EEU-730
EEU-704
EEU-5008
EEU-1416
U11354E
EEU-1317
EEU-1305
EEU-1335
EEU-1346
EEU-1363
EEU-1291
U10540E
C10943X
C10535J
C11531J
C10983J
MEM-539
C11893J
U11416J
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) Data
Sheet
µ
PD75P0116 Data Sheet
µ
PD750108 User’s Manual
µ
PD750008, 750108 Instruction List
75XL Series Selection Guide
U12301E (This manual)
U12603E
U11330E
-
U10453E
79
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet U12301EJ1V1DS
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between V
IL
(MAX)
and V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
80 Data Sheet U12301EJ1V1DS
Regional Information
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
J05.6
N
EC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Succursale Française
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-265 40 10
Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
µ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
80
MS-DOS is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.