Th + Winbond: Nckoe Elertranics Carp. W9320 ADPCM CODEC Table of Contents- & WwW NS 10. 11. 12. 4.1. Power Control Interface... 4.2. Analog Interface .. 4.3. ABPCM/PCM Serial interface . bee ce eee e cee eueeeeseneeeceeesneeesunteeteneeeteeetnuteesnssenieeetistsnteeenitesnieeeteetens 4.4 Serial Setup Port(SSP} Interface . CE EE EU EEE UU EEE EOE En eee eee niea 5.1 Pair Gain Syston oo. cece ee ce cece tee cene ee eeee cece ce neaeeeeeecececenaeeeeeeeeeeeeeeeeeeeeeeseeeesnaeeseesecnesentatenenes 5.2. Cordless Phone System 2.00.00... eee ee een ener en entrar enenenentincsenenenenens . FUNCTIONAL DESCRIPTIONS... 2.0. cececceeeeene eee e cane eeneeseernreenteeseneeesrseneesenneeeniteentessnieeenieeeerireness 7.1. Power Supply Management System 00... EE On ne ee ion ae ener ee 7.2. LA Codec-Filter .. 7.3. DSP Engine .. 7A. Serial Setup Port (SP)... 7.5. Sequence and COMPO eset ete 7B. UO LEVEL ccc cee nett eee ee tere eect ence ceeee tenses ee teeteegtensareeteeereeteneeeeeeeereeenes . CONTROL AND STATUS REGISTERS ooo. nn nner innate 8.1. Introduction.. 8.2. Byte Register Description .. . ELECTRICAL CHARACTERISTICS |... cece cccecene eects tens tenersesenteeetesnneeeseitentereenessnieeestersnnteesnterenneenn 9.1. Absolute Maximum Ratings .....0....0.000 cece ec ete ee eet eee beeen tenet ee tere ee tenet ee teeter teneeteeeenreeenes 9.2. DC Characteristics .. L 9.3. Analog Transmission Characteristics... 9.4. Analog Electrical Characteristics o.oo nn niin ier er 9.5. Digital Switching Characteristics 0.00 nnn itt er ere APPLICATION INFORMATION.. becttiteee 10.1. Handset Application for Wireless Communication . 10.2. Transformer Application for Public Switching Telephone Network (PSTN) beeen eect ne eee ee tetnnneneataeeeee HOW TO PROGRAM THE TONE GENERATOR ou... et ener ie trnee tn tenennietnieertgs 11.1 Introduction.. beceeteees 11.2 Tone Frequency Coefficient Caloulation.. 11.3 Tone Attenuation Coefficient CANCULALION ecco ceeoseeoeeete oes 11.4 Frequency Coefficients for the DTMF Signal ........0..0.00. cece cee ect eeeceee teen eee tene ieee seteetentes ooo ONAD aH RW wD wW DH D Bo BRN reer ener on ow mh hhh Jao KR KR BR ww Ww oo86 ww wo ww NN mM a w Lot) Publication Release Date: August 1997 Revision AlW9320 i ots cit, erp ae ~~ sthin Plectronics Corp. EI SITIES OOOO SISO ORRIN OOS ISO O REINO ODIO ORBAN OOOO S SOO EOIN ODDS SOO ERIN OOS S SOO BIONDI SSO O RIOT IN SEENON 1. GENERAL DESCRIPTION The Winbond ADPCM Godec is a single channel chip incorporating a XA PCM codec filter with a 32K, 24K, 16K ADPOM encoder/decoder complying with the CCITT G.721 and G.726 standards. In addition, this chip also meets the POM conformance specification of the CCITT G.714 recommendation. This chip allows full-duplex operation over a wide voltage range from 2.7 to 5.25 volts; it's low power consumption makes it ideal for battery or AC powered applications. The chip includes a serial setup port (SSP) interface with a 16 byte setup and status registers. A microcontroller can access many built-in features through the SSP interface. In addition, this chip also consists of some OP amplifiers integrated with a ZA PCM codec-tilter to allow for easy control of the analog interface. This chip can be used on two key applications. One application is for wireless telephone systems such as CT2, DECT. Another application is for public switch telephone network (PSTN) applications such as pair gain. See the section on application information for more details. 2. FEATURES Single 2.7 to 5.25 volt power supply Master clock rate: 10.24 MHz oscillator typically or 16.384 MHz for Winbond cordless system Full-duplex single channel speech codec Linear 14 bit [A PCM codec-filter for A/D and D/A converter Complete Mu-Law and A-Law companding * ADPCM transcoder for 64, 32, 24, and 16 Kbps bit rates Serial PCM/ADPCM transter data rate from 128 to 2048 Kbps Universal programmable dual tone generator such as DTMF application Noise burst detection algorithm for ADPCM receive path Analog input: ditferential OP amplitier with external gain adjustment for microphone interface Programmable transmit gain, receive attenuation, and sidetone gain Analog output: Differential power driver with 300 load and external gain adjustment Differential auxiliary driver with 300 Q load for ringer interface 3 Volt regulator for digital circuit 5 Volt charge pump for analog circuit low voltage applications 16 Setup and status registers with 8 bits for monitoring microcontroller applications Packaged in 28-pin DIP/SOPW9320 \ Minbond Flectronics Corp. IIR TIE 3. PIN CONFIGURATION OE, Te = 1 \/ 28 Vop Te =2 27 F FSR Tl = 43 26 F BCLKR VAG 4 25 - DR Ro 45 24 - = Cit AXO- 16 23 -= Ci- AXO, Oo 7 22 F= Vss Voge SJ 8 py = MCLK Veg 4? 20 = DT Pl c=q{i0 19 = BCLKT PO. S11 18 = FST PO: = 12 17 E= SSP Rx PDIRESET 13 16, SSP Tx SSPEn =={14 15 SSP CLK 4. PIN DESCRIPTIONS 4.1. Power Control Interface PIN NAME | PIN NO. | VO FUNCTION VEXT 9 | | This pin is the external power supply between 2.7 and 5.25 volt. This pin should be decoupled to VSS with a 0.1 WF capacitor. VDSP 8 O | This is the output of the on-chip 3 volt regulator which supplies the digital circuit of the chip. This pin should be decoupled to Vss with a 0.1 WF ceramic capacitor. This pin cannot be used for powering external loads. VDD 28 VO | This is the output of the on-chip 5 volt charge pump which supplies the analog circuit. When VEXT = +5V 15%, VDD is an input and should be connected to VEXT externally. Charge pump capacitor Gi+ and G1- should not be used and BRO[b2] must be written into logic "1". In this case VEXT and VDD can share the same 0.1 LF decoupling capacitor to VSs. When VEXT = 2.7 to 5.25 volt, VDD is a 5 volt charge pump output and should not be connected to VEXT. VDD should be decoupled to Vss with a 0.1 WF capacitor. This pin cannot be used for powering external loads. Vss 22 | | This pin connects the analog and digital ground and is typically connected to 0 volt. Publication Release Date: August 1997 Revision Ali ots . Winbond sie Flectronics Corp. SIPS DODO SIDI SIO IIIESII SIDI IION. ~ 4.1. Power Control Interface, continued W9320 PIN NAME PIN NO. vO FUNCTION VAG 4 O This is the analog ground output pin which supplies a 2.5 volt reference voltage for all analog signal processing. This pin should be decoupled to Vss with 0.1 LF capacitor. This pin becomes high impedance when the chip enters an analog power down mode. C1+, C1- 23, 24 The charge pump capacitor pins. When VEXT = +5V +5%, these capacitors C1+ and C1- should not be used and BRO[b2] must be written into logic "1". When VEXT = 2.7 to 5.25 volt, a 0.1 LF capacitor should be placed between C1+ and C1-. PDIVRESE T 13 The power down/reset input pin. When at logic 0, the chip enters a power down mode. When it switches from logic 0 to logic 1, this chip is active and resets the ADPCM transcoder and all circuits. 4.2. Analog Interface PIN NAME PIN NO. vO FUNCTION TG 1 This pin is the analog output of the transmit input amplitier. It can be used to set the gain by external resistors. When the chip is in analog power down mode, this pin is high impedance. TI- This pin is the inverting input of the transmit input amplifier. Connecting this pin and Tl+ (pin-3) to VDD will force TG into a high impedance state. Ti+ The non-inverting input of the transmit input amplifier. Connecting this pin and TI- (pin-2} to VDD will force TG to be high impedance. Note this pin may be connected to the VAG pin for an inverting configuration if the input signal is referenced to the VAG pin. RO This pin is the non-inverting analog output of the receive smoothing filter. This pin can typically drive a 2 KQ load to 1.13 volt peak referenced to the VAG pin. This pin may be dc referenced to either the VAG pin or VEXT/2 determined by BR2 (b7/). When the chip is in analog power down mode, this pin is high impedance. This pin is the auxiliary inverting analog output. This pin can drive a 300 load ditferentially. This pin may be dc reterenced to either the VAG pin or VEXT/2 by BR2 (b7). When the chip is in analog power down mode, this pin is nigh impedance. AXO+ This pin is the auxiliary non-inverting analog output. This pin can drive a 300 load differentially. This pin may be dc referenced to either the VAG pin or VEXT/2 by BR2 (b7). When the chip is in analog power down mode, this pin is high impedance.i ots Winbond | BDO sthin Plectronics Corp. SEIT OT 4.2. Analog Interface, continued W9320 PIN NAME | PIN NO. | VO FUNCTION Pl 10 | | This pin is the inverting input to the PO- (pin-11) power amplitier. It may be dc referenced to either the VAG pin or VEXT/2 by BR2 (b7). This pin and PO- are used to set the gain by using external resistors. Connecting this pin to VDD will power down the chip and the PO+ and PO- outputs will be high impedance. PO- 11 | This pin is the inverting power amplitier output. Its operation is same as the AXO- (pin-6). In the application, this pin can drive the speaker on the receiver. PO+ 12 O | This pin is the non-inverting power amplifier output. Its operation is the same as the AXO+ (pin-7}. In the application, this pin can drive the speaker of the receiver. 4,3. ADPCM/PCM Serial Interface PIN NAME | PIN NO. | VO FUNCTION MCLK 21 | | This pin is the system master clock input pin. It typically accepts 10.24 MHz or 16.384 MHz for Winbond cordless applications. This pin is the oscillator input. FST 18 | | This pin is an 8 KHz pulse train for transmission of frame syncs. This pin synchronizes the output of the DT pin (pin-260). BCLKT 19 | | The bit clock for transmission. It shifts out the data on the DT pin on the rising edge. The frequency may vary from 128K to 2048 KHz. DT 20 Q | This pin is tri-state output data for transmission controlled by FST and BCLKT pin. FSR af | | This pin is an 8K Hz pulse train to receive frame syncs. This pin synchronizes the input of the DR pin (pin-25). BCLKR 26 | | This pin is the receive bit clock. It shifts data on the DR pin into the chip on the falling edge. The frequency varies from 128K to 2048 KHz. DR 25 | | This pin is the receive input data controlled by the FSR and BCLKR pins. 4.4 Serial Setup Port(SSP) Interface PIN NAME | PIN NO. vO FUNCTION SSP EN 14 This pin is the enable signal for SSP setup. This pin is held low to select the16 control and status registers. There are two timing controls. One is for double 8 bit transfer mode; the other control is tor the single 16 bit transfer mode. See the timing diagram, Figure 7-6 to 7-9, in Section 7.4. Publication Release Date: August 1997 _5- Revision AlW9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT 4.4 Serial Setup Port(SSP) Interface, continued PIN NAME | PIN NO. | VO FUNCTION SSP CLK 15 | | This pin is the clock for SSP setup. Note that data is shifted out of the SSP on the falling edge of this pin, and shifted into the SSP on the rising edge. The SSP CLK can be any frequency from 0 to 2048 KHz. SSP TX 16 | This pin is the tri-state output data for SSP transmission controlled by the SSP CLK pin (pin-15). SSP RX 17 | | This pin is the receive input data for the SSP controlled by the SSP CLK pin (pin-15}. 5. SYSTEM DIAGRAM 5.1 Pair Gain System Applications for this device include the public switching telephone system. One such application is the pair gain system shown in Figure 5-1. The figure illustrates how the chip is used in a pair gain system to connect the telephone system between end users and the central office terminal. These chips are used on devices installed in both the central office terminal (COT) and in the remote office terminal (ROT). If the chip is operating in 32 Kbps ADPCM mode, the COT and ROT must use four chips for 4-channel communication because the U interface chip can support 2B channel, i.e., 128K bps. In the transmission path, the telephone system first sends the analog signal to the ADPCM chip in the ROT to compress it into a 32 Kbps digital signal. The U interface can then build a 2B+D channel, 128 Kbps, with four ADPGM chip channels, and send the 128 Kbps digital signal to the COT. After receiving the digital signal, the U interface in the COT separates the 128 Kbps data into four ADPCM channels (32 Kbps) and sends this data to the chip to execute the ADPCM decoder and for reconstruction into an analog signal. The analog signal is then sent to the central office (COQ) to complete the transmission operation. For the receive path itis the reverse operation of the transmission path mentioned above. In a pair gain system, the analog signal (voice signal, or modem signal) is digitized and compressed to a ADPCM signal e.g. 32 Kbps ADPCM. The subscriber loop, the connection between the end user and the central office, is digitized by the U interface transceiver. This provides two B-channels (2 x 64 Kbps) for data and one D channel for signaling. In short, data can be transmitted and received on the subscriber loop via the U interface transceiver. One B-channel can carry 64 Kbps data, i.e. two 32 Kbps ADPCM channels. Therefore the pair gain system can supply four telephones.W9320 Gc Winbond A ADO ccbis Flectronics Corp. RRS LLIB Remote Office Terminal Central Office Terminal ones ( | RO Office (CO appom {ROT) {COT) hook Tacaies 1 ADPCM el 4 tacode: Channel 4 ADPCM LI ADPSM Analog FaCadec H facies Channel 2 u u infertace inferaca 24D 2840 ADPCM | | ADPCM Arakg| TA Codec HH Pacodes Channel 3 Micro-C ontroller} Micro-Controller} ADPCM TaGadac || ADPOM Anakal LU sacodes rannal 4 End User Telephone System Figure 5-1 System Diagram for Pair Gain Application 5.2. Cordless Phone System Figure 5-2 shows a cordless phone system block diagram. On the transmission side, the voice is sent to the W9320 ADPCM Codec trom the external microphone. First, the analog speech signal is digitized into a 14-bit linear signal and compressed into 32 Kbps ADPCM data. The compressed signal is then sent to the W9310F SST which provides all the baseband functions required for an FOC Part 15 compliant cordless phone. The SST W9310 will generate the spread spectrum binary sequence for output to an RF modulator. The microprocessor manages the other functions of the cordless phone such as the keypad and display control. On the receive side, the WHT9360 RF Module converts the received signal to baseband. The W9310 SST then performs the de-correlation and demoulation and sends the 32K bps speech signal into the W9320 ADPCM. The W9320 then reconstructs the digital speech signal into an analog signal using the 32K ADPCM decoder betore sending this analog signal to the speaker. Antenna Microphone (p ADPCM Spread Spectrum Transcci 1 Voice Codec pread spectnum TTANScelver RF Module fessor pe YK W9320 SST W9310EF WHT9360 a Speaker * Microprocessor W921E880F Figure 5-2 System Diagram for Cordless Phone Application Publication Release Date: August 1997 _7_ Revision AlW9320 \finbond it Riectronics Corp. PIII ISI DIRS IP IIIS IIOIB II OSI ISIE SII SII II SSIS SIP IMIS IDOSIIIIESIIOIDIIEE SII SID HII SOP ISIIOWI SII OMIIIIESIISIPRIIIOII SIPING IID ISPD IIE SIIOIPI IEE SII IID HIIIOPIIIIOIISIIOMIIIIESIIIIPRIIIOIIIIPIIEIIPOSIIIIESIION 6. BLOCK DIAGRAM OE, OT Dr rn rr nts T ! SD Codec-filter Vy DSP Engine 1 DR PO+] 1 I'l Gigital ob Vy igital a ADPCM a ! I ' Decoder 1 FSR PO-| | vm a || BCLKR ty Digital 1 | TRA \ 1 ABO} Anelog Analog Digital = A Acti Alias et ee ee Caection Serial) | TN meothing LAF Demodulate| Intp. Filter ry f Data | | AxO4| | her 1! Universal Port | | AXO-| | il at Tone (SDP} I I I i Generator i FST Teh bom 1 ~*~ BELKT i Analog 5a ie Digital it Tx Gain, gi ADPCM et rae na iene a 41a it Loo ---------------_ +--+ ---- +--+ ----4 y [me | ; tA VAG 1 25 Power Supply 1 \ om a j Reference Voltage| Management System 1 --p------- 1 1 I r wa \ |_| y + Charge -Punp & 3 volt Regulatorfi MCLK CA [AY s voir Reguicto for Dapialsigia Mocenor || Serial Setup Port & 16*8 Bits >| Sequence vop | | Analog Processing Setup and Status Registers Control BDVAESET ! 1 VDSP| | \ A A A Sspen! ssPcikl gsptx ssp Ax Figure 6-1 Winbond ADPCM EA Codec Block Diagram 7. FUNCTIONAL DESCRIPTIONS Figure 6-1 illustrates the functional blocks of the Winbond ADPCM <A codec. The chip can be divided into four subsystems which are described in the following subsections. 7.1. Power Supply Management System In this block two groups comprise the power supply management system. One group is a 5-volt power supply system for all analog signal processing. The second group is a 3-volt power supply system for all digital signal processing. 7.1.1. Power Supply for All Analog Signals Processing All analog circuits except for output power amplifiers AXO and PO are supplied with 5-volt power. This voltage may be applied directly to the VDD pin or by the 5 volt charge pump circuit. Note that the power drivers AXO and PO are powered by the VEXT pin which is the main positive power supply pin. When VEXT = +5V 15% (e.g. base station applications) VDD is an input pin and should be connected externally to the VEXT pin. The charge pump capacitor Gi+ and G1- should not be used and the BRO[b2] must be set as a logic "1" to disable the charge pump circuit. In this case VEXT and VDD can share the same 0.1 uF decoupling capacitor to Vss. When VEXT = 2.7 to 5.25 volts (e.g. battery applications) VDD is a 5 volt charge pump circuit output and should not be connected to VEXT. VDD should be decoupled to Vss with a 0.1 pF capacitor. This pin cannot be used for powering external loads.W9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT 7.1.2. Power Supply for All Digital Signals Processing All digital circuits are supplied by the VDsP pin trom a 3-volt regulator circuit. This reduces the chip power consumption. Whatever the value on the power supply pin VEXT, range from 2.7 to 5 volts, the digital circuits will always be powered by a 3 volt voltage supply. Note that the VDSP pin should be decoupled to Vss with a 0.1 WF capacitor and that this pin cannot be used for powering external loads. 7.1.3. Reference Voltage Control System All analog reference voltages such as power amplifier RO, AXO, PO is 2.5 volt or VEXT/2 determined by BR2(b7). 7.2. SD Codec-Filter This device has a built in linear 14-bit PCM codec-filter using ZA technology. There are two paths in the block, a transmit path and a receive path. 7.2.1. Transmit Path in SD Codec-Filter An analog signal input, from a microphone interface, is passed to three terminal operational amplifiers (Tl+, Tl-, TG) driving a typical 2 K load externally to amplity the input analog signal. The analog signal can then be set to have further transmission gain from 0 to +7 dB, in 1 dB steps by the transmit gain control block. The gain is programmed through the SSP port in BR1(b2:b0). The ZA modulator block oversamples the analog signal at 1.024 MHz with one bit resolution. The next anti- aliasing decimation filter reduces the sampling frequency from 1.024 MHz (1 bit) to 32 KHz (15 bit). Digital biquad filters perform the decimation from 32K to 8 KHz and CCITT low-pass filtering at 3400 Hz. The digital HPF block performs the high-pass filtering at 300 Hz. In the final step, the 14 bit A/D conversed data is sent by the transmit path to the DSP engine for further signal processing (e.g. by the ADPCM encoder). 7.2.2. Receive Path in =A Codec-Filter A 14-bit linear digital signal from the Rx Attenuation control block in the DSP engine is first passed to the digital anti-aliasing interpolation filter block. The interpolation block performs the reverse operation of the decimation Tilter (described above in the transmit path) and the sampling rate will be increased from 8 KHz (14 bits) to 1.024 MHz (14 bits). The digital EA demodulator will then reduce the 14-bit samples (1.024 MHz) to 1 bit (1.024 MHz). The digital output signal will be passed to a 3400 Hz switched capacitor low-pass filter with sin(x}/x correction and an analog smoothing filter to reduce the spectral components of the switched capacitor filter. Finally, the analog output signal is sent to the power amplifier, RO, which is capable of driving a 2 KQ load connected to to the VAG pin, and high current analog output driver AXO simultaneously with a 300 ditferential load. Note the device provides ancther power amplitier, PO, connected in a push-pull configuration. The AXO and PO have different circuit configurations for different applications. The AXO is for handset ringer applications, but the PO driver can accommodate large gain ranges by adjusting two external resistors for applications such as driving a telephone line or a handset receiver. 7.3. DSP Engine This block is the kernel of the ADPCM transcoder and tone generator. There are two paths in this block, a transmit path and a receive path. Publication Release Date: August 1997 -9- Revision AlW9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT 7.3.1. Transmit Path in the DSP Engine A linear 14 bit sample input from the transmit path of the A Codec-filter block is sent in three processing directions: sidetone gain process, Mu/A law compressor/Linear, and ADPCM encoder/ tone encoder. In the sidetone gain block, the input sample is fedback to the receive path and is summed with the output of the digital receive gain. The value is kept in the -70 dB to -8.5 dB range by the SSP port in BR1(b6:b4).The A/D output is then saved linearly inte BR9(b7:b0) & BR10(b7:b2). The ADPCM encoder/tone encoder provides 16 Kbps, 24 Kbps, or 32 Kops ADPCM, or 64 Kbps PCM respectively, as determined by the length of the transmit frame sync (pin 18). The length of the frame sync is calculated by the number of falling edges at the BCLKT pin when the transmit frame sync FST pin is high. Because the frame sync clock is 8 KHz, the encode interrupt is performed once every 125 Ls. As a default value the transmit ADPCM will be delayed by two frames after being requested, i.e. if the current frame request is for ADPCM operation, it will be computed in the next frame and the ADPCM result is transmitted in the next two frames. For applications such as the signaling channel of T1 frame structure the delay status can be configured to a total of 6 frames by the SSP port in BR7(b5). The ADPCM output result will be sent to the serial data port (SDP) on the DT pin and the output data rate from 128 KHz to 2048 KHz will be controlled by the serial data port on the BCLKT pin. In the universal tone generator mode, the input of the ADPCM encoder comes from the output of the universal tone generator, not from the transmit path in the ZA codec-filter. The ADPCM encoder outputs the tone ADPCM signal through pin DT. 7.3.2. Receive Path in DSP Engine The device receives data from the DR pin via the serial data port (SDP) under the control of the BCLKR and FSR pins. The clock of the receive frame sync FSR is 8 KHz. The ADPCM decoder receives one decode interrupt every 125 1S. The serial data rate in the BCLKR is in the 128 KHz to 2048 KHz range. The input parameter data is sent to the ADPCM decoder which also provides 16 Kbps, 24 Kbps, or 32 Kbps ADPCM or 64 Kbps PCM, is determined by the length of the receive frame sync FSR pin. The length of the frame sync is calculated by the number of falling edges at the BGLKR pin when the receive frame sync FSR pin is high. The ADPCM decoder consists of a sync adjustment operation for the correction of sync. tandem application, except when the receive digital gain is used for a handset application. The digital receive gain is programmed trom -12 dB to +12 cB through the SSP port in BR3{b6:b0). In order to prevent noise trom influencing the result of the ADPCM decoder, the noise burst detection algorithm can be enabled by setting the BR7(b6) register to detect interfering sounds and to mute the receive path. The reconstructed linear PGM will be compressed by the Mu/A law compressor block and sent to BR11 (b7:b0) on the SSP port after sync. adjustment in G.726 for CCITT test mode. After the control of digital receive gain, the synthesized PCM data will be added to the feedback signal of the transmit path in the sidetone gain block. The sum value is then passed to the Rx attenuation control block to protect the output driver, RO, trom distortion when the amplitude of the synthesis data is too large (e.g. battery applications). The gain of the Rx. attenuation block is programmed through the BR2 (b2:b0) register in the SSP port. A receive attenuation range of trom 0 to -7 dB can be programmed in 1 dB steps. If the device enables the universal tone generator, the function of the ADPCM decoder will be disabled. Different tone types (i.e. tone 1 and tone 2) can be programmed through the BR7, BR4, and BR5 registers in the SSP port. The tone generator can be used to generate DTMF tones, different ringing tones, and call progress tones for handset applications. In telephone line applications, this tone generator can be used for signaling on the line. -10-W9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT 7.3.3. Frame Sync. Types The frame sync operation uses two industrial control types for the transfer of the ADPCM or PCM data words. These two types are the long frame sync and short frame sync. 7.3.3.1. Long Frame Sync The long frame sync types for various data rates are shown in Figure 7-1 to 7-4. The bit rate for the ADPCM or PCM encoder and decoder is determined by the length of the frame sync pin (FST or FSR). The length of the frame sync is calculated by the number of falling edges at the BCLKT or BCLKR pin when the frame sync FST or FSR pin is high. For example, if the number of the falling edges on the BCLKT or BCLKR pin is equal to 2 when the frame sync is high, this corresponds to the 16 Kbps bit rate for the encoder and decoder of the ADPCM operation. If the number is 8, the device becomes 64 Kbps PCM operator. The device shitts out the data on the DT pin at the BCLKT rising edge and shifts in the data on the DR pin at the BCLKR falling edge. The length of the frame sync may be changed on a frame by frame basis. 7.3.3.2. Short Frame Sync The short frame sync types for 32 Kops ADPCM timing is shown in Figure 7-5. The bit rate for this type of frame performs only 32 Kbps ADPCM encoding and decoding. The length of the frame sync is equal to 1. The device shifts cut data on the DT pin at the BCLKT rising edge and shifts in data on the DR pin at the BCLKR falling edge. Switching between long frame sync and short frame sync without going through a power down operation is not recommended. rt _ f/f \ (FSR) BCLKT NA AS AS NASS\ LNA _ (BCLKR) MSB LSB DT CP MSB LSB (FSR) BCLKT 1 2 3 4 5 6 7 8 (BCLKR) MSB LSB br = XEXe MSB LSB op mena KKK ce Figure 7-2 Long Frame Sync for 24 Kops ADPCM Timing Publication Release Date: August 1997 -ii- Revision AlW9320 i Winbond PBIB IIIT TITTIES FST / \ (FSR) BOLKT 1 2 3 4 5 6 7 8 (BCLKR) MSsB LSB ot Cs XXX MSB LSB DR Dont Gare D3 > be Di >< BO Of Dent Care Figure 7-3 Long Frame Sync for 32 Kops ADPCM Timing FST __/ \__ (FSR) BCLKT 1 2 3 4 5 6 7 8 _ (BCLKR) MSB LSB oe EEE EXE MSB LSB pn KDE Ce XK ot Figure 7-4 Long Frame Sync for 64 Kops ADPCM Timing FST /_\ (FSR) | : BT NV LVS NS AS AS ASAI ANS ASA (BCLKR} : : SB ISB | MSB LSB DR Dor't Care D3 9 D2 v1> C po X pon't Care Figure 7-5 Short Frame Sync for 32 Kbps ADPCM Timing 7.4. Serial Setup Port (SSP) The W9320 has sixteen 8-bit wide setup and status registers, BRO--BR15, for controlling and monitoring functions via the serial setup port (SSP). The SSP may be used by an external microcontroller such as the Winbond W921E880. The SSP has a Tull-duplex four wire interface (marked as SSP Tx, SSP Rx, SSP CLK, and SSP EN) for communicating with an external micro- -]2-W9320 \ Minbond Flectronics Corp. SSI RISE ITT i AS, controller. Two timing controls, a double 8-bit transfer mode and a single 16-bit transter mode, are available when SSP EN is held low to select the setup registers. The data rate for the SSP CLK ranges from 0 to 2048 KHz. The data is shifted out of the SSP port on the falling edge of SSP CLK, and shitted into the SSP port on the rising edge of the SSP CLK. This latch operation is the reverse of the serial data port in the DSP engine. The 16 byte registers are selected by bits 3 to O in the first byte from the SSP Rx pin as shown in Figure 7-6 to 7-9. Bit 7 of the first byte indicates whether the status is read (logic 1) or write (logic 9). The second byte is the data word (D7:D0). The description of setup and status registers, BRO--BR15 is described in greater detail in the next section 8. (Control and Status Registers). SSP EN ssp oN WAN High Impecence SSP Tx SSP Rx Tw | T] Joon can reXeexe Key HP LIP ont care XoXo 03K oI ooXoekoyXoyy{ on Care Figure 7-6 Double 8 bit for Write Operation of SSP Register SSP EN \ f SSP cK DWP SSP Tx opens KEK CON DAW onXD0) ssP RAZ] a [ff fron carkrsnnema Kage (LETT oom care Eff ff Figure 7-7 Double 8 bit for Read Operation of SSP Register SSP EN [_ 1 BIT aD SETS ry TT By ort 2p 4p 56 ssrou SWAN High Impecence SSP Tx SOP RAYAW [TTT KKK KEKONA XE EDK NE NE Bar owe Figure 7-8 Single 16 bit for Write Operation of SSP Register Publication Release Date: August 1997 - 13- Revision AlW9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT SSP EN 7 f SSP Tx CK oNKOHKO}KEEK ONE Noo) ssP rx Lf a [Pffoa coe Xe Key Hf iiffowrcne HITT Figure 7-9 Single 16 bit for Read Operation of SSP Register 7.5. Sequence and Control This block generates some internal clocks, providing clocks such as 1.024 MHz and 8 KHz for ZA codec-filter operation. The master clock MCLK, which supports the clock of the DSP engine, may be asynchronous to all other blocks. Its frequency is typically 10.24 MHz or 16.384 MHz for cordless applications using Winbond chips. The ZA cedec-tilter may use the BOLKR pin as a direct 1.024MHz input. The rising edge of this input clock must be approximately aligned with the rising edge of the FST. This mode requires that the ADPCM transmit and receive be contralled by the BCLKT pin. This is configured by the SSP port through the BRO(b7) register. There are two ways of forcing the device into a low power consumption condition in power down mode. One way is the hardware power down mode where the PDI/RESET pin is held to logic 0. The other way is the software power down mode where the register BRO(b1:b0) is set through the SSP. When the BRO({b1) setting initiates an analog power down, all clocks for analog signal processing will be halted. To initiate a digital power down, the BRO(b0) register can be programmed to logic 1 to halt all clocks for all digital signal processing. When the chip is powered down, the VAG, TG, RO, PO, AXO, DT and SSP Tx outputs are all high impedance. When the power is reactivated fram the power down mode, the ADPCM algorithm is reset to the CCITT initiate state. 7.6. /O Level Digital I/O for the device can be programmed in either Mu-law or A-law. Full scale and zero words for these two log-PGM forms are shown in Table 7-1. For analog signal processing, the maximum transmit level is 3.17 dBm0O tor Mu-Law or 3.14 dBm0 for A-Law. These values meet the CCITT G.711specifications. MU-LAW A-LAW Level Sign Segment Bits | Step Bits Sign Segment Bits Step Bits + max. scale 1 000 0000 1 010 1010 +Zero 1 111 1111 1 101 0101 - Zero 0 111 1111 0 101 0101 - max. scale 0 000 0000 0 010 1010 Table 7-1 Full Scale and Zero Word for Mu/A-Law _J4-W9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT 8. CONTROL AND STATUS REGISTERS 8.1. Introduction There are 16 available byte setup and status registers for the SSP port. The functional description and read/write status of each bit are illustrated in the sections that follow. The read or write status described in Table 8-1 is indicated by the symbol r, w, ro. SYMBOL TYPE MEANING rw Read/Write Data may be read from the SSP port or written inte the SSP port by micro-processor ro Read Only Data may only be read from the SSP port. Writing to this port has no effect. roAvo Read Only/Write Only | Data may be read or written by an external micro-processor and internal chip simultaneously. The value is written into the bit and read back by the external micro-controller Table 8-1 Read/Write Status Description in SSP Byte Register 8.2. Byte Register Description There are 16 byte registers for controlling and monitoring the status of the chip. These registers are labeled BRO to BR15. The descriptions are as follows. Note that "setting" is corresponding to logic "1 and "clearing" is corresponding to logic "0". . 8.2.1. Byte Register 0 (BRO) This is a control register. All bits are cleared when the PDI/RESET pin is set to logic zero. B7 B6 B5 Ba B3 B2 B1 Bo Ext 1024 |Mu/A Law} Analog | Function | Function | Charge Analog Digital KHz Select | Loopback] Mode Mode Pump Power Power Clock Select[1] | Select[0] | Disable Down Down rAw rAW raw rAW rw rw rw rAw BRO External 1024 KHz Clock {b7)}: This bit controls a mux. When this bit is cleared, the mux selects the 1024 KHz clock from the internal clock generator. When this bit is set, the BCLKR pin is used to provide an external 1024 KHz clock and the internal BCLKR is connected to BCLKT; the BRO[b1] must be set to "1" for reset codec. Mu/A Law (b6): When this bit is set to logic zero, the device selects Mu-Law companding of the Log-PCM. Setting this bit selects the A-Law companding of the Log-PCM. Analog Loopback (b5): Setting this bit causes an analog loopback from the receive path to the transmit path. Internally the RO output in the receive path is routed to the transmit gain control in the transmit path; the op-amp TG is bypassed. Publication Release Date: August 1997 -15- Revision AlW9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT Mode Select[1:0] (b4:b3): The function modes are shown in Table 8-2. The ADPGM Codec mode performs a combination of PGM codec and ADPCM transcoder in full duplex. The PCM codec made is a subset of the ADPCM codec mode, where only the PCM codec is executed. The CCITT test mode uses the CCITT ADPCM test vectors to do conformance testing. Enabling this mede will remove the ZA codec-filter operation. The test vectors go through the SSP port in BR[b7:b0] and BR10[b7:b0]. See the BR9 and BR10 descriptions for more details. The battery test mode allows testing of the voltage present at the VEXT pin. In this mode, the HPF output in register BR8[b4] must be disabled. Note that the steady linear code for the VEXT pin will be delayed by about 60 samples. The output result of linear 14 bits is stored in registers BR9 and BR10. FUNCTION MODE SELECT[1:0] (B4:B3) TYPE 00 ADPCM Codec 01 PCM Codec 10 CCITT Test 11 Battery Test Table 8-2 Function Mode Selection Charge Pump Disable (b?2}: Setting this bit disables the 5 volt charge pump. In this mode, the charge pump capacitor C1+ and C1- should not be used and the VDD pin should be connected externally to the VEXT pin. Analog Power Down (b1}: Setting this bit causes an analog power down. In this mode, all clocks for analog processing (e.g. the ZA codec) will be halted to reduce power consumption. The analog circuit will net operate normally until this bit is cleared. Digital Power Down (b0)}: Setting this bit causes a digital power down. In this mode, all clocks for digital processing (e.g. the DSP engine) will be halted to reduce power consumption. The digital circuit and the ADPCM initialization will not operate until this bit is cleared. 8.2.2. Byte Register 1 (BR1) This register controls the sidetone gain value and transmit gain. This register can also mute the transmit signal. All bits are cleared when the PDI/RESET pin is set to logic zero. B7 B6 B5 B4 B3 B2 B1 Bo Reserved | Sidetone | Sidetone | Sidetone | Transmit | Transmit | Transmit | Transmit BR1 Gain[2] Gain([1] Gain[0] Mute Gain|2] Gain[1] | Gain[0] riw riw rw rAW rAv rw rw -16-W9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT Reserved (b7/): This bit is reserved. Sidetone[2:0] (b6:b4): These two bits control the sidetone attenuation. The sidetone attenuation can range from -; to -8.5 dB as shown in Table 8-3. Transmit Mute (b3): Setting this bit will mute the transmit path in the ZA codec-tfilter block. A send zero is sent to the DSP engine for further processing. Transmit Gain (b2:b0}: These three bits control the transmit gain contrel as shown in Table 8-4. The gain range can be set in the 0 to 6.8 dB range in +1 dB steps. SIDETONE[2] (B6) | SIDETONE[1](B5) | SIDETONE[0](B4) | SIDETONE ATTEN. (DB) 0 0 0 =i -21.5 -18.0 -15.0 -13.5 -11.5 -10.5 -8.0 Table 8-3 Sidetone Attenuation TRANSMIT GAIN[2] | TRANSMIT GAIN[1]| TRANSMIT GAIN[0] TRANSMIT GAIN (B2) (B1) (BO) CONTROL(DB) 0 0 0 0 0 0 1 +1.5 0 1 0 +2 0 1 1 +3 1 0 0 +4 1 0 1 +5 1 1 0 +6 1 1 1 +6.8 Table 8-4 Transmit Gain Control Publication Release Date: August 1997 -17- Revision AlW9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT 8.2.3. Byte Register 2 (BR2) This register controls the operations of the receive path in the 2A code-tilter block. All bits are cleared when the PDI/RESET pin is set to logic zero. B7 B6 B5 B4 B3 B2 B1 Bo Reference} AXO PO RO Receive | Receive | Receive BR2 Point Enable | Disable | Reserved] Mute | Atten.[2] | Atten.[1] | Atten.[0] Select rAw rAw rw rAW raw rAW rAw Reference Point Select (b7): This bit determines the reference voltage for power amplifiers such as RO, AXO, and PO. The output of the VAG pin is the reference voltage. Setting this bit sets the reference voltage to 2.5 volts. When this bit is cleared, the reference voltage is the default value of VEXT/2. AXQ Enable (b6): This bit determines the status of the power amplifier AXO. Setting the bit will enable the operation of the AXO amplifier. When this bit is cleared, the amplitier AXO will be disabled by default. In power down mode, the output pins of AXO are high impedance. PO Disable (b5): This bit determines the status of power amplifier PO. Setting the bit will disable the operation of PO amplifier. When this bit is cleared, the amplifier PO is enabled by default. In the power down mode, the output pins of PO are high impedance. Reserved (b4): This bit is reserved. RO Mute (b3): Setting this bit will force the input of the RO amplifier to ground. The RO remains offset in order to avoid audible " pops" when turning the block on and oft. Receive Attenuation[?:0] (b2:b0): These three bits control the receive attenuation as shown in Table 8-5. The attenuation range can be set from 0 to -7 cB in -1 dB steps. RECEIVE ATTEN.[2] | RECEIVE ATTEN.[1] | RECEIVE ATTEN.[0] RECEIVE (B2) B1) (BO) ATTENUATION (DB) 0 0 0 0 0 0 | 0 1 0 -2 0 1 -3 -18 -W9320 & Winbond Continued RECEIVE ATTEN.[2] (B2) | RECEIVE ATTEN.[1] B1})| RECEIVE ATTEN.[0] RECEIVE ATTENUATION (BO) (DB) 1 0 0 -4 1 0 1 5 1 1 0 -6 1 1 1 7 Table 8-5 Receive Attenuation Control 8.2.4. Byte Register 3 (BR3) B7 B6 BS Ba B3 B2 B1 Bo Digital Rx | Dig. Rx Dig. Rx Dig. Rx Dig. Rx Dig. Rx Dig. Rx Dig. Rx BR3 Gain Gain[] Gain[5] Gain[4] Gain[3] Gain[zZ] Gain[1] Gain[0] Enable AW ray rAN hw rAW AW ray rAW This register contains information on the digital receive gain. All bits are cleared when the PDI/VRESET pin is set to logic zero. Digital Rx Gain Enable (b7): Setting this bit will enable the digital receive gain routine in the DSP engine. The receive gain can be programmed by setting the gain factors defined in this register BR3[B6:BO0]. When this bit is cleared, the digital receive gain routine is disabled. Digital Rx Gain[6:0](b6:b0): These seven bits show the value of the digital receive gain factor. The gain value is calculated as follows: 2 * b6 + b5+ 1/2 *b4 + 1/4 * b3 + 1/8 *b2 41/16 *b1 +1/32 * bO The first two bits (b6:b5) are integers and the last four bits are fractions. The decimal point is placed atter bit 5. The gain range is from -12 dB to +12 cB. 8.2.5. Byte Register 4 (BR4) B7 B6 B5 B4 B3 B2 B1 BO TonePar[7] | TonePar[] | TonePar[5] | TonePar[4] | TonePar[3] | TonePar[2] | TonePar[i] | TonePar[0] BR4 rAW rAW raw raw rAW rAW AW rAw This register holds the parameters for the tone generator. All bits are cleared when the PDI/RESET pin is set to logic zero. Tone Generator Parameters[7:0]{b7:b0): These seven bits contain the eight LSB frequencies or tone generator attenuation coefficients. The tone generator is enabled when the BR7[b3] register is set to 1. The four MSB tone parameters are placed in BR5[b3:b0]. Switching between the frequency and attenuation factor is determined by the BR5[b7:b6] register. Publication Release Date: August 1997 -19- Revision AlW9320 \ Minbond Flectronics Corp. IIR TIE OE, 8.2.6. Byte Register 5 (BR5) This register holds the parameters for noise burst detection and the tone generator. The noise burst detection and tone generator modes are enabled through the BR?(b3) register. All bits are cleared when the PDI/RESET pin is set to logic zero. B7 B6 B5 B4 B3 B2 B1 Bo NB Thd[7}/ NB Thd[6]/ | NB Thd[5}) | NB Tha[4]/ | NB Tha[3y NB Thd[e}y NB Thd[1}/ NBTha[oy BRS | ToneAddr[1] | ToneAddr[0] Don Care Don Care | TonePar[11] | TonePar[i0] | TonePar[9] | TonePar[8] rAW rAW rAW raw ri rAW thw raw Noise Burst Detect Threshold[7:0] (b7:b0}: When the device is in the noise burst detection mode (i.e. BR7[b3] = 0 and BR7[b6] = 1} these eight bits contain the threshold for noise burst detection. The detected algorithm use the trequency value to decide whether the noise is present or not. We suggest a threshold value greater than 80 (to be written in decimal format, i.e. 4 KHz above). Tone Generator Address[1:0](b7:b6): When the tone generator is enabled, (i.e. BR/[b3] = 1}, these two bits can be programmed to select the frequency or attenuation factor as shown in Table 8-6. Tone Generator Parameters/11:8](b3:b0): These four bits contain the four LSB frequencies or tone generator attenuation coefficients. The tone generator is enabled when the BR7 (b3) register is set to 1. The last eight LSBs are placed in the BR4[b7:b0] register. Switching between the frequency and attenuation factor is determined by bit 7 and bit 6. TONE TONE TONE PARAMETER SELECTION Frequency of Tone 1 Attenuation of Tone 1 Frequency of Tone 2 Attenuation of Tone 2 Table 8-6 Tone generator Address Parameters 8.2.7 Byte Register 6 (BR6) B7 B6 BS B4 BS B2 Bi BO | BR6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved This register is reserved. The user should not read or write to this register. 8.2.8. Byte Register 7 (BR7) This register is used to enable noise burst detection and the tone generator. Additional options include 2/6 frame delay and writing ready status for the BR4 and BR5 registers. All bits are cleared when the PDIVRESET pin is set to logic zero. B7 B6 B5 B4 B3 B2 Bt BO Ready for | NB Detect 2/6 Don t | Tone Gen. Tone1 Tone 2 BR7 BRA & Enable Delay Care Enable Reserved Enable Enable BR5 ro ro/wo rAN thw thw raw -20-W9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT Ready for Writing BR4 and BR5 (b7): This read-only bit indicates whether parameters have been written into the BR4 and BRS6 register. This bit is set after writing te BRS. This bit is cleared when the internal DSP Engine reads trom the BR4 and BR5 registers. Noise Burst Detect Enable (b6): This is a read-only/write-only bit. Setting this bit and bit 3 to O enables the ncise burst detection routine. If noise is detected, this bit is cleared and can be polled by an external micro-controller. This mutes the receive path. 2/6 Delay {(b5): This bit controls the frame delay status. Setting this bit inserts a 6-frame delay between frame control changes. Clearing this bit inserts a 2-frame delay between frame control changes. Don't Care (b4}: No effect whenever the bit is read or written to by an external micro-controller. Tone Generator Enable (b3}: Setting this bit performs the tone generator routine instead of the ADPCM decoder. In addition, the noise burst detection will be disabled. The result of the tone generator will be passed to the ADPCM encoder to compress the tone and transmit the encoded result to the DT pin. Reserved (b2)}: This bit is reserved. Tone 1 Enable (b1): Setting this bit enables the tone 1 routine for the tone generator. When this bit is cleared, the tone1 routine is disabled. Tone 2 Enable (b0): Setting this bit enables the tone 2 routine for the tone generator. When this bit is cleared, the tone 2 routine is disabled. If DTMF is enabled, the user must set tone 1 and tone 2 to enable. 8.2.9. Byte Register 8 (BR8) This register contains miscellaneous control bits. All bits are cleared when the PDI/RESET pin is set to logic zero. B7 B6 B5 B4 B3 B2 B1 BO S/W S/W Linear HPF BR8 Encoder Decoder Codec Disable | Reserved Reserved Reserved Reserved Reset Reset Mode rAN rAN rw rAW Sottware Encoder Reset (b7): Setting this bit forces the device to execute the ADPCM encoder initialization every time the encoder receives an interrupt. Publication Release Date: August 1997 -21- Revision AlW9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT Software Decoder Reset (b6): Setting this bit forces the device to execute the ADPCM decoder initialization every time the decoder receives an interrupt. Linear Codec Mode (b5): Setting this bit forces the device to perform as an 8 bit linear codec. The 6 LSB linear A/D converted output from the XA codec-tfilter will be truncated in this mode. HPE Disable (b4): Setting this bit will disable the high pass filter (HPF) in the transmit path fer applications such as battery test mode in BRO[b4:b3] = "1" - Reserved (b3:b0): These bits are reserved and should not be used by the user. CAUTION: Reserved bits (b3:b0) must be set fo zero af ail times for normal operation. 8.2.10. Byte Register 9 (BR9) B7 B6 BS B4 B3 B2 B1 Bo Tx Log Tx Log Tx Log Tx Log Tx Leg Tx Log Tx Leg Tx Log PCM[?]/ PCMI[6}/ PCM[]/ PCMI/4}/ PCM[3}/ PCM[2}/ PCM[1}/ PCMI[O}/ BRS Linear Linear Linear Linear Linear Linear Linear Linear PCM[123] PCM[12] PCM[11] PCM[10] PCM[9] PCM[8] PCM[7] PCM[6] roAwo ro/wo roAwo roAwo ro/wo roAwo ro/wo roAwo This register contains the PCM value of the transmit path. If the PCM value comes from the transmit path of the ZA codec-tilter, then BR9 may be internally written into the most siginificant bits of the 14 bit linear PCM (b13:b6). If the device is for applications such as CCITT test mode i.e. BRO[b4:b3] = "0" then BR9 may read the companding Log-PCM from an external micro-controller to be used for the ADPCM encoder. In the 14 bit linear mode, the 8 MSB are stored into this register and the lett 6 LSB will be placed in BR10[b7:b2]. See the description of BR10 for more details. Note that this register is read-only/write-only. 8.2.11. Byte Register 10 (BR10) B7 B6 B5 B4 B3 B2 B1 BO Encoder Encoder Encoder Encoder Encoder Encoder BR10 Linear Linear Linear Linear Linear Linear Reserved | Reserved PCM[5] PCMI[4] PCM[3] PCM[2] PCM[1] PCM[O] ro ro ro ro ro ro This register contains the 6 LSB of the linear PCM value for the transmit path. The PCM value must come from the transmit path of the =A codec-filter and not from an external micro-controller. The left 8 MSB are stored into BR9[b7:b0]. See the description of BR9 for more details. Note that this register is read-only. -~2?-OE, \ Minbond Flectronics Corp. W9320 IIR TIE 8.2.12. Byte Register 11 (BR11) B7 B6 B5 B4 BS B2 Bt BO Rx Log- Rx Log- Rx Log- Rx Log- Rx Log- Rx Lag- Rx Log- Rx Log- BR11 | PCM[7]/ | PCM[6]/ | PCM[5}/ PCM[4]/ PCM[3}/ PCM[2}/ PCM[1}/ PCM[O}/ DAG DAC DAG DAG DAC DAC DAC DAG PCM[13] | PCM[12] | PCM[14] | PCM[1C] PCM[S] PCM[8] PCM[7] PCMI6] ro ro ro ro ro ro ro ro This register contains the PCM value of the receive path. The PCM value comes from the companding Log-PCM generated by the sync adjustment block of the decoder in CCITT test mode, i.e. BRO (b4:63) is set to logic "0". Note that, this register is read-only. The combined BR11 (b7:b0) and BR12 (b/:b2) value is the same as sending the D/A converter . 8.2.13. Byte Register 12 (BR12) ro ro ro ro ro ro B7 B6 B5 B4 B3 B2 B1 BO DAG DAG DAG DAC DAG DAC Reserved Reserved BR12 PCN[5] PCMI/4] PCM[3] PCM[2] PCM[1] PCM[O] This register contains the 6 LSB of the linear PCM value for the D/A converter. The PCM value cannot be entered by an external microcontroller. The lett 8 MSB are stored into BR11[b7:b0]. See the description of BR11 for more details. Note that this register is read-only. 8.2.14. Byte Register 13 (BR13) B7 B B5 B4 B3 B2 B1 Bo BR13 Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved This register is reserved and should not be used by the user. 8.2.15. Byte Register 14 (BR14) B7 B6 BS B4 B3 B2 B1 BO BR14 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved This register is reserved and should not be used by the user. 8.2.16. Byte Register 15 (BR15) This register shows the version number of this device. B7 B6 BS B4 B3 B2 B1 BO Reserved | Reserved | Reserved | Reserved | Vers.[3] Vers. [2] Vers.[1] Vers.[0] BR15 ro ro ro ro -23- Publication Release Date: August 1997 Revision Ali ots . Winbond sie ~ Version[3:0] (b3:b0): These four bits determine the manufacturing version number of this chip. 9. ELECTRICAL CHARACTERISTICS 9.1. Absolute Maximum Ratings (Voltage Referenced to Vss pin) W9320 Flectronics Corp. IIPS I IS IDOI SIO II IIS II SII IID SII SID NIIIOR ISIS III IIESII IID DIISIIIIII III SIP INI IIE SII IIPS IBESIIIPDOII IID IIIIOI ASIII IID IIE SII IID HIIIOPIIIIOIBIIDONIIIIESII SIPS IEESIISID III SIPOSIIODSIIOSIIIEESIIIIN PARAMETER SYMBOL RATING UNIT Power Supply Voltage VEXT, VDD -0.3 106 V Analog Input/Output Voltage ~- -0.3 to VDD + 0.3 V Digital Input/Output Voltage ~- -0.3 to VEXT + 0.3 Vv Operating Temperature Top -25 to +85 od Storage Temperature TSTG -85 to +85 oT Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2. DC Characteristics (Vss = 0 volt Top = -25 to +85 C) PARAMETER SYM. CONDITION MIN. TYP. MAX. | UNIT Operating Voltage VEXT | ----- 2.7 3.0 5.25 V Operating Current IEXT | MCLK = 16.384 MHz, --- --- 25 mA Charge Pump "N" no load Power Down Current IPWDN | MCLK Off --- --- 0.5 mA Input High Voltage VIH All digital input pins VEXT -0.5 woe Pwr Vv Input Low Voltage VIL All digital input pins 0 no 0.5 Vv Output High Voltage VoH | DT, SSP Tx VEXT -0.5 wee weno V Output Low Voltage VoL | DT, SSP Tx 0 --- 0.4 Vv Input High Current lit Vss < VIN S VEXT -10 --- +10 UA Input Low Current IH Vss < VIN Ss VEXT -10 --- +10 uA Input Capacitance CIN All digital input pins to --- --- 10 pF Vss - 24 -\ Winbond sthin Plectronics Corp. OE, W9320 IIR TIE 9.3. Analog Transmission Characteristics (VDD = +5V +5%, Vss = 0 volt, Top = -25 to +85 C ; all analog signal referenced to VAG; 64 Kbps PCM; FST = FSR = 8 KHz; BCLKT = BCLKR = 2.048 MHz; MCLK = 16.384 MHz ; Unless otherwise noted) 9.3.1. Amplitude Response for Analog Transmission Performance PARAMETER SYM. CONDITION TYP. TRANSMIT RECEIVE UNIT MIN. | MAX. | MIN. | MAX. Absolute Level LABS 0 dBmo =-3 dBm @ 600 9 | 0.549 -_- _ _ _ Vrms Max. Transmit Level TXMAX | 0000 were 1.130 _ _ _ Vpk Frequency Response, GRTV 15 Hz aon- a--- -40 -0.5 0 dB eee to 0 domo @ 50 Hz _- _- 30 | -05 0 60 Hz - - -26 | -05 0 200 Hz --- -1.0 -04 | -05 0 300 ta 3000 Hz -- -0.20 | +0.15 | 0.20] +015 3300 Hz --- -0.35 40.15 | 0.35 | 40.15 3400 Hz --- -0.8 0 -0.8 0 4000 Hz --- --- -14 -- -14 4600 to 100, 000 Hz --- --- -32 --- -30 Gain Variation vs. Level GLT +3 to -40 dBmo --- -0.3 +0.3 -0.2 +0.2 dB Tone -40 to -50 dBm0 -- 1.0 | 41.0 | -04 | +04 (1020 Hz relative to -10 -50 to -55 dBmO -- 146 | 416 | -o8 | +08 dBm0o} 9.3.2. Distortion Characteristics for Analog Transmission Performance PARAMETER SYM. CONDITION TYP. TRANSMIT RECEIVE UNIT MIN. | MAX. | MIN. | MAX. Absolute Group Delay' DABS 1600 Hz --- --- 440 --- --- pS Group Delay#! DRTV 500 to 600 Hz -- -- 210 = = Referenced to 1600 Hz 600 to 800 Hz _. _. 430 __. _. 800 to 1000 Hz --- --- 70 --- --- 1000 to 1600 Hz --- --- 35 --- --- 1600 to 2600 Hz --- --- 70 --- --- 2600 te 2800 Hz --- --- 95 --- --- 2800 te 3000 Hz --- --- 145 --- --- Total Distortion vs. DLT +3 dBmo --- 36 --- 34 a dBc Level Tone 0 to -30 dBmo _- 36 36 _ (1020 Hz, Mu-Law, C- -40 dBmo _. 29 _ 30 _ Message) -45 dBmo --- 25 --- 25 -- Note: (1), (2): Guaranted by engineering test, not mass production. 25 - Publication Release Date: August 1997 Revision AlW9320 & Winbond 9.3.3. Noise Characteristic for Analog Transmission Performance PARAMETER SYM. CONDITION TYP. TRANSMIT RECEIVE UNIT MIN. | MAX. | MIN. MAX. Idle Channel with NIDE Mu-Law, C-Message _ _ 19 _ +11 dBrn Equipment Noise Spurious Out-of-Band NsPo 4600 ta 7600 Hz --- o-- --- o-- -30 dB at SPKO 7600 to 8400 Hz _- _ -- _ -40 (300 to 3400 Hz @ 0 8400 to 100,000 Hz - _- _-- _- -30 dBmo) In-Band Spurious NIBS 300 te 3000 Hz --- --- -48 --- -48 dB (1020 Hz @ 0 dBm0) Crosstalk NeTkK 300 to 3000 Hz --- --- -70 --- -70 dB (1020 Hz @ 0 dBmo) 9.4. Analog Electrical Characteristics (OP Amplifer TG, RO; Power Amplifer AXO, PO; VDD = +5V +5%, Vss = OV: Top = -25 to +85 C) PARAMETER SYM. CONDITIONS | MIN. | TYP. MAX. UNIT Input Offset voltage of TG VOFIN Ti+, TI- ~~ - +25 mV Input Common Mode Voltage Vemv TI+, Tl- 1.0 -- Vbb -2.0 Vv Load Capacitance for RO CLRO RO -- -- 100 pF Load Resistance to VAG for TG, RO Rib TG, RO 2 --- --- KO VAG Output Voltage VAG to Vss 24 2.5 2.6 Vv Power Supply Rejection Ratio PSRRdd TG oo 40 -- dBc (0 to 100 KHz @ 100m Vrms to Vop with C-Message) Load Capacitance for AXO, PO CLAP AXO- to AXO+; oo i 300 pF PO- to PO+ Load Resistance differentially for AXO, RLDAP AXO- to AXO+; 300 --- oe Q PO PO- to PO+ Input Offset Voltage for PI VoFPI ref to VAG noon +25 mV - 26 -W9320 f Winbond ronics Corp. PIII ISI NIRS II SID INI SII SSID SIE SII OID III ESII IID AII SOP IIIIOWI SII IMII IIE MIISIP RII SSIS IPD OII IID IIIIIIESII INDI IBE SII IED NII III NIIIOPI SII OMB IIESIIIIODIIIOIIIED III SID III IIPOSIIODSIIOSIIIEESIIIIN 9.5. Digital Switching Characteristics 9.5.1. Characteristic of Serial Data Port for Long Frame and Short Frame (VEXT = +2.7 to 5.25V ; Ves = OV; all digital circuits referenced to Vss; Top = -25 to +85 C, CL = 150 pF ) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. | UNIT Master Clock Frequency TMAST MCLK 10.232 10.240 | 10.247 | MHz 16.376 16.384 | 16.391 Bit Clock Frequency TBCLK BCLKT,BCLKR 128 -- 2048 KHz Frame Sync. Frequency TSYNG FST, FSR --- 8 -- KHz Clock Duty Cycle De MCLK, BCLKT, BCLKR 45 50 55 % Rise Time TIR All digital input pins - -- 50 ns Fall Time TIF All digital input pins - -- 50 ns Frame Sync. Pulse Width TFSP FST, FSR 100 --- --- ns Transmit Sync. Timing TXS BCLKT to FST 20 - -- ns TSX FST to BCLKT 80 --- --- Receive Sync. Timing TRS BCLKR to FSR 20 - --- ns TSR FSR to BCLKR 80 -- --- Setup Time for DR Valid TSTDR -- 20 -- -- ns Hold Time for DR Valid THDDR -- 50 - - ns Output Delay Time for DT Tpv BCLKT to DT 10 -- 140 ns Valid Output Delay Time for DT TDHI BCLKT to DT 10 -- 140 ns High Impedance Note: these parameters are shown in Figure 9-1 and 9-2. Publication Release Date: August 1997 - 27 - Revision AlW9320 OE, . Winbond sthin Plectronics Corp. IIR TIE Figure 9-1 Long Frame Sync, Timing FST BCLKT DT Figure 9-2 Short Frame Sync, Timing - 28 -& Winbond 9.5.2. Characteristic of Serial Setup Port (SSP) W9320 PIII, tenc SSP EN f teen H SSP CLK Figure 9-3 Serial Setup Port (SSP) Timing (VEXT = +2.7 to 5.25V ; Vss = OV; all Digital Circuit Referenced to Vss ; Top = -25 to +85 CG, CL = 150 pF) PARAMETER SYM. CONDITIONS MIN. | TYP. MAX. | UNIT SSP Clock Frequency TSSPC SSP CLK -- 2.048 MHz Clock Duty Cycle of SSP Dssp SSP CLK 40 50 60 % SSP Enable Timing TENG SSPEN to SSP CLK 50 o> ns TCEN SSP CLK to SSP EN 50 = --- SSP Rx Valid Timing TRVB Setup Time 50 -- --- ns TRVA Hold Time 50 --- --- Output Delay Time for SSP Tove SSP CLK to SSP Tx -- -- 140 ns Tx Valid Output Delay Time for SSP TDHC SSP En Rising to SSP Tx -- -- 140 ns Tx High Impedance SSP Disable Timing TcbI SSP CLK to SSP EN 50 --- --- ns Tole SSP EN to SSP CLK 50 o> Note: The parameters are shown in Figure 9-3. Publication Release Date: August 1997 Revision Al - 29 -W9320 \ Minbond Flectronics Corp. IIR TIE 10. APPLICATION INFORMATION OE, 10.1. Handset Application for Wireless Communication For wireless handset applications, VEXT is supplied from a 2.7 to 5.25 volt battery power supply. Meanwhile the VDD pin, connected with a 1.0 WF capacitor to ground, is a 5 volt output and should not be connected to VEXT. The VDSP pin, connected with a 0.1 uF capacitor to ground, is a 3 volt output. The VDD and VDSP pins should not be used to supply any external systems. The chip must also enable the charge pump by clearing the BRO[b2] of SSP port. The output power amplitier pins PO- and PO+ drive the receiver speaker. A ringer is driven by the differential power amplitier outputs AXO- and AXO+. The input to the transmitter amplifier is fram a microphone output. The application circuit, Figure 10-1 is as follows. Battery Power 1K Le ADPCM Chip = 20K = VDD 1K i 1.0uF 1K FSR = RA Theo el BCLKR {} ANA Tho3 oso 1.0uF 1K 20K VAG 44 oa DR ADPCM Data Input = 01 ufo I Cie a 150.0 20K AKO oF OTF Ri Vw <6 2g = nger Speaker AXO+r 7 2a VSS Battery Po ik aulery rower vDSP 21H MCLK (SCP) System Clock= 10.24/16.384 MHz 04 uF VEXT Ig 20K DT ADPCM Data Output =O1urF = Plo 42 BCLKT 2048 KHz Data Rate a POs 11 14 FST 8 KHz Frame Syne. Input Receiver poe KAR POs 5 17SSP Rx 1500 PDIRESET |. 1 |_SSP Tx SSP En h4 {q4S5P CLK Micro-Controller Figure 10-1 Typical Handset Application 10.2. Transformer Application for Public Switching Telephone Network (PSTN) For this application, VEXT = +5V 145%, VDD is an input and should be connected to VEXT externally. The charge pump capacitor Ci+ and G1- should not be used and the device must disable the charge pump circuit by setting BRO[b2]. Here VEXT and VDD can share the same 0.1 WF capacitor. The transmitter TI-, Tl+ and the receiver PO-, PO+ are connected to the secondary terminal of the telephone line transformer. The application circuit, Figure 10-2 is as follows. -30-W9320 & Winbond ccbis Flectronics Corp. (Battery Power ADPCM Chip 10K TG; \_/ pg fnVOD Jak Theo 7 ESR The 3 og BCLKR VAG 14 ppt DR ADPCM Data Input x= 0.4 uF Ana ___ RO} 5 pa Gl+ N.C. 20k AKO C1 N.C "6 page N.C. N.C__AXOur4 7 22a VSS VDSP rg 21 FLMCLK (SCP) Systern Glock= 10.24/16.384 MHz of uF =I VEXT ot une = 9 20nDT ADPCM Data Output = a 19H BCLKT 2048 KHz Data Rate aK PO FST. {oe ee 7 Ate 600.0 Tip 1509. W 18) & K Hz Frame Syne. Input POs SSP Rx = N=1 | N=OS ___ 12 ve PDVRESET. aa Chis 1628S? Tx SSP Eny4 16 S5P CLK Micro-Controlle Figure 10-2 Typical Transformer Application 11. HOW TO PROGRAM THE TONE GENERATOR 11.1 Introduction The chip can enable the tone generator by setting BR7(b3) to logic "1". Under this operation, the ADPCM decoder will be disabled. The tone generator is implemented by the DSP engine based on the function "c" os(nx) - The procedure for programming the W9320 tone generator is as follows. Setting BR7(d3} to logic "1" turns on the tone generator. In addition, BR7(b1:b0) must be set to logic "O" to avoid turning on tone or tone2, without first pregramming the coetticients for freqency and attenuation. Setup the 12-bit coefficients for freqency and attenuation. First the 8 least significant bits(LSB) of 12- bit coefficients must be written into BR4(b7:b0); then the 4 most significant bits(MSB) of 12-bit coefficients and address parameter will be written inte BR5(b3:b0) and BR5(b7:b6) simultaneously in the same cycle. The cycle of setup coefficients is once every FSR cycle (125 uS) because the DSP engine in device can access the SSP register only at every FSR cycle when the 12-bit coefficient in written into SSP refister. Poll BR7(b7) until BR7(b7) becomes a logic "0" before writing another 12-bit coefficent for BR4 and BR5. Set BR7(b1:b0) to logic "1" selects the tone 1 or tone2 generator. Publication Release Date: August 1997 -31- Revision AlW9320 i ots Winbond | BDO sthin Plectronics Corp. SEIT OT 11.2 Tone Frequency Coefficient Calculation The tone frequency coefficient is calculated by the function cos(2*PI*t/8000 radian)" where Pl = 3.14159, and fis frequency (Hz}. The number will then be converted into a 12-bit coefficient whose MSB is the sign and whose remaining 11 bits are the fractional part found by multiplying by 2048 and rounding off the number. For example, if the frequency is 1209 Hz, the frequency number is as followed. Cos (23.14159*1209/8000) = 0.582053 The converted binary number is 010010101000 and the hex number 4A8, where BR4 = 4 and BR5 = A8. 11.3 Tone Attenuation Coefficient Calculation The tone attenuation coefficient is calculated by the function "x/1.13 Vp" where x is the amplitude (Vp}. The number will be converted into a 12-bit coefficient whose MSB is the sign and whose remaining 11 bits are the fractional part, found by multiplying by 2048 and rounding off the number. For example, if the attenuation is -14 dBm (600 ) Hz, first change the dBm units into Vp format as follows. sqrt[10*exp(-14/10)*600*0.001] * sqrt(2} = 0.218570 Vp The attenuation is "0.218570/1.13 = 0.193425" the binary number is 000110001100 and the hex number is 18C where BR4 = 1 and BR5 = 8C. 11.4 Frequency Coefficients for the DTMF Signal Table 11-1 shows the 12-bit frequency coetticients for the DTMF signal. The 8 least significant bits are stored in BR4(b7:b0), the 4 most significant bits are stored in BR5(b3:b0). Table 11-2 illustrates the 12-bit attenuation coefficients for the DTMF signal such as -9 dBm (600 ) or -6 dBm (600 ) for column tone and -11 dBm (600 ) or -8 dBm (600 ) for row tone. FREQENCY BRS5 BR4 697 DS 770 95 852 46 941 EA 1209 A& 1336 FO 1477 32 1633 2 46 Table 11-1 Frequency Coefficients for the DTMF Signal ATTENUATION (DBM@600 W) PEAK VALUE (VP) BR5 (HEX) BR4 (HEX) -14 0.308738 2 30 -9 0.388679 2 co -8 0.436105 3 16 -6 0.549023 3 E3 Table 11-2 Attenuation Coefficients for the DTMF Signal -32-f Winbond 12. PACKAGE DIMENSIONS W9320 ronics Corp. PIII II SINR ISIS SID INI SII OID INES II IIIS IEE SII SID III IOPISIIONI SISO NPIS IE SIISIPNIIIOPI SIDING IID OSIIIIESIS INDI IIE SII IID HII IOPIIIIONI SII OWI IIE SIIIIPRIEIOIIIEPONE SID ISPD IIE SII OID IEE SII IID HIIINS ABRAASARRERRBRRRRE E Vue Sa 14 AB|A Figurei2-1 28-Lead Plastic SOP Package There are two packages for the W9320. One is a 28-lead plastic SOP shown in Figure 12-1, the other is a 28-lead plastic DIP shown in 12-2. DIMENSION IN MM SYMBOL DIMENSION IN INCH A 0.110 Max. 2.794 Max. Al 0.004 Min. 0.102 Min. A2 0.093 +0.005 2.362 10.127 b 0.016 +0.004 0.406 +0.102 -0.002 -0.051 c 0.010 +0.004 0.254 +0.102 -0.002 -0.051 D 0.705 TYP. (0.725 Max.) 17.90 TYP. (18.415 Max.) E 0.295 +0.005 7493 +0.127 0.050 +0.006 1.270 +0.152 el 0.370 Nom. 9.396 Nom. HE 0.406 +0.012 10.312 +0.305 L 0.036 +0.006 0.914 +0.203 LE 0.055 +0.006 1.397 +0.203 $ 0.043 Max. 0.102 Max. 8 0-10 degree 0-10 degree -33- Publication Release Date: August 1997 Revision Altity, OE, it Riectronics Winbond Corp. W9320 IIR TIE D 28 15 PS AD O oO nee Bat Bal Ge Se el a or a oe Bat a . E C= \ lc MUD Loo mip swerere [YO . - i = WJ JP Pe Seating Plane {| B 21 @ = Figurei2-2 28-Lead Plastic DIP Package SYMBOL DIMENSION IN INCH DIMENSION IN MM A 0.210 Max. 5.334 Max. At 0.010 Min. 0.254 Min. A2 0.155 +0.005 3.937 +0.127 B 0.018 +0.004 0.457 + 0.102 -0.002 - 0.051 B1 0.06 + 0.004 1.524 +0.102 - 0.002 -0.051 c 0.01 + 0.004 0.254 +0.102 - 0.002 -0.051 1.46 TYP. (1.47 Max.) 37.084 TYP. (37.33 Max.) 0.6 +0.01 15.24 20.254 E1 0.545 +0.005 13.843 +0.127 e1 0.100 +0.01 2.540 +0.254 L 0.130 +0.01 3.302 +0.254 eA 0.650 =0.02 16.51 20.508 Ss 0.09 Max. 2.286 Max. 0-15 degree 0-15 degree 34 -| Winbond sthin Plectronics Corp. OE, W9320 IIR TIE ete, (Winbond oi Electronics Corp. Headquarters Winhord Electronios (HAG) Lid. No. 4, Dyeatiogs Reb 1H, Sim. B03, Woris Trace Square, Tower H, Salonwue-Baged Init al Fark, 423 Wel Bun Rel, Swun Tang, Hsinghny, Taiwan Sowhoon, Nag Keng TEL: ABS LS7 SS YHA: SS2-2794 308 SAR: BRST SRT SAR: BSA-27 SS. GS Rite ew owned coe fy Veskte & Fax-uache manned: Ag. 278 BY Taine! Glos S40 Ne. 346, Sec. 3, Min-Bhang Kast 8., Talesi, Tabwan TRS RD s ROARS. FAX: S88.2.79 S789 Winhond Elaotronios North Ameioa Sorp. Winona Mamery Lab. Winkond Micrselaoiranios Garp. Winbond Syateme Lab. 730 Ckoherd Parkway. Sar dase, Ca SSHR4, UA. TER: Pade FAR: 1000-34 8088 [RRR RRR nn ene 88 TS TE TS Node. AM cote ond gagiiragbang aq Suttiged it ehaaye who nome, -35- Publication Release Date: August 1997 Revision Al