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May 2nd, 2014
Automotive Grade
AUIRS20302S
Pre-regulated Three Phase Gat e Driver
Features
• 3 phase gate driver for 24V & higher drives
• Under-voltage lockout for all channels
• Cross-conduction prevention logic
• High voltage pre-regulator MOSFE T
• Power-on reset architecture
• FAULT detection and Reset
• Current sense comparator
• Over-current blanking time
• 3.3V logic compatible
• Matched propagation delay for all channels
• Fully operational up to +200V
• Floating channels for bootstrap operation
• High negative transients immunity
• Pre-regulated supply line for uP
• Automotive qualified
• Leadfree, RoSH Compliant
Typical Applications
24V to 150V – 3 Phase Motor Drives
Automotive & Truck HVAC, PUMP
BLDC Motor Driv es
Typical Connection Diagram
Product Summary
Topology 3-phase gate driver
VOFFSET 200 V
VOUT 8.0 V – 17 V
Io+ & I o- (typical) 0.20 A & 0.35 A
tON & tOFF (typical) 530 ns / 530 ns
Deadtime (typical) 0.7 us
Package
SOIC 28WB
+ Bat
- Bat
U
W
AUIRS20302S
VPR
VCP
Vb1
Lin1
Vb2
Vs1
Vs2
Vs3
Ho1
Ho2
Ho3
Lo1
Lo2
Lo3
Cap
Com
Can
Vss
Ref
5V Reg
ASIC
or uP
Lin2
Lin3
Hin1
Hin2
Hin3
Flt
Frst
EN
Vb3
AUIRS20302S
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Table of Contents Page
Typical Connection Diagram 1
Description/Feature Comparison 3
Qualification Information 4
Absolute Maximum Ratings 5
Recommended Operating Conditions 5
Static Electrical Characteristics 6
Dynamic Electrical Characteristics 7
Functional Block Diagram 8
Input/Output P in E qui valent Circuit Diagram
9
Lead Definitions
10
Lead Assignments 10
Application Information and Additional Details 11
Parameter Temperature Trends 16
Package Details 21
Tape and Reel Details 22
Part Marking Information & Ordering Information 23
AUIRS20302S
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Description
The AUIRS20302S is a three phase gate driver dedicated to BLDC motor drive up to 600W. Proprietary HVIC
technology enables this rugged monolithic design with enforced Automotive ESD & Latch-up grades. Primarily
designed for 24V battery application, its drive capability goes from 12v to 200V which cover all the abnormal
conditions of the vehicle. The gate drive circuitry features cross-conduction preventive and minimum dead-time
blocks. It is powered by a constant voltage so that the gate drives never exceed 17V including during Load Dump
condition.
An external MOSFET is acting as a pre-regulator. The inner charge pump and voltage control loop drives its gate in
order to keep the VPR pin constant when the battery voltage varies. The AUIRS20302S also features an over-
current protection that definitively shuts down all gates in case of short-circuit. The fault condition is reset by cycling
the FRST pin while the I.C is disabled. A blanking time, synchronized with each high side switch command, avoids
any premature triggering of the protection.
The logic control block of the AUIRS20302S is developed in order to support a fast and reliable 3 phase BLDC
design. For example, its inputs are compatible with the 3.3V logic processors and feature a short-pulse/noise
rejection filter. The 6 commands include matched propagation delays, shoot-through protections and minimum
dead-time. The bootstrap capacitor voltage of each phase is monitored independently (UVLO). Also, the maximum
gate voltage is controlled by the pre-regulator in all conditions. No linear or abnormal gate drive is possible. The
VPR pin can also supply the surrounding system components if the total consumption doesn’t exceed 0.1A.
AUIRS20302S
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Qualification Information†
Qualification Level
Automotive
(per AEC-Q100
††
)
Comments: This family of ICs has passed an Automotive
qualification. IR’s Industrial and Consumer qualification level is
granted by extension of the higher Autom otive level.
Moisture Sensitivity Level SOIC28
MSL3††† 260°C
(per IPC/JEDEC J-STD-020)
ESD
Machine Model
M1 (+/-200V)
(per AEC-Q100-003)
Human Body Model
H1B (+/-2000V)
(per AEC-Q100-002)
Charged Device Model
C3B (+/-500 V)
(per AEC-Q100-011)
IC Latch-Up Test
Class II Level A
(per AEC-Q100-004)
RoHS Compliant
Yes
†
Qualification standards can be found at International Rec tifier’s web site http://www.irf.com/
††
Exceptions to AEC-Q 100 requirements are noted in the qualification report.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your International
Rectifier sales r epresentative for further information.
AUIRS20302S
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Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to VSS, all currents are defined positive into any lead. An operation above the absolute maximum limit is not impl ied and
could damage the part. The thermal resistance and power dissipation ratings are measured under board mounted and free air conditions
Symbol Definition Min. Max. Units
VB1,2,3
High side floating supply voltage
-0.3
220
V
VHO1,2,3
High side floating output voltage
VS1,2,3 - 0.3
VB 1,2,3 + 0.3
VS1,2,3
High side offset voltage
VB 1,2,3 - 20
VB 1,2,3 + 0.3
VPR
Low side supply voltage
-0.3
17
VCP
Charge pump output voltage
-0.3
17
COM
Power ground
-5
5
V
LO1,2,3, / FLT
Low side output voltage LO#; FLT pin -0.3 VPR + 0.3
VIN
Input pin voltage (LIN#, HIN#,)
-0.3
VPR + 0.3
Can/Cap
Over-current comparator inputs
-0.3
VPR + 0.3
EN/Frst
Enable & Fault Reset in puts
-0.3
VPR + 0.3
dV/dt
High side floating v oltage slew rate
—
50
V/ns
RthJA
Junction to ambient thermal resistance
—
80
°C/W
TJ
Maximum operating junction temperature
150
°C
TS
Maximum sto rage temperature
-55
150
TReflow
Reflow max. temperature (60 sec.)
—
260
Recommended Operating Conditi ons
The Input/Output timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions.
All voltage parameters are referenced to VSS. The VS & COM offset rating are tested with all supplies biased at 15V differential.
Symbol Definition Min. Max. Units
VB1,2,3
High side floating supply voltage
VS1,2,3 +6
VS1,2,3 +19
V
VHO 1,2,3
High side output voltage HO#
VS1,2,3-0.3
VB1,2,3+0.3
VS 1,2,3
High side floating supply voltage
(Note 1)
200
VPR
Low side supply voltage
6
17
VLO1,2,3
Low side output voltage LO#
-0.3
VPR+0.3
COM
Power ground
-5
5
VHO1,2,3
High side output voltage
VS1,2,3
VB1,2,3
VLO1,2,3
Low side output voltage
COM
VPR
VIN
Logic input voltage LIN, HIN, EN, CAp, CAn, FRST
VSS-0.3
VPR
Vcan/cap
Common mode voltage on the CAN & CAP inputs
0
5
VCP
Charge Pump Output Voltage
-
15
Note 1: Logic operational for VS between COM -5V to COM +200V. Logic state held for VS of COM -5 to COM – VBS.
(Please refer to the Design Tip DT97 -3 for more details).
AUIRS20302S
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Static Electrical Char act er istics
Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤ 125°C with bias conditions of
VBIAS (VPR,VBS 1,2,3) = 15V. The VIN , VTH and IN parameters are referenced to VSS and are applicable to all six channels (HS 1,2,3
and LS 1,2,3). The VO and IO parameters are referenced to COM and VS 1,2,3 and are applicable to the respective output leads: LO1,2,3
and HO1,2,3.
Symbol
Definition
Min
Typ
Max
Units
Test Condit ions
VIN,th+
Input positive going threshold
(Hin#, Lin#, EN, FRST)
-
1.9
2.5
V
VIN,th-
Input negative going threshold
(Hin#, Lin#, EN, FRST)
0,7
1
-
Iin+
Input bias current
(Lin#, Hin#, EN, FRST)
15
100
220
µA
Vin=5V
Iin-
Input bias current
(Lin#, Hin#, EN, FRST)
-1
0
1
Vin=0V
VPR,UVth+
VPR supply undervoltage positive going threshold
(note 2)
6.4
7.2
8,2
V
VPR,UVth-
VPR supply undervoltage negative going threshold
(note 2)
6
6.7
7.6
VPR,UVhys
VPR supply undervoltage hysteresis
(note 2)
0.4
0.5
0.7
VBS, UVth+
VBS supply undervoltage positive going threshold
6.4
7.2
8,2
VBS, UVth-
VBS supply undervoltage negative going threshold
6
6.7
7.6
VBS, UVhys
VBS supply undervoltage hysteresis
0.4
0.5
0.7
I
LK
Offset supply leakage current
-
5
50
µA
VB=VS=200V
Iqbs
Quiescent VBS supply current
20
45
120
Iqpr
Quiescent VPR supply current
1
2,5
5
mA
VPR=14V
V
OH
High level output voltage, VPR – VO, HO#
0,2
0.9
1.4
V Io =20mA
V
OL
Low level output voltage, VO, HO#
0,05
0.2
0.6
Io+
Output high short circuit pulsed current, HO#,LO#
105
200
450
mA
Vo =0V,
PW ≤10 µs
Io- Output low short circuit pulsed current, HO#,LO# 210 350 650 mA
Vo =15V,
PW ≤10 µs
VCP
Charge pump output voltage
VPR=4V
5
6
7,5
V Rext=100kΩ
VPR=8V
10
13
15
VPR=9V
13
15
17
VPR=14V
13
15
17
ICP+
Charge Pump source current
VPR=6V
100
200
400
µA
VPR=14V
200
500
1000
ICP-
Charge Pump sink current
-
5
10
mA
Vcl_Vcp
Vcp pin Activ e Clamp
17
18.6
21
Icp=10mA
V
FLT
FLT low output voltage
-
-
0.8
V
I
FLT
= 10mA
Ican
1
Comparator input high bias current
-
-
7
µA
Can=5V
Ican
0
Comparator input low bias current
-
-
7
Can=0V
Voff
Comparator input offset
-33
-
33
mV
Vcap= 5V
Tfrst
Minimum FAULT RESET time
20
-
-
us
Ton_EN
Minimum ENABLE time
20
-
-
us
(note 2):. UVPR is latched; when VPR>UVPR, FAULT remains pulled down. This leads to have the FAULT active and latched at VPR ramp
up if no fault reset occurs.
AUIRS20302S
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Dynamic Electrical Characteristi cs
Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤ 125°C with bias conditions of
VPR = VBS = 15V, VS1,2,3 = VSS = COM, and CL = 1000 pF.
Symbol
Definition
Min
Typ
Max
Units
Test Condit ions
Ton
Turn-on propagation delay, LO#, HO#
350
550
850
nS VIN = 0 & 5V
Toff
Turn-off propagation delay, LO#, HO#
350
600
850
LOtr , HOtr
Turn-on rise time LO#, HO#
10
100
300
LOtf , HOtr
Turn-off fall time LO#, HO#
5
35
75
T
OC
Over-current to output shutdown response time
-
1
1.7
uS V(Can)-V(Cap)=1V
T
FLT
Over-current FLT response time
-
0.7
1.2
tblank
Current limit blankin g time
5
6
7.5
tFILIN
Input filter time (HIN, LIN)
200
270
510
nS
VIN = 0 & 5V
DT
Dead-time
420
700
1000
VPR=15V
Truth Table
This table is valid for volt ages ranges defi ned in the recommended operating conditions section.
ENABLE
CAN>CA
P
FRST
LIN#/HIN
#
LO#/HO#
FLT
Comments
0
0
0
X
0
No Change
FLT keeps showing same status
0
1
0
X
0
Vss
0
0
1
X
0
Open
FLT Reset Sequence (Note3)
0
1
1
X
0
Vss
1
0
X
LIN#/HIN#
LO#/HO#
Open
Normal Operation: An anti-shoot-through
logic prevents each channel from turning on
simultaneously the HS and LS switches
1
1
0
LIN#/HIN#
0
Vss
Over-current detection (FLT)
1 *
1 *
1 *
LIN#/HIN# *
LO#/HO# *
Open*
* Not recommended
(cycling on default)
Note 3: The proper sequence to reset the Fault latch is to first set EN at 0V and then cycle the FRST pin. The gate drives return to normal
operation when EN is set again at 5V.
AUIRS20302S
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Functional Block Diagram
Lin1
EN
Hin1
Hin2
Hin3
Lin2
Lin3
Deadtime &
shoot-through
protection
HV level
shifter
Latch &
Undervoltage
detection
Driver
VB1
HO1
VS1
Driver
LO1
Deadtime &
shoot-through
protection
HV level
shifter
Latch &
Undervoltage
detection
Driver
VB2
HO2
VS2
Driver
LO2
Deadtime &
shoot-through
protection
HV level
shifter
Latch &
Undervoltage
detection
Driver
VB3
HO3
VS3
Driver
LO3
Over-current
Blanking time
+
_
CAp
CAn
Logic
Control
VPR
Pre-
Regulation
Control
VCP
COM
VSS
Q
R
S
Fault
latch
FRST
FLT
Vcc
AUIRS20302S
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Input/Output Pin Equi valent Circuit Diagram
AUIRS20302S
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Lead Definitions
Symbol Description
HIN#
Input for high side gate drive – A c tiv e high
LIN#
Input for low side gate drive – active high
VSS
Logic Ground
VCP
Pre-regulated MOSFET gate output – Analog gate drive
VPR
Power supply pin of the I.C (equivalent to Vcc)
LO#
Low side gate driver outputs (1,2 & 3)
COM
Common low side gate drive return pin & Power Ground
CAP
Non inverting input of the over-current comparator
CAN
Inverting input of the over-current comparator
VS#
High side floating supply return (1, 2 & 3)
HO#
High side gate driver outputs (1, 2 & 3)
VB#
High side floating supply (1, 2 & 3)
EN
Enable input – Active high
FAULT
Fault output pin – Open collector
FRST
Fault Reset input pin – Active high
Lead Assignments
AUIRS20302S
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Application Inform at ion and Additional Details
Input Short-Pulse / Noise Rejection Filter
The inputs of this I.C are compatible with CMOS and TTL standards. The AUIRS20302S has been designed in order to
also interface the 3.3V logic signals. The VIN th+ and VIN th- thresholds of the input Schmitt trigger were set to 1.9V
and 1V (typical). Figure #1 shows the inner logic signal versus the input profile.
Figure 1: Input Thresholds Figure 2: In put Filter
A filter is then implemented just after the S chmitt trigger on every input pin. HIN & LIN feature a 270 ns filter (typical)
while FRST & EN have a 50 ns one. Its principle greatly improves the input/output pulse symmetry as well as helps
reject noise spikes. The behaviour of the input filters is presented in the Figure #2. The parameter tFILIN represents the
minimum pulse duration to pass the filter.
Logic Control Block
This block centralizes all the logic signals in order to: Generate the proper Outputs drives with minimum dead-time
insertion, prevent shoot-through sequences, blank premature triggering of the short-circuit comparator and reset the
FAULT flag. The enable pin (EN) switches off all outputs immediately in case of an ur gent system request. It actually
can be used to cycle the gate s. The figure #3 shows all the signals timing.
Figure 3: Input/Output Timing Diagram
AUIRS20302S
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The AUIRS20302S features an embedded dead-time circuitry. It inserts a minimum time period in which both the high
and low side switches are forced OFF. By this mean and for each leg, each power switch is fully off before the next one
turns on. This dead-time is automatically inserted by the AUIRS20302S including when the command sequence does
include a shorter DT. Sequences with larger dead-time are not affected by the driver. Figures #4 & 5 show the dead-
time principle and timing on the outputs. The dead-times are matched not only for each leg (high side / low side
matching) but also among the three legs.
Figure 4: Dead-time Principle Figure 5: Output Timing (dead-time)
Protection Blanking time & Fault Reset Sequence
The CAN and CAP pins are intended to interface a shunt. In case of over-current protection (CAN>CAP), the FLT pin
and all the gates are pulled down. There is a blanking time circuitry on the over-current protection. The comparator
output is ignored for (tblank) µS after each HINx rising edge. The fault reset is achieved by the following sequence: a)
force EN pin to Gnd and b) cycle the FRST pin for the recommended minimum time (tfrst). Then, pulling-up again the
EN pin resumes normal operation. Figure #6 shows the fault and output sequences while figure #7 emphasizes the reset
sequence.
Figure 6: Fault/Output after SC Figure 7: Fault Reset Sequence
Pre-regulated VPR voltage
The AUIRS20302S features a pr e-regulated supply in order to maintain reasonable gate voltages in all conditions. This
circuitry is composed of a VCO controlled charge pump, a comparator and a protective active clamp. Those three
blocks were specifically design ed in order to minimize their EMI contribution to the whole system. The MOSFET gate
is regulated at 15V. Depending on th e MOSFET gate thr eshold, V PR is then stabilized at ‘’ VCP – Vt ‘’ which usu ally
ends up between 12V and 13.5 V. A higher VPR voltage is achievable by using a logic level MOSFET. The gate
voltage and the charge pump output are protected by a 17V clamp. The figure #8 presents the block diagram of the pre-
regulator cir c uitry with the 100K resistor needed between the Gate and the Drain of the MOSFET.
AUIRS20302S
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Figure 8: Pre-regulator Block Diagram
During the power-up sequence, the gate is biased thanks to the 100k resistor connected to its drain. When Vbat exceeds
4V, the charge pump output is already close to the MOSFET gate threshold. At 6V, VCP is typically higher than 9V
(see VCP values – page 5 – Static Electrical Characteristics). So, during Vbat ramp-up, the MOSFET is first biased by
the resistor until the charge pump overcomes the gate voltage and turns it fully on. As Vbat keeps increasing, the
MOSFET remains fully on until the voltage closed loop enters the linear mode to control and s tabilize VCP at 15V.
Pre-regulator MOSFET drive
The stabilized VP R voltage sup plies the I.C and the bootstrap diodes thus the MOSFET power dissipation is quite low.
It can also supply the system components. In that case, the power MOSFET dissipation has to be evaluated carefully
and the implementation of an extra heat-sink considered. In some applications, it may be necessary to know at what
exact voltage the charge pump overcomes the resistive bias of the pre-regulator MOSFET. This vo ltage depends on the
total MOSEFT drain current (Iqpr + system consumption). For example, the system intelligence may include a regulator
whose voltage drop influences the minimum operation voltage. If we consider the voltage drop of a 5V regulator at
0.8V, what is the status of the pre-regulator MOSFET when Vbat passes 5,8V (already fully on or still in the source
follower mode)?
Figure #9 summarizes the procedure to evaluate the exact Vbat voltage at which the pre-regulator MOSFET is turned
fully on by the charge pump. It is a 4 steps procedure where ‘’ I load ‘’ represents the quiescent current of the I.C p lus
the system consumption (in the voltage range considered). Looking to the MOSFET characteristic at the specific ‘’ I
load ‘’ drain current point gives the corresponding Vgs value. The MOSFET will be fully on when the VCP pin
exceeds this Vgs value. The charge p ump characterization is then u sed to determine the exact VPR voltage at wh ich the
quantity ‘’V CP-VPR’’ exactly equals th e identified Vgs. Finally, from the VPR value, the corresponding VCP voltage
Ref
Charge
Pump
VCO
VCP
Vss
-
+
Active Clamp
VCP Voltage Control Loop
VPR
Vcc
+ Bat
System
Intelligence
VCP comparator
100k
1.1M
2.2M
AUIRS20302S
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is extracted again from the charge pump characterization. At this point of operation, the VCP voltage equals the Vbat
potential at which the MOSFET becomes fully on (no voltage drop across the biasing resistor in th is mode).
Figure 9: The 4 Step Procedure
PCB recommendations
The PCB is designed in order to minimize the gate drive wires, make the power topology up to 15A continuous capable
and have the shunt interface as short as possible. Also, ground star connection is located at the bottom of the shunt.
Figure 10: Component Face Layout Figure 11: Solder Face Layout
AUIRS20302S
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The following schematic is an example of the AUIRS20302S application. It is a 100W-24V BLDC motor drive for an
actuator. The power MOSFETs and the pre-regulator are designed in order to pass the 60V truck load dump condition.
The system intelligence is powered via a 5V regulator connected to the VPR pin.
Title
Size Docum ent N um ber Rev
Date: Sheet of
<Doc> <RevCode>
AUIRS20302SDemoboard
A3
1 1Thursday, May 06, 2010
0
D2
BAV21
C2
100n
/100V
C11
1n
C3
100n
D3
BAV21
Tp1
1
C4
100n
R1 100k
R2 100k
R3 100k
R4 100k
R5 100k
C5
2.2u
R6 100k
R7 100k
R8 1k
R9 6k8
R10
10k
R11
10
C6
100n
R12
10
R13
10
R14
4k7
R15
4k7
Tp2
1
C7
100n
R16
4k7 R17 1k
R18 1k
0
R19 1k
R20 1k
/63V
R21 1k
R22 1k
R23 1k
R24
10k
R25
10k
R26
10k R27
100k
R28 22k
Vbusp
R29
1k2
Tp3
1
R30 0
R31
100k
R32 0
R33
100k
R34 0
R35
100k
GND
R36 0
0
R37
100k
R38 0
R39
100k
R40 0
R41
100k
Tp4
1
R42 2k2
Vcc5V
Vcc5V
A
B
C
Tp5
1
PWM
0
Tp6
1
U
ComS
0
0
Tp7
1
Ld1
Tp8
1
Sensor
Vcc Hall
Hall A
Hall B
Hall C
Tp9
1
Tp10
1
Frequency 20Khz
Sensor
Gnd Hall
Tp11
1
Tp12
1
Tp13
1
V
M1
IRFS3607
W
Tp14
1
Tp15
1
on
1 2
Sw1
Tp16
1
CompPWM
Phase W
Phase V
Phase U
Vcc5V
Shunt
R43
Forward
Bt1
12
3
Vcc5V
ENABLE
LO1
LO2
External drive
LO3
C8 100n
M3
IRFS3607
0
U2
IRS20302S
EN
1
HIN1
2
HIN2
3
HIN3
4
LIN1
5
LIN2
6
LIN3
7
VSS
8
VCP
9
VPR
10
LO1
11
LO2
12
LO3
13
COM
14 nc 15
CAn 16
CAp 17
VS3 18
HO3 19
VB3 20
VS2 21
HO2 22
VB2 23
VS1 24
HO1 25
VB1 26
FLT 27
FRST 28
M4
IRFS3607
HO3
M5
IRFS3607
HO2
Bt2
1
23
0
LO2
M6
IRFS3607
LO3
Vcc5V
ComS
M7
IRFS3607
Vcc5V
24V to 60V
Power Supply
0
D4
SMCJ54A
1 2
HO1 U
V
U1 MC7805CD
IN
1OUT 3
GND
2
HO2
W
HO3
0
HO1
LO1
M2
IRFS3607
Masse Logic
/100V
C9 100n
logicCPLD
CPLD
A
B
C
P
D
F
Vss
LIw
LIv
LIu
Hlw
Hlv
Hlu
Vcc
/100V
J8P1
12
3
4
5
6
7
8
0
+
Cp1
470µF
C10100n
0
Modif.: R30; R32; R34; R36; R38; R40 =0
D1
BAV21
C1
470n
0
Figure 12: 100W – 24V BLDC Application Schematic
AUIRS20302S
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Figure 13: Component Implementation
AUIRS20302S
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Parameter Temperature Trends
Figures illustrated in this chapter provide i nformation on the experimental performance of the AUIRS20302S
HVIC. The line plott ed i n each f i gure i s generat ed from actual lab data. A large number of indi vidual samples
were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) with supply voltage of 15V in order to
generate the experimental curve. The line consists of three data points (one dat a poi nt at each of the tested
temperatures) that have been connected t ogether to illustrate the understood trend. The indi vidual data
points on the Typ. curve were det erm i ned by calculating the averaged experimental value of the parameter
(for a given temperature).
Figure 14. Turn-On Propagation Delay vs. Temperat ure
Figure 15. Turn-Off Propagation Delay v s. Tem perature
Figure 16. Turn-On Rise Time vs. Temperature
Figure 17. Turn-Off Fall Time vs. Temperature
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Figure 18. Input Filter Time vs. Temperature
Figure 19. Current Limit B l anking Ti m e vs. Temperature
Figure 20. Over Current Response Time vs. Tem perat ure
Figure 21. Over Current Shutdown Tim e vs. Temperature
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Figure 22. Dead Time vs. T em perat ure
Figure 23. Offset Leakage Current v s. T em perat ure
Figure 24. Quiescent VPR Current vs. Tem perature
Figure 25. Quiescent VBS Current vs. Temperature
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Figure 26. Output High Pul se Current vs. Temperature
Figure 27. Output Low Pul se Current vs. Temperature
Figure 28. Charge Pump Source Current vs. T em perat ure
VPR = 6V
Figure 29. Charge Pump Source Current vs. T em perat ure
VPR = 14V
Figure 30. Comparator Input High Current vs. Temperature
Figure 31. Comparator Input Low Current vs. Temperat ure
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Figure 32. VPR UV+ Going Threshold v s. T em perat ure
Figure 33. VPR UV- Going Threshold vs. Temperature
Figure 34. VBS UV+ Going Threshold vs. Temperature
Figure 35. VBS UV- Going Threshold vs. Temperat ure
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Figure 36. High Level Output V oltage vs. Temperature
Io = 20mA
Figure 37. Low Level Output V ol tage vs. Temperature
Io = 20mA
Figure 38. FLT Low Output V ol tage vs. Temperature
Figure 39. Charge Pump Output V ol tage vs. Temperature
VPR = 4V
Figure 40. Charge Pump Output Voltage vs. Temperature
VPR = 8V
Figure 41. Charge Pump Output V ol tage vs. Temperature
VPR = 14V
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Package Details:
AUIRS20302S
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Tape and Reel Information
AUIRS20302S
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Part Marking Inform ation
AUIRS20302S
IR logo
AYWW ?
Part number
Date code
Pin 1
Identifier
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
? XXXX
MARKING CODE
Lead Free Released
Non-Lead Free Released
?
P
Ordering Information
Base Part Number Package Type
Standard Pack
Complete Part Number
Form
Quantity
AUIRS20302S SOIC28W Tube/Bulk 25 AUIRS20302S
Tape and Reel 1000 AUIRS20302STR
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IMPORTANT NOTI CE
Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR)
reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products
and services at any time and to discontinue any product or services without notice. Part numbers designated with the
“AU” prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance
and process change notification. All products are sold subject to IR’s terms and conditions of sale supplied at the time
of order acknowledgment.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with
IR’s standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to
support this warranty. Except where mandated by government requirements, testing of all parameters of each product
is not necessarily performed.
IR assumes no liability for applications assistance or customer product design. Customers are responsible for their
products and applications using IR components. To minimize the risks with customer products and applications,
customers should provide adequate design and operating safeguards.
Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information
with alterations is an unfair and deceptive business practice. IR is not responsible or liable for such altered
documentation. Inform ation of third parties may be subject t o addi tional restrictions.
Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that product
or service voids all express and any implied warranties for the associated IR product or service and is an unfair and
deceptive business practice. IR is not responsible or liabl e for any such statements.
IR products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or in other applications intended to support or sustain life, or in any other application in which the failure
of the IR product could create a situation where personal injury or death may occur. Should Buyer purchase or use IR
products for any such unintended or unauthorized application, Buyer shall indemnify and hold International Rectifier
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that IR was negligent regarding the
design or manufacture of the product.
Only products certified as military grade by the Defense Logistics Agency (DLA) of the US Department of Defense, are
designed and manufactured to meet DLA military specifications required by certain military, aerospace or other
applications. Buyers acknowledge and agree that any use of IR products not certified by DLA as military-grade, in
applications requiring military grade products, is solely at the Buyer’s own risk and that they are solely responsible for
compliance with all legal and regulatory requirem ents in connection with such use.
IR products are neither designed nor intended for use in automotive applications or environments unless the specific
IR products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number including the
designation “AU”. Buyers acknowledge and agree that, if they use any non-designated products in automotive
applications, IR will not be responsible for any failure to meet such requirements.
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Revision History
Date
Comment
Nov 20th, 2010
DR2 format and revision (Preliminary)
March 14th 2011
Note 2 at page 5 modified (“UVPR is latched”) and moved under st el char tabl e.
August 31, 2011
Added AU qualified, Leadf ree, RoSH; revised Qualification level table; added tri-temp graphs;
modified part marking graph; revise Not i ce page to the latest version.
Sep 13th, 2011
Abs Max Rat: COM limits set to -5V..5V; Max Oper Junc temp=150^C; static El Char: Voffset min=-
33mV. Fig4 and Fig5 and Fig6 change.
Sep 14th, 2011
Added AU qualified, leadfree RoSH; removed preliminary; revised DT condition V P R=15V
May 2nd, 2014
Update ESD protection scheme on page 9, pi ns CAn and CA p
For technical support, please contact IR’s Technical Assistance Cent er
http://www.irf.com/technical-info/
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101 N. Sepulveda Blvd., El Segundo, California 90245
Tel: (310) 252-7105
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AUIRS20302STR