2010 Microchip Technology Inc. DS22250A-page 1
MCP4902/4912/4922
Features
• MCP4902: Dual 8-Bit Voltage Output DAC
• MCP4912: Dual 10-Bit Voltage Output DAC
• MCP4922: Dual 12-Bit Voltage Output DAC
• Rail-to-Rail Output
• SPI Interface with 20 MHz Clock Support
• Simultaneous Latching of the Dual DACs
with LDAC pin
• Fast Settling Time of 4.5 µs
• Selectable Unity or 2x Gain Output
• External Voltage Reference Inputs
• External Multiplier Mode
• 2.7V to 5.5V Single-Supply Operation
• Extended Temperature Range: -40°C to +125°C
Applications
• Set Point or Offset Trimming
• Precision Selectable Voltage Reference
• Motor Control Feedback Loop
• Digitally-Controlled Multiplier/Divider
• Calibration of Optical Communication Devices
Related Products(1)
Description
The MCP4902/4912/4922 devices are dual 8-bit,
10-bit, and 12-bit buffered voltage output
Digital-to-Analog Converters (DACs), respectively. The
devices operate from a single 2.7V to 5.5V supply with
SPI compatible Serial Peripheral Interface. The user
can configure the full-scale range of the device to be
VREF or 2 * VREF by setting the Gain Selection Option
bit (gain of 1 of 2).
The user can shut down both DAC channels by using
SHDN pin or shut down the DAC channel individually
by setting the Configuration register bits. In Shutdown
mode, most of the internal circuits in the shutdown
channel are turned off for power savings and the output
amplifier is configured to present a known high
resistance output load (500 ktypical.
The devices include double-buffered registers,
allowing synchronous updates of two DAC outputs,
using the LDAC pin. These devices also incorporate a
Power-on Reset (POR) circuit to ensure reliable power-
up.
The devices utilize a resistive string architecture, with
its inherent advantages of low DNL error and fast
settling time. These devices are specified over the
extended temperature range (+125°C).
The devices provide high accuracy and low noise
performance for consumer and industrial applications
where calibration or compensation of signals (such as
temperature, pressure and humidity) are required.
The MCP4902/4912/4922 devices are available in the
PDIP, SOIC and TSSOP packages.
Package Types
P/N DAC
Resolution
No. of
ChannelS
Voltage
Reference
(VREF)
MCP4801 8 1
Internal
(2.048V)
MCP4811 10 1
MCP4821 12 1
MCP4802 8 2
MCP4812 10 2
MCP4822 12 2
MCP4901 8 1
External
MCP4911 10 1
MCP4921 12 1
MCP4902 8 2
MCP4912 10 2
MCP4922 12 2
Note 1: The products listed here have similar AC/
DC performances.
MCP4902: 8-bit dual DAC
MCP4912: 10-bit dual DAC
MCP4922: 12-bit dual DAC
141
2
3
4
13
12
11
10
9
8
5
6
7
14-Pin PDIP, SOIC, TSSOP
VDD
NC
CS
SCK VREFB
NC
NC
SDI
LDAC
SHDN
VOUTB
VOUTA
VREFA
VSS
MCP49X2
8/10/12-Bit Dual Voltage Output Digital-to-Analog Converter
with SPI Interface
MCP4902/4912/4922
DS22250A-page 2 2010 Microchip Technology Inc.
Block Diagram
Op Amps
VDD
VSS
CS SDI SCK
Interface Logic
Input
Register A Register B
Input
DACA
Register Register
DACB
String
DACB
String
DACA
Power-on
Reset
VOUTA VOUTB
LDAC
Output
Gain
Logic
Gain
Logic
Output
Logic
SHDN
VREF A VREF B
Buffer Buffer
2010 Microchip Technology Inc. DS22250A-page 3
MCP4902/4912/4922
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD....................................................................... 6.5V
All inputs and outputs w.r.t .....VSS –0.3V to VDD+0.3V
Current at Input Pins ......................................... ±2 mA
Current at Supply Pins ....................................±50 mA
Current at Output Pins ....................................±25 mA
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied ..... -55°C to +125°C
ESD protection on all pins 4 kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ)................+150°C
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to
GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Power Requirements
Operating Voltage VDD 2.7 — 5.5 V
Operating CurrentInput Cur-
rent
IDD — 350 700 µA VDD = 5V
VDD = 3V
VREF input is unbuffered, all digital
inputs are grounded, all analog
outputs (VOUT) are unloaded.
Code = 000h.
— 250 500 µA
Hardware Shutdown Current ISHDN — 0.3 2 µA Power-on Reset circuit is turned
off
Software Shutdown Current ISHDN_SW — 3.3 6 µA Power-on Reset circuit stays on
Power-on-Reset Threshold VPOR —2.0 — V
DC Accuracy
MCP4902
Resolution n 8 — — Bits
INL Error INL -1 ±0.125 1 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4912
Resolution n 10 — — Bits
INL Error INL -3.5 ±0.5 3.5 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4922
Resolution n12 — — Bits
INL Error INL -12 ±2 12 LSb
DNL DNL -0.75 ±0.2 +0.75 LSb Note 1
Offset Error VOS — ±0.02 1 % of
FSR
Code = 0x000h
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.
MCP4902/4912/4922
DS22250A-page 4 2010 Microchip Technology Inc.
Offset Error Temperature
Coefficient
VOS/°C — 0.16 — ppm/°C -45°C to 25°C
— -0.44 — ppm/°C +25°C to 85°C
Gain Error gE— -0.10 1 % of
FSR
Code = 0xFFFh, not including off-
set error
Gain Error Temperature
Coefficient
G/°C — -3 — ppm/°C
Input Amplifier (VREF Input)
Input Range – Buffered
Mode
VREF 0.040 — VDD – 0.040 V Note 2
Code = 2048
VREF = 0.2V p-p, f = 100 Hz and
1kHz
Input Range – Unbuffered
Mode
VREF 0— V
DD V
Input Impedance RVREF —165 — kUnbuffered Mode
Input Capacitance –
Unbuffered Mode
CVREF —7 — pF
Multiplier Mode -3 dB
Bandwidth
fVREF —450 — kHzV
REF = 2.5V ±0.2Vp-p,
Unbuffered, G = 1x
fVREF —400 — kHzV
REF = 2.5V ±0.2 Vp-p,
Unbuffered, G = 2x
Multiplier Mode –
Total Harmonic Distortion
THDVREF —-73 — dBV
REF = 2.5V ±0.2Vp-p,
Frequency = 1 kHz
Output Amplifier
Output Swing VOUT — 0.01 to
VDD – 0.04
— V Accuracy is better than 1 LSb for
VOUT = 10 mV to (VDD – 40 mV)
Phase Margin m — 66 — degrees
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC —15 24 mA
Settling Time tsettling — 4.5 — µs Within 1/2 LSb of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — 10 — nV-s
Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry
(0111...1111 to 1000...0000)
Digital Feedthrough — 10 — nV-s
Analog Crosstalk — 10 — nV-s
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to
GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.
2010 Microchip Technology Inc. DS22250A-page 5
MCP4902/4912/4922
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to
GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Power Requirements
Operating Voltage VDD 2.7 — 5.5 V
Operating Current IDD — 400 — µA VREF input is unbuffered, all digi-
tal inputs are grounded, all analog
outputs (VOUT) are unloaded.
Code=000h
Hardware Shutdown
Current
ISHDN — 1.5 — µA POR circuit is turned-off
Software Shutdown Current ISHDN_SW — 5 — µA POR circuit stays turned-on
Power-On Reset threshold VPOR —1.85— V
DC Accuracy
MCP4902
Resolution n 8 — — Bits
INL Error INL ±0.25 LSb
DNL DNL ±0.2 LSb Note 1
MCP4912
Resolution n 10 — — Bits
INL Error INL ±1 LSb
DNL DNL ±0.2 LSb Note 1
MCP4922
Resolution n12 — — Bits
INL Error INL ±4 LSb
DNL DNL ±0.25 LSb Note 1
Offset Error VOS — ±0.02 — % of FSR Code 0x000h
Offset Error Temperature
Coefficient
VOS/°C — -5 — ppm/°C +25°C to +125°C
Gain Error gE— -0.10 — % of FSR Code = 0xFFFh, not including off-
set error
Gain Error Temperature
Coefficient
G/°C — -3 — ppm/°C
Input Amplifier (VREF Input)
Input Range – Buffered
Mode
VREF — 0.040 to
VDD – 0.040
—VNote 1
Code = 2048,
VREF = 0.2V p-p, f = 100 Hz and
1kHz
Input Range – Unbuffered
Mode
VREF 0—V
DD V
Input Impedance RVREF — 174 — kUnbuffered mode
Input Capacitance –
Unbuffered Mode
CVREF —7—pF
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.
MCP4902/4912/4922
DS22250A-page 6 2010 Microchip Technology Inc.
Multiplying Mode
-3 dB Bandwidth
fVREF — 450 — kHz VREF = 2.5V ±0.1 Vp-p,
Unbuffered, G = 1x
fVREF — 400 — kHz VREF = 2.5V ±0.1 Vp-p,
Unbuffered, G = 2x
Multiplying Mode – Total
Harmonic Distortion
THDVREF ———dBV
REF = 2.5V ±0.1Vp-p,
Frequency = 1 kHz
Output Amplifier
Output Swing VOUT — 0.01 to
VDD – 0.04
— V Accuracy is better than 1 LSb for
VOUT = 10 mV to (VDD – 40 mV)
Phase Margin m — 66 — degrees
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC —17—mA
Settling Time tsettling — 4.5 — µs Within 1/2 LSb of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC to DAC Crosstalk — 10 — nV-s
Major Code Transition
Glitch
— 45 — nV-s 1 LSb change around major carry
(0111...1111 to
1000...0000)
Digital Feedthrough — 10 — nV-s
Analog Crosstalk — 10 — nV-s
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to
GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.
2010 Microchip Technology Inc. DS22250A-page 7
MCP4902/4912/4922
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
FIGURE 1-1: SPI Input Timing Data.
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C.
Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Schmitt Trigger High-Level
Input Voltage (All digital input
pins)
VIH 0.7 VDD ——V
Schmitt Trigger Low-Level
Input Voltage
(All digital input pins)
VIL ——0.2V
DD V
Hysteresis of Schmitt Trigger
Inputs
VHYS —0.05V
DD —V
Input Leakage Current ILEAKAGE -1 — 1 A SHDN = LDAC = CS = SDI =
SCK + VREF = VDD or VSS
Digital Pin Capacitance
(All inputs/outputs)
CIN,
COUT
—10—pFV
DD = 5.0V, TA = +25°C,
fCLK = 1 MHz (Note 1)
Clock Frequency FCLK ——20MHzT
A = +25°C (Note 1)
Clock High Time tHI 15 — — ns Note 1
Clock Low Time tLO 15 — — ns Note 1
CS Fall to First Rising CLK
Edge
tCSSR 40 — — ns Applies only when CS falls with
CLK high. (Note 1)
Data Input Setup Time tSU 15 — — ns Note 1
Data Input Hold Time tHD 10 — — ns Note 1
SCK Rise to CS Rise Hold
Time
tCHS 15 — — ns Note 1
CS High Time tCSH 15 — — ns Note 1
LDAC Pulse Width tLD 100 — — ns Note 1
LDAC Setup Time tLS 40 — — ns Note 1
SCK Idle Time before CS Fall tIDLE 40 — — ns Note 1
Note 1: This parameter is ensured by design and not 100% tested.
CS
SCK
SI
LDAC
tCSSR
tHD
tSU
tLO
tCSH
tCHS
LSb in
MSb in
tIDLE
Mode 1,1
Mode 0,0
tHI
tLD
tLS
MCP4902/4912/4922
DS22250A-page 8 2010 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 14L-PDIP JA —70—°C/W
Thermal Resistance, 14L-SOIC JA —120—°C/W
Thermal Resistance, 14L-TSSOP JA —100—°C/W
Note 1: The MCP4902/4912/4922 devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the maximum junction temperature of
150°C.
2010 Microchip Technology Inc. DS22250A-page 9
MCP4902/4912/4922
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-1: DNL vs. Code (MCP4922).
FIGURE 2-2: DNL vs. Code and
Temperature (MCP4922).
FIGURE 2-3: DNL vs. Code and VREF
,
Gain = 1 (MCP4922).
FIGURE 2-4: Absolute DNL vs.
Temperature (MCP4922).
FIGURE 2-5: Absolute DNL vs. Voltage
Reference (MCP4922).
FIGURE 2-6: INL vs. Code and
Temperature (MCP4922).
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 1024 2048 3072 4096
Code (Decimal)
DNL (LSB)
-0.2
-0.1
0
0.1
0.2
0 1024 2048 3072 4096
Code (Decimal)
DNL (LSB)
125C 85C 25C
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0 1024 2048 3072 4096
Code (Decimal)
DNL (LSB)
1 2 3 4 5.5
0.075
0.0752
0.0754
0.0756
0.0758
0.076
0.0762
0.0764
0.0766
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Absolute DNL (LSB)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
12345
Voltage Reference (V)
Absolute DNL (LSB)
-5
-4
-3
-2
-1
0
1
2
3
4
5
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
125C 85 25
Ambient Temperature
MCP4902/4912/4922
DS22250A-page 10 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-7: Absolute INL vs.
Temperature (MCP4922).
FIGURE 2-8: Absolute INL vs. VREF
(MCP4922).
FIGURE 2-9: INL vs. Code and VREF
(MCP4922).
FIGURE 2-10: INL vs. Code (MCP4922).
FIGURE 2-11: DNL vs. Code and
Temperature (MCP4912).
FIGURE 2-12: INL vs. Code and
Temperature (MCP4912).
0
0.5
1
1.5
2
2.5
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Absolute INL (LSB)
0
0.5
1
1.5
2
2.5
3
12345
Voltage Reference (V)
Absolute INL (LSB)
-4
-3
-2
-1
0
1
2
3
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
12345.5
VREF
Note: Single device graph (Figure 2-10) for
illustration of 64 code effect.
-6
-4
-2
0
2
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
-0.2
-0.1
0
0.1
0.2
0 128 256 384 512 640 768 896 1024
Code
DNL (LSB)
Temp = - 40oC to +125oC
-3.5
-2.5
-1.5
-0.5
0.5
1.5
0 128 256 384 512 640 768 896 1024
Code
INL (LSB)
125oC
85oC
25
oC
- 40oC
2010 Microchip Technology Inc. DS22250A-page 11
MCP4902/4912/4922
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-13: DNL vs. Code and
Temperature (MCP4902).
FIGURE 2-14: INL vs. Code and
Temperature (MCP4902).
FIGURE 2-15: IDD vs. Temperature and
VDD.
FIGURE 2-16: IDD Histogram (VDD = 2.7V).
FIGURE 2-17: IDD Histogram (VDD =
5.0V).
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0 32 64 96 128 160 192 224 256
Code
DNL (LSB)
Temp = -40oC to +125oC
-0.5
-0.25
0
0.25
0.5
0 326496128160192224256
Code
INL (LSB)
125
oC
-40oC to +85oC
200
250
300
350
400
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
IDD (µA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0
2
4
6
8
10
12
14
16
18
20
215
225
235
245
255
265
275
285
295
305
315
325
IDD (μA)
Occurrence
0
2
4
6
8
10
12
14
16
250
265
280
295
310
325
340
355
370
385
400
415
IDD (μA)
Occurrence
MCP4902/4912/4922
DS22250A-page 12 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-18: Hardware Shutdown Current
vs. Ambient Temperature and VDD.
FIGURE 2-19: Software Shutdown Current
vs. Ambient Temperature and VDD.
FIGURE 2-20: Offset Error vs. Ambient
Temperature and VDD.
FIGURE 2-21: Gain Error vs. Ambient
Temperature and VDD.
FIGURE 2-22: VIN High Threshold vs
Ambient Temperature and VDD.
FIGURE 2-23: VIN Low Threshold vs
Ambient Temperature and VDD.
0
0.5
1
1.5
2
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
ISHDN (μA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0
1
2
3
4
5
6
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
ISHDN_SW (μA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Offset Error (%)
VDD
5.5V
4.0
V
5.0V
3.0V
2.7V
-0.16
-0.14
-0.12
-0.1
-0.08
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Gain Error (%)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
1
1.5
2
2.5
3
3.5
4
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VIN Hi Threshold (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VIN Low Threshold (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
2010 Microchip Technology Inc. DS22250A-page 13
MCP4902/4912/4922
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-24: Input Hysteresis vs. Ambient
Temperature and VDD.
FIGURE 2-25: VREF Input Impedance vs.
Ambient Temperature and VDD.
FIGURE 2-26: VOUT High Limit vs. Ambient
Temperature and VDD.
FIGURE 2-27: VOUT Low Limit vs. Ambient
Temperature and VDD.
FIGURE 2-28: IOUT High Short vs. Ambient
Temperature and VDD.
FIGURE 2-29: IOUT vs VOUT
. Gain = 1x.
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VIN_SPI Hysteresis (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
155
160
165
170
175
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VREF_UNBUFFERED Impedance
(kOhm)
VDD
5.5V -
2.7V
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VOUT_HI Limit (VDD-Y)(V)
VDD
5.5V
4.0
V
5.0V
3.0V
2.7V
0.0015
0.002
0.0025
0.003
0.0035
0.004
0.0045
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VOUT_LOW Limit (Y-AVSS)(V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
10
11
12
13
14
15
16
17
18
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
IOUT_HI_SHORTED (mA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0246810121416
IOUT (mA)
VOUT (V)
VREF=4.0
Output Shorted to VSS
Output Shorted to VDD
MCP4902/4912/4922
DS22250A-page 14 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-30: VOUT Rise Time.
FIGURE 2-31: VOUT Fall Time.
FIGURE 2-32: VOUT Rise Time.
FIGURE 2-33: VOUT Rise Time.
FIGURE 2-34: VOUT Rise Time Exit
Shutdown.
FIGURE 2-35: PSRR vs. Frequency.
VOUT
SCK
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
Time (1 µs/div)
VOUT
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Ripple Rejection (dB)
Frequency (Hz)
2010 Microchip Technology Inc. DS22250A-page 15
MCP4902/4912/4922
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.50V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-36: Multiplier Mode Bandwidth.
FIGURE 2-37: -3 db Bandwidth vs. Worst
Codes.
FIGURE 2-38: Phase Shift.
-12
-10
-8
-6
-4
-2
0
100 1,000
Frequency (kHz)
Attenuation (dB)
D = 160
D = 416
D = 672
D = 928
D = 1184
D = 1440
D = 1696
D = 1952
D = 2208
D = 2464
D = 2720
D = 2976
D = 3232
D = 3488
D = 3744
Note:
V
REF
Dn • G
4096
( )
()
V
OUT
Attenuation (dB) = 20 log - 20 log
400
420
440
460
480
500
520
540
560
580
600
160
416
672
928
1184
1440
1696
1952
2208
2464
2720
2976
3232
3488
3744
Worst Case Codes (decimal)
Bandwidth (kHz)
G = 1
G = 2
-180
-135
-90
-45
0
100 1,000
Frequency (kHz)
qVREF – q
VOUT
D = 160
D = 416
D = 672
D = 928
D = 1184
D = 1440
D = 1696
D = 1952
D = 2208
D = 2464
D = 2720
D = 2976
D = 3232
D = 3488
D = 3744
MCP4902/4912/4922
DS22250A-page 16 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22250A-page 17
MCP4902/4912/4922
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3 -1 .
TABLE 3-1: PIN FUNCTION TABLE
3.1 Supply Voltage Pins (VDD, VSS)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS and can range from
2.7V to 5.5V. The power supply at the VDD pin should
be as clean as possible for a good DAC performance.
It is recommended to use an appropriate bypass
capacitor of about 0.1 µF (ceramic) to ground. An
additional 10 µF capacitor (tantalum) in parallel is also
recommended to further attenuate high frequency
noise present in application boards.
VSS is the analog ground pin and the current return path
of the device. The user must connect the VSS pin to a
ground plane through a low-impedance connection. If
an analog ground path is available in the application
Printed Circuit Board (PCB), it is highly recommended
that the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
3.2 Chip Select (CS)
CS is the Chip Select input, which requires an active
low signal to enable serial clock and data functions.
3.3 Serial Clock Input (SCK)
SCK is the SPI compatible serial clock input pin.
3.4 Serial Data Input (SDI)
SDI is the SPI compatible serial data input pin.
3.5 Latch DAC Input (LDAC)
LDAC (latch DAC synchronization input) pin is used to
transfer the input latch registers to their corresponding
DAC registers (output latches, VOUT). When this pin is
low, both VOUTA and VOUTB are updated at the same
time with their input register contents. This pin can be
tied to low (VSS) if the VOUT update is desired at the
rising edge of the CS pin. This pin can be driven by an
external control device such as an MCU I/O pin.
3.6 Hardware Shutdown Input (SHDN)
SHDN is the hardware shutdown input pin. When this
pin is low, both DAC channels are shut down. DAC
output is not available during the shutdown.
3.7 Analog Outputs (VOUTA, VOUTB)
VOUTA is the DAC A output pin, and VOUTB is the DAC
B output pin. Each output has its own output amplifier.
The DAC output amplifier of each channel can drive the
output pin with a range of VSS to VDD.
3.8 Voltage Reference Inputs
(VREFA, VREFB)
VREFA is the voltage reference input for DAC channel
A, and VREFB is the reference input for DAC channel B.
The reference on these pins is utilized to set the
reference voltage on the string DAC. The input signal
can range from VSS to VDD. These pins can be tied to
VDD.
Pin No. Symbol Function
1V
DD Supply Voltage Input (2.7V to 5.5V)
2 NC No Connection
3CS
Chip Select Input
4 SCK Serial Clock Input
5 SDI Serial Data Input
6 NC No Connection
7 NC No Connection
8LDAC
Synchronization Input. This pin is used to transfer DAC settings (Input Registers)
to the output registers (VOUT)
9SHDN
Hardware Shutdown Input
10 VOUTB DACB Output
11 VREFB DACB Reference Voltage Input (VSS to VDD)
12 VSS Ground reference point for all circuitry on the device
13 VREFA DACA Reference Voltage Input (VSS to VDD)
14 VOUTA DACA Output
MCP4902/4912/4922
DS22250A-page 18 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22250A-page 19
MCP4902/4912/4922
4.0 GENERAL OVERVIEW
The MCP4902, MCP4912 and MCP4922 are dual
voltage-output 8-bit, 10-bit and 12-bit DAC devices,
respectively. These devices include input amplifiers,
rail-to-rail output amplifiers, reference buffers for
external voltage reference, shutdown and
reset-management circuitry. The devices use an SPI
serial communication interface and operate with a
single supply voltage from 2.7V to 5.5V.
The DAC input coding of these devices is straight
binary. Equation 4-1 shows the DAC analog output
voltage calculation.
EQUATION 4-1: ANALOG OUTPUT
VOLTAGE (VOUT)
The ideal output range of each device is:
• MCP4902 (n = 8)
(a) 0 V to 255/256 * VREF when gain setting = 1x.
(b) 0 V to 255/256 * 2 * VREF when gain setting = 2x.
• MCP4912 (n = 10)
(a) 0 V to 1023/1024 * VREF when gain setting = 1x.
(b) 0 V to 1023/1024 * 2 * VREF when gain setting = 2x.
• MCP4922 (n = 12)
(a) 0 V to 4095/4096 * VREF when Gain setting = 1x.
(b) 0 V to 4095/4096 * 2 * VREF when gain setting = 2x.
1 LSb is the ideal voltage difference between two
successive codes. Table 4-1 illustrates the LSb
calculation of each device.
4.1 DC Accuracy
4.1.1 INL ACCURACY
Integral Non-Linearity (INL) error is the maximum
deviation between an actual code transition point and
its corresponding ideal transition point, after offset and
gain errors have been removed. The two end points
(from 0x000 and 0xFFF) method is used for the calcu-
lation. Figure 4-1 shows the details.
A positive INL error represents transition(s) later than
ideal. A negative INL error represents transition(s) ear-
lier than ideal.
FIGURE 4-1: Example for INL Error.
4.1.2 DNL ACCURACY
A Differential Non-Linearity (DNL) error is the measure
of variations in code widths from the ideal code width.
A DNL error of zero indicates that every code is exactly
1LSb wide.
Note: See the output swing voltage specification
in Section 1.0 “Electrical Characteris-
tics”.
VOUT
VREF Dn
2n
-------------------------------G=
Where:
VREF =EXternal voltage reference
Dn= DAC input code
G=
=
=
Gain Selection
2 for <GA> bit = 0
1 for <GA> bit = 1
n=
=
=
=
DAC Resolution
8 for MCP4902
10 for MCP4912
12 for MCP4922
TABLE 4-1: LSb OF EACH DEVICE
Device Gain
Selection LSb Size
MCP4902
(n = 8)
1x VREF/256
2x (2* VREF)/256
MCP4912
(n = 10)
1x VREF/1024
2x (2* VREF)/1024
MCP4922
(n = 12)
1x VREF/4096
2x (2* VREF)/4096
where VREF is the external voltage reference.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
INL < 0
Ideal Transfer
Function
INL < 0
DAC Output
MCP4902/4912/4922
DS22250A-page 20 2010 Microchip Technology Inc.
FIGURE 4-2: Example for DNL Accuracy.
4.1.3 OFFSET ERROR
An offset error is the deviation from zero voltage output
when the digital input code is zero.
4.1.4 GAIN ERROR
A gain error is the deviation from the ideal output,
VREF– 1 LSb, excluding the effects of offset error.
4.2 Circuit Descriptions
4.2.1 OUTPUT AMPLIFIERS
The DAC’s outputs are buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
offset voltage and low noise. The output stage enables
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for the analog output voltage range
and load conditions.
In addition to resistive load driving capability, the
amplifier will also drive high capacitive loads without
oscillation. The amplifier’s strong outputs allow VOUT to
be used as a programmable voltage reference in a
system.
Selecting a gain of 2 reduces the bandwidth of the
amplifier in Multiplying mode. Refer to Section 1.0
“Electrical Characteristics” for the Multiplying mode
bandwidth for given load conditions.
4.2.1.1 Programmable Gain Block
The rail-to-rail output amplifier has configurable gain,
allowing optimal full-scale outputs for different voltage
reference inputs. The output amplifier gain has two
selections, a gain of 1x (<GA> = 1) or a gain of 2x
(<GA> = 0).
The default value is a gain of 2 (<GA> = 0).
4.2.2 VOLTAGE REFERENCE
AMPLIFIERS
The input buffer amplifiers for the MCP4902/4912/4922
devices provide low offset voltage and low noise. A
Configuration bit for each DAC allows the VREF input to
bypass the VREF input buffer amplifiers, achieving a
Buffered or Unbuffered mode. Buffered mode provides
a very high input impedance, with only minor limitations
on the input range and frequency response.
Unbuffered (<BUF> = 0) is the default configuration.
Unbuffered mode provides a wide input range (0V to
VDD), with a typical input impedance of 165 k with
7pF.
4.2.3 POWER-ON RESET CIRCUIT
The internal Power-on Reset (POR) circuit monitors the
power supply voltage (VDD) during the device
operation. The circuit also ensures that the DACs
power-up with high output impedance (<SHDN> = 0,
typically 500 k. The devices will continue to have a
high-impedance output until a valid write command is
performed to either of the DAC registers and the LDAC
pin meets the input low threshold.
If the power supply voltage is less than the POR
threshold (VPOR = 2.0V, typical), the DACs will be held
in their Reset state. The DACs will remain in that state
until VDD > VPOR and a subsequent write command is
received.
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the VDD pin, can
provide additional transient immunity.
FIGURE 4-3: Typical Transient Response.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
transfer
function
Ideal transfer
function
Narrow code, < 1 LSb
DAC Output
Wide code, > 1 LSb
Transients above the
Transients below the
5V
Time
Supply Voltages
Transient Duration
V
POR
V
DD
- V
POR
TA =
Transient Duration (µs)
10
8
6
4
2
012345
V
DD
– V
POR
(V)
2010 Microchip Technology Inc. DS22250A-page 21
MCP4902/4912/4922
4.2.4 SHUTDOWN MODE
The user can shut down each DAC channel selectively
by using a software command or shut down all chan-
nels by using the SHDN pin. During Shutdown mode,
most of the internal circuits in the channel that was shut
down are turned off for power savings. The serial inter-
face remains active, thus allowing a write command to
bring the device out of the Shutdown mode. There will
be no analog output at the channel that was shut down
and the VOUT pin is internally switched to a known
resistive load (500 ktypical. Figure 4-4 shows the
analog output stage during the Shutdown mode.
The condition of the Power-on Reset circuit during the
shutdown is as follows:
a) Turned-off, if the shutdown occurred by the
SHDN pin;
b) On, if the shutdown occurred by the software.
The device will remain in Shutdown mode until the
SHDN pin is brought to high or a write command with
<SHDN> bit = 1 is latched into the device. When a DAC
is changed from Shutdown to Active mode, the output
settling time takes less than 10 µs, but more than the
standard active mode settling time (4.5 µs).
FIGURE 4-4: Output Stage for Shutdown
Mode.
500 k
Power-Down
Control Circuit
Resistive
Load
VOUT
Op
Amp
Resistive String DAC
MCP4902/4912/4922
DS22250A-page 22 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22250A-page 23
MCP4902/4912/4922
5.0 SERIAL INTERFACE
5.1 Overview
The MCP4902/4912/4922 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, which is available on many microcontrollers
and supports Mode 0,0 and Mode 1,1. Commands and
data are sent to the device via the SDI pin, with data
being clocked-in on the rising edge of SCK. The
communications are unidirectional, thus the data
cannot be read out of the MCP4902/4912/4922. The
CS pin must be held low for the duration of a write
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches.
Register 5-1 to Register 5-3 detail the input register
that is used to configure and load the DACA and DACB
registers for each device. Figure 5-1 to Figure 5-3
show the write command for each device.
Refer to Figure 1-1 and SPI Timing Specifications
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
5.2 Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the selected DAC’s input registers. The
MCP4902/4912/4922 utilizes a double-buffered latch
structure to allow both DACA’s and DACB’s outputs to
be synchronized with the LDAC pin, if desired. Upon
the LDAC pin achieving a low state, the values held in
the DAC’s input registers are transferred into the DAC’s
output registers. The outputs will transition to the value
and held in the DACX register.
All writes to the MCP4902/4912/4922 are 16-bit words.
Any clocks past the 16th clock will be ignored. The
Most Significant 4 bits are Configuration bits. The
remaining 12 bits are data bits. No data can be
transferred into the device with CS high. This transfer
will only occur if 16 clocks have been transferred into
the device. If the rising edge of CS occurs prior to that,
shifting of data into the input registers will be aborted.
MCP4902/4912/4922
DS22250A-page 24 2010 Microchip Technology Inc.
REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4922 (12-BIT DAC)
REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4912 (10-BIT DAC)
REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4902 (8-BIT DAC)
Where:
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
A/B BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 0
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
A/B BUF GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x
bit 15 bit 0
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
A/B BUF GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 xxxx
bit 15 bit 0
bit 15 A/B: DACA or DACB Selection bit
1 = Write to DACB
0 = Write to DACA
bit 14 BUF: VREF Input Buffer Control bit
1 = Buffered
0 = Unbuffered
bit 13 GA: Output Gain Selection bit
1 =1x (V
OUT = VREF * D/4096)
0 =2x (V
OUT = 2 * VREF * D/4096)
bit 12 SHDN: Output Shutdown Control bit
1 = Active mode operation. VOUT is available.
0 = Shutdown the selected DAC channel. Analog output is not available at the channel that was shut down.
VOUT pin is connected to 500 ktypical)
bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored.
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
2010 Microchip Technology Inc. DS22250A-page 25
MCP4902/4912/4922
FIGURE 5-1: Write Command for MCP4922 (12-bit DAC).
FIGURE 5-2: Write Command for MCP4912 (10-bit DAC).
FIGURE 5-3: Write Command for MCP4902 (8-bit DAC).
SDI
SCK
CS
021
A/B GA SHDN D11 D10
config bits 12 data bits
LDAC
3 4
D9
567
D8 D7 D6
8 9 10 12
D5 D4 D3 D2 D1 D0
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
BUF
SDI
SCK
CS
021
A/B GA SHDN D9 D8
config bits 12 data bits
LDAC
3 4
D7
5 6 7
D6 D5 D4
8910 12
D3 D2 D1 D0 X X
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
BUF
Note: X = “don’t care” bits
SDI
SCK
CS
021
A/B GA SHDN
config bits 12 data bits
LDAC
3 4 5 6 7
X
D7 D6
8910 12
D5 D4 D3 D2 D1 D0
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
XX
X
BUF
Note: X = “don’t care” bits
MCP4902/4912/4922
DS22250A-page 26 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22250A-page 27
MCP4902/4912/4922
6.0 TYPICAL APPLICATIONS
The MCP4902/4912/4922 family of devices are gen-
eral purpose DACs intended to be used in applications
where a precision with low-power and moderate
bandwidth is required.
Applications generally suited for the devices are:
• Set Point or Offset Trimming
• Sensor Calibration
• Digitally-Controlled Multiplier/Divider
• Portable Instrumentation (Battery Powered)
• Motor Control Feedback Loop
6.1 Digital Interface
The MCP4902/4912/4922 utilizes a 3-wire synchro-
nous serial protocol to transfer the DAC’s setup and
output values from the digital source. The serial proto-
col can be interfaced to SPI or Microwire peripherals
that is common on many microcontroller units (MCUs),
including Microchip’s PIC® MCUs and dsPIC® DSCs.
In addition to the three serial connections (CS, SCK
and SDI), the LDAC signal synchronizes the two DAC
outputs. By bringing down the LDAC pin to “low”, all
DAC input codes and settings in the two DAC input
registers are latched into their DAC output registers at
the same time. Therefore, both DACA and DACB
outputs are updated at the same time. Figure 6-1
shows an example of the pin connections. Note that the
LDAC pin can be tied low (VSS) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16-clock transmission has been received and CS pin
has been raised.
6.2 Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise. The noise can be
induced onto the power supply’s traces from various
events such as digital switching or as a result of
changes on the DAC’s output. The bypass capacitor
helps to minimize the effect of these noise sources.
Figure 6-1 illustrates an appropriate bypass strategy. In
this example, two bypass capacitors are used in
parallel: (a) 0.1 µF (ceramic) and (b) 10 µF (tantalum).
These capacitors should be placed as close to the
device power pin (VDD) as possible (within 4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 6-1: Typical Connection
Diagram.
6.3 Layout Considerations
Inductively-coupled AC transients and digital switching
noises can degrade the input and output signal
integrity, and potentially reduce the device perfor-
mance. Careful board layout will minimize these effects
and increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs and
isolated outputs with proper decoupling, is critical for
the best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
VDD
VDD VDD
AVSS
AVSS VSS
VREFA
VOUTA
VREFB
VOUTB
PIC® Microcontroller
VREFA
VOUTA
VREFB
VOUTB
SDI
SDI
CS1
SDO
SCK
LDAC
CS0
C1 C1 C2
C2
MCP49x2
MCP49x2
C1
C1 = 10 µF
C2 = 0.1 µF
MCP4902/4912/4922
DS22250A-page 28 2010 Microchip Technology Inc.
6.4 Single-Supply Operation
The MCP4902/4912/4922 family of devices are rail-to-
rail voltage output DAC devices designed to operate
with a VDD range of 2.7V to 5.5V. Its output amplifier is
robust enough to drive small-signal loads directly.
Therefore, it does not require any external output buffer
for most applications.
6.4.1 DC SET POINT OR CALIBRATION
A common application for the DAC devices is
digitally-controlled set points and/or calibration of
variable parameters, such as sensor offset or slope.
For example, the MCP4922 provides 4096 output
steps. If the external voltage reference (VREF) is
4.096V, the LSb size is 1 mV. If a smaller output step
size is desired, a lower external voltage reference is
needed.
6.4.1.1 Decreasing Output Step Size
If the application is calibrating the bias voltage of a
diode or transistor, a bias voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common methods to achieve a 0.8V range is to either
reduce VREF to 0.82V or use a voltage divider on the
DAC’s output.
Using a VREF is an option if the VREF is available with
the desired output voltage range. However,
occasionally, when using a low-voltage VREF
, the noise
floor causes SNR error that is intolerable. Using a
voltage divider method is another option and provides
some advantages when VREF needs to be very low or
when the desired output voltage is not available. In this
case, a larger value VREF is used while two resistors
scale the output range down to the precise desired
level.
Example 6-1 illustrates this concept. Note that the
bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the
environment.
EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION
VDD
SPI
3-wire
VTRIP
R1
R20.1 uF
Comparator
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUT VREF GDn
2N
------
=
VCC+
VCC–
VOUT
Vtrip VOUT
R2
R1R2
+
--------------------
=
VDD
RSENSE
DAC
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
VREF VO
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
2010 Microchip Technology Inc. DS22250A-page 29
MCP4902/4912/4922
6.4.1.2 Building a “Window” DAC
When calibrating a set point or threshold of a sensor,
typically only a small portion of the DAC output range is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
If the threshold is not near VREF or VSS, then creating
a “window” around the threshold has several
advantages. One simple method to create this
“window” is to use a voltage divider network with a
pull-up and pull-down resistor. Example 6-2 and
Example 6-4 illustrate this concept.
EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC
VREF VDD
SPI
3
Vtrip
R1
R20.1 µF
Comparator
R3
VCC-
VCC+ VCC+
VCC-
VOUT
R23
R2R3
R2R3
+
------------------=
V23
VCC+ R2
VCC- R3
+
R2R3
+
-----------------------------------------------------=
Vtrip
VOUTR23 V23 R1
+
R2R23
+
--------------------------------------------=
R1
R23
V23
VOUT VO
Thevenin
Equivalent
Rsense
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUT VREF GDn
2N
------
=
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
DAC
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
MCP4902/4912/4922
DS22250A-page 30 2010 Microchip Technology Inc.
6.5 Bipolar Operation
Bipolar operation is achievable using the MCP4902/
4912/4922 family of devices by using an external
operational amplifier (op amp). This configuration is
desirable due to the wide variety and availability of op
amps. This allows a general purpose DAC, with its cost
and availability advantages, to meet almost any
desired output voltage range, power and noise
performance.
Example 6-3 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC’s output to a selected
offset. Note that R4 can be tied to VREF instead of VSS,
if a higher offset is desired. Also note that a pull-up to
VREF could be used instead of R4, if a higher offset is
desired.
EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE
6.5.1 DESIGN EXAMPLE: DESIGN A BIPOLAR
DAC USING EXAMPLE 6-3 WITH 12-BIT
MCP4922 OR MCP4921
An output step magnitude of 1 mV with an output range
of ±2.05V is desired for a particular application.
The following steps show the details:
Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V.
Step 2: Calculate the resolution needed:
4.1V/1 mV = 4100
Since 212 = 4096, 12-bit resolution is
desired.
Step 3:The amplifier gain (R2/R1), multiplied by VREF
,
must be equal to the desired minimum output
to achieve bipolar operation. Since any gain
can be realized by choosing resistor values
(R1+R2), the VREF source needs to be deter-
mined first. If a VREF of 4.1V is used, solve for
the gain by setting the DAC to 0, knowing that
the output needs to be -2.05V. The equation
can be simplified to:
Step 4: Next, solve for R3 and R4 by setting the DAC to
4096, knowing that the output needs to be
+2.05V.
VREF
VREF
VDD
SPI
3
VOUT R3
R4
2
R1
VIN+
0.1 µF
VCC+
VCC–
VO
VIN+
VOUTR4
R3R4
+
--------------------=
VOVIN+ 1R2
R1
------+
VDD
R2
R1
------
–=
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUT VREF GDn
2N
------
=
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
DAC
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
R2
–
R1
---------2.05–
VREF
------------- 2.05–
4.1
-------------==
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
R2
R1
------1
2
---=
R4
R3R4
+
-----------------------
2.05V0.5VREF
+
1.5VREF
----------------------------------------- 2
3
---
==
If R4 = 20 k, then R3 = 10 k
2010 Microchip Technology Inc. DS22250A-page 31
MCP4902/4912/4922
6.6 Selectable Gain and Offset Bipolar
Voltage Output Using a Dual DAC
In some applications, precision digital control of the
output range is desirable. Example 6-4 illustrates how
to use the MCP4902/4912/4922 to achieve this in a
bipolar or single-supply application.
This circuit is typically used in Multiplier mode and is
ideal for linearizing a sensor whose slope and offset
varies. Refer to Section 6.9 “Using Multiplier Mode”
for more information on Multiplier mode.
The equation to design a bipolar “window” DAC would
be utilized if R3, R4 and R5 are populated.
EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET
VREFA
DACB
VDD
R3
R4
R2
DACA
VDD
R1
DACA (Gain Adjust)
DACB (Offset Adjust)
SPI
3
R5
VCC+
Thevenin
Bipolar “Window” DAC using R4 and R5
0.1uF
VCC–
VCC+
VCC–
VOUTB VREFBGB
DB
2N
-------=
VOUTA
VOUTB
VOUTA VREFAGA
DA
2N
-------=
VIN+
VOUTBR4VCC-R3
+
R3R4
+
------------------------------------------------=
VOVIN+ 1R2
R1
------
+
VOUTA
R2
R1
------
–=
Equivalent V45
VCC+ R4VCC- R5
+
R4R5
+
--------------------------------------------
=R45
R4R5
R4R5
+
------------------
=
VIN+
VOUTBR45 V45R3
+
R3R45
+
-----------------------------------------------=VOVIN+ 1R2
R1
------+
VOUTA
R2
R1
------
–=
Offset Adjust Gain Adjust
Offset Adjust Gain Adjust
VREFB
GX = Gain selection (1x or 2x)
DA, DB = Digital value of DAC (0-255) for MCP4902
= Digital value of DAC (0-1023) for MCP4912
= Digital value of DAC (0-4095) for MCP4922
N = DAC Bit Resolution
VO
Dual Output DAC:
MCP4902
MCP4912
MCP4922
MCP4902/4912/4922
DS22250A-page 32 2010 Microchip Technology Inc.
6.7 Designing a Double-Precision
DAC Using a Dual DAC
Example 6-5 illustrates how to design a single-supply
voltage output capable of up to 24-bit resolution from a
dual 12-bit DAC. This design is simply a voltage divider
with a buffered output.
As an example, if a application similar to the one
developed in Section 6.5.1 “Design Example: Design
a Bipolar DAC Using Example 6-3 with 12-bit
MCP4922 or MCP4921” required a resolution of 1 µV
instead of 1 mV and a range of 0V to 4.1V, then 12-bit
resolution would not be adequate.
Step 1: Calculate the resolution needed:
4.1V/1 µV = 4.1x106. Since 222 = 4.2x106, 22-
bit resolution is desired. Since DNL = ±0.75
LSb, this design can be attempted with the
MCP4922.
Step 2: Since DACB’s VOUTB has a resolution of 1 mV,
its output only needs to be “pulled” 1/1000 to
meet the 1 µV target. Dividing VOUTA by 1000
would allow the application to compensate for
DACB’s DNL error.
Step 3: If R2 is 100, then R1 needs to be 100 k.
Step 4:The resulting transfer function is not perfectly
linear, as shown in the equation of
Example 6-5.
EXAMPLE 6-5: SIMPLE, DOUBLE-PRECISION DAC WITH MCP4922
VREF
MCP4922
VDD
R2
MCP4922
VDD
R1
DACA (Fine Adjust)
DACB (Course Adjust)
SPI
3
R1 >> R2
VO
VOUTAR2VOUTBR1
+
R1R2
+
-----------------------------------------------------=
G = Gain selection (1x or 2x)
D = Digital value of DAC (0- 4096)
0.1 µF
VCC+
VCC–
VOUTA VREFAGA
DA
212
-------=
VOUTB VREFBGB
DB
212
-------=
VOUTA
VOUTB
VO
2010 Microchip Technology Inc. DS22250A-page 33
MCP4902/4912/4922
6.8 Building Programmable Current
Source
Example 6-6 shows an example for building a
programmable current source using a voltage follower.
The current sensor (sensor resistor) is used to convert
the DAC voltage output into a digitally-selectable
current source.
Adding the resistor network from Example 6-2 would
be advantageous in this application. The smaller Rsense
is, the less power dissipated across it. However, this
also reduces the resolution that the current can be
controlled with. The voltage divider, or “window”, DAC
configuration would allow the range to be reduced, thus
increasing resolution around the range of interest.
When working with very small sensor voltages, plan on
eliminating the amplifier’s offset error by storing the
DAC’s setting under known sensor conditions.
EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE
DAC
RSENSE
Ib
Load
IL
VDD
SPI
3-wire
VCC+
VCC–
VOUT
IL
VOUT
Rsense
---------------
1+
------------=
Ib
IL
----=
G = Gain select (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUT VREF GDn
2N
------
=
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
Common-Emitter Current Gainwhere
VREF
VDD or VREF
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
MCP4902/4912/4922
DS22250A-page 34 2010 Microchip Technology Inc.
6.9 Using Multiplier Mode
The MCP4902/4912/4922 family of devices use exter-
nal reference, and these devices are ideally suited for
use as a multiplier/divider in a signal chain. The
common applications are: (a) Precision programmable
gain/attenuator amplifiers and (b) Motor control
feedback loop. The wide input range (0V – VDD) is in
Unbuffered mode and near rail-to-rail range in Buffered
mode: its bandwidth (> 400 kHz), selectable 1x/2x gain
and low power consumption give maximum flexibility to
meet the application’s needs.
To configure the MCP4902/4912/4922 family of
devices for multiple applications, connect the input sig-
nal to VREF and serially configure the DAC’s input buf-
fer, gain and output value. The DAC’s output can utilize
any of Examples 6-1 to 6-6, depending on the applica-
tion requirements. Example 6-7 is an illustration of how
the DAC can operate in a motor control feedback loop.
If the gain selection bit is configured for 1x mode
(<GA>=1), the resulting input signal will be attenuated
by D/2n. With the 12-bit DAC (MCP4921 or MCP4922),
if the gain is configured for 2x mode (<GA>=0), the
codes less than 2048 attenuate the signal, while the
codes greater than 2048 gain the signal.
A DAC provides significantly more gain/attenuation
resolution when compared to typical Programmable
Gain Amplifiers. Adding an op amp to buffer the output,
as illustrated in Examples 6-2 to 6-6, extends the
output range and power to meet the precise needs of
the application.
EXAMPLE 6-7: MULTIPLIER MODE USING VREF INPUT
VCC+
VCC-
VREF DAC
VRPM
+
–
VDD
SPI
3
VOUT
Rsense
VRPM_SET
ZFB
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
VOUT VREF GDn
2N
------
=
2010 Microchip Technology Inc. DS22250A-page 35
MCP4902/4912/4922
7.0 DEVELOPMENT SUPPORT
7.1 Evaluation and Demonstration
Boards
The Mixed Signal PICtailTM Demo Board supports the
MCP4902/4912/4922 family of devices. Please refer to
www.microchip.com for further information on this
products capabilities and availability.
MCP4902/4912/4922
DS22250A-page 36 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22250A-page 37
MCP4902/4912/4922
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for customer-specific information.
3
e
3
e
14-Lead PDIP (300 mil) Example:
14-Lead TSSOP Example:
14-Lead SOIC (150 mil) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP4922
1011256
4922E/ST
1011
256
XXXXXXXXXX
MCP4922
1011256
3
e
E/P
3
e
E/SL
MCP4902/4912/4922
DS22250A-page 38 2010 Microchip Technology Inc.
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DS22250A-page 40 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS22250A-page 41
MCP4902/4912/4922
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DS22250A-page 42 2010 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010 Microchip Technology Inc. DS22250A-page 43
MCP4902/4912/4922
APPENDIX A: REVISION HISTORY
Revision A (April 2010)
• Original Release of this Document.
MCP4902/4912/4922
DS22250A-page 44 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22250A-page 45
MCP4902/4912/4922
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: MCP4902: Dual 8-Bit Voltage Output DAC
MCP4902T: Dual 8-Bit Voltage Output DAC
(Tape and Reel)
MCP4912: Dual 10-Bit Voltage Output DAC
MCP4912T: Dual 10-Bit Voltage Output DAC
(Tape and Reel)
MCP4922: Dual 12-Bit Voltage Output DAC
MCP4922T: Dual 12-Bit Voltage Output DAC
(Tape and Reel)
Temperature
Range:
E= -40C to +125C (Extended)
Package: P = 14-Lead Plastic Dual In-Line (PDIP)
SL = 14-Lead Plastic Small Outline - Narrow (SOIC)
ST = 14-Lead Plastic Think Shrink Small Outline
(TSSOP)
Examples:
a) MCP4902-E/P: Extended temperature,
PDIP package.
b) MCP4902-E/SL: Extended temperature,
SOIC package.
c) MCP4902T-E/SL: Extended temperature,
SOIC package, Tape
and Reel
d) MCP4902-E/ST: Extended temperature,
TSSOP package.
e) MCP4902T-E/ST: Extended temperature,
TSSOP package, Tape
and Reel
f) MCP4912-E/P: Extended temperature,
PDIP package.
g) MCP4912-E/SL: Extended temperature,
SOIC package.
h) MCP4912T-E/SL: Extended temperature,
SOIC package, Tape
and Reel
i) MCP4912-E/ST: Extended temperature,
TSSOP package.
j) MCP4912T-E/ST: Extended temperature,
TSSOP package, Tape
and Reel
k) MCP4922-E/P: Extended temperature,
PDIP package.
l) MCP4922-E/SL: Extended temperature,
SOIC package.
m) MCP4922T-E/SL: Extended temperature,
SOIC package, Tape
and Reel
n) MCP4922-E/ST: Extended temperature,
TSSOP package.
o) MCP4922T-E/ST: Extended temperature,
TSSOP package, Tape
and Reel
MCP4902/4912/4922
DS22250A-page 46 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22250A-page 47
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
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suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
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MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
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All other trademarks mentioned herein are property of their
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© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-129-1
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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DS22250A-page 48 2010 Microchip Technology Inc.
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Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
01/05/10
