Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
D
Single-Chip Ethernet Adapter for the
Peripheral Component Interconnect (PCI)
Local Bus
– 32-Bit PCI Glueless Host Interface
– Compliant With PCI Local-Bus
Specification (Revision 2.0)
– 33-MHz Operation
– 3-V or 5-V I/O Operation
– Adaptive Performance Optimization
(APO) by Texas Instruments (TI) for
Highest Available PCI Bandwidth
– High-Performance Bus Master
Architecture With Byte-Aligning DMA
Controller for Low Host CPU and Bus
Utilization
– Plug-and-Play Compatible
D
Supports 32-Bit Data Streaming on PCI Bus
– Time Division Multiplexed SRAM
– 2-Gbps Internal Bandwidth
D
Driver Compatible With All Previous
ThunderLAN Components
D
Switched-Ethernet Compatible
D
Full-Duplex Compatible With Independent
Transmit and Receive Channels
D
No On-Board Memory Required
D
Auto-Negotiation (N-Way) Compatible
D
Supports the Card Bus CIS Pointer
Register
D
Integrated 10 Base-T, and 10 Base-5
Attachment Unit Interface (AUI) Physical
Layer Interface
– Single-Chip IEEE 802.3 and Blue Book
Ethernet-Compliant Solution
– DSP-Based Digital Phase-Locked Loop
– Smart Squelch Allows for Transparent
Link Testing
– Transmission Waveshaping
– Autopolarity (Reverse Polarity
Correction)
– External/Internal Loopback Including
Twisted Pair and AUI
– 10 Base-2 Supported Via AUI Interface
D
Low-Power CMOS Technology
– Green PC Compatible
– Microsoft Advanced Power
Management
D
EEPROM Interface Supports Jumperless
Design and Autoconfiguration
D
Hardware Statistics Registers for
Management Information Base (MIB)
D
DMTF (Desktop Management Task Force)
Compatible
D
IEEE Standard 1149.1 Test Access Port
(JTAG)
D
144-Pin Quad Flat Packages (PCM Suffix)
and Thin Quad Flat Packages (PGE Suffix)
PCI
Bus
PCI
Bus Master
Control
FIFO
Registers
Multiplexed
SRAM
FIFO
Ethernet
LAN
Controller
10 Mbps
10 Base-T
Physical
Layer
Interface
10 Base-T
Ethernet
10 Base-5
(AUI)
Figure 1. ThunderLAN Architecture
Copyright 1996, Texas Instruments Incorporated
The PCI Local-Bus Specification, Revision 2.0 should be used as a reference with this document.
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
ThunderLAN, Adaptive Performance Optimization, and TI are trademarks of Texas Instruments Incorporated.
Ethernet is a trademark of Xerox Corporation.
Microsoft is a trademark of Microsoft Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
2POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
description
ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet
solution. The TNETE110A, one implementation of the ThunderLAN architecture, is an intelligent protocol
network interface. The ThunderLAN SRAM FIFO-based architecture eliminates the need for external memory
and offers a single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board physical layer
interface. See Figure 1.
The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz and is capable of
internal data-transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The TNETE1 10A
offers jumperless autoconfiguration using PCI configuration read/write cycles. Customizable configuration
registers, which can be autoloaded from an external serial EEPROM, allow designers of TNETE110A-based
systems to give their systems a unique identification code. The TNETE110A PCI interface, developed in
conjunction with other leaders in the semiconductor and computer industries, has been vigorously tested on
multiple platforms to ensure compatibility across a wide array of available PCI products. In addition, the
ThunderLAN drivers and ThunderLAN architecture use TI’s patented adaptive performance optimization (APO)
technology to dynamically adjust critical parameters for minimum latency, minimum host CPU utilization, and
maximum system performance. This technology ensures that the maximum capabilities of the PCI interface are
used by automatically tuning the adapter to the specific system in which it is operating.
An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for
minimum overhead related to multiple protocols, using common state machines to implement 95 percent of the
total protocol handler. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC)
fields, and interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC
and error checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from
the PH by way of circular-buffer FIFOs in the FIFO SRAM.
Compliant with IEEE Standard 1149.1, the TNETE110A provides a 5-pin test-access port that is used for
boundary-scan testing.
The TNETE110A is available in a 144-pin quad flat package and thin quad flat package.
differences between TNETE110 and TNETE110A:
The TNETE110A implements the CIS pointer register as defined in the PC card standard. This register can be
found in the PCI configuration registers at offset 28h. For other differences between the TNETE110 and
TNETE110A, consult the
ThunderLAN Programmer’s Guide
(literature number SPWU013).
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
3
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
pin assignments
PCM and PGE PACKAGES
(TOP VIEW)
TDO
ARCVN
VDDR
ARCVP
FRCVN
VDDR
FRCVP
VSSR
VSST
AXMTN
AXMTP
FXMTN
FXMTP
VDDT
MRST
VDDL
MDIO
VSSL
MDCLK
NC
NC
VSSI
NC
NC
NC
VDDL
NC
NC
NC
NC
VDDL
NC
NC
NC
VSSL
NC
NC
PAD24
PC/BE3
VSSI
PIDSEL
PAD23
VDDI
PAD22
PAD21
PAD20
VSSI
PAD19
PAD18
PAD17
VDDI
PAD16
PC/BE2
PFRAME
VSSL
PIRDY
PTRDY
PDEVSEL
VDDL
PSTOP
PPERR
PSERR
VSSI
PPAR
PC/BE1
PAD15
PAD14
VSSI
PAD13
PAD12
VDDI
PAD11
PAD10
PAD25144 PAD26143
142 PAD27141 PAD28140
139 PAD29138
137
136 PAD31135
134
133 PGNT
132 PCLK131
130
129
128
127
126
125 TCLK124 TMS123
122 TRST
121 RESERVED120
119 FATEST118
117 FIREF
116
115 FXTL2
114 FXTL1113
112
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
DDL
V
PAD9
PAD8
PC/BE0
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
EAD5
EAD4
EAD3
EAD2
EAD1
EOE
EALE
EXLE
EDCLK
EDIO
PAD0
111 ACOLN
110 ACOLP
109
70
71
72
NC
EAD7
PREQ
PAD30
TDI
PRST
PINTA
VDDI
VSSI
VDDI
VSSL
VDDL
VSSI
VDDI
VSSVCO
VDDVCO
VDDOSC
VSSOSC
VSSR
SSI
V
SSL
V
DDI
V
SSI
V
PCLKRUN
EAD6
DDL
V
EAD0
SSL
V
SSI
V
DDL
V
NC
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
4POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
functional block diagram
EXLE
EALE
EOE
PFRAME
PTRDY
PIRDY
PSTOP
PDEVSEL
PIDSEL
PCI
Interface
(PCIIF)
Test-Access
Port
(TAP)
Config
& I/O
Memory
Registers
Config
EEPROM
Interface
BIOS
ROM/LED
Driver
Interface
DMA
Controller
S
l
a
v
e
M
a
s
t
e
r
FIFO
Pointer
Registers
(FPREGs)
FSRAM
(FIFO SRAM)
3
128
Byte List
1.5K-Byte
Rx Buffer
0.75K-Byte
Tx Buffer
0.75K-Byte
Tx Buffer
PCLK
PCLKRUN
PRST
PINTA
PPERR
PSERR
PREQ
PGNT
PAD[31:0]
PC/BE[3:0]
EDCLK
EDIO
EAD[7:0]
64 64
Protocol
Handler
(PH)
10-Mbps
Ethernet
Physical
Layer
(PHY)
Interface
AXMTP
AXMTN
ARCVP
ARCVN
ACOLP
ACOLN
FXMTP
FXMTN
FRCVP
FRCVN
FXTL1
FXTL2
FIREF
FATEST
TRST
TMS
TCLK
TDO
TDI
TNETE110A
(ThunderLAN)
PPAR
Address
and Data
BIOS ROM
and
LED I/F
Interface
Control
Error
Reporting
IEEE
1149.1
Test-
Access
Port
Configuration
EEPROM
Interface
Bus
Arbitration
System
Control
10 Base-T
Interface
AUI
Interface
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
5
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
Pin Functions
PIN
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
TEST PORT
TCLK 124 ITest clock. TCLK is used to clock state information and test data into and out of the device during
operation of the test port.
TDI 126 ITest data input. TDI is used to shift test data and test instructions serially into the device during
operation of the test port.
TDO 125 OTest data output. TDO is used to shift test data and test instructions serially out of the device during
operation of the test port.
TMS 123 ITest mode select. TMS is used to control the state of the test port controller within TNETE110A.
TRST 121 ITest reset. TRST is used for asynchronous reset of the test port controller.
PCI INTERFACE
PAD31 135
PAD30 137
PAD29 138
PAD28 140
I/O
PCI address/data bus Byte 3 (most significant) of the PCI address/data bus
PAD27 141
I/O
PCI
address/data
b
u
s
.
B
y
te
3
(most
significant)
of
the
PCI
address/data
b
u
s
.
PAD26 143
PAD25 144
PAD24 1
PAD23 5
PAD22 7
PAD21 8
PAD20 9
I/O
PCI address/data bus Byte 2 of the PCI address/data bus
PAD19 11
I/O
PCI
address/data
b
u
s
.
B
y
te
2
of
the
PCI
address/data
b
u
s
.
PAD18 12
PAD17 13
PAD16 15
PAD15 29
PAD14 30
PAD13 32
PAD12 33
I/O
PCI address/data bus Byte 1 of the PCI address/data bus
PAD11 35
I/O
PCI
address/data
b
u
s
.
B
y
te
1
of
the
PCI
address/data
b
u
s
.
PAD10 36
PAD9 38
PAD8 39
I = input, O = output, I/O = 3-state input/output
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
6POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
Pin Functions (Continued)
PIN
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
PCI INTERFACE (CONTINUED)
PAD7 42
PAD6 43
PAD5 45
PAD4 46
I/O
PCI address/data bus Byte 0 (least significant) of the PCI address/data bus
PAD3 47
I/O
PCI
address/data
b
u
s
.
B
y
te
0
(least
significant)
of
the
PCI
address/data
b
u
s
.
PAD2 49
PAD1 50
PAD0 51
PCLK 131 I PCI clock. PCLK is the clock reference for all PCI bus operations. All other PCI pins except PRST and
PINTA are sampled on the rising edge of PCLK. All PCI bus timing parameters are defined with respect
to this edge.
PCLKRUN 53 I/OClock run control. PCLKRUN is the active-low PCI clock request/grant signal that allows the
TNETE110AA to indicate when an active PCI clock is required. (This is an open drain.)
PC/BE3
PC/BE2
PC/BE1
PC/BE0
2
16
28
41
I/O
PCI bus command and byte enables. PC/BE3 enables byte 3 (MSB) of the PC/BE pins.
PCI bus command and byte enables. PC/BE2 enables byte 2 of PCI address/data bus.
PCI bus command and byte enables. PC/BE1 enables byte 1 of PCI address/data bus.
PCI bus command and byte enables. PC/BE0 enables byte 0 of PCI address/data bus.
PDEVSEL 21 I/O
PCI device select. PDEVSEL indicates that the driving device has decoded one of its addresses as
the target of the current access. The TNETE1 10A drives PDEVSEL when it decodes an access to one
of its registers. As a bus master, the TNETE110A monitors PDEVSEL to detect accesses to illegal
memory addresses.
PFRAME 17 I/O PCI cycle frame. PFRAME is driven by the active bus master to indicate the beginning and duration
of an access. PFRAME is asserted to indicate the start of a bus transaction and remains asserted
during the transaction, only being deasserted in the final data phase.
PGNT 132 IPCI bus grant. PGNT is asserted by the system arbiter to indicate that the TNETE110A has been
granted control of the PCI bus.
PIDSEL 4 I PCI initialization device select. PIDSEL is the chip select for access to PCI configuration registers.
PINTA 128 O/D PCI interrupt. PINTA is the interrupt request from the TNETE110A. PCI interrupts are shared, so this
is an open-drain (wired-OR) output.
PIRDY 19 I/O
PCI initiator ready . PIRDY is driven by the active bus master to indicate that it is ready to complete the
current data phase of a transaction. A data phase is not completed until both PIRDY and PTRDY are
sampled asserted. When the TNETE110A is a bus master, it uses PIRDY to align incoming data on
reads or outgoing data on writes with its internal RAM-access synchronization (maximum one cycle
at the beginning of burst). When the TNETE110A is a bus slave, it extends the access appropriately
until both PIRDY and PTRDY are asserted.
PTRDY 20 I/O
PCI target ready. PTRDY is driven by the selected device (bus slave or target) to indicate that it is ready
to complete the current data phase of a transaction. A data phase is not completed until both PIRDY
and PTRDY are sampled asserted.
ThunderLAN uses PTRDY to ensure every direct I/O (DIO) operation is correctly interlocked.
PPAR 27 I/O PCI parity . PPAR carries even parity across PAD[31:0] and PC/BE[3:0]. It is driven by the TNETE110A
during all address and write cycles as a bus master and during all read cycles as a bus slave.
PPERR 24 I/O PCI parity error. PPERR indicates a data parity error on all PCI transactions except special cycles.
I = input, I/O = 3-state input/output, O/D = open-drain output
Open drain
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
7
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
Pin Functions (Continued)
PIN
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
PCI INTERFACE (CONTINUED)
PREQ 134 I/O PCI bus request. PREQ is asserted by the TNETE110A to request control of the PCI bus. This is not
a shared signal.
PRST 129 IPCI reset signal.
PSERR 25 O/D PCI system error. PSERR indicates parity errors, or special cycle data parity errors.
PSTOP 23 I/O PCI stop. PSTOP indicates the current target is requesting the master to stop the current transaction.
BIOS ROM/LED DRIVER INTERFACE
EAD7
EAD6
EAD5
EAD4
EAD3
EAD2
EAD1
EAD0
54
55
56
57
59
60
61
62
I/O
EPROM address/data. EAD[7:0] is a multiplexed byte bus that is used to address and read data from
an external BIOS ROM.
On the cycle when EXLE is asserted low, EAD[7:0] is driven with the high byte of the
address.
On the cycle when EALE is asserted low, EAD[7:0] is driven with the low byte of the
address.
When EOE is asserted, BIOS ROM data should be placed on the bus.
These pins can also be used to drive external status LEDs. Low-current (25 mA) LEDs can be
connected directly (through appropriate resistors). High-current LEDs can be driven through buffers
or from the BIOS ROM address latches.
EALE 65 OEPROM address latch enable. EALE is driven low to latch the low (least significant) byte of the BIOS
ROM address from EAD[7:0].
EOE 64 OEPROM output enable. When EOE is active (low) EAD[7:0] is in the high-impedance state and the
output of the BIOS ROM should be placed on EAD[7:0].
EXLE 66 OEPROM extended address latch enable. EXLE is driven low to latch the high (most significant) byte
of the BIOS ROM address from EAD[7:0].
CONFIGURATION EEPROM INTERFACE
EDCLK 68 OEEPROM data clock. EDCLK transfers serial clocked data to the 2K-bit serial EEPROMs (24C02) (see
Note 1).
EDIO 69 I/O EEPROM data I/O. EDIO is the bidirectional serial data/address line to the 2K-bit serial EEPROM
(24C02). EDIO requires an external pullup for EEPROM operation. T ying EDIO to ground disables the
EEPROM interface and prevents autoconfiguration of the PCI configuration register.
NETWORK INTERFACE (10 Base-T AND AUI)
ACOLN
ACOLP 111
109 AAUI receive pair . ACOLN and ACOLP are differential line-receiver inputs and connect to receive pair
via transformer isolation, etc.
ARCVN
ARCVP 108
106 AAUI receive pair . ARCVN and ARCVP are differential line-receiver inputs and connect to receive pair
via transformer isolation, etc.
AXMTP
AXMTN 99
100 AAUI transmit pair. AXMTP and AXMTN are differential line-transmitter outputs.
FATEST 118 AAnalog test pin. FATEST provides access to the filter of the reference PLL. This pin should be left as
a no connect.
FIREF 116 ACurrent reference. FIREF is used to set a current reference for the analog circuitry.
FRCVN
FRCVP 105
103 A10 Base-T receive pair . FRCVN and FRCVP are differential line receiver inputs and connect to receive
pair via transformer isolation, etc.
FXTL1
FXTL2 113
114 ACrystal oscillator pins. Drive FXTL1 from a 20-MHz crystal oscillator module.
I = input, O = output, I/O = 3-state input/output, O/D = open-drain output, A = analog
NOTE 1: This pin should be tied to VDD with a 4.7-k
W
– 10-k
W
pullup resistor.
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
8POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
Pin Functions (Continued)
PIN
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
NETWORK INTERFACE (10 Base-T AND AUI) (CONTINUED)
FXMTP
FXMTN 97
98 A10 Base-T transmit pair. FXMTP and FXMTN are differential line transmitter outputs.
RESERVED 120 IReserved. Tie this pin low .
SERIAL MANAGEMENT INTERFACE
MDIO 93 I/O Management data I/O. MDIO is part of the serial management interface.
MDCLK 91 OManagement data clock. MDCLK is part of the serial management interface to physical-media
independent (PMI)/PHY chip.
MRST 95 OMII reset. MRST is the reset signal.
POWER
VDDI
6, 14,
34, 48,
122,
136,
142
PWR PCI VDD pins. VDDI pins provide power for the PCI I/O pin drivers. Connect VDDI pins to a 5-V power
supply when using 5-V signals on the PCI bus. Connect VDDI pins to a 3-volt power supply when using
3-V signals on the PCI bus.
VDDL
22, 37,
58, 70,
79, 84
94,
130
PWR Logic VDD pins (5 V). VDDL pins provide power for internal TNETE1 10A logic, and they should always
be connected to 5 V.
VDDOSC 115 PWR Analog power pin. VDDOSC is the 5-V power for the crystal oscillator circuit.
VDDR 104
107 PWR Analog power pin. VDDR is the 5-V power for the receiver circuitry.
VDDT 96 PWR Analog power pin. VDDT is the 5-V power for the transmitter circuitry.
VDDVCO 117 PWR Analog power pin. VDDVCO is the 5-V power for the voltage controller oscillator (VCO) and filter input.
VSSI
3, 10,
26, 31,
40, 52,
67, 88,
127,
139
PWR PCI I/O ground pins
VSSL
18, 44,
63, 75,
92,
133
PWR Logic ground pins
VSSOSC 112 PWR Analog power pin. Ground for crystal oscillator circuit
VSSR 102
110 PWR Analog power pin. Ground for receiver circuitry
VSST 101 PWR Analog power pin. Ground for transmitter circuitry
VSSVCO 119 PWR Analog power pin. Ground for VCO and filter input
I = input, A = analog, PWR = power
architecture
The major blocks of the TNETE110A include the PCI interface (PCIIF), protocol handler (PH), physical layer
(PHY), FIFO pointer registers (FPREGS), FIFO SRAM (FSRAM), and a test-access port (TAP). The
functionality of these blocks is described in the following sections.
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
9
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
PCI interface (PCIIF)
The TNETE110A PCIIF contains a byte-aligning DMA controller that allows frames to be fragmented into any
byte length and transferred to any byte address while supporting 32-bit data streaming. For multipriority
networks it can provide multiple data channels, each with separate lists, commands, and status. Data for the
channels is passed to and from the PH by way of circular buffer FIFOs in the SRAM, controlled through FIFO
registers. The configuration EEPROM interface (CEI), BIOS ROM/LED driver interface (BRI), configuration and
I / O memory registers (CIOREGS), and DMA controller are subblocks of the PCIIF. The features of these
subblocks are as follows:
configuration EEPROM interface (CEI)
The CEI provides a means for autoconfiguration of the PCI configuration registers. Certain registers in the PCI
configuration space may be loaded using the CEI. Autoconfiguration allows builders of TNETE110A-based
systems to customize the contents of these registers to identify their own system, rather than using the TI
defaults. The EEPROM is read at power up and can then be read from, and written to, under program control.
BIOS ROM/LED driver interface (BRI)
The BRI addresses and reads data from an external BIOS ROM via a multiplexed byte-wide bus. The ROM
address/data pins can also be multiplexed to drive external status LEDs.
configuration and I/O memory registers (CIOREGS)
The CIOREGS reside in the configuration space, which is 256 bytes in length. The first 64 bytes of the
configuration space is the header region, which is explicitly defined by the PCI standard.
DMA controller (DMAC)
The DMAC is responsible for coordinating TNETE110A requests for mastership of the PCI bus. The DMAC
provides byte-aligning DMA control allowing byte-size fragmented frames to be transferred to any byte address
while supporting 32-bit data streaming.
protocol handler (PH)
The PH implements the serial protocols of the network. On transmit, it serializes data, adds framing and CRC
fields, and interfaces to the network PHY. On receive, it provides address recognition, CRC and error checking,
frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of
circular buffer FIFOs in the FSRAM controlled through FPREGS.
10 Base-T physical layer (PHY)
The PHY acts as an on-chip front-end providing physical layer functions for 10 Base-5 (AUI), 10 Base-2, and
10 Base-T (twisted pair). The PHY provides Manchester encoding/decoding from smart squelch, jabber
detection, link pulse detection, autopolarity control, 10 Base-T transmission waveshaping, and antialiasing
filtering. Connection to the AUI drop cable for the 10 Base-T twisted pair is made via simple isolation
transformers (see Figure 2) and no external filter networks are required. Suitable external termination
components allow the use of either shielded or unshielded twisted-pair cable (150
W
or 100
W
). Some of the
key features of the on-chip PHY include the following:
D
Integrated filters
D
10 Base-T transceiver
D
AUI transceiver
D
10 Base-2 transceiver
D
Autopolarity (reverse polarity correction)
D
Loopback for twisted pair and AUI
D
Full-duplex mode for simultaneous 10 Base-T transmission and reception
D
Low power
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
10 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
10 Base-T physical layer (continued)
TNETE110APCI
FXMTP
FXMTN
FRCVP
FRCVN
RJ-45
Figure 2. Schematic for 10 Base-T Network Interface Using TNETE110A
FIFO pointer registers (FPREGS)
The FPREGS are used to implement circular buffer FIFOs in the SRAM. They are a collection of pointer and
counter registers used to maintain the FIFO operation. Both the PCIIF and PH use FPREGS to determine where
to read or write data in the SRAM and to determine how much data the FIFO contains.
FIFO SRAM (FSRAM)
The FSRAM is a conventional SRAM array accessed synchronously to the PCI bus clock. Access to the RAM
is allocated on a time-division multiplexed (TDM) basis, rather than through a conventional shared bus. This
removes the need for bus arbitration and provides ensured bandwidth. Half of the RAM accesses (every other
cycle) are allocated to the PCI controller . It has a 64-bit access port to the RAM, giving it 1 Gbps of bandwidth,
sufficient to support 32-bit data streaming on the PCI bus. The PH has one quarter of the RAM accesses, and
its port may be up to 64 bits wide. A 64-bit port for the PH provides 512 Mbps of bandwidth, more than sufficient
for a full-duplex 100-Mbps network. The remaining RAM accesses can be allocated toward providing even more
PH bandwidth. The RAM also is accessible (for diagnostic purposes) from the TNETE110A internal data bus.
Host DIO (mapped I/O) accesses are used by the host to access internal TNETE110A registers and for adapter
test.
Some of the features of the FSRAM follow:
D
3.375K bytes of FSRAM
D
1.5K-byte FIFO for receive channel
D
One 1.5K-byte FIFO for transmit channel
D
Three 128-byte lists
Supporting 1.5K byte of FIFO per channel allows full-frame buffering of Ethernet frames.
test-access port (TAP)
Compliant with IEEE Standard 1149.1, the T AP is composed of five pins that are used to interface serially with
the device and the board on which it is installed for boundary-scan testing.
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
11
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, VDD (see Note 2) 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (see Note 2) 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation 1.15 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC 0°C to 95°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction to ambient package thermal impedance,
airflow = 100 LFPM, TJA(100) PGE 45.4°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction to ambient package thermal impedance,
airflow = 0 LFPM, TJA(0) PGE 51°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction to ambient package thermal impedance,
airflow = 0 LFPM, TJA(0) PCM 41.4°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction to ambient package thermal impedance,
airflow = 100 LFPM, TJA(100) PCM 38.0°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction to case package thermal impedance, TJC 0.22°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 2: Voltage values are with respect to VSS, and all VSS pins should be routed so as to minimize inductance to system ground.
The recommended operating conditions and the electrical characteristics tables are divided into groups,
depending on pin function:
D
PCI interface pins
D
Logic pins
D
Physical layer pins
The PCI signal pins are operated in one of two modes shown in the PCI tables.
D
5-V signal mode
D
3-V signal mode
recommended operating conditions (PCI interface pins) (see Note 3)
3-V SIGNALING
OPERATION 5-V SIGNALING
OPERATION UNIT
MIN NOM MAX MIN NOM MAX
VDD Supply voltage (PCI) 3 3.3 3.6 4.75 5 5.25 V
VIH High-level input voltage 0.5
VDDVDD+0.52.0 VDD+0.5 V
VIL Low-level input voltage, TTL-level signal (see Note 4) 0.50.50.5 0.8 V
IOH High-level output current TTL outputs 0.5–2 mA
IOL Low-level output current
(see Note 5) TTL outputs 1.56 mA
Specified by design spice IV curve (please refer to PCI specification revision 2.1, section 4.2, paragraph 2 for explanation)
NOTES: 3. PCI interface pins include VDDI, PCLKRUN, PFRAME, PTRDY, PIRDY, PSTOP, PDEVSEL, PIDSEL, PPERR, PSERR, PREQ,
PGNT, PCLK, PPAR, PRST, PINTA, PAD[31:0], PC/BE[3:0], TRST, TMS, TCLK, TDO, TDI.
4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
12 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (PCI interface pins)
PARAMETER TEST CONDITIONS
3-V SIGNALING
OPERATION 5-V SIGNALING
OPERATION UNIT
MIN MAX MIN MAX
VOH High-level output voltage,
TTL-level signal (see Note 6) VDD = MIN, IOH = MAX 0.9
VDD2.4 V
VOL Low-level output voltage,
TTL-level signal VDD = MAX, IOL = MAX 0.1
VDD0.5 V
IOZ
High im
p
edance out
p
ut current
VDD = MAX, VO = 0 V 10 10
µA
I
OZ
High
-
impedance
o
u
tp
u
t
c
u
rrent
VDD = MAX, VO = VDD –10 – 10 µ
A
IIInput current, any input or input/output VI = VSS to VDD
"
10
"
10 µA
IDD Supply current VDD = MAX 50 60 mA
CiInput capacitance, any input§f = 1 MHz, Others at 0 V 10 10 pF
COOutput capacitance, any output or
input/output§f = 1 MHz, Others at 0 V 10 10 pF
For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions.
Assured by SPICE IV Curve (see PCI specification revision 2.1, section 4.2, paragraph 2 for explanation)
§Specified by design
NOTE 6: The following signals require an external pullup resistor: PSERR, PINTA.
recommended operating conditions (logic pins) (see Note 7)
MIN NOM MAX UNIT
VDD Supply voltage (5 V only) 4.75 5 5.25 V
VIH High-level input voltage 2 VDD+0.3 V
VIL Low-level input voltage, TTL-level signal (see Note 4) 0.3 0.8 V
IOH High-level output current TTL outputs –4 mA
IOL Low-level output current (see Note 5) TTL outputs 4 mA
NOTES: 4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
7. Logic pins include VDDL, EAD[7:0], EXLE, EALE, EOE, EDCLK, EDIO.
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(logic pins)
PARAMETER TEST CONDITIONSMIN NOM MAX UNIT
VOH High-level output voltage, TTL-level signal VDD = MIN, IOH = MAX 2.4 V
VOL Low-level output voltage, TTL-level signal VDD = MAX, IOL = MAX 0.5 V
IO
High im
p
edance out
p
ut current
VDD = MIN, VO = VDD 10
µA
I
O
High
-
impedance
o
u
tp
u
t
c
u
rrent
VDD = MIN, VO = 0 V –10 µ
A
IIInput current VI = VSS to VDD
"
10 µA
IDD
Supply current @ 25 MHz (PCLK)
190mA
I
DD Supply current @ 33 MHz (PCLK)
DD =
228mA
CiInput capacitance, any input§f = 1 MHz, Others at 0 V 10 pF
CoOutput capacitance, any output or input/output§f = 1 MHz, Others at 0 V 10 pF
For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions.
§Specified by design
Characterized in system test not tested
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
13
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
recommended operating conditions (physical layer pins) (see Note 8)
MIN NOM MAX UNIT
VDD Supply voltage 4.75 5 5.25 V
NOTE 8: Physical layer pins include VDDOSC, VDDR, VDDT, VDDVCO, ACOLN, ACOLP , ARCVN, ARCVP, AXMTP, AXMTN, F A TEST , FIREF,
FRCVN, FRCVP, FXTL1, FXTL2, FXMTP, and FXMTN.
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(physical interface pins)
10 Base-T receiver input (FRCVP, FRCVN)
PARAMETER JEDEC
SYMBOL TEST CONDITIONS MIN MAX UNIT
VI(DIFF) Differential input voltageVID 0.6 2.8 V
I(CM) Common-mode currentIIC 4 mA
VSQ+ Rising input pair squelch threshold (see Note 9) VCM = VSB, See Note 10 360 mV
VSQ– Falling input pair squelch threshold (see Note 9) VCM = VSB, See Note 10 360 mV
See recommended operating conditions.
NOTES: 9. VSQ is the voltage at which input is assured to be seen as data.
10. VSB is the self-bias of the input FRCVP and FRCVN.
10 Base-T transmitter drive characteristics (FXMTP, FXMTN)
PARAMETER JEDEC
SYMBOL TEST CONDITIONS MIN MAX UNIT
VSLW Dif ferential voltage at specified slew rate VOD(SLEW)
"
2.2
"
2.8 V
VO(CM) Common-mode output voltage VOC See Figure 3d 0 4 V
VO(DIFF) Differential output voltage VOD Into open circuit 5.25 V
VO(I) Output idle differential voltage VOD(IDLE)
"
50 mV
IO(FC) Output current, fault conditionIO(FC) 300 mA
Specified by design
AUI receiver input (ARCVP, ARCVN, ACOLP, ACOLN)
PARAMETER JEDEC
SYMBOL TEST CONDITIONS MIN MAX UNIT
VI(DIFF)1 Differential input voltage 1VID(1) See Note 11 0 3 V
VI(DIFF)2 Differential input voltage 2VID(2) See Note 12 0 100 mV
V(SQ) Falling input pair squelch threshold See Note 13 325 mV
See recommended operating conditions.
NOTES: 11. Common-mode frequency range – 10 Hz to 40 kHz
12. Common-mode frequency range – 40 kHz to 10 MHz
13. Input bias over the common mode dc voltage range
AUI transmitter drive characteristics (AXMTP, AXMTN)
PARAMETER JEDEC
SYMBOL TEST CONDITIONS MIN MAX UNIT
VO(DIFF)1 Differential output voltageVOD(1) See Note 14
"
240
"
1300 mV
VOI(DIFF) Output idle differential voltageVOD(IDLE)
"
50 mV
VOI(DIFF)U Output differential undershootVOD(IDLE)U 100 mV
IO(FC) Output current, fault conditionIO(FC) 150 mA
See recommended operating conditions.
Specified by design
NOTE 14: The differential voltage is measured as per Figure 3b.
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
14 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(physical interface pins) (continued)
crystal-oscillator characteristics
PARAMETER JEDEC
SYMBOL TEST CONDITIONS MIN MAX UNIT
VSB(FXTL1) Input self-bias voltage VIB 1.7 2.8 V
IOH(FXTL2) High-level output current IOH V(FXTL2) = VSB(FXTL1)
V(FXTL1) = VSB(FXTL1) + 0.5 V – 1.3 – 5.0 mA
IOL(FXTL2) Low-level output current IOL V(FXTL2) = VSB(FXTL1)
V(FXTL1) = VSB(FXTL1) – 0.5 V – 0.4 1.5 mA
PARAMETER MEASUREMENT INFORMATION
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V . These levels
are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low
is 0.8 V . For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level
at which the signal is said to be high is 2 V, as shown below.
The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically
1.5 ns.
0.8 V (low)
2 V (high)
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
15
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
test measurement
The test-load circuit shown in Figure 3 represents the programmable load of the tester pin electronics that are
used to verify timing parameters of the TNETE110A output signals.
(c) FIREF TEST CIRCUIT
(b) AXMTP AND AXMTN TEST LOAD (AC TESTING)
(a) TTL OUTPUT TEST LOAD
180
FIREF
AXMTN
AXMTP Test Point
CL
IOH
VLOAD
IOL
Point
Test
Test
Under
Output
TTL
50
78 50
X1
X1–Fil–Mag 23Z90(1:1)
(d) FXMTP AND FXMTN TEST LOAD (AC TESTING)
FXMTN
FXMTP Test Point
50
50
X2
X2–Fil–Mag 23Z128(1:2)
25
25 FXMTN
FXMTP Test Point
50
50
50
(e) FXMTP and FXMTN TEST LOAD (DC TESTING)
Test Point
50
Where: IOL = Refer to IOL in recommended operating conditions
IOH = Refer to IOH in recommended operating conditions
VLOAD = 1.5 V, typical dc-level verification or
0.7 V, typical timing verification
CL= 18 pF, typical load-circuit capacitance
Figure 3. Test and Load Circuit
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
16 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
switching characteristics, PCI 5-V and 3.3-V (see Note 15 and Figure 3 and Figure 4)
PARAMETER MIN MAX UNIT
tVAL Delay time, PCLK to bused signals valid (see Notes 16 and 17)211 ns
tVAL(PTP) Delay time, PCLK to bused signals valid point-to-point (see Notes 16 and 17) 2 12 ns
ton Float-to-active delay 2 ns
toff Active-to-float delay 28 ns
Characterized by design
NOTES: 15. Some of the timing symbols in this table are not currently listed with EIA or JEDEC standards for semiconductor symbology but are
consistent with the PCI Local-Bus Specification, Revision 2.0.
16. Minimum times are measured with a 0-pF equivalent load; maximum times are measured with a 50-pF equivalent load. Actual test
capacitance may vary, but results should be correlated to these specifications.
17. PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT
has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.
timing requirements, PCI 5-V and 3.3-V (see Note 15 and Figure 4)
MIN MAX UNIT
tsu Setup time, bused signals valid to PCLK (see Note 17) 7 ns
tsu(PTP) Setup time to PCLK—point-to-point (see Note 17) 10, 12 ns
thInput hold time from PCLK 0 ns
tcCycle time, PCLK (see Note 18) 30 500ns
tw(H) Pulse duration, PCLK high 12 ns
tw(L) Pulse duration, PCLK low 12 ns
tslew Slew rate, PCLK (see Note 19)1 4 V/ns
Specified by design and system specification.
NOTES: 15. Some of the timing symbols in this table are not currently listed with EIA or JEDEC standards for semiconductor symbology but are
consistent with the PCI Local-Bus Specification, Revision 2.0.
17. PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT
has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.
18. As a requirement for frame transmission/reception, the minimum PCLK frequency varies with network speed. The clock may only
be stopped in a low state.
19. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform.
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
17
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
timing requirements, PCI 5-V and 3.3-V (see Note 15 and Figure 4) (continued)
5-V Clock
3.3-V Clock
0.8 V
2 V
1.5 V
Output
Delay
3-State
Output
Input
tc
tw(H) tw(L)
tVAL
ton
tsu th
Inputs
Valid VMAX
toff
0.475 × VDD
0.4 × VDD
0.326 × VDD
Figure 4. PCI 5-V and 3.3-V Timing
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
18 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
timing requirements for management data I/O (MDIO) (see Figure 3 and Figure 5)
MIN MAX UNIT
ta(MDCLKH-MDIOV) Access time, MDIO valid from MDCLK high (see Note 20) 0 300 ns
switching characteristics for management data I/O (MDIO) (see Figure 6)
PARAMETER MIN MAX UNIT
tsu(MDIOV-MDCLKH) Setup time, MDIO valid to MDCLK high (see Note 21) 10 ns
th(MDCLKH-MDIOX) Hold time, MDCLK high to MDIO changing (see Note 21) 10 ns
NOTES: 20. When the MDIO signal is sourced by the PMI/PHY, it is sampled by TNETE110A synchronous to the rising edge of MDCLK.
21. MDIO is a bidirectional signal that can be sourced by TNETE110A or the PMI/PHY. When TNETE110A sources the MDIO signal,
TNETE110A asserts MDIO synchronous to the rising edge of MDCLK.
ta(MDCLKH-MDIOV)
MDCLK
MDIO
Figure 5. Management Data I/O Timing (Sourced by PHY)
tsu(MDIOV-MDCLKH)
th(MDCLKH-MDIOX)
MDCLK
MDIO
Figure 6. Management Data I/O Timing (Sourced by TNETE110A)
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
19
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
timing requirements, BIOS ROM and LED interface (see Figure 3 and Figure 7)
MIN MAX UNIT
tsu Setup time, data 250 ns
thHold time, data 0 ns
switching characteristics, BIOS ROM and LED interface (see Figure 7)
PARAMETER MIN MAX UNIT
td(EADV-EXLEL) Delay time, address high byte valid to EXLE low (address high byte setup time for external
latch) 0 ns
td(EXLEL-EADZ) Delay time, EXLE low to address high byte invalid (address high byte hold time for external
latch) 10 ns
td(EADV-EALEL) Delay time, address low byte valid to EALE low (address low byte setup time for external latch) 0 ns
td(EALEL-EADZ) Delay time, EALE low to address low byte invalid (address low byte hold time for external latch) 10 ns
taAccess time, address 288 ns
The EPROM interface, consisting of 11 pins, requires only two TTL ’373 latches to latch the high and low addresses.
td(EADV-EXLEL)
EAD[7:0]
EXLE
EALE
EOE
td(EXLEL-EADZ)
ta
tsu th
Data
td(EALEL-EADZ)
High
Address Low
Address
td(EADV-EALEL)
Figure 7. BIOS ROM and LED Interface Timing
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
20 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
switching characteristics, configuration EEPROM interface (see Figure 3 and Figure 8)
PARAMETER MIN MAX UNIT
fCLK(EDCLK) Clock frequency, EDCLK 0 100 kHz
td(EDCLKL-EDIOV) EDCLK low to EDIO data in valid 0.3 3.5 µs
td(EDIO free) T ime the bus must be free before a new transmission can start 4.7 µs
td(EDIOV-EDCLKL) Delay time, EDIO valid after EDCLK low (start condition hold time for EEPROM) 4µs
tw(L) Low period, clock 4.7 µs
tw(H) High period, clock 4µs
td(EDCLKH-EDIOV) Delay time, EDCLK high to EDIO valid (start condition setup time) 4.7 µs
td(EDCLKL-EDIOX) Delay time, EDCLK low to EDIO changing (data out hold time) 0µs
td(EDIOV-EDCLKH) Delay time, EDIO valid to EDCLK high (data out setup time) 250 ns
trRise time, EDIO and EDCLK 1µs
tfFall time, EDIO and EDCLK 300 ns
td(EDCLKH-EDIOH) Delay time, EDCLK high to EDIO high (stop condition setup time) 4.7 µs
td(EDCLKL-EDIOX) Delay time, EDCLK low to EDIO changing (data in hold time) 300 ns
td(EDCLKH-EDIOV)
EDCLK
EDIO (OUT)
EDIO (IN)
td(EDIOV-EDCLKL)
tf
td(EDCLKL-EDIOV)
tw(H) tw(L)
td(EDCLKL-EDIOX)
td(EDIOV-EDCLKH)
td(EDCLKL-EDIOX)
tr
td(EDCLKH-EDIOH)
td(EDIO free)
Figure 8. Configuration EEPROM Interface Timing
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
21
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
timing requirements, crystal oscillator (see Figure 9)
MIN TYP MAX UNIT
td(VDDHFXTL1V) Delay time from minimum VDD high level to first valid FXTL1V full swing period 100ms
tw(H) Pulse duration at FXTL1 high 13ns
tw(L) Pulse duration at FXTL1 low 13ns
ttT ransition time of FXTL1 7 ns
tcCycle time, FXTL1 50 ns
Tolerance of FXTL1 input frequency
"
0.01 %
The FXTL signal may be implemented by either connecting a 20-MHz crystal across the FXTL1 and FXTL2 pins or by driving the FXTL1 from
a 20-MHz crystal oscillator module.
This specification is provided as an aid to board design. This specification is not tested during manufacturing testing.
FXTL1
VDD
td(VDDHFXTL1V)
Minimum VDD High Level
tc
tw(H)
tw(L)
tt
tt
Figure 9. Crystal Oscillator Timing
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
22 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
PCM (S-PQFP-G***) PLASTIC QUAD FLATPACK
4040024/B 10/94
144 PIN SHOWN
A
73
144
160
0,38
0,22
72
37
NO. OF
PINS***
22,75 TYP
25,35 TYP
0,16 NOM
0,25
0,73
1,03
36
Seating Plane
0,25 MIN
Gage Plane
108
109
144
A
SQ
SQ
31,45
1
28,20
30,95
27,80
3,60
3,20
4,10 MAX 0,10
0,65
M
0,13
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
D. The 144 PCM is identical to the 160 PCM except that four leads per corner are removed.
ThunderLAN TNETE110A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996
23
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK
4040147/B 10/94
0,27
72
0,17
37
73
0,13 NOM
0,25
0,75
0,45
0,05 MIN
36
Seating Plane
Gage Plane
108
109
144
SQ
SQ
22,20
21,80
1
19,80
17,50 TYP
20,20
1,35
1,45
1,60 MAX
M
0,08
0°–7°
0,08
0,50
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated