AM29SL800CT-100WBI - Advanced Micro Devices

This Data Sheet state s AMD’ s c urrent specif ication s regarding the Pr oducts desc ribed herein. This Data Sheet ma y

be revised by s ubsequ ent versions or modifications due to changes in technical specifica tions. Publicati on# 22230 Rev: DAmendment/+2

Issue Date: Novembe r 14, 2000

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29SL800C

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 1.8 Volt-only Super Low Voltage Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

— 1.8 to 2.2 V for read, program, and erase

operations

— Ideal for battery-powered applications

■Manufactured on 0.32 µm process technology

— Compatible with 0.35 µm Am29SL800B device

■High performan c e

— Access times as fast as 100 ns

■Ultra low power consumption (typical v alues at 5

MHz)

— 1 µA Automatic Sleep Mode current

— 1 µA standby mode current

— 5 mA read current

— 20 mA program/erase current

■Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

A hardw are method of loc king a sector to pre vent

any program or erase operations within that

sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect f eature allows code

changes in prev iously locked sectors

■Unlock Bypass Program Comm and

— Reduces ov erall prog ramming time when issuing

multiple program command sequences

■Top or bottom boot block configurations

available

■Embedded Algorithms

— Embedded Erase algorithm automatically

preprogr ams and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■Minimum 1,000,000 write cycle guarantee per

sector

■20-year data retention at 125°C

■Package option

— 48-pin TSOP

— 48-ball FBGA

■Compatibility with JEDEC standards

— Pinout and software compatible with single-

pow er supply Flash

— Superior inadvertent write protection

■Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

■Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■Erase Suspend/Erase Resume

— Suspends an er ase operation t o read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■Hardware reset pin (RESET#)

— Hardware method to res et the devic e to reading

array data

2 Am29SL800C

GENERAL DESCRIPTION

The Am29SL800C is an 8 Mbit, 1.8 V volt-only Flash

memory organized as 1,048,576 bytes or 524,288

words. The device is offered in 48-pin TSOP and 48-

ball FBGA packages. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device is designed to be

programmed and erased in-system with a single 1.8

volt VCC supply. No VPP is for write or erase operations.

The device can also be programmed in standard

EPROM programmers.

The standard device offers access times of 100, 120,

and 150 ns, allowing high speed microprocessors to

operate wit hout wait st ates. To eliminate b us contention

the device has separate chip enable (CE#), write

enable ( WE#) and output enable (OE#) controls.

The device requires only a single 1.8 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The de vice is entirely command set compatib le with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automati-

cally preprograms the array (if it is not already

programmed) before executing the erase operation.

During erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by obser ving the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the de v ice is ready to read arr ay data

or accept another command.

The sector erase ar chitecture allo ws me mory se ctors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of

memory. This can be achieved in-system or via pro-

gramming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure . True bac kgro und eras e can thus be achie ved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading arr a y data. The RESET# pin ma y be tied to the

system reset circuitr y. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also plac e the de v ice into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality , reliability and cost effectiv eness.

The device electrically erases all bits within a sector

simultaneously via Fowler-Nordheim tunneling. The

data is programmed using hot electron injection.

Am29SL800C 3
TABLE OF CONTENTS
Product Selecto r Guide  . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Special Handling Instructions for FBGA Packages  ..... .. ...........6
Pin Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol   . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
Ordering Information  . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Am29SL800C Device Bus Operations ................................9
Word/Byte Configuration  ..........................................................9
Requirements for  Reading Array Data  .......... ................ ...........9
Writing Commands/Command Sequence s  ............ .. ........ .. .. .. ..9
Program and Erase Operation Status  ....................................10
Standby Mode  ........ ...................... ................ ...................... ....10
Automatic Sleep Mode  ............ .. ........ .. .. ................... .......... ....10
RESET#: Hardware Reset Pin  ...............................................10
Output Disable Mode ..............................................................11
Table 2. Am29SL800CT Top Boot Block Sector Address Table .....11
Table 3. Am29SL800CB Bottom Boot Block Sector Address Table 12
Autoselect Mode ........ ................... ............................ ..............13
Table 4. Am29SL800C Autoselect Codes (High Voltage Method) ..1 3
Sector Protection/Unprotection ...............................................13
Temporary Sector Unprotect  ..................................................13
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 14
Figure 2. Temporary Sector Unprotect Operation........................... 15
Hardware Data Protection  ......................................................15
Low V
CC
 Write Inhibit ..............................................................15
Write Pulse “Glitch” Protection  ...............................................15
Logical Inhibit ..........................................................................15
Power-Up Write Inhibit ............................................................15
Command Definitions . . . . . . . . . . . . . . . . . . . . .  15
Reading Array Data ................................................................15
Reset Command ............. ................ ...................... ................ ..15
Autoselect Command Sequence ............................ ................16
Word/Byte Program Command Sequence .............................16
Unlock Bypass Command Sequence ................ .....................16
Fig ur e 3. Pro g ra m Ope ra tion .................................................... ...... 17
Chip Erase Command Sequence ...........................................17
Sector Erase Command Sequence ........................................17
Erase Suspend/Erase Resume Commands ........ ........ .. .........18
Figure 4. Erase Operation............................................................... 18
Command Definitions............................................................. 19
Table 5. Am29SL800C Comman d Definitions  ................................19
Write Operation Status . . . . . . . . . . . . . . . . . . . .  20
DQ 7 : Da t a#  P o ll i n g  .......... ....... .. ....... ........ ....... .. ....... ....... ....... .20
Figure 5. Data# Polling Algorithm ................................................... 20
RY/BY#: Ready/Busy#  ...........................................................21
DQ6: Toggle Bit I ....................................................................21
DQ2: Toggle Bit II ...................................................................21
Reading Toggle Bits DQ6/DQ2  ..............................................21
Figure 6. Toggle Bit Algorithm......................................................... 22
DQ5: Exceeded Timing Limits ................................................22
DQ3: Sector Erase Timer  .......................................................22
Table 6. Write Operation Status ..................................................... 23
Absolute Maximum Ratings  . . . . . . . . . . . . . . . . 24
Figure 7. Maximum Negative Overshoot Waveform .......... .. ....... .. .  24
Figure 8. Maximum Positive Overshoot Waveform....... ....... ....... ...  24
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. I
CC1
 Current vs. Time (Showing Active and Autom atic 
Sleep Currents)............... ..................................................... ..........  26
Figure 10. Typical I
CC1
 vs. Frequency...........................................  26
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Test Setup.....................................................................  27
Table 7. Test Specifications ........................................................... 27
Key to Switching Waveforms ..................................................27
Figure 12. Input Waveforms and Measurement Levels .................  27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Opera tions  ............ ................ ...................... ................ ..28
Figure 13. Read Operations Tim ings ..................................... ........  28
Figure 14. RESET# Timings ..........................................................  29
Word/Byte Configuration (BYTE#)  ........................................30
Figure 15. BYTE# Ti ming s for Read Op eratio ns. ............ ...............  30
Figure 16. BYTE# Timings for Write Operations............................  30
Erase/Program Operations .....................................................31
Figure 17. Program Operation Timings..........................................  32
Figure 18. Chip/Sector Erase Operation Timings ..........................  33
Figure 19. Data# Polling Timings (During Embedded Algorithms).  34
Figure 20. Toggle Bit Timings (During Embedded Algorithms)..... .  34
Figure 21. DQ2 vs. DQ6.................................................................  35
Temporary Sector Unprotect  ..................................................35
Figure 22. Temporary Sector Unprotect Timing Diagram ..............  35
Figure 23. Sector Protect/Unprotect Timing Diagram....................  36
Alternate CE# Controlled Erase/Progr am Operat ions ............37
Figure 24. Alternate CE# Controlled Write Operation Tim ing s ......  38
Erase and Programming Performance   . . . . . . . 39
Latchup C haracteristics. . . . . . . . . . . . . . . . . . . . 39
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 39
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 048—48-Pin Standard TSOP ............................................40
TSR048—48-Pin Reverse TSOP  ...........................................41
FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
6 x 9 mm package  ..................................................................42
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision A (August 1998) ................ .. ................... ..................43
Revision B (January 1999)  .....................................................43
Revision B+1 (March 5, 1999) ...... .. ........ .. ................... ...........43
Revision C (December 6, 1999)  ............ ...... ................ ...........43
Revision D (Feb ruary 21, 2000) ..................... ................ .........43
Revision D+1  (May 8, 2000) ................... ................ ................43
Revision D+2 (November 14, 2000) .......................................43

4 Am29SL800C

PRODUCT SELECTOR GUIDE

Note: See “AC Character ist ics ” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29SL800C

Speed Options -100 -120 -150

Max access time, ns (tACC) 100 120 150

Max CE# access time, ns (tCE) 100 120 150

Max OE# access time, ns (tOE) 355065

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

BYTE#

CE#

OE#

STB

DQ0

–

DQ15 (A-1)

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A18

Am29SL800C 5

CONNECTION DIAGRAMS

A15

A18

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A18

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

Reverse TSOP

Standard TSOP

6 Am29SL800C

CONNECTION DIAGRAMS (Continued)

Special Handling Instructions for FBGA

Packages

Special handling is required f or Flash Memory products

in FBGA packages.

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 VSS

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

VCC DQ4DQ12DQ5NCNCRESET#WE#

DQ11 DQ3DQ10DQ2NCA18NCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# VSS

CE#A0A1A2A4A3

48-Ball FBGA

(Top View, Balls Facing Down)

Am29SL800C 7

PIN CONFIGURATION

A0–A18 = 19 addresses

DQ0–DQ14 = 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/outpu t, word mode),

A-1 (LSB address input, byte mode)

BYTE# = Selects 8-bit or 16-bit mode

CE# = Chip enable

OE# = Output enable

WE# = Write enable

RESET# = Hardware reset pin, active low

RY/BY# = Ready/Busy# output

VCC = 1.8–2.2 V single power supply

VSS = De vice ground

NC = Pin not connected internally

LOGIC SYMBOL

19 16 or 8

DQ0–DQ15

(A-1)

A0–A18

CE#

OE#

WE#

RESET#

BYTE# RY/BY#

8 Am29SL800C

ORDERING INFORMATION

Standard Pr o ducts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is for m ed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in v olume for this device. Consult the local AMD sales

office to confirm av ailability of specific valid combinations and

to check on newly released combinations.

Am29SL800C T -100 E C

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

WB = 48- Ba ll Fin e-Pi tch Ba ll Gr id Array (FBGA)

0.80 mm pitch, 6 x 9 mm package (FBB048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29SL800C

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages

AM29SL800CT-100,

AM29SL800CB-100

EC, EI, FC, FI

AM29SL800CT-120,

AM29SL800CB-120

AM29SL800CT-150,

AM29SL800CB-150

Valid Combin ations for FBGA Packages

Order Number Package Marking

AM29SL800CT-100,

AM29SL800CB-100

WBC,

WBI

A800CT10V,

A800CB10V

C, I

AM29SL800CT-120,

AM29SL800CB-120 A800CT12V,

A800CB12V

AM29SL800CT-150,

AM29SL800CB-150 A800CT15V,

A800CB15V

Am29SL800C 9
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The regi st er is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Am29SL800C Device Bus Operatio ns
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10 
± 
1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector 
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 oper ate  in t he b y te  or  word c onfigur a-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function. 
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set  for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocess or read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 f or the timing diagram. ICC1 in the
DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE # to  V IH.
Operation CE# OE# WE# RESET# Addresses
(Note 1) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE# 
= VIL
Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z, 
DQ15 = A-1
Write L H L H AIN DIN DIN
Standby VCC ± 
0.2 V XXVCC ± 
0.2 V X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) L H L VID
Sector Addre ss, 
A6 = L, A1 = H, 
A0 = L DIN XX
Sector Unp rot ect  (Note 2) L H L VID
Sector Addre ss, 
A6 = H, A1 = H, 
A0 = L DIN XX
Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z

10 Am29SL800C
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information. 
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to progr am a word or b yte, instead of f our. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
An erase oper at ion can er ase  one sect or, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect  mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
arra y) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Ref er to the A utoselect Mode and A utose-
lect Command Sequence sections for more
information.
ICC2 in the DC Characteristics table represents the
active current specification f or the write mode. The “A C
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or prog ram oper ation, th e system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. St andard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to t he device ,
it can place the device in the standby mode. In this
mode, current  co nsumption is g reat ly reduced,  and  the
outputs are placed in the high impedance state, inde-
pendent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.2 V.
(Note that this is a more restricted voltage range than
VIH.)  If CE# and  RESET# are he ld at  VIH, b ut not within
VCC ± 0.2 V, the de vice will be in the standb y mode,  but
the standby current will be greater .  The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy  consumption. The dev ice automatically  enables
this mode when addresses remain stable for tACC + 50
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE#  control signals. St andard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hard ware Reset Pin
The RESET# pin p rovides a hard ware method of  reset-
ting the device to reading array data. When the
RESET# pin is driven low f or at least a period of tRP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.2 V, the device
dra ws CMOS standby  current (ICC4). If RESET# is held
at VIL b ut  not within VSS±0.2 V, the standb y current  will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system res et would thus also reset the Flash
memory, enabling the sys tem to read the boot-up firm-
ware from the Flash memory.
If RESET# is ass erted during a progr am or er ase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor R Y/BY# to determine whether
the reset operation is  complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 14 for the timing diagram.

Am29SL800C 11

Output Disable Mode

When the OE# input is at VIH, outpu t from the de vice is

disabled. The output pins are placed in the high imped-

ance state.

Table 2. Am29SL800CT Top Boot Block Sector Address Table

Sector A18 A17 A16 A15 A14 A13 A12

Sector Size

(Kbytes/

Kwords)

Address Ran g e (in hexade cim al )

(x8)

Address Ran g e (x16)

Address Range

SA00000XXX 64/32 00000h–0FFFFh 00000h–07FFFh

SA10001XXX 64/32 10000h–1FFFFh08000h–0FFFFh

SA20010XXX 64/32 20000h–2FFFFh10000h–17FFFh

SA30011XXX 64/32 30000h–3FFFFh18000h–1FFFFh

SA40100XXX 64/32 40000h–4FFFFh20000h–27FFFh

SA50101XXX 64/32 50000h–5FFFFh28000h–2FFFFh

SA60110XXX 64/32 60000h–6FFFFh30000h–37FFFh

SA70111XXX 64/32 70000h–7FFFFh38000h–3FFFFh

SA81000XXX 64/32 80000h–8FFFFh40000h–47FFFh

SA91001XXX 64/32 90000h–9FFFFh48000h–4FFFFh

SA101010XXX 64/32 A0000h–AFFFFh50000h–57FFFh

SA111011XXX 64/32 B0000h–BFFFFh58000h–5FFFFh

SA121100XXX 64/32 C0000h–CFFFFh60000h–67FFFh

SA131101XXX 64/32 D0000h–DFFFFh68000h–6FFFFh

SA141110XXX 64/32 E0000h–EFFFFh70000h–77FFFh

SA1511110XX 32/16 F0000h–F7FFFh78000h–7BFFFh

SA161111100 8/4 F8000h–F9FFFh7C000h–7CFFFh

SA171111101 8/4 FA000h–FBFFFh7D000h–7DFFFh

SA18111111X 16/8 FC000h–FFFFFh7E000h–7FFFFh

12 Am29SL800C

Table 3. Am29SL800CB Bottom Boot Block Sector Address Table

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration”

section for more information.

Sector A18 A17 A16 A15 A14 A13 A12

Sector Size

(Kbytes/

Kwords)

Address Ran g e (in hexade cim al )

(x8)

Address Ran g e (x16)

Address Range

SA0000000X 16/8 00000h–03FFFh 00000h–01FFFh

SA10000010 8/4 04000h–05FFFh02000h–02FFFh

SA20000011 8/4 06000h–07FFFh03000h–03FFFh

SA300001XX 32/16 08000h–0FFFFh04000h–07FFFh

SA40001XXX 64/32 10000h–1FFFFh08000h–0FFFFh

SA50010XXX 64/32 20000h–2FFFFh10000h–17FFFh

SA60011XXX 64/32 30000h–3FFFFh18000h–1FFFFh

SA70100XXX 64/32 40000h–4FFFFh20000h–27FFFh

SA80101XXX 64/32 50000h–5FFFFh28000h–2FFFFh

SA90110XXX 64/32 60000h–6FFFFh30000h–37FFFh

SA100111XXX 64/32 70000h–7FFFFh38000h–3FFFFh

SA111000XXX 64/32 80000h–8FFFFh40000h–47FFFh

SA121001XXX 64/32 90000h–9FFFFh48000h–4FFFFh

SA131010XXX 64/32 A0000h–AFFFFh50000h–57FFFh

SA141011XXX 64/32 B0000h–BFFFFh58000h–5FFFFh

SA151100XXX 64/32 C0000h–CFFFFh60000h–67FFFh

SA161101XXX 64/32 D0000h–DFFFFh68000h–6FFFFh

SA171110XXX 64/32 E0000h–EFFFFh70000h–77FFFh

SA181111XXX 64/32 F0000h–FFFFFh78000h–7FFFFh

Am29SL800C 13
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended f or  programming equipment
to automatically match a de vice to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A1, and A0 must be as shown in Table 4. In addi-
tion, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Tables 2 and 3). Table 4 shows the
remaining address bits that are don’t care. When all
necessary b its hav e been set as  required, the progr am-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Ta ble 4. Am29SL800C Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH,  SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
progr am and er ase opera tions in an y  sect or. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods. 
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo-
rithms and Figure 23 shows the timing diagram. This
method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors
must first  be protected  prior to the fi rst sector un protect
wr ite cycle. 
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written f or earlier 3.0 v olt-only  AMD flash de vi ces. Pub-
lication number 21622 c ontains further details.  Contact
an AMD representative to request the document con-
taining further details.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possib le to determine whether a sector is protected
or unprotected. See “Autoselect  Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-s ystem. The
Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly pro-
tected sectors can be programmed or erased by
selecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 2 shows the algo-
rithm, and Figure 22 shows the timing diagrams, for this
feature.
Description Mode CE# OE# WE#
A18
to 
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL X 01h
Device ID: 
Am29SL800C
(Top Boot Block)
Word L L H XXV
ID XLXLH22h EAh
Byte L L H X EAh
Device ID: 
Am29SL800C
(Bottom Boot Block)
Word L L H XXV
ID XLXLH22h 6Bh
Byte L L H X 6Bh
Sector Protection V erification L L H SA X VID XLXHL X01h 
(protected)
X00h 
(unprotected)

14 Am29SL800C

Figure 1. In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

Am29SL800C 15
Figure 2. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not
accept any wr ite cycles. This protects data dur ing VCC
power-up and power-do wn. The command register and
all internal program/er ase circuits are  disabled, and  the
dev ice resets . Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH  or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operati ons . Table 5  defin es  the  v al id regis ter c ommand
sequences. Writing incorrect address and data
values or writing them in the improper sequence
resets the device to reading array data. 
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Charac teristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system 
must
 issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “ Requirements fo r Reading  Arr ay Data”  in  the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command. 
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once 
again.

16 Am29SL800C
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the de vice to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect  command sequence.
Once in the au toselect mode , the r eset command 
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to  access the man uf acture r and devices  codes ,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternativ e to that  shown in Table 4, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A  read cycle at address  XX00h retriev es the
manufacturer code. A read cycle at address 01h in
word mode (or 02h in byte mode) returns the device
code. A read cycle containing a sector address (SA)
and the address 02h in word mode (or 04h in byte
mode) returns 01h if that sector is protected, or 00h if  it
is unprotected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles,  follo wed by t he program set-up  command.
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
syst em is 
not
 required to p rovide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
5 shows the address and data requirements for the
byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the stat us of the prog ram operatio n by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for inform ation on these status bits. 
Any commands written to the device during the
Embedded Progr am Algorithm are ignored.  Note tha t a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure  data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempti ng to do so ma y halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howe ver,  a succeeding read will sho w that the
data is still “0”. Only erase operations can conv ert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
progr am bytes or words to the device fas ter than using
the standard prog ram command sequence.  The unlock
bypass command sequence is initiated by first writing
two unloc k cycles. Thi s is follo wed by a third  write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock  bypass progr am command sequence is  all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the seco nd cycle contains the progr am
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock
Bypass Progr am and Unlock Bypass  Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t cares. The device then returns to reading
array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.

Am29SL800C 17
Note: See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six  b us cy cle oper ation.  The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles ar e then followed b y the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does 
not
 require the system to
preprogram prior  to erase . The Embedded Erase algo-
rithm automatically preprogr ams a nd v e rifies the entire
memor y for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these  operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
har dware r eset during the chip erase oper ation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase oper-
ation by using DQ 7, DQ6, DQ2, or R Y/ BY#. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
dev ice returns to  reading arr a y dat a and addr esses are
no longer latched. 
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cy cles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements f or the sector eras e command sequence.
The device does 
not
 require the system to preprogram
the memory prior to er ase.  The Embedded Erase algo-
rithm automatically progr ams and verifies the s ector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations. 
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase  buffer
may be done in any sequence, and the number of
sectors may  be from one sector t o all sectors. The t ime
between these additional cycles must be less than 50
µs, ot herwise the last address and comman d might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enab led after the las t Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can  monitor DQ3 t o determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All othe r commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has retur ned to
reading array data, to ensure data integrity.
START
Write Program
Command Sequence
Data Poll 
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
 Completed
Increment Address
Embedded
Program
algorithm
 in progress

18 Am29SL800C
When the Embedded Erase algorithm is complete, the
dev ice returns to reading arra y data and addresses are
no longer latched. The system can determine the
status of the er ase operation b y using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to “Write Operat ion Status” for infor-
mation on these status bits.)
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteris tics” section for paramet ers , and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase oper ation, the de vice requires  a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected f or eras ure. (The de vice “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions  apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is activ ely erasing o r is erase-sus-
pended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is com-
plete, t he system can once again read arr ay data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more
information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid  operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the s ector erase oper ati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
START
Write Erase 
Command Sequence
Data Poll 
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded 
Erase
algorithm
in progress

Am29SL800C 19
Command Definitions
Table 5. Am29SL800C Command  Definitions
Legend:
X = Don’t care
RA = Address of the memory locat ion to be read. 
RD = Data read from location RA during read operation.
PA  = Address of the memory location to be programmed. 
Addresses latch on the falling edge of the WE# or CE# pulse, 
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the 
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be v erified (in autoselect mode) or 
erased. Address bits A18–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus 
cycles are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and 
command cycles.
5. Address bits A18–A11 are don’t cares for unlock and 
command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading 
array data, unless SA or PA required.
7. The Reset command is required to return to reading array 
data when device is in the autoselect mode, or if DQ5 
goes high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is 
a read cycle.
9. The data is 00h for an unprotected sector and 01h for a 
protected sector.  See “Autoselect Command Sequence” for 
more information.
10. The Unlock Bypass command is required prior to the 
Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return 
to reading array data when the device is in the unlock 
bypass mode.
12. The system may read and program in non-erasing 
sectors, or enter the autoselect mode, when in the Erase 
Suspend mode. The Erase Suspend command is valid 
only during a sector erase operation.
13. The Erase Resume command is valid only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2-5)
First Second Third  Fourth Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID, 
Top Boot Block  Word 4555 AA 2AA 55 555 90 X01 22EA
Byte AAA 555 AAA X02 EA
Device ID,
Bottom Boot Block Word 4555 AA 2AA 55 555 90 X01 226B
Byte AAA 555 AAA X02 6B
Sector Pro tect Verify 
(Note 9)
Word 4555 AA 2AA 55 555 90
(SA)
X02 XX00
XX01
Byte AAA 555 AAA (SA)
X04 00
01
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 10) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Sus pend (Note 12) 1 XXX B0
Erase Resume (Note 13) 1 XXX 30

20 Am29SL800C

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 6 and the following subsec-

tions describe the functions of these bits. DQ7,

R Y /BY#, and DQ6 e ach offer a method for determining

whether a progr am or er ase operat ion is complete or in

progress . These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded A lgorithm is in prog ress

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete , or if the de v ice enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous t o the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

infor mation on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 i s active for ap pro x imately 100 µs , then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protec ted.

When the system detects DQ7 has changed from the

complement to true data, it can read valid dat a at DQ7–

DQ0 on the

following

read cycles . This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is as serted lo w. Figure 19, Data#

Polling Timings (During Embedded Algorithms), in the

“AC Characteristics” section illustrates this.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

Am29SL800C 21
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC.
If the outpu t is low (Busy ), the de vice is activ ely er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 14, 17
and 18 shows RY/BY# for reset, program, and erase
operations, respecti vely.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I  may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sect or er ase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle (The system may use either OE#
or CE# to control the read cycles). When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for er asing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 6 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 20 in the
“AC Char acteristics” section sho ws the t oggle bit timing
diagrams. Figure 21 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the  Embedded Er ase algo rithm is in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle. 
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. But DQ2 cannot dist inguish whether the s ector is
actively erasing or is erase-suspended. DQ6, by com-
parison, indicates whether the device is actively
erasing,  or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sector and mode informa-
tion. Refer to Table 6 to compare outputs for DQ2 and
DQ6. 
Figure 6 shows the toggle bit algorithm in flowchart
for m, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status,  it must read DQ7–DQ0 at leas t twice in a ro w to
determine whether a toggle bit is toggling. Typically, the
system would note and store th e v alue of  the t oggle bit
after the first read. After the second read, the system
would compare the new value of t he toggle bit with the
first. I f the  toggle bit is not t oggling, the de vice has com-
pleted the prog ram or er ase operation.  The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as  DQ5 went high. If  the toggle bit is  no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the res et command to return
to reading array data. 

22 Am29SL800C

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system ma y contin ue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system t ask s. In this cas e, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the pro gram or er ase cycle w as

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” If the time between additional sector

erase commands from the system can be assumed to

be less than 50 µs, the system need not monitor DQ3.

See also the “Sector Erase Command Sequence”

section.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the c ommand sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the s ystem softw are should chec k the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 6 shows the output s for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

Figure 6. Toggle Bi t Algor ith m

(Notes

1, 2)

(Note 1)

Am29SL800C 23

Table 6. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits”for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Operation DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

24 Am29SL800C

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

A9, OE#,

and RESET# (Note 2) . . . . . . . .–0.5 V to +11.0 V

All other pins (Note 1) . . . . . –0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot VSS to

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC voltage on input or I/O pins is VCC +0.5 V. During

voltage transitions, input or I/O pins may overshoot to VCC

+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may ov ershoot VSS to –2.0 V for periods of up to

20 ns. See . Maximum DC input voltage on pin A9 is +11.0

V which may overshoot to 12.5 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature ( TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature ( TA) . . . . . . . . . –40°C to +85°C

VCC Supply Voltages

VCC, all speed options . . . . . . . . . . . .+1.8 V to +2.2 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

20 ns

0.0 V

–0.5 V

20 ns

–2.0 V

Figure 7. Maximum Negative

Overshoot Waveform

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

Figure 8. Maximum Positive

Overshoot Waveform

Am29SL800C 25
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIH. Typical VCC is 2.0 V.
2. The maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 50 ns.
5. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 11.0 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Notes 1, 2)
CE# = VIL, OE# = VIH,
Byte Mode 5 MHz 5 10
mA
1 MHz 1 3
CE# = VIL, OE# = VIH,
Word Mode 5 MHz 5 10
1 MHz 1 3
ICC2 VCC Active Write Current 
(Notes 2, 3, 5) CE# = VIL, OE# = VIH 20 25 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.2 V 1 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.2 V 1 5 µA
ICC5 Automatic Sleep Mode 
(Notes 2, 3) VIH = VCC ± 0.2 V; 
VIL = VSS ± 0.2 V 15µA
VIL Input Low Voltage –0.5 0.2 x VCC V
VIH Input High Voltage 0.8 x VCC VCC + 0.3 V
VID Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 2.0 V 9.0 11.0 V
VOL1 Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.25 V
VOL2 IOL = 100 µA, VCC = VCC min 0.1 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min  0.7 x VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.1 V
VLKO Low VCC Lock-Out Voltage 
(Note 4) 1.2 1.5 V

26 Am29SL800C

DC CHARACTERISTICS (Continued)

Zero Power Flash

00 500 1000 1500 2000 2500 3000 3500 4000

Supp ly Curr en t in mA

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

12345

Frequency in MHz

Supply Current in mA

Note: T = 25

Figure 10. Typical ICC1 vs. Frequency

1.8 V

2.2 V

Am29SL800C 27

TEST CONDITIONS

Ta ble 7. Test Specifications

Key to Switching Waveforms

Device

Under

Test

Figure 11. Test Setup

Test Condition -100 -120,

-150 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–2.0 V

Input timing measurement

reference levels 1.0 V

Output timing measurement

reference levels 1.0 V

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

2.0 V

0.0 V 1.0 V 1.0 V OutputMeasurement LevelInput

Figure 12. Input Waveforms and Measurement Levels

28 Am29SL800C

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

Parameter

Description

Speed Options

JEDEC Std Test Setup -100 -120 -150 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 100 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 100 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 100 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 35 50 65 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns

tOEH Outp ut Ena ble

Hold Time (Note 1)

Read Min 0 ns

Tog gle and

Data# Polling Min 30 ns

tAXQX tOH Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

Figure 13. Read Operations Timings

Am29SL800C 29

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (see Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (see Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (see Note) Min 200 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

Figure 14. RESET# Timings

30 Am29SL800C

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Description

Speed Options

JEDEC Std -100 -120 -150 Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 10 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 50 60 60 ns

tFHQV BYTE# Switching High to Output Active Min 100 120 150 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Outpu t

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

Figure 15. BYTE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 16. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

Am29SL800C 31

AC CHARACTERISTICS

Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Spe ed Op tion s

JEDEC Std Description -100 -120 -150 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 100 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 50 60 70 ns

tDVWH tDS Data Setup Time Min 50 60 70 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Set up Tim e Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 50 60 70 ns

tWHWL tWPH Write Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 10 µs

Word Typ 12

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

tVCS VCC Set up Tim e Min 5 0 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 200 ns

32 Am29SL800C

AC CHARACTERISTICS

OE#

WE#

CE#

Data

Addresses

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

BUSY

Notes:

1. PA = program address, PD = program data, DOUT is the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

Am29SL800C 33

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

34 Am29SL800C

AC CHARACTERISTICS

WE#

CE#

OE#

High

tOE

High

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = V alid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

Am29SL800C 35

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

tVIDR

10 V

0 or 1.8 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 1.8 V

Figure 22. Temporary Sector Unprotect Timing Diagram

36 Am29SL800C

AC CHARACTERISTICS

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect Timing Diagram

Am29SL800C 37

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

Description

Speed Options

JEDEC Std -100 -120 -150 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 100 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 50 60 70 ns

tDVEH tDS Data Setup Time Min 50 60 70 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Wid th Min 50 60 7 0 n s

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation

(Notes 1, 2) Byte Typ 10 µs

Word Typ 12

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

38 Am29SL800C

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written, DOUT = data written

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

Am29SL800C 39

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 2.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 2 15 s Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 38 s

Byte Programming Time 10 300 µs

Excludes system level

overhead (Note 5)

Word Programming Time 12 360 µs

Chip Programming Time

(Note 3)

Byte Mode 10 80 s

Word Mode 7 60 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE #, and RESE T#) –1.0 V 11.0 V

Input voltage with respect to VSS on all I/O pins –0.5 V VCC + 0.5 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

40 Am29SL800C

PH YS ICAL DIMENSIONS *

TS 048—48-Pin Standard TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering

Dwg rev AA; 10/99

Am29SL800C 41

PH YS ICAL DIMENSIONS

TSR048—48-Pin Reverse TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

42 Am29SL800C

PH YS ICAL DIMENSIONS

FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

6 x 9 mm package

Dwg rev AF; 10/99

Am29SL800C 43

REVISION SUMMARY

Revision A (August 1998)

Initial release.

Revision B (January 1999)

Distinctive Characteristics

Corrected power consumption specifications to match

those in DC Characteristics table.

Connection Diagrams

FBGA diagram now shows top view.

Ordering Information

Added FBGA markings to valid combinations table.

Revision B+1 (March 5, 1999)

Physi cal Dimensions

FBB048: Corrected ball grid la yout in drawing.

Revision C (December 6, 1999)

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18. Chip/Sector

Erase Operations

Deleted tGHWL and changed OE# waveform to star t at

high.

Physi cal Dimensions

Replaced figures with more detailed illustrati ons.

Revision D (February 21, 2000)

Removed “preliminary” designation from data sheet.

Data sheet parameters are now stable; only speed,

package, and temperature range combinations are

expected to change in future revisions.

Added dash to part numbers.

Device Bus Operations table

Changed standby voltage specification to VCC ± 0.2 V.

Standby Mode, RESET#: Hardware Reset Pin

Changed standby voltage specification to VCC ± 0.2 V.

DC Characteristics tab le

Changed test conditions for ICC3, ICC4, ICC5 to VCC ±

0.2 V.

Revision D+1 (May 8, 2000)

Ordering Information

Optional processing

: Deleted the burn-in option

AC Characteristics—Read Operations

Changed tDF to 16 ns for all speeds.

Revision D+2 (November 14, 2000)

Added table of contents. Deleted burn-in option from

Ordering Information section.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification pur poses only and may be trademarks of their respective companies.