RD28F3208W30T70 - Intel Corporation

Intel® 1.8 Volt Wireless Flash Memory

with 3 Volt I/O and SRAM (W30)

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary Datasheet

Product Features

Intel® 1.8 Volt Wireless Flash Memory with 3 Volt I/O combines state-of-the-art Intel® Flash technology

with low power SRAM to provide the most versatile and compact memory solution for high performance,

low power, board constraint memory applications.

Intel® 1.8 Volt Wireless Flash Memory with 3 Volt I/O offers a multi-partition, dual-operation flash

architecture that enables the device to read from one partition while programming or erasing in another

partition. This Read-While-Write or Read-While-Erase capability makes it possible to achieve higher data

throughput rates as compared to single partition devices and it allows two processors to interleave code

execut ion because program and erase operations can now occur as background processes.

Intel® 1.8 Volt Wireless Flash Memory with 3 Volt I/O incorporates a new Enhanced Factory

Prog rammi ng (EFP) mode to im prove 12 V factory programming perfor mance. T his new feature helps

eliminate manufacturing bottlenecks associated with programming high density flash devices. Compare the

EFP program time of 3. 5 µs per w ord to the standar d factory progra m time of 8.0 µs per word and save

significant factory programming time for improved factory efficiency.

Additiona lly, Intel® 1.8 Volt Wirele ss Flash Memory with 3 Volt I/O incl udes block lock-down,

programmable WAIT signal polarity and is supported by an array of software tools. All these features make

thi s product a perfect solution for any demanding memory appl icati on.

■Flash Performa nce

—70 ns Initial Access Sp eed

—25 ns Page-Mode Read Speed

—20 ns Burst-Mode Read Speed

—Burst and Page Mode in All Blocks and

across All Partition Boundaries

—Enhanced Factory Programming:

3.5 µs per Word Program Time

—Programmable F-WAIT Signal Polarity

■Flash Power

—VCC = 1.70 V – 1.90 V

—VCCQ = 2 .20 V – 3.30 V

—Standby Current = 6 µA (typ.)

—Read Current = 7 mA

(4 word burst, typ.)

■Flash Software

—5/9 µs (typ.) Program/Erase Suspend

Latency Time

—Intel® Flash Data Integrator (IFDI) and

Common Flash Interface (CFI)

Compatible

■Quality an d R eliabil i ty

—Operating Temperature:

–25 °C to +85 °C

—100K Minimum Erase Cycles

—0.18 µm ETOX™ VII Process

■Flash Architecture

—Mu ltiple 4- Mbit Partitions

—D ual Operation: RWW or RW E

—Parameter Block Size = 4-Kword

—Main block size = 32-Kword

—Top and Bottom Parameter Devices

■Flash Security

—128-bit Protection Register

—Absolute Write Protection with VPP at

Ground

—Program and Erase Lockout during

Power Transitio ns

—Individual and Instantaneous Block

Locking/Unlocking with Lock-Down

■SRAM

—70 ns Access Speed

—16-bit Data Bus

—Low Voltage Data Retention

—S-VCC = 2.20 V – 3.30 V

■Density and Packaging

—32-Mbit Di screte in a 56-Ball VF BGA

Package (7.7 mm x 9 mm)

—32/4-, 32/ 8-, 64/8- an d 128/ TBD- (F lash

+ SRAM) in a 80-Ball Stacked-CSP

Package (14 mm x 8 mm)

—16-bit Data Bus

290702-001

October 2000

Notice: This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

Preliminary

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 1.8 Volt Intel® Wireless Flash Memory (with 3 Volt I/O and SRAM) may contain design defects or errors known as errata which may cause the

product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

*Other brands and names are the property of their respective owners.

Preliminary iii
 28F320W30, 28F3204W30, 28F3208W30, 28F6408W30
Contents
0 Product Introduction.................................................................................................1
1 Document Purpose................................................................................................1
2 Nomenclature........................................................................................................1
0 Product Description..................................................................................................2
1 Product Overview..................................................................................................2
2 Package Diagram..................................................................................................3
3 Package Dimensions.............................................................................................4
4 Signal Description .................................................................................................5
5 Block Diagram.......................................................................................................6
6 Flash Memory Map................................................................................................6
0 Product Operations...................................................................................................9
1 Bus Operation .......................................................................................................9
2 Flash Command Definitions ..................................................................................9
0 Fl ash Read Modes ...................................................................................................13
1 Read Array..........................................................................................................13
1.1 Asynchronous Mode...............................................................................13
1.2 Synchronous Mode ................................................................................13
2 Set Configuration Register (CR)..........................................................................14
2.1 Read Mode (RM)....................................................................................15
2.2 First Latency Count (LC2–0)..................................................................15
2.3 WAIT Polarit y (WT) ............ ...... ...... ....... ...... ....... ...... .................... ...... ....1 7
2.4 Data Output Configuration (DOC)..........................................................17
2.5 WAIT Configu ratio n (WC)................................... ................... ....... ..........18
2.6 Burst Sequence (BS)..............................................................................19
2.7 Clock Configu ratio n (CC) ......... ...... ....... ...... ....... ...... .................... ...... ....2 0
2.8 Burst Wrap (BW) ....................................................................................20
2.9 Burst Length (BL2–0).............................................................................20
3 Read Query Register...........................................................................................20
4 Read ID Register.................................................................................................21
5 Read Status Register..........................................................................................21
5.1 Clear Status Register.............................................................................23
6 Read-While-Write/Erase......................................................................................23
0 Flash Program Modes............................................................................................24
1 Low Power Programming....................................................................................24
2 High Speed Program mi ng........ ....... ...... ...... ....... ...... ....... ...... ....... ...... .................2 4
3 Enhanced Factory Programming (EFP) ..............................................................25
3.1 EFP Requirements.................................................................................25
3.2 Setup Phase...........................................................................................26
3.3 Program Phase .................. ................... ................... ....... ................... ....2 6
3.4 Verify Phase...........................................................................................26
3.5 Exit Phase..............................................................................................26
4 Write Protection (VPP < VPPLK) ...........................................................................27

28F320W30, 28F3204W30, 28F3208W30, 28F6408W30
iv Preliminary
0 Flash Erase Mode ....................................................................................................27
1 Block Erase.........................................................................................................27
2 Erase Protection (VPP < VPPLK)..........................................................................27
0 Flash Suspend/Resume Modes..........................................................................28
1 Program/Erase Suspend.....................................................................................28
2 Program/Erase Resume......................................................................................28
0 Flash Security Modes.............................................................................................29
1 Block Lock...........................................................................................................29
2 Block Unlock .......................................................................................................29
3 Block Lock-Down ................................................................................................30
4 Block Lock Operations during Erase Suspend....................................................30
5 WP# Lock-Down Control.....................................................................................30
0 Flash Protection Register.....................................................................................31
1 Protecti on Regist er Read...... ...... ....... ...... ...... ....... ................... ....... ................... .31
2 Protecti on Regist er Progra m. ...... ....... ...... ...... ....... ...... ....... ................... ..............31
3 Protecti on Regist er Lock....... ...... ................... ....... ................... .................... ...... .31
0 Power and Reset Considerations......................................................................32
1 Power-Up/Down Characteristics .........................................................................32
2 Power Supply Decoupling...................................................................................32
3 Flash Reset Characteristics ................................................................................32
0 Electr ical Specif ications........................................................................................33
1 Absolute Maximum Ratings ................................................................................33
2 Extend ed Tempe rature Op eration.................. ....... ...... ....... ................... ..............33
3 DC Characteristics..............................................................................................34
4 Discrete Capacitance (32-Mbit VF BGA Package) .............................................36
5 Stacked Capacitance (32/4, 32/8 and 64/8 Stacked-CSP Package) ..................37
0 Flash AC Characteristics......................................................................................38
1 Flash Read Operations.......................................................................................38
2 Flash Write Operations .......................................................................................44
3 Flash Program and Erase Operations.................................................................46
4 Reset Operations ................................................................................................46
0 SRAM AC Characteristics.....................................................................................48
1 SRAM Read Operation .......................................................................................48
2 SRAM Write Operation........................................................................................50
3 SRAM Data Retention Operation........................................................................51
0 Ordering Information..............................................................................................53
Appendix A Flash Write State Machine (WSM)................................................................54
Appendix B Flowcharts.............................................................................................................56
Appendix C Common Flash Interface .................................................................................63

Preliminary v

28F320W30, 28F3204W30, 28F3208W30, 28F6408W30

Revision History

Date of

Revision Version Description

09/19/00 -001 Original Version

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 1

1.0 Product Introduction

1.1 Document Purpose

This document contains information pertaining to the Intel® 1.8 Volt Wireless Flash Memory with

3 Volt I/O and SRAM. Section 1.0 provides a product introduction. Section 2.0 provides a product

description. Section 3.0 describes general device operations. Sections 4.0 through 9.0 describe the

flash functionality. Section 10 describes device power and reset considerations. Section 11.0

describes the device electrical specifications. Section 12.0 describes the flash AC characteristics.

Section 13.0 describes the SRAM AC characteristics. Section 14.0 describes ordering information.

1.2 Nomenclature

•Block: a group of flash bits that share common erase circuitry and erase simultaneously.

•Partition: a group of flash blocks that share common program/erase circuitry and status

partitions.

•To p/Bottom Partition: a group of flash blocks that are located at the top/bottom of the flash

memory map.

•Main Block: a flash block of 32-Kword.

•Parameter Block: a flash block of 4-Kword.

•Main Partition: a partitio n that only contains main blocks.

•Parameter Partition: a partition that contains both main and parameter blocks.

•Top/Bottom Parameter Device: the parameter blocks are located at the top/bottom of the

flash memory map. A top/bottom partition contains 15 blocks; 7 main blocks and 8 parameter

blocks.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

2Preliminary

2.0 Product Description

2.1 Product Overview

Intel® 1.8 Volt W ireless Flash Memory with 3 Volt I/O and SRAM combines flash and SRAM into

one package. The 1.8 Volt Intel® Wi reles s Flash Memory wit h 3 Volt I/O divides th e flash memory

into many separate 4-Mbit partition s. By doing this, the d e vice can perform simultaneous read-

while-write or read-while-erase operations. W ith this new architecture, the 1.8 Volt Intel® Wireless

Flash Memory with 3 Volt I/O can read from one partition while programming or erasing in another

partition. This read-while-write or read-while-erase capability greatly increases data throughput

performance.

Each partition contains eight 32-Kword blocks, called “main blocks.” However , for a top or bottom

parameter device, the upper or lower 32-Kword block is segmented into eight, separate 4-Kword

blocks, called “parameter blocks.” Parameter blocks are ideally suited for frequently updated

variables or boot code storage. Both main and parameter blocks support page and burst mode

reads.

The 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O also incorporates a new Enhanced

Factory Programming (EFP) mode. In EFP mode, this device provides the fastest NOR flash

factory progr amming tim e po ssible at 3 .5 µs per data word . Th is f eature can gr eatly red uce facto ry

flash programming time and thereby increase manufacturing effi ciency.

The 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O offers both hardware and software

forms of data protection. Software can individually lock and unlock any block for “on-the-fly” run-

time data protection. For absolute data protection , all blocks are locked when the VPP voltage falls

below the VPP lockout threshold.

Upon initial power up or return from reset, the 1.8 Volt Intel® Wireless Flash Memory with 3 Volt

I/O defaults to page mode. To enable burst mode, write and configure the configuration register.

While in burst mode , the 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O is synchronized

with the host CPU. Additionally, a confi gur able WAIT signal can be used to provide easy flash-to-

CPU synchronization.

The 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O maintains co mpatibility with Intel®

Command User Interface (CUI), Common Flash Interface (CFI) and Intel® Flash Data Integrator

(IFDI) software tools. CUI is used to control the flash device, CFI is used to ob tain specific product

information, and IFDI is used for data management.

The 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O and SRAM offers two low-power

savings features: Automatic Power Savings (APS) and Standby mode. The flash device

automatically enters APS following the completion of any read cycle. Flash and SRAM standby

modes are enabled when the appropriate chip select signals are de-asserted.

Finally, the 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O provides program and erase

suspend /resume operations to allow system so ftware to s ervice higher priority tas ks . It offers a

128-bit protection register that can be used for unique device identification and/or system security

purposes.

Combined, all these featu res make the 1.8 Volt Intel® Wireless Flash Memory with 3 Vo lt I/O and

SRAM an ideal solution for any high-performance, low-power, board-constrained memory

application.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 3

2.2 Package Diagram

NOTES:

1. On lower density devices, upper address balls can be treated as no connects. For example, on a 32-Mbit device, A23-21 will

be no connects.

Figure 1. 80-Ball Matrix, 0.80 mm Ball Pitch, Stacked-CSP for 32/4-, 32/8-, 64/8- and 128/TBD-

Mbit Devices (Flash + SRAM)

S-V

S-WE# F-CLK A

2 3 4 5 6 7 8

S-LB# A

S-V

S-CS

S-V

F-V

F-WP# A

F-ADV# A

S-UB# F-RST# F-WE# A

F-WAIT DU

S-OE# DQ

S-CS

# F-OE# DQ

F-CE# DU DU S-V

S-V

DU F-V

CCQ

S-V

F-V

SSQ

F-V

CCQ

F-V

S-V

F-V

SSQ

F-V

S-V

F-CLK S-WE# S-V

7 6 5 4 3 2 1

S-V

S-CS

S-V

S-LB# A

F-V

F-ADV#A

F-WP A

F-WE# F-RST# S-UB# A

DU F-WAIT DQ

DU DQ

S-OE#

DU DQ

F-OE S-CE

S-V

F-V

CCQ

DU S-V

S-V

DU DU F-CE#

S-V

F-V

SSQ

S-V

F-V

CCQ

F-V

SSQ

S-V

Top View - Ball Side Down

Complete Ink Mark Not Shown Bottom View - Ball Side Up

DU DU DU

DUDU

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

4Preliminary

NOTE:

1. All balls will be populated; however, addresses A21 and A22 will be NC.

Figure 2. 56-Ball Matrix, 0.75 mm Ball Pitch, VF BGA Package for the 32-Mbit Discrete Device

CLK RST# A

ADV# WE# A

WAIT A

WP# A

CCQ

CE# A

OE#

SSQ

CCQ

SSQ

RST# CLK A

WE# ADV#

WP# D

WAIT A

CE# D

CCQ

OE# D

SSQ

CCQ

SSQ

Top View - Ball Side Down

Complete Ink Mark Not Shown Bottom View - Ball Side Up

8 7 6 5 4 3 2 11 2 3 4 5 6 7 8

2.3 Package Dimensions

Table 1. Package Outline Dimensions

Package

Type Device

Density Dimension-D

(± 0.1 mm) Dimension-E

(± 0.1 mm) Height

(max.) (mm )

VF BGA 32 7.7 9.0 1.00

Stacked-CSP 32/4, 32/8,

64/8 14 8 1.40

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 5

2.4 Signal Description

Table 2. Signal Description (Sheet 1 of 2)

Symbol Type Name and Function

A25–0 IADDRESS: Device address. Addresses are internally latched during read and write cycles.

32-Mbit flash: A20–0; 64-Mbit flash: A21–0; 128-Mbit flash: A22–0; 4-Mbit SRAM: A17–0; 8-Mbit SR AM: A18–0

DQ15–0 I/O DATA: Inputs data and commands during write cycles. Outputs data during read cycles. Data signals float

when the chip or outputs are deselected.

ADV# I FLASH ADDRESS VALID: Internally latches addresses. In page mode, addresses are internally latched on

the rising edge of ADV#. In burst mode, address internally latched on the rising edge of ADV# or rising/

falling edge of CLK, whichever occurs first.

CE# I FLASH CHIP ENABLE: Enables/disables flash device. CE#-low enables the device. CE#-high disables the

device and places the device into standby mode. CE# high places data and WAIT signals at a High-Z level.

S-CS1#I

SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders and sense

amplifiers. S-CS1# is active low. S-CS1# high deselects the SRAM memory device and reduces power

consumption to standby levels.

S-CS2ISRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders and sense

amplifiers. S-CS2 is active high. S-CS2 low deselects the SRAM memory device and reduces power

consumption to standby levels.

CLK I FLASH CLOCK: Synchronizes the device to the system bus frequency. (Used only in burst mode.)

OE# I FLASH OUTPUT ENABLE: Enables/disables device output buffers . OE# low enables the device output

buffers. OE# high disables the device output buffers and places all outputs at a High-Z level.

S-OE# I SRAM OUTPUT ENABLE: Activates the SRAM outputs through the data buffers during a read operation.

S-OE# is active low.

RST# I FLASH RESET: Enables/disables device operation. RST# low initializes internal circuitry and disables

device operation. RST# high enables device operation.

WAIT O FLASH WAIT: Indicates valid data in burst read mode. WAIT is at High-Z until the configuration register bit

CR.10 is set, which also determines its polarity when asserted. WAIT is only active in burst read mode.

WE# I FLASH WRITE ENABLE: Enables/disables device write buffers. WE# low enables the device write buff ers.

Data is latched on the rising edge of WE#. WE# high disables the device write buffers.

S-WE# I S RAM W RITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low .

S-UB# I SRAM UPPER BYTE ENABLE: Enables the upper bytes for SRAM (DQ15-8). S-UB# is active low.

S-LB# I SRAM LOWER BYTE ENABLE: Enables the lower bytes for SRAM (DQ7-0). S-LB# is active low.

WP# I FLASH WRITE PROTECT: Enables/disables the device lock-down function. WP# low enables the lock-

down mechanism and blocks marked lock-down cannot be unlocked by system software. WP# high

disables the lock-down mechanism and blocks m arked lo ck-dow n can be unlocked by system software.

VPP Pwr

FLASH PROGRAM/ERASE POWER: Hardware erase and program protection. A valid VPP voltage on this

ball allows erase or programming. Memory contents cannot be altered when VPP < VPPLK. Block erase and

program at invalid VPP voltages should not be attempted. Set VPP = VCC for in-system read, program, and

erase operations. VPP must remain above V PP1Min t o perform in-system operations. VPP2 can be applied to

main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be VPP2 for a

cumulative total, not to exceed 80 hours maximum. Extended use of this ball at VPP2 may reduce block

cycling capability.

VCC Pwr FLASH POW E R SUPP LY: Flash operations at invalid VCC voltages should not be attempted.

VCCQ Pwr FLASH OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ.

VSS Pwr FLASH POWER SUPPLY GROUND: Balls for internal device circuitry must be connected to system

ground.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

6Preliminary

2.5 Block Diagram

2.6 Flash Memory Map

The 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O memory is divided into separate

partitions to support the read-while-write/erase fun ction. Each partition is 4-Mbits in size and can

operate independently from other partitions.

A 32-Mbit device will have eight partition s; a 64 -Mbit device will have 16 partitions; a

128-Mbit device will have 32 partitions. Each main block is 32-Kword in size.

VSSQ Pwr FLASH OUTPUT POWER SUPPLY GROUND: Balls for internal device circuitry must be connected to

system ground.

S-VCC Pwr SRAM POWER SUPPLY: Device operations at invalid S-VCC voltages should not be attempted.

S-VSS Pwr SRAM GROUND: Balls for all internal device circuitry must be connected to system ground.

DU DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, control signals

and/or any other ball and must be floated.

NC NO CONNECT: No internal connection. Can be driven or floated.

Figure 3. 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O and SRAM Block Diagram

Table 2. Signal Description (Sheet 2 of 2)

Symbol Type Name and Function

32, 64, 128 Mbit

Flash Memory

CE#

OE#

WE#

RST#

WP#

CCQ

4 or 8 Mbit

SRAM

S-SC

S-OE#

S-WE#

S-LB#

S-V

0-17

/ A

0-18

18-20

/ A

19-21

or A

19-22

15-0

ADV#

CLK WAIT

SSQ

S-UB#

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 7

The 1.8 Volt Intel® W ir eless Flas h Memory with 3 Volt I/O support s CPUs th at boot from either t he

top or bottom of the flash memory map. A top parameter flash device has the highest addressable

32-Kword bl ock di vided in to eight smaller blocks. C onversely, a bottom par ameter flash devi ce has

the lowest addressable 32-Kword block divided into eight smaller blocks. Each of these eight 4-

Kword blocks are called parameter blocks. Parameter blocks are useful for frequently stored data

variables. Their smaller block size allows them to erase faster than main blocks. Page- and burst-

mode reads are also permitted in all blocks an d across all partition boun daries.

It should be mentioned that the SRAM does not adhere to this multi-p arti tion architecture. The

SRAM memory is organized as a single memory array.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

8Preliminary

NOTES:

1. Partition size: 4-Mbit/256-Kword/512-Kbytes.

2. Main block size: 32-Kword/64-Kbytes.

3. Parameter block size: 4-Kword/8-Kbytes.

4. All partitions have 8 main blocks, except for top/bottom parameter partitions.

5. Top/bottom parameter partitions have 15 blocks, 7 main and 8 parameter.

Figure 4. Flash Memory Map

Partition 15

8 Blocks

Start - Stop Addr

3F8000 - 3FFFFF

3F0000 - 3F7FFF

3E8000 - 3E7FFF

3E0000 - 3E7FFF

3D8000 - 3D7FFF

3D0000 - 3D7FFF

3C8000 - 3CFFFF

3C0000 - 3C7FFF

4 Mbit

Partition 0

8 Blocks

Start - Stop Addr

38000 - 3FFFF

30000 - 37FFF

28000 - 2FFFF

20000 - 27FFF

18000 - 1FFFF

10000 - 17FFF

08000 - 0FFFF

00000 - 07FFF

Partition 7

8 Blocks

Start - Stop Addr

1F8000 - 1FFFFF

1F0000 - 1F7FFF

1E8000 - 1EFFFF

1E0000 - 1E7FFF

1D8000 - 1DFFFF

1D0000 - 1D7FFF

1C8000 - 1CFFFF

1C0000 - 1C7FFF

Partition 2

8 Main Blocks

80000 - BFFFF

Partition 1

8 Main Blocks

40000 - 7FFFF

8 Mbit

Partition 3

8 Main Blocks

C0000 - FFFFF

12 Mbit

Partition 4

8 Main Blocks

100000 - 13FFFF

16 Mbit

20 Mbit

Partition 5

8 Main Blocks

140000 - 17FFFF

24 Mbit

Partition 6

8 Main Blocks

180000 - 1BFFFF

28 Mbit

32 Mbit 64 Mbit

60 Mbit

Partition 14

8 Main Blocks

380000 - 3BFFFF

Partition 1

8 Main Blocks

40000 - 7FFFF

4 Mbit

8 Mbit

Partition 0

8 Blocks

Start - Stop Addr

38000 - 3FFFF

30000 - 37FFF

28000 - 2FFFF

20000 - 27FFF

18000 - 1FFFF

10000 - 17FFF

08000 - 0FFFF

00000 - 07FFF

xx8000 - xx8FFF

xx9000 - xx9FFF

xA000 - xxAFFF

xxB000 - xxBFFF

xxC000 - xxCFFF

xxD000 - xxDFFF

xxE000 - xxEFFF

xxF000 - xxFFFF

0000 - 0FFF

1000 - 1FFF

2000 - 2FFF

3000 - 3FFF

4000 - 4FFF

5000 - 5FFF

6000 - 6FFF

7000 - 7FFF

Bottom Parameter Device

divides the lowest 32-Kword

main block into eight

4-Kword parameter blocks

Top Parameter Device

divides the highest

32-Kword main block

into eight 4-Kword

parameter blocks

Partition 31

8 Blocks

Start - Stop Addr

7F8000 - 7FFFFF

7F0000 - 7F7FFF

7E8000 - 7E7FFF

7E0000 - 7E7FFF

7D8000 - 7D7FFF

7D0000 - 7D7FFF

7C8000 - 7CFFFF

7C0000 - 7C7FFF

Partition 30

8 Main Blocks

780000 - 7BFFFF

Partition 1

8 Main Blocks

40000 - 7FFFF

Partition 0

8 Blocks

Start - Stop Addr

38000 - 3FFFF

30000 - 37FFF

28000 - 2FFFF

20000 - 27FFF

18000 - 1FFFF

10000 - 17FFF

08000 - 0FFFF

00000 - 07FFF

4 Mbit

8 Mbit

128 Mbit

124 Mbit

8 Main Blocks

Start - Stop Addr

F8000-FFFFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 9

3.0 Product Operations

3.1 Bu s Operation

The 1.8 Volt Intel® Wireless Flash Memory’s on-chip Write State Machine (WSM) manages erase

and program algorithms. The local CPU controls the in-system read, program, and erase operations

of the flash device. Bus cycles to and from the flash device conform to standard microprocessor

bus operations. RST#, CE#, OE#, WE#, and ADV# signals control the flash. WAIT informs the

CPU of valid data during burst reads. S-OE#, S-WE#, S-CS1#, S-CS2, S-LB# and S-UB# control

the SRAM. Table 3 summarizes bus operations.

NOTES:

1. Manufacturer and device ID codes are accessed by Read ID Register command.

2. Query and status register accesses use only DQ7-0. All other accesses use DQ15-0.

3. X must be VIL or VIH for control signals and addresses.

4. Refer to Table 5, “Command Bus Definitions” on page 11 for valid DIN during a write operation.

5. Two devices may not drive the memory bus at the same time.

6. The SRAM can be placed into data retention mode by lowering the S-VCC to the VDR limit when in standby

mode.

7. Always tie S-UB# and S-LB# together.

3.2 Flash Comm and Definitions

Device operations are selected by writing specific commands to the Command User Interface

(CUI). Table 4, “Command Code and Descriptions” on page 10 lists all possible command codes

and d escriptions . Table 5, “Command Bus Definitions” on page 11 further defines command bus

cycle operations . Since co mmands are partition-specific , it is important to write commands within

the target partition range.

Multi-cycle comm a nd writes to the flash m e mory partition must be issued sequentially withou t

intervening comm a nd writes. For example, an Erase Setup command to partition X must be

immediately followed by the Erase Confirm command in order to be executed properly. The

address given during the Erase Confirm comman d determines the location o f the erase. If th e Erase

Confirm command is g iven to partition X, then the command will be executed, and a b lock in

Table 3. Bus Operations

Mode

Note

RST#

CE#

OE#

WE#

ADV#

WAIT

S-CS1#

S-CS2

S-OE#

S-WE#

S-UB#

S-LB#7

[15:0]

FLASH

Read 1,2, 5 VIH VIL VIL VIH VIL Valid SRAM must be in High-Z DOUT

Output Disable 3 VIH VIL VIH VIH X High-Z

Any Valid SRAM Mode

High-Z

Standby 3 VIH VIH X X X High-Z High-Z

Reset 3 VIL X X X X High-Z High-Z

Write 4, 5 VIH VIL VIH VIL VIL High-Z SRAM must be in High Z DIN

SRAM

Read 5 Flash must be in High-Z High-Z VIL VIH VIL VIH VIL DOUT

Output Disable 3

Any Valid FLASH Mode

VIL VIH VIH VIH X High-Z

Standby and

Data Retention 3, 6 VIH X X X X High-Z

IL X X X High-Z

Write 5 Flash must be in High-Z High-Z VIL VIH VIH VIL VIL DIN

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

10 Preliminary

partition X will be erased. Alternatively, if the Erase Confirm command is given to partition Y, the

command will still be executed, and a b lock in partition Y will b e eras ed. Any other command

given to ANY partition prior to the Erase Confirm command will result in a command sequence

error , which is posted in the status register. After the erase has successfully started in partition X or

Y, read cycles can occur in any other partition.

Table 4. Command Code and Descriptions (Sheet 1 of 2)

Mode

Instruction

Code Command Description

Read

FFh Read Array Places addressed partition in read array mode.

70h Read S tatus

read status register mode after a valid Program/Erase command is executed.

90h Read ID Register ,

Read Configuration

Puts the addressed partition in read device identifier mode. The device outputs

manufacturer and device ID codes, configuration register settings, block lock status and

protection register data. Data is output on DQ15-0.

98h Read Query

Interface (CFI) information on DQ7-0.

50h Clear Status

Program

40h Word Program

Setup

The preferred first bus cycle program command that prepares the WSM for a program

operation. The second bus cycle command latches the address and data. A Read Array

command is required to read array data after programming.

10h Alternate Word

Program Setup Equivalent to a Word Program Setup command (40h).

30h Enhanced Factory

Programming

Setup

Activates Enhanced Factory Programming mode (EFP). The first bus cycle sets up the

command. If the second bus cycle is a Confirm command (D0h), subsequent writes provide

program data. All other commands are ignored once EFP mode begins.

D0h Enhanced Factory

Programming

Confirm

If the first command was Enhanced Factory Programming Setup (30h), the CUI latches the

address, confirms command data, and prepares the device for EFP mode.

Erase

20h Block Erase Setup

Prepares the WSM for a block erase operation. The device erases the block addressed by

the Erase Confirm command. If the next command is not Erase Confirm, the CUI

(a) sets status register bits SR.4 and SR.5 to “1,”

(b) places the partition in the read status register mode

D0h Erase Confirm

If the first command was Erase Setup (20h), the WSM latches address and data and erases

the block indicated by the erase confirm cycle address. During program/erase, the partition

responds only to Read St atus Register, Program Suspend, and Erase Suspend commands.

CE# or OE# toggle updates status register data.

Suspend

B0h Program or

Erase Suspend

This command issued at any device address initiates suspension of the currently executing

program/erase operation. The status register, invoked by a Read St atus Register command,

indicates successful operation suspension by setting (1) status bits SR.2 (program suspend)

or SR.6 (erase suspend) and SR.7. The WSM remains in the suspend mode regardless of

control signal states, except RST# = VIL.

D0h Suspend Resume This command issued at any device address resumes suspended program or erase

operation.

Block Locking

60h Lock Setup Prepares the WSM lock configuration. If the next command is not Block-Lock, Unlock, or

Lock-D own the WSM sets SR.4 and SR.5 to indicate command sequence error.

01h Lock Block If the previous command was Lock Setup (60h), the CUI locks the addressed block.

D0h Unlock Block After a Lock Setup (60h) command the CUI latches the address and unlocks the addressed

block. If previously Locked-down, the operation has no effect.

2Fh Lock-Down After a Lock Setup (60h) command, the CUI latches the address and locks-down the

addressed block.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 11

NOTE: Unassigned instruction codes should not be used. Intel reserves the right to redefine these codes for

future functions.

NOTES:

1. First cycle command addresses should be the same as the operation’s target address. Examples: the first-

cycle address for the Read ID Register command should be the same as the Identification Code address

(IA); the first cycle address for the Program command should be the same as the word address (WA) to be

programmed; the first cycle address for the Erase/Program Suspend command should be the same as the

address within the block to be suspended; etc.

XX = Any valid address within the device.

IA = Identification code address.

BA = Address within the block.

LPA = Lock Protection Address is obtained from the CFI (via the Read Query command). Intel 1.8 Volt

Protection

C0h Protection Program

Setup

Prepares the WSM for a protection register program operation. The second bus cycle

latches address and data. To read array data after programming, issue a Read Array

command.

Configuration

60h Configuration

Setup Prepares the WSM for device configuration. If Set Configuration Register is not the next

command, the WSM sets SR.4 and SR.5 to indicate command sequence error .

03h Set Configuration

If the previous command was Configuration Setup (60h), the WSM writes data into the

configuration register via A15-0. Following a Set Configuration Register command,

subsequent read operations access array data.

Table 4. Command Code and Descriptions (Sheet 2 of 2)

Mode

Instruction

Code Command Description

Table 5. Command Bus Definitions

Mode

Command Bus

Cycles

First Bus Cycle Second Bus Cycle

Oper Addr(1) Data(2,3) Oper Addr(1) Data(2,3)

READ

Read Array 1 Write PnA FFh

Read ID Register 2 Write XnA 90h Read XnA+IA IC

Read Query Register 2 Wri te PnA 98h Read PnA+QA QD

Read S tatus Register 2 Write PnA 70h Read BA SRD

Clear S tatus Register 1 Write XX 50h

PROGRAM

ERASE

Block Erase 2 Write BA 20h Write BA D0h

Word Program 2 Write WA 40h/10h Write WA WD

Enhanced Factory Program >2 Write WA 30h Write WA D0h

Program/Erase Suspend 1 Write XX B0h

Program/Erase Resume 1 Write XX D0h

LOCK

Lock Block 2 Write BA 60h Write BA 01h

Unlock Block 2 Write B A 60h Write BA D0h

Lock-Down Block 2 Write BA 60h Write BA 2Fh

PROTEC-

TION

Protection Program 2 Write PA C0h Write PA PD

Lock Protection Program 2 Write LPA C0h Write LPA FFFDh

CONFIG-

URATION

Set Configuration Register 2 Write CD 60h Wri te CD 03h

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

12 Preliminary

Wireless Flash Memory Flash Memory family’s LPA is at 0080h.

PA = User programmable 4-word protection address in the device identification plane.

PnA = Address within the partition.

XnA = Base Address where X can be partition, main block or parameter block. See Figure 11, “Device

Identification Codes” on page 21 for details.

QA = Query code address.

WA = Word address of memory location to be written.

2. SRD = Data read from the status register.

WD = Data to be written at location W A .

IC = Identifier code data.

PD =User programmable 4-word protection data.

QD = Query code data on DQ7-0.

CD = Configuration register code data presented on device addresses A15–0. AMAX-16 address bits can select

any partition

See Table 6, “Configuration Register Bits” on page 14 for configuration register bits

descriptions.

3. Comm ands other than those shown above are reserved by Intel for future device implementations and

should not be used.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 13

4.0 Flash Read Modes

4.1 Read Array

4.1.1 Asynchronous Mode

The 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O supports asynchronous reads. An

asynchronous read is executed by implementing a read operation without the use of the CLK

signal. During an asynchronous read operation, the CLK signal is ignored. If asynchronous reads

will be the only read mode of operation, it is recommended that the CLK signal be held at a valid

VIH level .

Page mode is the default read mode after power-up or reset. A page-mode read outputs 4 words of

asynchronous data; however, by manipulating certain control signals, the device can be made to

output less than 4 words.

After power-up or reset, it is not necessary to execute the Read Array command before accessing

the flash memory. However, to perfor m a flash read at any o t her time, it is necessary to execute th e

Read Array command before accessing the flash memory.

Page mode is permit ted in all blocks, across all p a rtition boundaries and operates independent of

VPP. A single-word read can be used to access register information. During asynchronou s reads, the

address is latched on the rising edge of ADV#.

Upon completion of reading the array, the device automatically enters an Autom atic Power Savings

(APS) mode. APS mode consumes power comparable to standby mode.

4.1.2 Synchronous Mode

The 1.8 Volt Intel® Wireless Flash Memory supports synchronous reads. A synchronous read is

executed by implementing a read operation with the use of the CLK signal. During a synchronous

read operation, the CLK signal edge (rising or falling) controls flash array access.

A burst-mo de read is sy nch r on ized to t he CLK s ignal and out pu t s a 4- , 8- or cont inu ous -word data

stream based on configuration register settings. However, by manipulating certain control signals,

the device can be made to output less then 4-, 8- or continuous-words.

Burst mo de is not the default mo de after power -up or a devi ce reset. To perfor m a burst-mode read,

the configuratio n register must be set. To set the configuration register, refer to Section 4.2, “Set

Configu ration Re gister (CR)” on page 14. After setting the configuration register, if the first device

operation is a burst-mode read, it is not necessary to execute the Read Array command before

accessing the flash memory. However, to perform a flash read at any other time, it is necessary to

execute the Read Array command before accessing the flash memory array.

Burst mode is permitted in all blocks, across all partition boundaries and operates independently of

VPP. A sing l e-word burst - mode read cannot be used to access register information. In burst mode,

the address is latched by either the rising edge of ADV# or the rising edge of CLK with ADV# low ,

whichever occurs first.

Upon completion of reading the array , the device automatically enters an Autom atic Power Savings

(APS) mode. APS mode consumes power comparable to standby mode.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

14 Preliminary

4.2 Set Configuration Register (CR)

The configuration register is 16 bits wide. This register is used to configure all the burst mode

parameters. Therefore, if using page mode, it is not necessary to set this register.

To set the configuration register, execute the Set Configuration Register command. The 16 bits of

data used by this command must be placed on address lines A15–0. A ll other address lines must be

held low (VIL).

After setting the configuration register, if the first device operatio n is a flash burst-mode read, it is

not necessary to execute the Read Array comma nd before accessing the f lash memory. However , to

perform a burst-mode read at any other time, it is necessary to execute the Read Array command

before accessing the flash memory.

NOTES:

1. ‘R’ bits are reserved bits. These bit s and all other address lines must be set low.

2. On power-up or return from reset, all bits are set to “1.”

Table 6. Configuration Register Bits

Configuration Register Bits2

A15 A14 A13 A12 A11 A10 A9A8A7A6A5A4A3A2A1A0

RM R1LC2-0 WT DOC WC BS CC R1R1BW BL2-0

000

Table 7. Configuration Register Bit Settings (Sheet 1 of 2)

Bit Name Setting

Read Mode (RM)

CR.15 0 = Burst or synchronous mode.

1 = Page or asynchronous mode.

First Latency Count (LC2-0)

CR13 – CR.11

Code 0 = 000. Reserved.

Code 1 = 001. Reserved.

Code 2 = 010.

Code 3 = 011.

Code 4 = 100.

Code 5 = 101.

Code 6 = 110. Reserved.

Code 7 = 111. Reserved.

WAIT Polarity (WT)

CR.10 0 = active low signal.

1 = active high signal

Data Output Configuration (DOC)

CR.9 0 = hold data for one clock cycle.

1 = hold data for two clock cycles.

WAIT Configuration (WC)

CR.8

0 = WAIT signal asserted during 16-word row boundary transition.

1 = WAIT signal assert one data cycle before 16-word row boundary

transition.

Burst Sequence (BS)

CR.7 0 = Intel burst sequence.

1 = linear burst sequence.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 15

4.2.1 Read Mode (RM)

CR.15 sets the flash read mode. The two read modes are page mode (default mode) and burst

mode. The flash device can only be configured for one of these modes at any one time.

4.2.2 First Latency Count (LC2–0)

The First Access Latency Count configuration tells the device how many clocks must elapse from

ADV#-high (VIH) before the first data word should be driven onto its data pins. The input clock

frequency determines this value. See Table 8 on page 1 5 for latency values.

Use these equations to calculate First Access Latency Count:

Eq. (1) {1/ Frequency} = CLK Period (ns)

Eq. (2) n ≥ (tAV QV (ns) + tADD-DELAY (ns) + tDATA (ns))/CLK Period

Where ‘n’ is the number of clock periods. If necessary, rounded up.

Eq. (3) First Access Latency Count (LC) = See Table 8.

Clock Configuration (CC)

CR.6 0 = falling edge of clock.

1 = rising edge of clock.

Burst Wrap (BW)vCR.3 0 = Wrap enabled.

1 = Wrap disabled.

Burst Length (BL2-0)

CR.2 – CR.0

001 = 4 Word burst mode.

010 = 8 Word burst mode.

011 = Reserved.

111 = Continuous burst mode.

Table 7. Configuration Register Bit Settings (Sheet 2 of 2)

Bit Name Setting

Table 8. First Latency Count (LC)

LC Setting Mode Wrap Aligned to 4-word

Boundary Wait Asserted on 16-Word

Boundary Crossing

n-1 4 or 8 disabled no yes, occurs on every occurrence

n-2 4 or 8 disabled yes no

n-2 4 or 8 enabled no no

n-2 4 or 8 enabled yes no

n-1 cont inuous X X yes, occurs once

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

16 Preliminary

NOTE:

1. The 16-word boundary is the end of device word-line.

Parameters defined by CPU:

tADD-DELAY = Clock to CE#, ADV#, or Address Valid whichever occurs last.

tDATA = Data set up to Clo c k .

Parameters defined by f la sh:

tAVQV = Address to Output Delay

Example:

CPU Clock Speed = 40 MHz

tADD-DELAY = 6 ns (typical speed from CPU) (max)

tDATA = 4 ns (typical speed from CPU) (min)

tAVQV = 70 ns (from AC Characteristic - Read Only Operations Table)

From Eq. (1) 1/40 (MHz) = 25 ns

From Eq. (2) n(25 ns) ≥ 70 ns + 6 ns + 4 ns

n(25 ns) ≥ 80 ns

n ≥ 80/25 = 3.2 --> 4 (Integer)

From Eq. (3) n - 2 = 4 - 2 = 2

First Access Laten c y Count Setting to the CR is Code 2.

(Figure 6, “Data Output with LC Setting at Code 2” on page 17 displa ys

example data)

The formula tAVQV (ns) + tADD-DELAY (ns) + tDATA (ns) is also known as initial access time.

Figur e 6 shows the data output available and valid after f our latencies from ADV# going low in the

first clock period with the LC setting at 2 .

Figure 5. Word Boundary

0123456789ABCDEF

16 Word Boundary

Word 0 - 3 Word 4 - 7 Word 8 - B Word C - F

4 Word Boundary

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 17

4.2.3 WAIT Polarity (WT)

CR.10 sets the WAIT signal polarity to either an active high or active low mode of operation. After

powerup o r reset, WAIT defaults to an act ive low mode of op eration. To set WAIT to an activ e high

mode of operation, set CR.10. The WAIT signal is only asserted (i.e., active high or active low)

during burst-mode reads. At all other times, WAIT is in a High-Z state. The WAIT signal is not a

valid signal during asynchronous read operations.

4.2.4 Data Output Configuration (DOC)

CR.9 sets the data hold time. The data hold time determines the numbers of clock edges the output

data will be held val id. Data o ut put can be held for either one or two clock cycles. To determine if

the system can support burst-mode reads with zero-wait between subsequent reads, equation 4

must be true.

Eq. (4) (tCHQV + tDATA + tSYS) < (CLK Period)

Where tDATA is data setup time of the interfacing processo r in nan oseconds; tCHQV is the flash

data output hold time and t SYS is the system overh ead time in nanosecond s. t SYS is typically

1–3 ns.

If equation 4 is true, the data o utput hold time can b e set to one (1). If equation 4 is false, the data

output hold tim e must be set to two (2).

Figure 6. Data Output with LC Setting at Code 2

MAX-0

15-0

(D/Q)

CLK (C)

CE#

ADV#

Valid

Output

High Z

ADD

DATA

2nd1st 3rd 4th 5th

Val id Addres s

Code 2

R103

Valid

Output

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

18 Preliminary

4.2.5 WAIT Conf ig uration (WC)

CR.8 sets the WAIT signal delay. The WAIT signal delay determines when the WAIT signal is

asserted. The WAIT signal can be asserted either one clock before or at the time of the misaligned

16-word boundary crossing. An asserted WAIT signal indicates invalid data on the data bus.

In synchronous mode, WAIT is active when CE# is asserted. The WAIT signal is asserted if a

burst-mode read is misaligned to a 4-word boundary. By misaligned, we imply that the address

must be on a mod-4 boundary; such as xx00h, xx04h, xx08h or xx0Ch. If the address is aligned to

a 4-word boundary, the “delay” will never be seen. Also, a “delay” will only occur once per burst -

mode read sequence. When a misaligned burst-mode read crosses a 16-word boundary, the device

must deselect one row in order to select the next row. It is this selecting/de-selecting (or ener gizing/

de-energizing) of memory rows that causes the device to “delay” output data. It is the assertion of

the WAIT signal that informs the interfacing processor of this pending flash “delay.” During the

“delay,” subsequent data reads are prohibited.

The WAIT signal is asserted depending on the burst starting address and latency count. If the

starting address is aligned to the 4-word boundary, a delay will not occur. If the starting address is

aligned to the end of a 4-word boundary, a delay equal to one clock cycle less than the latency

count will occur (worst case scenario). See Table 9, “WAIT Delay” on page 19. If the starting

address falls between, the delay will be dependent upon the latency count value and the starting

address as indicated in Table 9.

In 4- and 8-word burst m odes with burst wrap enabled, the device will not assert the WAIT signal.

However , with the burst wrap disabled, the flash device will assert the WAIT signal if a burst-mode

read is misaligned and crosses a 16-word bound ary. With wrap disabled, the b urst mode will read 4

or 8 consecutive words based o n th e initial address. If the initial address is aligned on a mod-4

boundary, the WAIT sign a l will not be asserted. However, if the initial address is misalign ed on a

mod-4 boundary and crosses the 16-word boundary limit, the WAIT signal will be asserted.

In continuous- word burst mode, the bur st wrap feature do es not apply and the WAIT signal is only

asserted on the first 16-word boundary crossing. The WAIT signal is inactive or at a High-Z state

when accessing register information.

Figure 7. Data Hold Example

15-0

[D/Q]

CLK [C]

Valid

Output Valid

Output

15-0

[D/Q]

Valid

Output

Valid

Output

1 CLK

Data Hold

2 CLK

Data Hold

OUT_CONF.WMF

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 19

Table 9. WAIT Delay

4.2.6 Burst Sequence (BS)

CR.7 sets the burs t sequen ce. The bur st se quence de termines t he 4- o r 8-word output o rder. In 4 - or

8-word burst modes, the burst sequence is defined as either linear or Intel. In continuous burst

mode, the burst sequence is always linear. The burst sequence depends on the interfacing

processor ’s characteristics.

Starting Burst Address WAIT Delay in Clock Cycles After

Crossing 16-Word Boundary 4-Word Boundary

xx0h, xx4h, xx8h, xxCh No Delay Start of Boundary

xx1h, xx5h, xx9h, xxDh LC - 3

xx2h, xx6h, xxAh, xxEh LC - 2

xx3h, xx7h, xxBh, xxFh LC - 1 End of Boundary

Table 10. Sequence and Burst Length (Sheet 1 of 2)

Start Addr

(Decimal) Wrap

(CR.3)

Burst Addressing Sequence (Decimal)

4-Word Burst

Length

(CR2-0 = 001)

8-Word Burst Length

(CR2-0 = 010) Continuous Burst

(CR2-0 = 111)

Linear Intel Linear Intel Linear

0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-...

1 0 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-...

2 0 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-...

3 0 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-...

40 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-...

50 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-...

60 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-...

70 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-...

...

14 0 14-15-16-17-18-19-20-

...

15 0 15-16-17-18-19-20-21-

...

0 1 0-1-2-3 NA 0-1-2-3-4-5-6-7 NA 0-1-2-3-4-5-6-...

1 1 1-2-3-4 NA 1-2-3-4-5-6-7-8 NA 1-2-3-4-5-6-7-...

2 1 2-3-4-5 NA 2-3-4-5-6-7-8-9 NA 2-3-4-5-6-7-8-...

3 1 3-4-5-6 NA 3-4-5-6-7-8-9-10 NA 3-4-5-6-7-8-9-...

41 4-5-6-7-8-9-10-11 NA 4-5-6-7-8-9-10-...

51 5-6-7-8-9-10-11-12 NA 5-6-7-8-9-10-11-...

61 6-7-8-9-10-11-12-13 NA 6-7-8-9-10-11-12-...

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

20 Preliminary

4.2.7 Clock Configuration (CC)

CR.6 sets the clock configuration. The clock con figur ation determines which edge of the clock the

flash devi ce w ill respond to while in bu rst mode. The device can be configured to either track on

the rising or fallin g edge of the clock.

4.2.8 Burst Wrap (BW)

CR.3 sets the burst wrap. The b urst wrap determ ines how th e dev ice will h and le a bu rst-mod e read

that crosses a 16-word row boundary. W rap can be set to have either the burst mode wrap around to

the same row or have the burst read consecutive addresses.

Wrap applies to 4- and 8-word burst modes only. Wrap has no effect in continuous burst mode. In

4- and 8-word b urs t mode with wrap enabled, the WAIT sign al will not be asserted. In 4- and 8 -

word burst mode with wrap disabled, the WAIT signal will b e asserted only if a 16-word row

boundary is crossed.

4.2.9 Burst Length (BL2–0)

CR.2–CR.0 sets the bur st length . The burst l ength determ ines the max imum number of con secutive

words the device will out put during a burst-mode read. 1.8 Volt Intel ® W ireless Flash Memory with

3 Volt I/O supports 4-, 8- and continuous-word burst lengths.

4.3 Read Query Register

The query register contains an assortment of flash product information such as block size, density,

allowable command sets, electrical specifications and other product information. The data

contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any

information from the query register, execute the Read Query Register command. Refer to

Appendix B for a deta iled expl anation o f the CFI register. Inf ormatio n contained in this register can

only be accessed by executing a single-word asynchronous read.

71 7-8-9-10-11-12-13-

14 NA 7-8-9-10-11-12-13-...

...

14 1 14-15-16-17-18-19-20-

...

15 1 15-16-17-18-19-20-21-

...

Table 10. Sequence and Burst Length (Sheet 2 of 2)

Start Addr

(Decimal) Wrap

(CR.3)

Burst Addressing Sequence (Decimal)

4-Word Burst

Length

(CR2-0 = 001)

8-Word Burst Length

(CR2-0 = 010) Continuous Burst

(CR2-0 = 111)

Linear Intel Linear Intel Linear

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 21

4.4 Read ID Register

The Identification (ID) Register contains various product information, such as manufacturer ID,

device ID, block lock status, protection register information, and configuration register settings. To

obtain any information from the ID register, execute the Read ID Register command. Information

contained in this register can only be accessed by executing a single-word asynchronous read.

NOTES:

1. PBA = Partition Base Address. PBA = AMAX - 18 .

2. MBBA = Main Block Base Address. MBBA = AMAX - 15.

3. PBBA = Par amet e r Block Bas e Address. PBBA = A MAX - 12.

4. See the Block Lock St atus section for valid lock status.

5. CD = Configuration Register Settings.

6. PR-LK = Protection Register Lock status.

7. PR = Protection Register data.

4.5 Read Status Register

The status register is 8 bits wide. The status register contains information pertaining to the current

condition of the flash devi ce and its p a rt itions. To determine a partition’s status, execute the Read

Status Register command. To read status register data, execute a signal-wo rd asynchro nous read. A

status register bit is considered set if its value is a one (1) and cleared if its value is a zero (0).

Status re gister data is output on DQ7–0; DQ15–8 outputs 0 0h . Each partition h a s its own stat us

word asynchronous read.

Table 11. Device Identification Codes

Item Address(1,2,3) Data

Manufacturer Code PBA + 0 0089h

Device Code:

32 Mbit - T PBA + 1 8852h

- B 8853h

64 Mbit - T PBA + 1 8854h

- B 8855h

128 Mbit - T PBA + 1 8856h

- B 8857h

Block Lock Configuration(4) MBBA + 2

PBBA + 2,

depends on block

• Block Is Unlocked DQ0 = 0

• Block Is Locked DQ0 = 1

• Block Is Not Locked-Down DQ1 = 0

• Block Is Locked-Down DQ1 = 1

Configuration Register Settings PBA + 5 CD(5)

Protection Register Lock Status PBA + 80h PR-LK(6)

Protection Register Data PBA + 81h - 88h P R(7)

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

22 Preliminary

Table 12. Status Register Definitions

DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0

DWS ESS ES PS VPPS PSS DPS PWS

SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0

SR bit Bit Name NOTES

SR.7 Device WSM S tatus (DWS) 0 = Device busy with a program or erase operation.

1 = Device ready.

For EF P, see Table 13.

SR.6 Erase Suspend Status (ESS) 0 = No erase operation, if any, is being suspended.

1 = An erase operation is being suspended.

SR.5 Erase Suspend (ES) 0 = Block erase successful.

1 = Block erase error. One of three bits set to indicate a command sequence

error.

SR.4 Program Status (PS) 0 = Word program successful.

1 = Word program error. One of three bits set to indicate a command sequence

error.

SR.3 VPP Status (VPPS)

0 = VPP voltage level > VPPLK.

1 = VPP voltage level < VPPLK. Hardware program/erase lockout.

Note: This bit does not provide continuous VPP feedback. Signal functionality is

not guaranteed when VPP ≠ VPP1 or VPP2.

SR.2 Program Suspend Status (PSS) 0 = No program operation, if any, is being suspended.

1 = A program operation is being suspended.

SR.1 Devi ce Protect Status (DPS) 0 = Block unlocked.

1 = An erase or program operation was attempted on a locked block. WP# = VIL.

SR.0 Partiti on Writ e/Erase St atus (PWS) 0 = No other partition is busy.

1 = Another partition is busy performing an erase or program operation.

For EF P, see Table 13.

Table 13. Status Register DWS and PWS Description

DWS

(SR.7) PWS

(SR.0) Description

Normal Mode: Addressed partition is performing a program/erase operation. No other partition is active.

EFP Mode: Device has finished programming/verifying data.

Normal Mode: A partition other than the one currently addressed is performing a program/erase operation.

EFP Mode: Device is either programming or verifying data.

Normal Mode: No program/erase operation in progress in any partition. Program/erase suspend bits (SR.6

and SR.2) indicate whether other partitions are suspended.

EFP Mode: Device has exited EFP mode.

Normal mode: Won’t occur.

EFP Mode: VPP or block-lock error.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 23

4.5.1 Clear Status Register

To clear the status register, execute the Clear Status Register command. When the status register is

cleared, only bits 1, 3, 4, an d 5 are cleared. A status r egister bit is considered set if its value is a one

(1) and cleared if its value is a zero (0). Since bits 0, 2, 6 and 7 indicated different error conditions

and/or device states, these bits can only be set and cleared by th e WSM and are no t cleared wh en a

Clear Status Register comm and is given. The status register should be cleared before implementing

any program or erase operations. After executing the Clear Status Register command, the device

returns to read array mode. A device reset also clears the status register.

4.6 Read-While-Write/Erase

1.8 Volt Intel® Wireless Flash Memory supports a new flash multi-partition architecture. By

dividing the flash memory into many separate partitions, the device is capable of reading from one

partition while programing or erasing in another partition; hence the terms, Read-While-Write

(RWW) and Read-While-Erase (RWE). Both of these features greatly enhance flash data storage

performance.

To perform a RWW operation, execu te the Word Program command to one partition. While this

operation is being performed by the flash WSM, execute the Read Array command to another

partition.

To perform a RWE operation, execute the Block Erase com mand to one partition. While this

operation is being performed by the flash WSM, execute the Read Array command to another

partition.

1.8 Volt Intel® Wireless Flash Memory does not support simultaneous program and erase

operations. Attempting to perform operations such as these will result in a command sequence

error. Only one partition may be programming or erasing while another partition is reading.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

24 Preliminary

5.0 Flash Program Modes

5.1 Low Power Programming

Lower power programming is obtained when VPP is within the VPP1 range. Flash programing is

performed on a word-by-word basis; therefore, only one word may be programmed at any given

time.

To program a word into the flash memory, execute the Word Program command. To determine the

status of a word program, poll the status register and analyze the bits.

If the flash device is pu t in standby mod e duri ng a program operation, the dev ice will co ntinue to

program the word u nt il the operation is complete; then the device will enter stand by mode.

Refer t o Figure 26, “P rogramm ing Flowchart ” on page 56 for a detailed flow on how to implement

a word program operation.

5.2 High Speed Programming

High speed pr ogramming is obtained when V PP is within the VPP2 range. This mode is intended for

factory programming applications only and is not recommended for extended use. VPP may be

connected to VPP2 for a maximum total of 80 hours. Stressing the device beyond this limit may

cause premature device degradation.

When VPP = VPP2, the device draws program current directly from the VPP supply. Figure 8,

“Example of VPP Power S upply Configurations” on page 25 shows examples of flash power

supply usage in various configurations.

Flash programing is performed on a word-by-word basis; therefore, only one word may be

programmed at any given time.

To program a word into the flash memory, execute the Word Program command. To determine the

status of a word program, poll the status register and analyze the bits.

If the device is put in standby mode during a program operation, the device will con tinue to

program the word u nt il the operation is complete; then the device will enter stand by mode.

Refer t o Figure 26, “P rogramm ing Flowchart ” on page 56 for a detailed flow on how to implement

a word program operation.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 25

NOTE: If the VCC supply can sink adequate current, an appropriately valued resistor can be used.

5.3 E nhanced Factory Programm ing (EFP)

Intel introduces a new Enhanced Factory Programming (EFP) mode that substantially reduces the

convention a l 12 volt facto ry programmin g t i me associated wit h p rog rammi ng t oday ’s h i gh dens i ty

flash devices. By implementing a combination of Write State Machine (WSM) changes, the device

is capable of programming an entire block with a single CUI command. Additionally , while in EFP

mode, the device internally increments the memory address; thereby eliminating the need for the

host programmer to continuously update the address to be programmed.

The EFP operation consists of fo ur phases. Each phase mu st be executed cor rectly to ensure prop er

EFP implementation. Refer to Figure 28, “En hance d F actory Program F lowchart ” on pag e 58 for a

detailed flowchart on how to implement an EFP operation.

5.3.1 EFP Requirements

To ensure proper EFP op e ration, these conditions must be met:

•Device operating temperature must be 25 °C, ±5 °C.

•VCC must be within the specified operating range.

•VPP must be within the specified VPP2 operating range.

•The block must be unlocked.

•Only one block can be programmed at a time.

•EFP does not support suspend/resume operations.

•EFP does not support read-while-write/erase operations.

•For optimal EFP performance, it is recommended to cy cle (i.e. progr am in EFP mode and th en

erase) a block no more then ten times. Excessive EFP cycling may cause some performance

degradation due to overstressed conditions. However, if excessive cycling does occur, all

device ope rations wil l continue to func tion.

Figure 8. Example of VPP Power Supply Configurations

•

12 V fast programm i ng

•

Absolute write protection with V

≤

PPLK

System supply

(Note 1)

12 V supply

•

Low voltage and 12 V fast programming

System supply

12 V supply

•

Low-voltage programming

•

Absolut e write protection via logic signal

System supply V

Prot# (logic signal)

•

Low-voltage programming

System supply V

≤

10K

Ω

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

26 Preliminary

5.3.2 Setup Phase

To program a block in EFP mode, execute the Enhanced Factory Program command. There is an

initial delay associated with issuing the EFP command. This delay is needed to allow the device to

check for a valid V PP2 lev el and t o dete rmine th e bl ock l ock st atus . To determine the devi ce st at us,

poll the status register. If a proper VPP2 level does not ex ist and/or the block is locked, an error is

set in the st atus register and the EFP operati on is terminated.

5.3.3 Program Phase

After a successful EFP Setup, the device is ready for data-streaming where subsequent data writes

to the flash device program subsequent words within a block. The host programmer must poll the

status register for a ‘Program Done’ (SR.0 = 0) before proceeding to the next data word.

The address supplied for all data-stream writes must remain within the target block. The address

can either be held constant or incremen t within the block’s address range. The device compares the

setup and confirm address with the corresponding address bits of each successive data streaming

write. If the block address matches the stored address given during the setup and confirm

command, the device will program a new data word. If the block address differs, the device jumps

to the new address location. If the address is outside the target block range, EFP terminates the

program phase and enters the verify phase.

The program phase terminates when the interfacing pro grammer writes to a b lock address dif ferent

from that of the EFP setup command; data must be FFFFh. Upon program phase termination, the

device then enters the EFP verify phase.

5.3.4 Verify Phase

A high percentage of t he flash bits pr ogram on t he first attemp t. However, for those bits that do not

completely prog ram on the first attempt, the EPF verify phase identifies these bits and ap plies

additional program pulses.

The verify phase is identical in flow to the program phase except that instead of programming data,

the device compares the incoming data with the data already programmed in the device during the

program phase. If the data comparison is correct, then proceed to the next word. However, if the

comparison is incorrect, the device applies additional program pulses to the appropriate bits.

The host programmer must reset its initial verify-word address to the address used when the EFP

setup and confirm command was issued in the setup phase. The host programmer then reissues

each data word in the same order that it did during the program phase. The host programmer may

write each word to the initial verify-word address (WA0) or incremen t the ad dress within the block

address range.

The verify phase terminates when the in terfacing programmer writes a block ad dress different f rom

that of the EFP setup command; data must be FFFFh. Upon verify phase termination, the device

then enters the EFP exit phase.

5.3.5 Exit Phase

The status register indicates (SR.7 = 1) when the device returns to a n ormal oper atin g mode. A fu ll

status register check should be performed to ensure the block programmed correctly. After exiting

EFP mode, any valid CUI command can be issued.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 27

5.4 Write Protection (VPP < VPPLK)

If the VPP voltage is below the VPP lockout threshold, word programming is prohibited. To ensure

a proper word p rogram operati on, VPP must be set to one of the two valid VPP ranges. T o determine

the status of a word program, poll the status register and analyze the bits.

When VPP is at VPP1, program currents are drawn through the VCC supply. If VPP is driven by a

logic signal, VPP1 must remain above the VPP1 minimu m valu e in or der to progr am erase mode.

6.0 Flash Erase Mode

6.1 Block Erase

Flash erasing is performed on a block-by-block basis; therefore, only one block may be erased at

any given time. Once a block is erased, all bits within that block will read as a logic level one (1).

To erase a block, execute the Block Erase command. To determine the status of a block erase, poll

the status register and analyze the bits.

If the device is put in standby mode during an erase operation, the device will continue to erase

until to operation is complete; then it will en ter standby mode.

Refer t o Figure 29, “Block Erase Flowch art” on page 59 for a detailed flow on h ow to implement a

block erase operation.

6.2 Erase Protection (VPP < VPPLK)

If the VPP voltage is below the VPP lockout threshold voltage, block erasure is prohibited. To

ensure a proper block erase operation, VPP must be set to one of the two valid VPP levels. To

determine the status of a block erase, poll the status register and analyze the bits.

When VPP is at VPP1, erase currents are drawn through the VCC supply. If VPP is driven by a logic

signal, VPP1 must remain above the VPP1 minimum value in order to erase a block.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

28 Preliminary

7.0 Flash Suspend/Resume Modes

7.1 Program/Erase Suspend

To execute a program or erase suspend, execute the Program/Erase Suspend command. A suspend

operation halts any in-progress word programming or block erase operation. The Suspend

command can be written to any device address, and the partition being addressed remains in its

previous command state. A Suspend command allows data to be accessed from any memory

location other than those suspended.

A program operation can be suspended to perform a device read. An erase operation can be

suspended to perform either a word program or a device read within any block, except the block

that is suspended. A program operation nested within an erase suspend op eration can be suspende d

to read the flash device. Once th e program/erase process star ts, a suspend o peration can on ly o ccur

at certain points in the program/erase algorithm. Erase suspend operations cannot resum e until

program operations initiated during the erase suspend are complete. All device read functions are

permitted during a susp end operation.

Durin g a su spend, VPP must remain at a valid program level and WP# must not change. Also, a

minimum amount of time is required between issuing a Program or Erase command and then

issuing a Suspend command.

7.2 Program/Erase Resume

To resume (i.e., continue) a program or erase suspend operation, execute the Program/Erase

Resume command. The Resume command can be written to any device address. See Figure 27,

“Program Suspend/Resume Flowchart” on page 57 and Figure 30, “Erase Suspend/Resume

Flowchart” on page 60.

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 29

8.0 Flash Security Modes

The 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O offers both hardware and software

security features to protect the flash data. The software security feature is used by executing the

Lock Block command. The hardware security feature is used by executing the Lock-Down Block

command AND by asserting the WP# and VPP signals.

For details on VPP data security, refer to Section 5.4, “W rite Protection (VPP < VPPLK)” on page 27

and Secti on 6.2 , “Erase Protecti on ( VPP < VPPLK)” on page 27. Refer to Figure 9, “Block Locking

State Diagram for a state diagram of the flash security features. Also see Figure 31, “Locking

Operations Flowchart” on page 61.

NOTES:

1. The notation (X,Y,Z) denotes the locking state of a block, The current locking state of a block is defined by the

state of WP# and the two bits of the block-lock status DQ1-0.

2. Solid line indicates WP# asserted (low). Dashed line indicates WP# unasserted (high).

8.1 Block Lock

All blocks default to a locked state after power-up or device reset. Locked blocks cannot be

programmed or erased , but can be read. Attempts to program or erase a locked b lock will result in

an error that will be indicated in the status register. To lock a block, execute the Lock Block

command. To lock a block that has been previously locked-down, de-assert WP#. A block lock

status can be read by executing the Read ID Register command. Refer to Section 4.4, “Read ID

8.2 Block Unlock

Unlocked blocks can be read, programmed, erased and suspended. To unlock a locked block,

execute the Unlock Block command. To unlock a locked-down block, unassert WP# then use the

Unlock Block command. All unlocked blocks revert to a locked state during power-up or device

reset.

Figure 9. Block Locking State Diagram

Power-up

Reset

Block

Locked

Block

Unlocked

Block

Locked-

Down

(001)

(101)

Unlock Cmd

(000)

Initial Lock-Down Cmd

or Assert WP #

(011)

Lock Cmd

(001)

Unassert WP#

(111)

Initial Lock-Down Cmd

or Assert WP#

(011)

(X) (Y) (Z)

WP# DQ

Block Status

0 0 0 unlocked

0 0 1 locked; default

0 1 0 invalid

0 1 1 locked down

1 0 0 unlocked

1 0 1 locked

1 1 0 unlocked

1 1 1 locked

Notes: 1.) X = WP# = write protect signal.

2.) Y = DQ

= Lock-down status.

3.) Z = DQ

= Lock status.

Unlock Cmd

(110)

(101)

(100)

Lock Cmd

(101)

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

30 Preliminary

8.3 Block Lock-Down

Locked-down blocks cannot be programmed or erased, but can be read. With WP# asserted, a

locked-down block cannot be unlocked by the Unlock Block command. Attempts to program or

erase a locked-down block will result in an error that will be indicated in the status register . To lock

down a block, WP# must be asserted (i.e., low) and the Lock-Down Block command must be

issued to that block.

If WP# is not ass ert ed (i.e., high) , l ock ed-d own bl o cks rev ert to a locked st at e an d can be unlocked

by the Unlock Block command. Locked-down blocks revert to the locked state at device reset or

power-down. When a block is lo cked-down, th e bloc k lock status bit will also be set. Blocks that

were previously locked-down using the Lock-Down command, but are now locked or unlocked

due to WP# being high, revert to a locked-down state when WP# is asserted.

8.4 Block Lock Operations during Erase Suspend

Blocks can be locked and locked-down during an erase suspend operation, but the locking

mechanism does not take effect until after the block erase has resumed and is fully completed.

Therefore, once the block erase suspend/resume operation is complete, the block will transition to a

locked or locked-down state. If a block is locked or locked-down during an erase suspended

operation, the block lock status will indicate a locked block. But again, the locking mechanism

does not g e t set until after the su spend/resume operation is complete.

8.5 WP# Lock-Down Control

The WP# signal is used to control the block lock-down function. If WP# is ass e rted (i.e., low), the

lock-down function is enabled and a block can be locked-down by using the Block Lock-Down

command. A locked-do wn block cannot be progr ammed or erased, but can be read. A locked -down

block with WP# assert cannot be unlocked by the Unlock Block command. To unlock a locked-

down block, unassert WP# (i.e., high) to disable the lock-down function. By unasserting WP#, all

locked-down blocks revert to a locked state. From the locked state, a block can be unlocked using

the Unlock Block command. Blocks can then be locked and unlocked while WP# remains high.

However, when WP# goes low, previously locked-down blocks return to the lock-down state,

regardless of cha nges made whi l e WP # was high. A dev ice r eset or p ower-down reverts all lo cked-

down blocks to the locked state. See Table 14.

Table 14. Write Protection Truth Table

VPP WP# RST# Write Protectio n

XXV

IL Reset mode, device Inaccessible

VIL XV

IH Program and Erase Prohibited

> VPPLK VIL VIH All Lock-down Blocks are Locked

>VPPLK VIH VIH All Lock-down Blocks are Unlockable

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 31

9.0 Flash Protection Register

The 1.8 Volt Intel® Wireless Flash Memory includes a 128-bit protection register. This protection

bits within the protection register are programmed by Intel with a unique number in each flash

device. The upper 64 bits within the protection register are left for the customer to program. Once

protection register bits are programmed, they can never be erased.

9.1 Protection Register Read

To read the contents of the protection register, execute the Read ID Register command. See

Table 11, “Device Identification Codes” on page 21 .

9.2 Protection Register Program

To program the customer portion of the protection register (upper 64 bits), execute the Protection

Program command. Th e Protection Program command must be executed at the lowest addressable

partition and programs 16 bits at a time. Execu ting this command at any othe r partition, or at an

already locked protection register, will result in a program error. See Table 15 and Figu re 32 ,

“Protection Register Programming Flowchart” on page 62.

NOTE: Addresses A17–A8 should be set to zero. AMAX–A18 = partition base address (PBA).

9.3 Protection Register Lock

The user-programmable portion of the protection register is lockable by executing the Lock

Protection Program command. Bit-0 of the protection lock word is programmed at the Intel factory

to lock in the unique device number. Bit-1 of the protection lock word can be programmed by the

user to lock the upper 64-bit portion.

After the lock protection bit is set by th e user, no further change s can be made to the protection

Table 15. Protection Register Addressing

Word U se ID Offset A7A6A5A4A3A2A1A0Word

LOCK Both PBA+000080h 1 0 0 0 0 0 0 0 LOCK

0 Intel PBA+000081h 1 0 0 0 0 0 0 1 0

1 Intel PBA+000082h 1 0 0 0 0 0 1 0 1

2 Intel PBA+000083h 1 0 0 0 0 0 1 1 2

3 Intel PBA+000084h 1 0 0 0 0 1 0 0 3

4 Customer PBA+000085h 1 0 0 0 0 1 0 1 4

5 Customer PBA+000086h 1 0 0 0 0 1 1 0 5

6 Customer PBA+000087h 1 0 0 0 0 1 1 1 6

7 Customer PBA+000088h 1 0 0 0 1 0 0 0 7

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

32 Preliminary

10.0 Power and Reset Considerations

10.1 Power-Up/Down Characteristics

In order to prevent any condition that may result in a spurious write or erase operation, it is

recommended to power-up VCC, VCCQ and S-VCC together. Conversely, VCC, VCCQ and S-VCC

must power-down together.

It is also recommended to power-up VPP with or slightly after VCC. Conversely, VPP must power-

down with or slightly before VCC.

10.2 Power Supply Decoupling

When the device is accessed, many internal conditions change. Circuits are enabled to charge

pumps and voltages are switched. Al l this internal activity pro duces transient signals. The

magnitude of these transient signals depends on the device and the system capacitive and inductive

loading. To minimize the ef f ect of these transient signals, a 0.1 µF ceramic decoupling capacitor is

required across each VCC, VCCQ, VPP, S-VCC to system ground. Capacitors should also be placed

as close as possible to the package balls.

10.3 Flash Reset Characteristics

By holding the flash device in reset during power-up/down transitions, invalid bus conditions can

be masked. The flash device enters a reset mode when RST# is driven low. In reset mode, internal

flash circuitry is turned off and outputs are placed in a high-impedance state.

After return from reset, a certain amount of time is required before the flash device is capab le of

performing normal operations. Upon return from reset, the flash device defaults to page mode.

If RST# is driven low during a program or erase operation, the operation will be aborted and the

memory contents at the aborted block or address are no longer valid. See Figure 20, “Reset

Operations Waveforms” on page 47 for detailed information regarding reset timings.

Figure 10. Block Locking State Diagram

Lock Register 0

4 Words (64 bits)

User Programmed

1 Word (16bits)

4 Words (64 bits)

Intel Factory Programmed

0084h

0088h

0085h

0081h

0080h

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 33

11.0 Electrical Specifications

11.1 Absolute Maximum Ratings

NOTES:

1. All specified voltages are with respect to VSS. Minimum DC voltage is –0.5 V on input/output signals and

–0.2 V on VCC and VPP supplies. During transitions, this level may undershoot to –2.0 V for periods <20 ns

which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns.

2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns.

3. VPP program voltage is normally VPP1. VPP can be VPP2 for 1000 cycles on the main blocks and 2500 cycles

on the parameter blocks during program/erase.

4. Output shorted for no more than one second. No more than one output shorted at a time.

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress

ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure

beyond the “Operating Conditions” may affect device reliability.

11.2 Extended Temperature Operation

Parameter Note Maximum Rating

Temperature under Bias –25 °C to +85 °C

S torage Temperature –65 °C to +125 °C

Voltage On Any Signals (except VCC, VCCQ, VPP and S-VCC) 1 –0.5 V to +3.80 V

VPP Voltage 1,2,3 –0.2 V to +14 V

VCC V oltage 1 –0.2 V to +2.40 V

VCCQ and S-VCC Voltage 1 –0.2 V to +3.36 V

Output Short Circuit Current 4 100 mA

NOTICE: This datasheet contains preliminary information on new products in production. Specifications are

subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before

finalizing a design.

Symbol Parameter Note Min Max Unit

TAOperating Tem peratu re –25 85 °C

VCC VCC Supply Voltage 1.70 1.90 V

VCCQ, S-VCC Flash I/O and SRAM Supply Voltages 2 2.20 3.30 V

VPP1 VPP Voltage Supply (Logic Level) 1 0.90 1.90 V

VPP2 Factory Programming VPP 1 11.4 12.6

tPPH Maximum VPP Hours VPP = VPP2 1 80 Hours

Block Erase

Cycles

Main and Parameter Blocks VPP = VCC 1 100,000

CyclesMain Blocks VPP = VPP2 1 1000

Parameter Blocks VPP = VPP2 1 2500

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

34 Preliminary

NOTES:

1. In normal operation, the VPP program voltage is VPP1. V PP can be connected to 11.4 V–12.6 V for 1000

cycles on main blocks for extended temperatures and 2500 cycles at extended temperat ure on parameter

blocks.

2. VCCQ and S-VCC must be tied together, except when in Data Retention Mode.

11.3 DC Characteristics

Sym Parameter (1) Devic

eNote Min Typ Max Unit Test Condition

ILI Input Load Current Flash/

SRAM 1±2µA

VCC = VCCMax

VCCQ = VCCQMax

S-VCC = S-VCCMax

Inputs = VCCQ or VSS

ILO Output

Leakage

Current DQ15-0, WAIT Flash/

SRAM 1±10µA

ICCS Standby Current

Flash 1 6 18 µA

VCC = VCCMax

VCCQ = VCCQMax

CE# = VCC

RST# =VCC or VSS

4-Mbit

SRAM 120µA

S-VCC = S-VCCMax

S-CS1# = S-VCC

S-CS2 = S-VCC or S-VSS

Inpu ts = S-VCC or S-VSS

8-Mbit

SRAM 140µA

ICC Operating Power Supply

Current (cycle time = 1 µs)

4-Mbit

SRAM 110mAI

IO = 0 mA, S- C S1# = VIL

S-SC2 = S-WE# = VIH

Inputs = VIL or VIH

8-Mbit

SRAM 120mA

ICC2 Operating Power Supply

Current (min cycle time)

4-Mbit

SRAM 145mA

Cycle time = min 100% duty

IIO = 0 mA, S- C S1# = VIL

S-SC2 = VIH

Inputs = VIL or VIH

8-Mbit

SRAM 165mA

ICCR Average

VCC Read

Current

Asynchronous

Page Mode

Read Flash 2 4 7 mA 4-Word Read

VCC = VCCMax

CE# = VIL

OE# = VIH

Inputs = VIH or VIL

Synchronous

CLK = 40 MHz Flash 2, 3

712mA

4 -Word

Burst

9 16 mA 8-Word Burst

12 22 mA Continuous

Burst

ICCW VCC Program Current Flash 4, 5 18 40 mA VPP = VPP1

815mAV

PP = VPP2

ICCE VCC Block Erase Current Flash 4, 6 18 40 mA VPP = VPP1

815mAV

PP = VPP2

ICCWS VCC Program Suspend

Current Flash 4 6 18 µA CE# = VCCQ

ICCES VCC Erase Suspend Current Flash 4, 7 6 18 µA CE# = VCC

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 35

NOTES:

1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25 °C.

2. Automa tic Pow er Savings (AP S) reduces ICCR to approximately standby levels in static operation.

3. The burst wrap bit (CR.3) determines whether 4-, or 8-word burst accesses wrap within the burst-length

boundary, or whether they cross word-length boundaries to perform linear accesses. In the no-wrap mode

(CR.3 = 1), the device operates similar to continuous linear burst mode, but consumes less power.

4. Sampled, not 100% tested.

5. VCC read + program current is the summation of VCC read and VCC program currents.

6. VCC read + erase current is the summation of VCC read and VCC block erase currents.

7. ICCES is specified with device deselected. If device is read while in erase suspend, current draw is sum of

ICCES and ICCR.

8. Erase and program operations are inhibited when VPP ≤ VPPLK and not guaranteed outside valid VPP1 and

VPP2 ranges.

9. VIL can undershoot to –0.4 V and VIH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less. AC I/O

Te st Conditions

IPPS

(IPPWS,

IPPES)

VPP Standby Current

VPP Progr am Sus pend

Current

VPP Erase Suspend Current

Flash 4 0.2 5 µA VPP1 ≤ VCC

IPPR VPP Read Current Flash 2 15 µA VPP ≤ VCC

IPPW VPP Program Current Flash 4 0.05 0.10 mA VPP = VPP1

822 V

PP = VPP2

IPPE VPP Erase Current Flash 4 0.05 0.10 mA VPP = VPP1

822 V

PP = VPP2

VIL Input Low V o ltage Flash /

SRAM 90 0.4V

VIH Input High Voltage Flash /

SRAM 9VCCQ

- 0.4 VCCQ V

VOL Output Low Voltage Flash /

SRAM 0.1 V VCC = VCCMin

VCCQ = VCCQMin

IOL = 100 µA

VOH Output High Voltage Flash /

SRAM VCCQ

- 0.1 VVCC = VCCMin

VCCQ = VCCQMin

IOH = –100 µA

VPPLK VPP Lock-Out V oltage Flash 8 0.4 V

VLKO VCC Lock Voltage Flash 1.0 V

VLKOQ VCCQ Lock-Out Voltage Flash 0.90 V

Sym Parameter (1) Devic

eNote Min Typ Max Unit Test Condition

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

36 Preliminary

NOTES:

1. AC test inputs are driven at VCCQ for a Logic “1” and 0.0 V for a Logic “0.” Input timing begins, and output

timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when

VCC = VCCMin.

2. Timing conditions apply to both flash and SRAM.

NOTES:

1. See table for component values.

2. Test configuration component value for worst case speed conditions.

3. CL includes jig capacitance.

11.4 Discrete Capacitance (32-Mbit VF BGA Package)

TA = +25°C, f = 1 MHz

NOTE: 1. Sampled, not 100% tested.

Figure 11. AC Input/Output Reference Waveform

CCQ

/2 V

CCQ

Test Points

Input Output

Figure 12. Transient Equivalent Testing Load Circuit

Device

Under Test

VCCQ

CLR2

Out

Test Configurat ion CL (pF) R1 (Ω)R

2 (Ω)

VCCQMin Standard Test 30 25K 25K

Sym Parameter(1) Typ Max Unit Condition

CIN Input Capacit ance 6 8 pF VIN = 0.0 V

COUT Output Capacitance 8 12 pF VOUT = 0.0 V

CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 37

11.5 Stacked Capacitance (32/4, 32/8 and 64/8 Stacked-CSP Package)

TA = +25°C, f = 1 MHz

NOTE: 1. Sampled, not 100% tested.

Sym Parameter(1) Typ Max Unit Condition

CIN Input Capacitance 16 18 pF VIN = 0.0 V

COUT Output Capacitance 18 22 pF VOUT = 0.0 V

CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

38 Preliminary

12.0 Flash AC Characteristics

12.1 Flash Read Operations

# Sym Parameter (1,2) Speed –70 –85 Unit

Note Min Max Min Max

R1 tAVAV Read Cycle Time 3 70 85 ns

R2 tAVQV Address to Output Delay 3 70 85 ns

R3 tELQV CE# Low to Output Delay 70 85 ns

R4 tGLQV OE# Low to Output Delay 5 30 30 ns

R5 tPHQV RST# High to Output Delay 150 150 ns

R7 tGLQX OE# Low to Output in Low-Z 5, 6 0 0 ns

R8 tEHQZ CE# High to Output in High-Z 6 25 25 ns

R9 tGHQZ OE# High to Output in High-Z 5, 6 25 25 ns

R10 tOH CE#, (OE#) High to Output in Low-Z 5, 6 0 0 ns

R101 tAVVH Address Setup to ADV# High 10 10 ns

R102 tELVH CE# Low to ADV# High 10 10 ns

R103 tVLQV ADV# Low to Output Delay 70 85 ns

R104 tVLVH ADV# Pulse Width Low 10 10 ns

R105 tVHVL A DV# Pulse W idth High 6 10 10 ns

R106 tVHAX Address Hold from ADV# High 4 9 9 ns

R108 tAPA Page Address Access Time 4 25 25 ns

R200 fCLK CLK Frequency 40 33 MHz

R201 tCLK CLK Period 25 30 ns

R202 tCH/L CLK High or Low Time 9.5 9.5 ns

R203 tCHCL CLK Fall or Rise Time 3 5 ns

R301 tAVCH Address Valid Setup to CLK 9 9 ns

R302 tVLCH ADV# Low Setup to CLK 10 10 ns

R303 tELCH CE# Low Setup to CLK 9 9 ns

R304 tCHQV CLK to Output Delay 20 22 ns

R305 tCHQX Output Hold from CLK 5 5 ns

R306 tCHAX Address Hold from CLK 4 10 10 ns

R307 tCHTL/

HCLK to WAIT Asserted 20 22 ns

R308 tELTL OE# Low to WA IT Active 7 20 22 ns

R309 tEHTZ CE# (OE#) High to WAIT High-Z 6, 7 25 25 ns

R310 tEHEL CE# Pulse Width High 7 20 20 ns

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 39

NOTES:

1. See Figure 11, “AC Input/Output Reference Waveform” on page 36 for timing measurements and maximum

allowable input slew rate.

2. AC specifications assume the data bus voltage is less than or equal to VCCQ when a read operation is

initiated.

3. tAVAV = 85 ns for 128-Mbit device.

4. Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is

satisfied first.

5. OE# may be delayed by up to tELQV– tGLQV after the falling edge of CE# without impact to tELQV.

6. Sampled, not 100% tested.

7. Applies only to subsequent synchronous reads.

Figure 13. Single Word Asynchronous Read Waveform

Valid

Address

High Z

Valid

Output

R10

Generic_Async_Rd

Address [A]

CE# [E]

OE# [G]

WE# [W]

Data [D/Q]

RST# [P]

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

40 Preliminary

Figure 14. Single Word Latched Asynchronous Read Waveform

High Z Valid

Output

Valid

Address

Data [D/Q]

WE# [W]

OE# [G]

CE# [E]

AMAX-2 [A]

ADV# [V]

RST# [P]

R102

R104

R10

R103

R101

R105 R106

Generic_Latch_Async_Rd

1-0

[A]

Valid

Address

Valid

Address

Valid

Address

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 41

Figure 15. Page Mode Read Waveform

R105

High Z Valid

Output Valid

Output

Valid

Address

Valid

Address Valid

Address

R102

R104

ADV# [V]

CE# [E]

OE# [G]

WE# [W]

Data [D/Q]

RST# [P]

MAX-2

[A]

1-0

[A]

R101

R106

R103

R108

R10

Generic_Pg_Rd

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

42 Preliminary

NOTES:

1. Section 4.2.2, “First Latency Count (LC2–0)” on page 15 describes how to insert clock cycles during the initial

access.

2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.

Figure 16. Single Word Burst Read Waveform

Generic_1W_Sync_Rd

Note 1

Valid

Address

High Z Valid

Output

R101

R102

R302

R301 R306

R106R105

R103

R10

R305

High Z

R304

CLK [C]

RST# [P]

Address [A]

ADV# [V]

OE# [G]

WE# [W]

WAIT [T]

Data [D/Q]

CE# [E]

R303

R104

High Z

R308

R309

Note 2

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 43

NOTES:

1. Section 4.2.2, “First Latency Count (LC2–0)” on page 15 describes how to insert clock cycles during the initial

access.

2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.

Figure 1 7. 4 Word Burst Read Waveform

G i 4W S Rd

Valid

Address

Note 1

Valid

Output Valid

Output

High Z

R105

R102

R301

R302

R306

R101

R106

R103

R304

R305

RST# [P]

WAIT [T]

WE# [W]

OE# [G]

CE# [E]

ADV# [V]

Address [A]

CLK [C]

Data [D/Q]

Note 2

R104

R303

R10

R307

High Z

R308 R309

R310

High Z

Figure 18. Clock Input AC Waveform

CLK [C]

R203R202

R201

CLKINPUT.WMF

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

44 Preliminary

12.2 Flash Write Operations

NOTES:

1. Write timing characteristics during erase suspend are the same as during write-only operations.

2. A write operation can be terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or

WE# high (whichever occurs first); hence, tWP = tWLWH = tELEH = tWLEH = tELWH.

5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE#

low (whichever is last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.

6. System designers should take this into account and may insert a software No-Op instruction to delay the first

read after issuing a command.

7. For commands other than resume commands.

8. VPP should be held at VPP1 or VPP2 until block erase or program success is determined.

# Sym Parameter (1,2) Speed –70 –85 Unit

Note Min Max Min Max

W1 tPHWL

(tPHEL)RST# High Recovery to WE# (CE#) Low 150 150 ns

W2 tELWL (tWLEL) CE# (WE# ) Setup to WE# (CE#) Low 0 0 ns

W3 tWLWH

(tELEH)WE# (CE#) Write Pulse Width Low 4 45 60 ns

W4 tDVWH

(tDVEH)Data Setup to WE# (CE#) High 45 60 ns

W5 tAVWH

(tAVEH)Address Setup to WE# (CE#) High 45 60 ns

W6 tWHEH

(tEHWH)CE# (WE#) Hold from WE# (CE#) High 0 0 ns

W7 tWHDX

(tEHDX)Data Hold from WE# (CE#) High 0 0 ns

W8 tWHAX

(tEHAX)Address Hold from WE# (CE#) High 0 0 ns

W9 tWHWL

(tEHEL)WE# (CE#) Pulse Width High 5, 6, 7 25 25 ns

W10 tVPWH

(tVPEH)VPP Setup to WE# (CE#) High 3 200 200 ns

W11 tQVVL VPP Hold from Valid St atus Register Data 3, 8 0 0 ns

W12 tQVBL WP# Hold from Valid Status Register Data 3, 8 0 0 ns

W13 tBHWH

(tBHEH)WP# Setup to WE# (CE#) High 3 200 200 ns

W14 tWHGL

(tEHGL)Write Recovery before Read 0 0 ns

W16 tWHQV WE# High to Valid Data 6 tAVQV +

40 tAVQV +

50 ns

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 45

NOTE:

1. VCC power-up and standby.

2. Write Program or Erase Setup command.

3. Write valid address and data (for program) or Erase Confirm command.

4. Automated program/e rase delay.

5. Read status register data (SRD) to determine program/era se operation completion.

6. OE# and CE# must be driven active (low) and WE# must be de-asserted (high) for read operations.

Figure 19. Write Waveform

Generic Write

Note 1 Note 2 Note 3 Note 4 Note 5

Address [A]

Valid

Address Valid

Address

CE# [E]

Note 6

OE# [G]

WE# [W]

RST# [P]

W11

W12

[V]

PP1

or V

PP2

WP# [B]

Data [D/Q]

Command Valid

SRD

ADV# [V]

W16W1

W10

W13

W14

R101

R106

Valid

Address

Note 6

R104

R105

Data or

Command

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

46 Preliminary

12.3 Flash Program and Erase Operations

NOTES:

1. Ty pical values measured at TA = +25 °C and nominal voltages.

2. Excludes external system-level overhead.

3. These performance numbers are valid for all speed versions.

4. Samp led, but not 100% tested.

5. Exact results may vary based on system overhead.

12.4 Reset Operations

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. The device may reset if tPLPH is <tPLPHMin, but this is not guaranteed.

3. Not applicable if RST# is tied to VCC.

4. Samp led, but not 100% tested.

5. Reset will complete within tPLPH if RST# is asserted while a block erase or program operation is not

executing.

Extended Temperatures F-VPP1 F-VPP2 Unit

# Operation Symbol Parameter Notes Typ Max Typ Max

Program Time

tWHQV1/

tEHQV1 Word 1-Word 1,2,3,4 12 150 8 130 µs

Enhanced Factory

Programming Mode 1,3,4 N/A N/A 3.5 16

tBWPB Block 4-KW Parameter 1,2,3,4 0.05 0.23 0.03 0.07 s

tBWMB 32-KW Main 1,2,3,4 0.4 1.8 0.24 0.6 s

tBWPB EF P Mod e 4-KW Paramet er 1,2,3,4,

5n/a n/a 0.015 n/a s

tBWMB 32-KW Main 1,2,3,4,

5n/a n/a 0.12 n/a s

Erase Time tWHQV2/

tEHQV2 Block 4-KW Parameter 1,2,3,4 0.3 2.5 0.25 2.5 s

32-KW Main 1,2,3,4 0.7 4 0.4 4 s

Suspend

Latency

tWHRH1/

tEHRH1 Program Suspend 1,2,3,4 5 10 5 10 µs

tWHRH2/

tEHRH2 Erase Suspend 1,2,3,4 9 20 9 20

EFP Latency

tEFP-SETUP EFP Setup 1,3 ,4 N/A N/A N/A 5

µstEFP-TRAN Program to Verify Transition 1,3,4 N/A N/A 2.7 5.6

tEFP-VERIFY Verify 1,3,4 N/A N/A 1.7 130

# Symbol Parameter Note Min Max Unit

P1 tPLPH RST# Low to Reset during Read 1, 2, 3, 4 100 ns

P2 tPLRH

RST# Low to Reset during Block

Erase 1, 3, 4, 5 20

µs

RST# Low to Reset during Program 1, 3, 4, 5 10

P3 tVCCPH VCC Power Valid to Reset 1, 3, 4 60

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 47

Figure 20. Reset Operations Waveforms

(

A) Reset during

read mode

(B) Reset during

program or block erase

≤

program or block erase

≥

RST# [P]

Abort

Complete

Abort

Complete

(D) VCC Power-up to

RST# high

P1 R5

P2 R5

RESET.WMF

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

48 Preliminary

13.0 SRAM AC Characteristics

13.1 SRAM Re ad Op eration

NOTE:

1. See Figure 21, “AC Waveform: SRAM Read Operation” on page 49.

2. Samp led, but not 100% tested.

3. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) for a given device and from

device-to-device interconnection.

4. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and

are not referenced to output voltage levels.

# Sym Parameter1

Density 4/8 Mbit

Unit

S-VCC 2.2 V – 3.3 V

Speed -70 -85

Note Min Max Min Max

R1 tRC Read Cycle Time 70 –85– ns

R2 tAA Address to Output Delay – 70 – 85 ns

R3 tCO1,

tCO2 S-CS1#, S-CS2 to Output Delay – 70 – 85 ns

R4 tOE S-OE# to Output Delay – 35 – 40 ns

R5 tBA S-UB#, S-LB# to Output Delay – 70 – 85 ns

R6 tLZ1,

tLZ2 S-CS1#, S-CS2 to Output in Low-Z 2, 3 5 – 5 – ns

R7 tOLZ S-OE# to Output in Low-Z 2 0 – 0 – ns

R8 tHZ1,

tHZ2 S-CS1#, S-CS2 to Output in High-Z 2, 3, 4 0 25 0 30 ns

R9 tOHZ S-OE# to Output in High-Z 2, 4 0 25 0 30 ns

R10 tOH Output Hold from Address, S-CS1#,

S-CS2, or S-OE# Change, Whichever Occurs First 0–0–ns

R11 tBLZ S-UB#, S-LB# to Output in Low-Z 2 0 – 0 – ns

R12 tBHZ S-UB#, S-LB# to Output in High-Z 2 0 25 0 30 ns

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 49

Figure 21. AC Waveform: SRAM Read Operation

High Z

Valid Output

Address Stable

Data Valid

Device

Address Selection

Standby

ADDRESSES (A)

# (E

)

OE# (G)

WE# (W)

DATA (D/Q)

UB#, LB#

High Z

R10

)

R11 R12

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

50 Preliminary

13.2 SRAM Write Operation

NOTES:

1. See Figure 22, “AC Waveform: SRAM Write Operation” on page 51.

2. A write occurs during the overlap (tWP) of low S-CS1# and low S-WE#. A write begins when S-CS1# goes low

and S-WE# goes low with asserting S-UB# or S-LB# for single-byte operation, or simultaneously asserting

S-UB# and S-LB# for double-byte operation. A write ends at the earliest transition when S-CS1# goes high

and S-WE# goes high. The tWP is measured from the beginning of write to the end of write.

3. tWP is measured from S-CS1# going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change; tWR applied in case a write ends as S-CS1# or

S-WE# going high.

# Sym Parameter1

Density 4/8 Mbit

Unit

S-VCC 2.2 V – 3.3 V

Speed -70 -85

Note Min Max Min Max

W1 tWC Write Cycle Time 2 70 –85– ns

W2 tAS Address Setup to S-WE# (S-CS 1#) and S-UB#, S-LB# Going Low 4 0 – 0 – ns

W3 tWP S-WE# (S-CS1#) Pulse Width 3 55 – 60 – ns

W4 tDW Data to W r ite Time Overlap 30 – 35 – ns

W5 tAW Address Setup to S-WE# (S-CS 1#) Going High 60 – 70 – ns

W6 tCW S-SC1# (S-WE#) Setup to S-WE# (S-CS1#) Going High and S-SC2

Going Low 60 – 70 – ns

W7 tDH Data Hold Time from S-WE# (S-CS1#) High 0 – 0 – ns

W8 tWR Write Recovery 5 0 – 0 – n s

W9 tBW S-UB#, S-LB# Setup to S-WE # (S-CS 1#) Going High 60 – 70 – ns

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 51

13.3 SRAM Data Retention Operation

NOTES:

1. Typical values at nominal S-VCC, TA= +25 °C.

2. S-CS1# > S-VCC – 0.2 V, S-CS2 > S-VCC – 0.2 V (S-CS1# controlled) or S-CS2 < 0.2 V (S-CS2 controlled).

Figure 22. AC Waveform: SRAM Write Operation

Sym Parameter Device Note Min Typ Max Unit Test Conditions

VDR S-VCC for Data Retention 4/8-

Mbit 1, 2 1.5 – 3.3 V S-CS1# ≥ S-VCC – 0.2 V

IDR Deep Retention Current 4-Mbit 1, 2 ––5

µA S-VCC = 1.5 V

S-CS1# ≥ S-VCC – 0.2 V

8-Mbit – – 25

tSDR Data Retention Setup

Time 4/8-

Mbit 10––ns

See Data Retention

Waveform

tRDR Recovery Time 4/8-

Mbit 1t

RC ––ns

High Z

Data In

Address Stable

Device

Address Selection

Standby

ADDRESSES (A)

# (E

)

OE# (G)

WE# (W)

DATA (D/Q)

UB#, LB#

High Z

)

W4 W7

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

52 Preliminary

Figure 23. SRAM Data Retention Waveform

S-V

S-CS

# (E1)

S-V

IHMAX

IHMIN

Data Retention Mode

SDR

RDR

S-V

ILMAX

S-CS

)

S-V

IHMIN

Data Retention Mode

SDR

RDR

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 53

14.0 Ordering Information

Figure 24. Component Ordering Breakdown

Table 16. Valid Component Combinations

Stacked-CSP VF BGA

32M

RD28F3204W30T70

RD28F3204W30B70

RD28F3204W30T85

RD28F3204W30B85

RD28F3208W30T70

RD28F3208W30B70

RD28F3208W30T85

RD28F3208W30B85

GE28F320W30T70

GE28F320W30B70

GE28F320W30T85

GE28F320W30B85

64 M

RD28F6408W30T70

RD28F6408W30B70

RD28F6408W30T85

RD28F6408W30B85

TBD

128 M

TBD TBD

R D 2 8 F 6 4 0 8 W T 7 0

Package Designator,

Extended Temperature

(-25 C to +85 C)

GE = 0.75 MM VF BGA

RD = Stacked CSP

Product line designator

for all Intel

Flash products

Access Speed

70 ns

85 ns

Product Family

W30 = Intel 1.8 Volt Wireless

Flash Memory with 3 Volt I/O

= 1.70 V - 1.90 V

CCQ

= 2.20 V - 3.30 V

Flash Density

320 = x16 (32-Mbit)

640 = x16 (64-Mbit)

128 = x16 (128-Mbit)

Parameter Partition

T =

Top Parameter Device

B =

Bottom Parameter Device

SRAM Density,

for Stacked-CSP

Products Only

4 = x16 (4-Mbit)

8 = x16 (8-Mbit)

3 0

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

54 Preliminary

Appendix A Flash Write State Machine (WSM)

This table shows the comm a nd state transitions based o n in coming comma nds. Only on e partition

can be actively programming or erasing at a time. Each partition stays in its last output state (Array,

ID/CFI or Status) until a new command changes it. The next WSM state does not depend on the

partition’s output state.

Figure 25. Write State Machine — Next State Table (Sheet 1 of 2)

Chi

Next State after Command In

Read

Array(3) Program

Setup(4,5) Erase

Setup(4,5)

Enhanced

Factory

Pgm

Setup(4)

BE Confirm,

P/E Resume,

ULB

Confirm(9)

Program/

Erase

Suspend

Read

Status

Clear

Status

Read

ID/Query

(FFH) (10H/40H) (20H ) (30H) (D0H) (B0H) (70H) (50H) (90H, 98H)

Ready Ready Program

Setup Erase

Setup EFP

Setup Ready

Lock/CR Setup Ready (Lock Error) Ready Ready (Lock Error)

Setup OTP Busy

Busy

Setup Program Busy

Busy Program Busy Pgm Susp Program Busy

Suspend Program Suspend Pgm Busy Program Suspend

Setup Ready (Error) Erase Busy Ready (Error)

Busy Erase Busy Erase Susp Erase Busy

Suspend Erase

Suspend

Pgm in

Erase

Susp Setup Erase Suspend Erase Busy Erase Suspend

Setup Program in Erase Suspend Busy

Busy Program in Erase Suspend Busy Pgm Susp in

Erase Susp Program in Erase Suspend Busy

Suspend Program Suspend in Erase Suspend Pgm in Erase

Susp Busy Program Suspend in Erase Suspend

Erase Suspend (Lock Error) Erase Susp Erase Suspend

(Lock Error)

Setup Ready (Error) EFP Busy Ready (Error)

EFP Busy EFP Bus

(7)

EFP Verify Verif

Bus

(7)

Out

Next State after Command In

Status

ID/Query

Write State Machin e (W SM ) Next State Table

Output Next State Table

(1)

Lock/CR Setup,

Lock/CR Setup in Erase Susp

OTP Busy

Current Chip

State(8)

Ready,

Pgm Busy,

Pgm Suspend,

Erase Busy,

Erase Suspend,

Pgm In Erase Susp Busy,

Pgm Susp In Erase Susp

Pgm Setup,

Erase Setup,

OTP Setup,

Pgm in Erase Susp Setup,

EFP Setup,

EFP Busy,

Verify Busy

Lock/CR Setup in Erase

Suspend

Erase

Program

Program in

Erase Suspend

OTP

Enhanced

Factory

Program

Output

does not

change

Array(3) Status Output does not change Status

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 55

NOTES:

1. The output state shows the type of data that appears at the outputs if the partition address is the same as the command

address. A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued.

Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM state

does not depend on the partition’s output state. For example, if partition #1’s output state is Read Array and partition #4’s

output state is Read Status, every read from partit ion #4 (without issuing a new co mmand) outputs the Status register.

2. Illegal commands are those not defined in the command set.

3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in

undermined data when a partition address is read.

4. Both cycles of 2-cycle commands should be issued to the same partition address. If they are issued to different partitions, the

second write determines the active partition. Both partitions will output status information when read.

5. If the WSM is active, both cycles of a 2-cycle command are ignored. This differs from previous Intel devices.

6. The Clear Status command clears status register error bits except when the WSM is running (Pgm Busy, Erase Busy, Pgm

Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase

Suspend).

7. EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if Block Address = address at EFP Confirm

command. Any other commands are treated as data.

8. The “current state” is that of the WSM, not the partition.

9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then

move to the Ready State.

Figure 25. Write State Machine — Next State Table (Sheet 2 of 2)

Chi

Next S tate after Com m and In

Lock,

Unlock,

Lock-down,

CR setup(5)

OTP

Setup(5)

Lock

Block

Confirm(9)

Lock-

Down

Block

Confirm(9)

Write CR

Confirm(9)

Enhanced

Fact P gm

Exit (blk add

<> W A 0)

Illegal

com m ands or

EFP data(2)

(60H ) (C0H ) (01H) (2FH ) (03H ) (XX XX H ) (other codes)

Ready Lock/CR

Setup OTP

Setup Ready

Lock/CR S etup R eady (Lock Error) R eady Ready Ready Ready (Lock E rror)

S e tu p OT P Bu s y

Busy Ready

Setup Program B usy N/A

Bus y Program B usy Ready

Suspe nd Program S uspend

Setup Ready (Error)

Bus y Erase B usy Erase Busy R eady

Suspend Lock/CR

Setup in

Erase Susp E rase Suspend

Setup Progra m in Erase S uspend B usy

Busy Program in Erase Suspend Busy Erase

Suspend

Suspe nd Program S uspend in E rase S uspend

Erase S uspend

(L o ck Erro r) Erase S usp E rase Susp Erase Susp Erase S uspend (Lock Error)

Setup Ready (Error)

EFP Busy EFP Bus

(7) EFP Verify EF P Bus

(7)

EFP Verify Verif

Bus

(7) Ready EFP Verif

(7) Ready

Out

Ne xt State after Command In

Status

Status Array Status

Write State Machine (WS M) Next State Tabl e

Output Next State Table(1)

Program

Erase

Program in

Erase Suspend

Current C hip

State(8)

OTP

Lock/CR S etup in Erase

Suspend

Enhanced

Factory

Program

O utput does

not change

O utput does

not change

WSM

Operation

Completes

N/A

O utput does not change A rrayStatus

Pgm S etup,

Erase Setup,

OTP Setup,

Pgm in Erase Susp S etup,

EFP Setup,

EFP Busy,

V e rif y B u s y

Lock/CR S etup,

Lock/CR S etup in Erase Susp

OTP Busy

Ready,

Pgm B usy,

Pgm S uspend,

Erase Busy,

Erase Suspend,

Pgm In Erase Susp Busy,

P g m S u s p I n Era s e Su s p

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

56 Preliminary

Appendix B Flowcharts

Figure 26. Programming Flowchart

Suspend

Program

Loop

Start

Write 40h,

Word Address

Write Data

Word Address

Read Status

SR.7 =

Full Status

Check

(if desired)

Program

Complete

FULL STATUS CHECK PROCEDURE

Suspend

Program

Read Status

Program

Successful

SR.3 =

SR.1 =

SR.4 =

Yes

Range

Error

Device

Protect Error

Program

Error

WORD PROGRAM PROCEDURE

SR.3 MUST be cleared before the Write State Machine will

allow further program attempts

Only the Clear Staus Register command clears SR.1, 3, 4.

If an error is detected, clear the status register before

attempting a program retry or other error recovery.

Standby

Bus

Operation Command

Check SR.3

1 = V

error

Check SR.4

1 = Data program error

Comments

Repeat for subsequent programming operations.

Full Status register check can be done after each program or

after a sequence of program operations.

Write FFh after the last operation to enter read array mode.

Comments

Bus

Operation Command

Data = 40h

Addr = Location to program (WA)

Write Program

Setup

Data = Data to program (WD)

Addr = Location to program (WA)

Write Data

Status register data. Toggle CE# or

OE# to update Status register

Read

Check SR.7

1 = WSM ready

0 = WSM busy

Standby

Standby Check SR.1

1 = Attempted program to locked block

Program aborted

PGM_WRD.WMF

Program Word

Data/ Confirm

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 57

Figure 27. Program Suspend/Resume Flowchart

Read Status

SR.7 =

SR.2 =

Write FFh

Susp Partition

Read Array

Data

Program

Completed

Done

Reading

Write FFh

Pgm’d Partition

Write D0h

Any Address

Program

Resumed Read Array

Data

Yes

PROGRAM SUSPEND / RESUME PROCEDURE

Write Program

Resume Data = D0h

Addr = Suspended block (BA)

Bus

Operation Command Comments

Write Program

Suspend Data = B0h

Addr = Block to suspend (BA)

Standby Check SR.7

1 = WSM ready

0 = WSM busy

Standby Check SR.2

1 = Program suspended

0 = Program completed

Write Read

Array Data = FFh

Addr = Block address to read (BA)

Read Read array data from block other than

the one being programmed

Read

Status register data

Toggle CE# or OE# to update Status

Addr = Suspended block (BA)

PGM_SUS.WMF

Start

Write B0h

Any Address

Program Suspend

Read Status

Program Resume Read Array

Read Array

Write 70h

Same Partition

Write Read

Status Data = 70h

Addr = Same partition

If the suspended partition was placed in Read Array mode:

Write Read

Status

Return partition to Status mode:

Data = 70h

Addr = Same partition

Write 70h

Same Partition

Read Status

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

58 Preliminary

Figure 28. Enhanced Factory Program Flowchart

EFP Setup EFP Program EFP Verify

EFP Exit

1. WA

= first Word Address to be programmed within the target block. The BBA (Block Base

Address) must remain constant throughout the program phase data stream; WA can be held

constant at the first address location, or it can be written to sequence up through the addresses

within the block. Writing to a BBA not equal to that of the block currently being written to

terminates the EFP program phase, and instructs the device to enter the EFP verify phase.

2. For proper verification to occur, the verify data stream must be presented to the device in the

same sequence as that of the program phase data stream. Writing to a BBA not equal to WA

terminates the EFP verify phase, and instructs the device to exit EFP .

3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive

additional program-pulse attempts during the EFP verify phase. The device will report any

program failure by setting SR.4=1; this check can be performed during the full status check after

EFP has been exited for that block, and will indicate any error within the entire data stream.

Comments

Bus

State

Repeat for subsequent operations.

After EFP exit, a Full Status Check can

determine if any program error occurred.

See the Full Status Check procedure in the

Word Program flowchart.

Write

Standby

Read

Write

(note 2)

Read

Standby

Write

Read

Standby

EFP

Setup

Program

Done?

Exit

Program

Phase

Last

Data?

Exit

Verify

Phase

EFP

Exited?

Write EFP

Confirm

Read

Standby EFP

Setup

Done?

Read

Standby Verify

Stream

Ready?

Write Unlock

Block

Write

(note 1)

Standby Last

Data?

Standby

(note 3) Verify

Done?

SR.0=1=N

Write Data

Address = WA

Last

Data?

Write FFFFh

Address

≠

BBA

Program

Done?

Read

Status Register

SR.0 = 0 = Y

SR.0=1=N

Write Data

Address = WA

Verify

Done?

Last

Data?

Read

Status Register

Write FFFFh

Address

≠

BBA

Verify Stream

Ready?

Read

Status Register

SR.7=0=N

Full Status Check

Procedure

Operation

Complete

Read

Status Register

EFP

Exited?

SR.7 = 1 = Y

SR.0=1=N

Start

Write 30h

Address = WA

= 12V

Unlock Block

Write D0h

Address = WA

EFP Setup

Done?

Read

Status Register

SR.7 = 1 = N

Exit

EFP Program EFP Verify EFP ExitEFP Setup

ENHANCED FACTORY PROGRAMMING PROCEDURE

Comments

Bus

State

Data = 30h

Address = WA

Data = D0h

Address = WA

Status Register

Check SR.7

0 = EFP ready

1 = EFP not ready

= 12V

Unlock block

Check SR.0

0 = Program done

1 = Program not done

Status Register

Data = FFFFh

Address not within same

BBA

Data = Data to program

Address = WA

Device automatically

increments address.

Comments

Bus

State

Data = Word to verify

Address = WA

Status Register

Device automatically

increments address.

Data = FFFFh

Address not within same

BBA

Status Register

Check SR.0

0 = Ready for verify

1 = Not ready for verify

Check SR.0

0 = Verify done

1 = Verify not done

Status Register

Check SR.7

0 = Exit not finished

1 = Exit completed

Check V

& Lock

errors (SR.3, SR.1)

Data Stream

Ready?

Read

Status Register

SR.0 = 0 = Y

SR.7=0=Y

SR.0=1=N

Standby

Read

Data

Stream

Ready?

Check SR.0

0 = Ready for data

1 = Not ready for data

Status Register

SR.0 = 0 = Y

EFP setup time

Standby Setup

Time Refer to Program and

Erase Operations Table.

Standby Error

Condition

Check

If SR.7 = 1:

Check SR.3, SR.1

SR.3 = 1 = V

error

SR.1 = 1 = locked block

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 59

Figure 29. Block Erase Flowchart

Start

FULL ERASE STATUS CHECK PROCEDURE

Repeat for subsequent block erasures.

Full Status register check can be done after each block erase or

after a sequence of block erasures.

Write FFh after the last operation to enter read array mode.

SR. 1 and 3 MUST be cleared before the Write State Machine

will allow further erase attempts.

Only the Clear Staus Register command clears SR.1, 3, 4, 5.

If an error is detected, clear the Status register before

attempting an erase retry or other error recovery.

Suspend

Erase

0 Yes

Suspend

Erase

Loop

Write 20h

Block Address

Write D0h and

Block Address

Read Status

SR.7 =

Full Erase

Status Check

(if desired)

Block Erase

Complete

Read Status

Block Erase

Successful

SR.1 = Erase of

Locked Block

Aborted

BLOCK ERASE PROCEDURE

Bus

Operation Command Comments

Write Block

Erase

Setup

Data = 20h

Addr = Block to be erased (BA)

Write Erase

Confirm Data = D0h

Addr = Block to be erased (BA)

Read Status register data. Toggle CE# or

OE# to update Status register data

Standby Check SR.7

1 = WSM ready

0 = WSM busy

Bus

Operation Command Comments

SR.3 = V

Range

Error

SR.4,5 = Command

Sequence Error

SR.5 = Block Erase

Error

Standby Check SR.3

1 = V

error

Standby Check SR.4,5

Both 1 = Command sequence error

Standby Check SR.5

1 = Block erase error

Standby Check SR.1

1 = Attempted erase of locked block

Erase aborted

ERAS_BLK.WMF

Block Erase

Erase Confirm

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

60 Preliminary

Figure 30. Erase Suspend/Resume Flowchart

Erase

Completed

Write FFh

Erased Partition

Read Array

Data

Read

Program

Loop

Read Array

Data

Yes

Start

Write B0h

Any Address

Read Status

SR.7 =

SR.6 =

Write D0h

Any Address

Erase Resumed

Read or

Program?

Done?

Write

Standby

Write

Erase

Suspend

Read Array

or Program

Program

Resume

Data = B0h

Addr = Any address

Data = FFh or 40h

Addr = Block to program or read

Check SR.7

1 = WSM ready

0 = WSM busy

Check SR.6

1 = Erase suspended

0 = Erase completed

Data = D0h

Addr = Any address

Bus

Operation Command Comments

Read Status register data. Toggle CE# or

OE# to update Status register

Addr = Same partition

Read or

Write Read array or program data from/to

block other than the one being erased

ERASE SUSPEND / RESUME PROCEDURE

ERAS_SUS.WMF

Write 70h

Same Partition

Write Read

Status Data = 70h

Addr = Same partition

Erase Resume

Erase Suspend

Read Status

Read Array

Write 70h

Same Partition

Read Status

If the suspended partition was placed in

Read Array mode or a Program Loop:

Write Read

Status

Return partition to Status mode:

Data = 70h

Addr = Same partition

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 61

Figure 31. Locking Operations Flowchart

Optional

Start

Write 60h

Block Address

Write 90h

Read Block Lock

Status

Locking

Change?

Lock Change

Complete

Write 01,D0,2Fh

Block Address

Write FFh

Partition Address

Yes

Write

(Optional)

Read

(Optional)

Standby

(Optional)

Write

Lock

Setup

Lock,

Unlock, or

Lockdown

Confirm

Read ID

Plane

Block Lock

Status

Read

Array

Data = 60h

Addr = Block to lock/unlock/lock-down (BA)

Data = 01h (Lock block)

D0h (Unlock block)

2Fh (Lockdown block)

Addr = Block to lock/unlock/lock-down (BA)

Data = 90h

Addr = Block address offset +2 (BA+2)

Block Lock status data

Addr = Block address offset +2 (BA+2)

Confirm locking change on DQ

, DQ

(See Block Locking State Transitions Table

for valid combinations.)

Data = FFh

Addr = Block address (BA)

Bus

Operation Command Comments

LOCKING OPERATIONS PROCEDURE

LOCK_OP.WMF

Lock Confirm

Lock Setup

Read ID Plane

Read Array

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

62 Preliminary

Figure 32. Protection Register Programming Flowchart

FULL STATUS CHECK PROCEDURE

Protection Program operations addresses must be within the

protection register address space. Addresses outside this

space will return an error.

Repeat for subsequent programming operations.

Full Status register check can be done after each program or

after a sequence of program operations.

Write FFh after the last operation to enter read array mode.

SR.3 MUST be cleared before the Write State Machine will

allow further program attempts.

Only the Clear Staus Register command clears SR.1, 3, 4.

If an error is detected, clear the Status register before

attempting a program retry or other error recovery.

Yes

1,1

0,1

1,1

PROTECTION REGISTER PROGRAMMING PROCEDURE

Start

Write C0h

Addr=Prot addr

Write Protect.

Address / Data

Read Status

SR.7 = 1?

Full Status

Check

(if desired)

Program

Complete

Read Status

Program

Successful

SR.3, SR.4 =

SR.1, SR.4 =

Range Error

Programming Error

Locked-Register

Program Aborted

Standby

Bus

Operation Command

SR.1 SR.3 SR.4

011V

Error

0 0 1 Prot. Reg.

Prog. Error

Comments

Write

Standby

Protection

Program

Setup

Protection

Program

Data = C0H

Addr = First Location to Program

Data = Data to Program

Addr = Location to Program

Check SR.7

1 = WSM Ready

0 = WSM Busy

Bus

Operation Command Comments

Read Status Register Data Toggle CE# or

OE# to Update Status Register Data

Standby 1 0 1 Register Locked:

Aborted

PROTFLOW.WMF

Program Setup

Confirm Data

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 63

Appendix C Common Flash Interface

This appendix defines the data structure or “database” returned by the Common Flash Interface

(CFI) Query command. System software should parse this structure to gain critical information

such as block size, density, x8/x16, and electrical specifications. Once this information has been

obtained, the s oftware will know which command sets to use to enab le flash writes, block erases,

and otherwise control the flash component. The Query is part of an overall specification for

multiple command set and control interface descriptions called Common Flash Interface, or CFI.

C.1 Query Structure Output

The Query database allows system software to obtain information for controlling the flash device.

This section describes the device’s CFI-compliant interface that allows access to Query data.

Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset

value is the address relative to the maximum bus wid th supported by the device. On this family of

devices, the Query table device starting address is a 10h, which is a word address for x16 devices.

For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on

the low byte at word address es 10h and 11h. This CFI-compl iant device out pu t s 00h dat a on up per

bytes. The device outputs ASCII “Q” in the low byte (DQ0-7) and 00h in the high byte (DQ8-15).

At Query addresses containing two or more bytes of information, the least significant data byte is

presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always

“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is

shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

Table C1. Summary of Query Structure Output as a Function of Device and Mode

Table C2. Example of Query Structure Output of x16- and x8 Devices

Device Hex

Offset Hex

Code ASCII

Value

00010: 51 "Q"

Device Addresses 00011: 52 "R"

00012: 59 "Y"

Word Addressing: Byte Addressing:

Offset Hex Code Value Offset Hex Code Value

–A

–D

–A

–D

00010h 0051 "Q" 00010h 51 "Q"

00011h 0052 "R" 00011h 52 "R"

00012h 0059 "Y" 00012h 59 "Y"

00013h P_ID

PrVendor 00013h P_ID

PrVendor

00014h P_ID

ID #

00014h P_ID

ID #

00015h P

PrVendor 00015h P_ID

ID #

00016h P

TblAdr 00016h ... ...

00017h A_IDL

AltVendor 00017h

00018h A_IDHI

ID #

00018h

... ...

...

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

64 Preliminary

C.2 Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)

Query structure or “database.” The structure subsections and address locations are summarized

below.

Table C3. Query Structure

NOTES:

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is

32K-word).

3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

C.3 Block Status Register

The Block Status Register indicates whether an erase operation completed successfully or whether

a given block is locked or can be accessed for flash program/erase operations.

Block Erase Status (BSR.1) allows system software to determine the success of the last block erase

operation. BSR.1 can be used just after power-up to verify that the VCC supply was not

accidentally removed during an erase op eration. Only issuing another operation to the block resets

this bit. The Block Status Register is accessed from word address 02h within each block.

Table C4. Block Status Register

NOTE: BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64KB block) beginning

location in word mode).

Offset Sub-Section Name

Description

(1)

00000h Manufacturer Code

00001h Device Code

(BA+2)h

(2) Block Status re

ister

Block-specific information

00004-Fh Reserved Reserved for vendor-specific information

00010h CFI query identification string Command set ID and vendor data offset

0001Bh S ystem interface information Device timing & voltage information

00027h Device geometry definition Flash device layout

P(3) Primary Intel-specific Extended Query Table Vendor-defined additional information specific

to the Primary Vendor Algorithm

Offset Length Description Add. Value

(

BA+2

)

h(1) 1 Block Lock Status Register BA+2 --00 or --01

BSR.0 Block lock status

0 = Unlocked

1 = Locked

BA+2 (bit 0): 0 or 1

BSR.1 Block lock-down status

0 = Not locked down

1 = Locked down

BA+2 (bit 1): 0 or 1

BSR 2–7: Reserved for future use BA+2 (bit 2–7): 0

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 65

C.4 CFI Query Identification S tring

The Identification String provides verification that the component supports the Common Flash

Interface specification. It also indicates the specification version and supported vendor-specified

command set(s).

Table C5. CFI Identification

Table C6. System Interface Information

Offset Length Description Add. Hex

Code Value

10h 3Query-unique ASCII string “QRY“ 10: --51 "Q"

11: --52 "R"

12: --59 "Y"

13h 2 Primary vendor command set and control interface ID code. 13: --03

16-bit ID code for vendor-specified algorithms 14: --00

15h 2 Extended Query Table primary algorithm address 15: --39

16: --00

17h 2 Alternate vendor command set and control interface ID code. 17: --00

0000h means no second vendor-specified algorithm exists 18: --00

19h 2 Secondary algorithm Extended Query Table address. 19: --00

0000h means none exists 1A: --00

Offset Length Description Add. Hex

Code Value

1Bh 1 1B: --17 1.7V

1Ch 1 1C: --19 1.9V

1Dh 1 1D: --B4 11.4V

1Eh 1 1E: --C6 12.6V

1Fh 1 “n” such that t

pical sin

le word pro

ram time-out = 2n

-sec 1F: --04 16

20h 1 “n” such that t

pical max. buffer write time-out = 2n

-sec 20: --00 NA

21h 1 “n” such that t

pical block erase time-out = 2n m-sec 21: --0A 1s

22h 1 “n” such that t

pical full chip erase time-out = 2n m-sec 22: --00 NA

23h 1 “n” such that maximum word pro

ram time-out = 2n times t

pical 23: --04 256µs

24h 1 “n” such that maximum buffer write time-out = 2n times t

pical 24: --00 NA

25h 1 “n” such that maximum block erase time-out = 2n times t

pical 25: --03 8s

26h 1 “n” such that maximum chip erase time-out = 2n times t

pical 26: --00 NA

VPP [programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

4–7 HEX v

VPP [programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

4–7 HEX v

VCC logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

4–7 B

D v

VCC logic supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

66 Preliminary

C.5 Device Geometry Definition

Table C7. Device Geometry Definition

Offset Length Description Code

27h 1“n” such that device size = 2n in number of b

tes 27: S ee ta ble be l ow

76543210

28h 2 x1K x512 x256 x128 x64 x32 x16 x8 28: --01 x16

15 14 13 12 11 10 9 8

————————29:--00

2Ah 2“n” such that maximum number of b

tes in write buffer = 2n2A: --00 0

2B: --00

2Ch 1 2C:

2Dh 4 Erase Block Region 1 Information - Bottom paramenter device 2D:

Erase Block Region x-3 Information - Top Paramenter device 2E:

bits 0–15 = y, y+1 = number of identical-size erase blocks 2F:

bits 16–31 = z, region erase block(s) size are z x 256 bytes 30:

31h 4 Erase Block Region 2 Information 31:

bits 0–15 = y, y+1 = number of identical-size erase blocks 32:

bits 16–31 = z, region erase block(s) size are z x 256 bytes 33:

34:

35h 4 Erase Block Re

ion 3-x Information for Bottom parameter devic

35:

Erase Block Region 1 Information for Top paramenter device 36:

bits 0–15 = y, y+1 = number of identical-size erase blocks 37:

bits 16–31 = z, region erase block(s) size are z x 256 bytes 38:

Se e t abl e belo w

Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions

with one or more contiguous same-size erase blocks.

3. Symmetrically blocked partitions have one blocking region

4. Partition size =

(

total blocks

)

(

individual block size

)

Flash device interface code assignment:

"n" such that n+1 specifies the bit field that represents the flash

device width capabilities as described in the table:

Se e t abl e belo w

Address 16 Mbit 32 Mbit

–B –T –B –T –B –T –B –T

27: --15 --15 --16 --16 --17 --17 --18 --18

28: --01 --01 --01 --01 --01 --01 --01 --01

29: --00 --00 --00 --00 --00 --00 --00 --00

2A: --00 --00 --00 --00 --00 --00 --00 --00

2B: --00 --00 --00 --00 --00 --00 --00 --00

2C: --05 --05 --09 --09 --11 --11 --21 --21

2D: --07 --07 --07 --07 --07 --07 --07 --07

2E: --00 --00 --00 --00 --00 --00 --00 --00

2F: --20 --00 --20 --00 --20 --00 --20 --00

30: --00 --01 --00 --01 --00 --01 --00 --01

31: --06 --06 --06 --06 --06 --06 --06 --06

32: --00 --00 --00 --00 --00 --00 --00 --00

33: --00 --00 --00 --00 --00 --00 --00 --00

34: --01 --01 --01 --01 --01 --01 --01 --01

35: --07 --07 --07 --07 --07 --07 --07 --07

36: --00 --00 --00 --00 --00 --00 --00 --00

37: --00 --20 --00 --20 --00 --20 --00 --20

38: --01 --00 --01 --00 --01 --00 --01 --00

64 Mbit 128 Mbit

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 67

C.6 Intel-Specific Extended Query Table

Table C8. Primary Vendor-Specific Extended Query

Offset

(1) Len

th Descri

tion Hex

P = 39h (Optional flash features and commands) Add. Code Value

(P+0)h 3 Primary extended query table 39: --50 "P"

(P+1)h Unique AS CII s tri ng “P RI “ 3A : --5 2 "R"

(P+2)h 3B: --49 "I"

(P+3)h 1 Major version number, ASCII 3C: --31 "1"

(P+4)h 1 Minor version number, ASCII 3D: --33 "3"

(P+5)h 4 Optional feature and command support (1=yes, 0=no) 3E: --E6

(P+6)h

bits 10–31 are reserved; undefined bits are “0.” If bit 31 is

3F: --03

(P+7)h

“1” then another 31 bit field of Optional features follows at

40: --00

(P+8)h

the end of the bit–30 field.

41: --00

bit 0 Chip erase supported bit 0 = 0 No

bit 1 Suspend erase supported bit 1 = 1 Yes

bit 2 Suspend program supported bit 2 = 1 Yes

bit 3 Legacy lock/unlock supported bit 3 = 0 No

bit 4 Queued erase supported bit 4 = 0 No

bit 5 Instant individual block locking supported bit 5 = 1 Yes

bit 6 Protection bits supported bit 6 = 1 Yes

bit 7 Pagemode read supported bit 7 = 1 Yes

bit 8 S

nchronous read supported bit 8 = 1 Yes

bit 9 Simultaneous operations supported bit 9 = 1 Yes

(P+9)h 1 Supported functions after suspend: read Array, Status, Query

Other supported operations are:

bits 1–7 reserved; undefined bits are “0”

42: --01

bit 0 Program supported after erase suspend bit 0 = 1 Yes

(P+A)h 2 Block status register mask 43: --03

(P+B)h

bits 2–15 are Reserved; undefined bits are “0”

44: --00

bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes

bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes

(P+C)h 1 VCC logic supply highest performance program/erase voltage

bits 0–3 BCD value in 100 mV

bits 4

–

7 BCD value in volts

45: --18 1.8V

(P+D)h 1 VPP optimum program/erase supply voltage

bits 0–3 BCD value in 100 mV

4–7 HEX v

in v

46: --C0 12.0V

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

68 Preliminary

Table C9. Protection Register Information

Table C10. Burst Read Information

Table C11. Partition and Erase-block Region Information

Offset

(1) Len

th Descri

tion Hex

P = 39h (Optional flash features and commands) Ad d. Code Value

(P+E)h 1 Number of Protection register fields in JEDEC ID space.

“00h

” indicates that 256 protection fields are available 47: --01 1

(P+F)h 4 Protection Field 1: Protection Description 48: --80 80h

(P+10)h This field describes user-available One Time Pro

rammable 49: --00 00h

(P+11)h (OTP) Protection register bytes. Some are pre-programmed 4A: --03 8 byte

(P+12)h with device-unique serial numbers. Others are user

programmable. Bits 0–15 point to the Protection register Lock

byte, the section’s first byte. The following bytes are factory

pre-progr ammed and user-programmable.

bits 0–7 = Lock/bytes Jedec-plane physical low address

bits 8–15 = Lock /bytes Jedec-plane physical high address

bits 16–23 = “n” such that 2n = factory pre-programmed bytes

bits 24–31 = “n” such that 2n = user pro

rammable b

tes

4B: --03 8 byte

Offset

(1) Len

th Descri

tion Hex

P = 39h (Optional flash features and commands) Add. Code Value

(P+13)h 1 Page Mode Read capabilit y

bits 0–7 = “n” such that 2n HEX value represents the number of

read-page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates no

read

age buffer

4C: --03 8 byte

(P+14)h 1 Number of synchronous mode read configuration fields that

follow. 00h indicates no burst capabilit

.4D: --03 3

(P+15)h 1 Synchronous mode read capability configuration 1

Bits 3–7 = Reserved

bits 0–2 “n” such that 2n+1 HEX value represents the

maximum number of continuous synchronous reads when

the device is configured for its maximum word width. A value

of 07h indicates that the device is capable of continuous

linear bursts that will output data until the internal burst

counter reaches the end of the device’s burstable address

space. This field’s 3-bit value can be written directly to the

Read Configuration Register bits 0–2 if the device is

configured for its maximum word width. See offset 28h for

word width to determine the burst data out

ut width

4E: --01 4

(P+16)h 1 Synchronous mode read capability configuration 2 4F: --02 8

(P+17)h 1 Synchronous mode read capability configuration 3 50: --07 Cont

Bottom Top See table below

Offset

(1)

Offset

(1) Descri

tion Address

P = 39h P = 39h (Optional flash features and commands) Len Bot Top

(P+18)h (P+18)h Number of device hardware-partition regions within the device.

x = 0: a single hardware partition device (no fields follow).

x specifies the number of device partition regions containing

one or more conti

uous erase block re

ions.

1 51: 51:

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 69

Partition Region 1 Information

Offset

(1) See table below

P = 39h Descri

tion Address

Bottom Top (Optional flash features and commands) Len Bot Top

(P+19)h (P+19)h Number of identical partitions within the partition region 2 52: 52:

(P+1A)h (P+1A)h 53: 53:

(P+1B)h (P+1B)h 1 54: 54:

(P+1C)h (P+1C)h 1 55: 55:

(P+1D)h (P+1D)h 1 56: 56:

(P+1E)h (P+1E)h 1 57: 57:

(P+1F)h (P +1F)h Partition Region 1 Erase Block Region 1 Information 4 58: 58:

(P+20)h (P+20)h bits 0–15 = y, y+1 = number of identical-size erase blocks 59: 59:

(P+21)h (P+21)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 5A: 5A:

(P+22)h (P+22)h 5B: 5B:

(P+23)h (P+23)h Partition 1 (Erase Region 1) 25C:5C:

(P+24)h (P+24)h Minimum block erase cycles x 1000 5D: 5D:

(P+25)h (P+25)h 1 5E: 5E:

(P+26)h (P+26)h 1 5F: 5F:

(P+27)h Partition Region 1 Erase Block Region 2 Information 4 60:

(P+28)h bits 0–15 = y, y+1 = number of identical-size erase blocks 61:

(P+29)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 62:

(P+2A)h (bottom parameter device only) 63:

(P+2B)h Partition 1

(

Erase Re

ion 2

)

minimum block erase c

cles x 1000 2 64:

(P+2C)h (bottom parameter device only) 65:

(P+2D)h 1 66:

(P+2E)h 1 67:

Simultaneous program and erase operations allowed in other

partitions while a partition in this region is in Program mode

bits 0–3 = number of simultaneous Program operations

bits 4–7 = number of simultaneous Erase operations

Simultaneous program and erase operations allowed in other

partitions while a partition in this region is in Read mode

bits 0–3 = number of simultaneous Program operations

bits 4–7 = number of simultaneous Erase operations

Simultaneous program and erase operations allowed in other

partitions while a partition in this region is in Erase mode

bits 0–3 = number of simultaneous Program operations

bits 4–7 = number of simultaneous Erase operations

Partitions' erase block regions in this Partition Region.

x = 0 = no erase blocking; the Partition Region erases in

“bulk”

x = number of erase block regions w/ contiguous same-size

ase

tri

rtiti

Partition 1 (erase region 1) bits per cell; internal error correction

bits 0–3 = bits per cell in erase region

bit 4 = reserved for “internal ECC used” (1=yes, 0=no)

bits 5–7 = reserve for future use

Partition 1 (erase region 1) page mode and synchronous mode

capabilities defined in Table 10.

bit 0 = page-mode host reads permitted (1=yes, 0=no)

bit 1 = synchronous host reads permitted (1=yes, 0=no)

bit 2 = synchronous host writes permitted (1=yes, 0=no)

bits 3

–

reserved for future use

Partition 1 (Erase Region 2) bits per cell

(bottom parameter device only)

bits 0–3 = bits per cell in erase region

bit 4 = reserved for “internal ECC used” (1=yes, 0=no)

bits 5–7 = reserve for future use

Partition 1 (Erase Region 2) pagemode and synchronous mode

capabilities defined in Table 10 (bottom parameter device only)

bit 0 = page-mode host reads permitted (1=yes, 0=no)

bit 1 = synchronous host reads permitted (1=yes, 0=no)

bit 2 = synchronous host writes permitted (1=yes, 0=no)

bits 3

–

reserved for future use

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

70 Preliminary

Partition Region 2 Information

Offset

(1) See table below

P = 39h Descri

tion Address

Bottom Top (Optional flash features and commands) Len Bot Top

(P+2F)h (P+27)h Number of i dentical partit ions within t he partit ion region 2 68: 60:

(P+30)h (P+28)h 69: 61:

(P+31)h (P+29)h 1 6A: 62:

(P+32)h (P+2A)h 1 6B: 63:

(P+33)h (P+2B)h 1 6C: 64:

(P+34)h (P+2C)h 1 6D: 65:

(P+35)h (P+2D)h Partition Regi on 2 Erase Block Region 1 Inf ormation 4 6E : 66:

(P+36)h (P+2E)h bits 0–15 = y, y+1 = number of ident i cal-size eras e bloc ks 6F: 67:

(P+37)h (P+2F)h bits 16–31 = z , region erase block(s) size are z x 256 byt es 70: 68:

(P+38)h (P+30)h 71: 69:

(P+39)h (P+31 )h Partit i on 2 (Erase Region 1) 2 72: 6A:

(P+3A)h (P+32)h Minimum block erase cycles x 1000 73: 6B:

(P+3B)h (P+33)h 1 74: 6C:

(P+3C)h (P+34)h 1 75: 6D:

(P+35)h P artition Region 2 Erase Bl ock Regi on 2 Info rmation 4 6E:

(P+36)h bits 0–15 = y, y+1 = number of ident i cal-si ze eras e bl ock s 6F:

(P+37)h bits 16–31 = z, region erase bl ock (s) siz e are z x 256 byt es 70:

(P+38)h (top pa rameter device only ) 71:

(P+39)h Partition 2

(

Erase Re

ion 2

)

minimum bloc k erase c

cles x 100

2 72:

(P+3A)h (top parameter dev i ce only) 73:

(P+3B)h 1 74:

(P+3C)h 1 75:

(P+3D)h (P+3D)h Features Space defini tions (Reserved for future use) TBD 76: 76:

(

P+3E

)

(

P+3E

)

h Reserved for f uture us e Resv ' d 77: 77:

Simultaneous program and erase operations allowed i n other

partiti ons whil e a partition in thi s region i s in Program mode

bits 0–3 = number of simultaneous P rogram operati ons

bits 4–7 = number of simultaneous E rase operat i ons

Simultaneous program and erase operations allowed i n other

partiti ons whil e a partition in thi s region i s in Read mode

bits 0–3 = number of simultaneous P rogram operati ons

bits 4–7 = number of simultaneous E rase operat i ons

Partit i on 2 (Eras e Region 2) bit s per c el l (top paramet er only)

bits 0–3 = bits per c el l i n erase region

bit 4 = reserved for “internal E CC used” (1=yes, 0=no)

bits 5–7 = reserve for future use

Partit i on 2 (Eras e Region 2) pag emode and sy nchronous mode

capabilit ies as defined in Table 10. (top paramet er only)

bit 0 = page-mode host reads permitted (1=yes, 0=no)

bit 1 = synchronous hos t reads permi tted ( 1=yes, 0=no)

bit 2 = synchronous hos t writes permit ted (1=y es, 0=no)

bits 3

–

reserved for future use

Simultaneous program and erase operations allowed i n other

partiti ons whil e a partition in thi s region i s in Erase mode

bits 0–3 = number of simultaneous P rogram operati ons

bits 4–7 = number of simultaneous E rase operat i ons

Partit i ons' erase block regions i n this Parti tion Regi on.

x = 0 = no erase blocking; the Partition Region erases in

“bulk”

x = number of erase bl ock regions w/ contiguous same-size

erase blocks. Symmetrically blocked

artitions have one

Partition 2 (E rase Regi on 1) bits per cel l

bits 0–3 = bits per c el l in erase region

bit 4 = reserved for “internal ECC used” (1=yes, 0=no)

bits 5–7 = reserve for future use

Partit i on 2 (erase region 1) pagemode and sy nchronous mode

capabilit ies as defined in Table 10.

bit 0 = page-mode host reads permitted (1=yes, 0=no)

bit 1 = synchronous hos t reads permi tted ( 1=yes, 0=no)

bit 2 = synchronous hos t writes permit ted (1=y es, 0=n o)

bits 3

–

reserved for future use

28F6408W30, 28F3208W30, 28F3204W30, 28F320W30

Preliminary 71

Partition and Erase-block Region Information

NOTES:

1. The variable P is a pointer which is defined at CFI offset 15h.

2. For a 16Mb the 1.8 Volt Intel® Wireless Flash memory z1 = 0100h = 256 ⇒ 256 * 256 = 64K, y1 = 17h = 23d

⇒ y1+1 = 24 ⇒

24 * 64K = 1½MB ⇒ Partition 2’s offset is 0018 0000h bytes (000C 0000h words).

3. TPD - Top parameter device; BPD - Bottom parameter device.

4. Partition: Each partition is 4Mb in size. It can contain main blocks OR a combination of both main and

parameter blocks.

5. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains

all the partitions that are made up of main blocks only. B. contains the partition that is made up of the

parameter and the main blocks.

Address 16 Mbit 32 Mbit

–B –T –B –T –B –T –B –T

51: --02 --02 --02 --02 --02 --02 --02 --02

52: --01 --03 --01 --07 --01 --0F --01 --1F

53: --00 --00 --00 --00 --00 --00 --00 --00

54: --01 --01 --01 --01 --01 --01 --01 --01

55: --00 --00 --00 --00 --00 --00 --00 --00

56: --00 --00 --00 --00 --00 --00 --00 --00

57: --02 --03 --02 --07 --02 --F --02 --1F

58: --07 --07 --07 --07 --07 --07 --07 --07

59: --00 --00 --00 --00 --00 --00 --00 --00

5A: --20 --00 --20 --00 --20 --00 --20 --00

5B: --00 --01 --00 --01 --00 --01 --00 --01

5C: --64 --64 --64 --64 --64 --64 --64 --64

5D: --00 --00 --00 --00 --00 --00 --00 --00

5E: --01 --01 --01 --01 --01 --01 --01 --01

5F: --02 --03 --02 --03 --02 --03 --02 --03

60: --06 --01 --06 --01 --06 --01 --06 --01

61: --00 --00 --00 --00 --00 --00 --00 --00

62: --00 --01 --00 --01 --00 --01 --00 --01

63: --01 --00 --01 --00 --01 --00 --01 --00

64: --64 --00 --64 --00 --64 --00 --64 --00

65: --00 --02 --00 --02 --00 --02 --00 --02

66: --01 --06 --01 --06 --01 --06 --01 --06

67: --03 --00 --03 --00 --03 --00 --03 --00

68: --03 --00 --07 --00 --0F --00 --1F --00

69: --00 --01 --00 --01 --00 --01 --00 --01

6A: --01 --64 --01 --64 --01 --64 --01 --64

6B: --00 --00 --00 --00 --00 --00 --00 --00

6C: --00 --01 --00 --01 --00 --01 --00 --01

6D: --03 --03 --07 --03 --F --03 --1F --03

6E: --07 --07 --07 --07 --07 --07 --07 --07

6F: --00 --00 --00 --00 --00 --00 --00 --00

70: --00 --20 --00 --20 --00 --20 --00 --20

71: --01 --00 --01 --00 --01 --00 --01 --00

72: --64 --64 --64 --64 --64 --64 --64 --64

73: --00 --00 --00 --00 --00 --00 --00 --00

74: --01 --01 --01 --01 --01 --01 --01 --01

75: --03 --02 --03 --02 --03 --02 --03 --02

64Mbit 128Mbit