CY62126EV30LL45ZSXIT - CYPRESS SEMICONDUCTOR

10-Bit, 4× Oversampled SDTV Video Decoder

with Differential Inputs and Deinterlacer

Data Sheet

ADV7283

Rev. A Document Feedback

Info rm at ion f urn i sh ed b y An alo g Device s is b e li e ve d to b e accu rate and r el i ab le . How e ve r, no

re sp on si bi l it y i s a s sum ed by A na lo g De v ic es fo r i t s u s e, no r fo r any in fr ing em en t s of pa te nt s o r o th er

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Trademark s and register ed trademark s are the property of their respective owners.

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Technica l Support www.analog.com

FEATURES

Worldwide NTSC/PAL/SECAM color demodulation support

One 10-bit analog-to-digital converter (ADC), 4× oversampling

per channel for CVBS, Y/C, and YPrPb modes

6 analog video input channels with on-chip antialiasing

filters

Video input support for CVBS (composite), Y/C (S-Video), and

YPrPb (component)

Fully differential, pseudo differential, and single-ended

CVBS video input support

NTSC/PAL/SECAM autodetection

Up to 4 V common-mode input range solution

Excellent common-mode noise rejection capabilities

5-line adaptive 2D comb filter and CTI video enhancement

Adaptive Digital Line Length Tracking (ADLLT), signal

processing, and enhanced FIFO management provide

time-base correction (TBC) functionality

Integrated automatic gain control (AGC) with adaptive peak

white mode

Fast switching capability

Integrated interlaced-to-progressive (I2P) video output

converter (deinterlacer)

Adaptive contrast enhancement (ACE)

Down dither (8-bit to 6-bit)

Rovi® (Macrovision) copy protection detection

8-bit ITU-R BT.656 YCrCb 4:2:2 output

Full featured vertical blanking interval (VBI) data slicer with

world system teletext (WST) support

Power-down mode available

2-wire, I2C-compatible serial interface

Qualified for automotive applications

−40°C to +105°C automotive temperature grade

−40°C to +85°C industrial qualified temperature grade

32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP

APPLICATIONS

Automotive infotainment

Smartphone/multimedia handsets

DVRs for video security

Media players

GENERAL DESCRIPTION

The ADV7283 is a versatile one-chip, multiformat video

decoder that automatically detects standard analog baseband

video signals compatible with worldwide NTSC, PAL, and

SECAM standards in the form of composite, S-Video, and

component video.

The ADV7283 converts the analog video signals into a YCrCb

4:2:2 video data stream that is compatible with the 8-bit ITU-R

BT.656 interface standard.

The six analog video inputs of the ADV7283 can accept single-

ended, pseudo differential, and fully differential signals.

The ADV7283 contains a deinterlacer (I2P converter) that

allows the device to output video in a progressive format.

The ADV7283 is programmed via a 2-wire, serial bidirectional

port (I2C compatible) and is fabricated in a 1.8 V CMOS

process.

The ADV7283 is provided in a space-saving LFCSP surface-

mount, RoHS-compliant package.

The ADV7283 is available in an automotive grade rated over the

−40°C to +105°C temperature range, as well as a −40°C to +85°C

temperature range, making the device ideal for both automotive

and industrial applications.

ADV7283 Data Sheet

Rev. A | Page 2 of 21

TABLE OF CONTENTS

Features .....................................................................................1

Applications...............................................................................1

General Description ..................................................................1

Revision History ........................................................................2

Functional Block Diagram.........................................................3

Specifications .............................................................................4

Electrical Specifications .........................................................4

Video Specifications...............................................................5

Analog Specifications.............................................................6

Clock and I2C Timing Specifications......................................6

Pixel Port Timing Specifications ............................................7

Absolute Maximum Ratings ......................................................8

Thermal Resistance ................................................................8

ESD Caution ..........................................................................8

Pin Configuration and Function Descriptions...........................9

Theory of Operation................................................................10

Analog Front End ................................................................10

Standard Definition Processor .............................................11

Power Supply Sequencing ........................................................12

Optimal Power-Up Sequence ...............................................12

Simplified Power-Up Sequence ............................................12

Power-Down Sequence........................................................ 12

DVDDIO Supply Voltage .......................................................... 12

Power Supply Requirements ................................................ 12

Input Networks........................................................................ 13

Single-Ended Input Network ............................................... 13

Differential Input Network .................................................. 13

Short-to-Battery Protection ................................................. 13

Applications Information ........................................................ 14

In put Con f ig urat ion............................................................. 14

Adaptive Contrast Enhancement ......................................... 15

I2P Function ........................................................................ 15

ITU-R BT.656 Transmitter Configuration ........................... 15

I2C Port Description ............................................................ 16

PCB Layout Recommendations ........................................... 18

Typical Circuit Connection ..................................................... 20

Outline Dimensions ................................................................ 21

Ordering Guide ................................................................... 21

Automotive Products ........................................................... 21

REVISION HISTORY

10/2016—Rev. 0 to Rev. A

Changes to Ordering Guide .....................................................21

5/2014—Revision 0: Initial Version

Data Sheet ADV7283

Rev. A | Page 3 of 21

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

XTALP

XTALN

DIFFERENTIAL

SINGLE-ENDED

ANALOG VIDEO

INPUTS

FILTER

DIGITAL

PROCESSING

BLOCK

2D COM B

VBI SLICER

I2P

COLOR

DEMOD

SCLK SDATA ALSB RESET PWRDWN

10-BI T ADC

REFERENCE

PLL ADL LT PROCESS ING

CLOCK PROCE S S ING BLOCK

C/CONTROL

MUX BLOCK

FIFO

OUTPUT BLOCK

ADV7283

SHA

–

ADC

LLC

INTRQ

ACE

DOWN

DITHER

12347-001

8-BIT

PIXEL DATA

P0 TO P7

NOTES

1. SHA IS A SAM P LE-AND- HOLD AM P LIF IER CI RCUIT.

ADV7283 Data Sheet

Rev. A | Page 4 of 21

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Ty p Max Unit

STATIC PERFORMANCE

ADC Resolution N 10 Bits

Integral Nonlinearity INL CVBS mode 2 LSB

Differential Nonlinearity DNL CVBS mode ±0.6 LSB

DIGITAL INPUTS

Input High Voltage VIH DVDDIO = 3.3 V 2 V

DVDDIO = 1.8 V 1.2 V

Input Low Voltage VIL DVDDIO = 3.3 V 0.8 V

DVDDIO = 1.8 V 0.4 V

Input Leakage Current IIN RESET pin −10 +10 µA

SDATA, SCLK pins −10 +15 µA

PWRDWN, ALSB pins −10 +50 µA

Input Capacitance CIN 10 pF

CR Y STA L I NP U T

Input High Voltage VIH XTA L N p i n 1.2 V

Input Low Voltage VIL XTA L N pin 0.4 V

DIGITAL OUTPUTS

Output High Voltage VOH DVDDIO = 3.3 V, ISOU R CE = 0.4 mA 2.4 V

DVDDIO = 1.8 V, ISOU R CE = 0.4 mA 1.4 V

Output Low Voltage VOL DVDDIO = 3.3 V, ISIN K = 3.2 mA 0.4 V

DVDDIO = 1.8 V, ISIN K = 1.6 mA 0.2 V

High Impedance Leakage Current ILEAK 10 µA

Output Capacitance COUT 20 pF

POWER REQUIREMENTS1, 2, 3

Digital I/O Power Supply DVDDIO 1.62 3.3 3.63 V

PLL Power Supply PVDD 1.71 1.8 1.89 V

Analog Power Supply AVDD 1.71 1.8 1.89 V

Digital Power Supply DVDD 1.71 1.8 1.89 V

Digital I/O Supply Current IDVDDIO 5 mA

PLL Supply Current

IPVDD 12 mA

Analog Supply Current

IAVDD

Single-Ended CVBS Input 47 mA

Differential CVBS Input

Fully differential and pseudo

differential CVBS

69 mA

Y/C Input 60 mA

YPrPb Input 75 mA

Digital Supply Current IDVDD

Single-Ended CVBS Input 70 mA

Differential CVBS Input

Fully differential and pseudo

differential CVBS

70 mA

Y/C Input 70 mA

YPrPb Input 70 mA

Data Sheet ADV7283

Rev. A | Page 5 of 21

Parameter Symbol Test Conditions/Comments Min Ty p Max Unit

POWER-DOWN CURRENTS1

Digital I/O Supply Power-Down

Current

IDVDDIO_PD

73 µA

PLL Supply Power-Down Current IPVDD_PD 46 µA

Analog Supply Power-Down Current IAVDD_PD 0.2 µA

Digital Supply Power-Down Current IDVDD_PD 420 µA

Total Power Dissipation in Power-

Down Mode

1 mW

1 Guaranteed by characterization.

2 Typical current consumption values are measured with nominal voltage supply levels and an SMPTE bar test pattern.

3 All specifications apply when the I2P core is activated, unless otherwise stated.

VIDEO SPECIFICATIONS

AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.

Specifications guaranteed by characterization.

Table 2.

Parameter Symbol Test Conditions/Comments Min Ty p Max Unit

NONLINEAR SPECIFICATIONS1

Differential Phase DP CVBS input, modulated five-step 0.9 Degrees

Differential Gain DG CVBS input, modulated five-step 0.5 %

Luma Nonlinearity LNL CVBS input, five-step 2.0 %

NOISE SPECIFICATIONS

Signal-to-Noise Ratio (SNR),

Unweighted

SNR Luma ramp 57.1 dB

Luma flat field 58 dB

Analog Front-End Crosstalk 60 dB

Common-Mode Rejection Ratio 2 CMRR 73 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range −5 +5 %

Vertical Lock Range

40 70 Hz

Subcarrier Lock Range

fSC ±1.3 kHz

Color Lock-In Time 60 Lines

Synchronization Depth Range 20 200 %

Color Burst Range 5 200 %

Fast Switch Speed3 100 ms

1 These specifications apply for all CVBS input types (NTSC, PAL, and SECAM), as well as for single-ended and differential CVBS inputs.

2 The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Networks section). The CMRR measurement

was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.

3 Fast switch speed is the time required for the ADV7283 to switch from one analog input (single-ended or differential) to another, for example, switching from AIN1 to AIN2.

ADV7283 Data Sheet

Rev. A | Page 6 of 21

ANALOG SPECIFICATIONS

AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.

Specifications guaranteed by characterization.

Table 3.

Parameter Test Conditions/Comments Min Ty p Max Unit

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 µF

Input Impedance Clamps switched off 10 MΩ

Large Clamp Source Current 0.4 mA

Large Clamp Sink Current 0.4 mA

Fine Clamp Source Current 10 µA

Fine Clamp Sink Current 10 µA

CLOCK AND I2C TIMING SPECIFICATIONS

AVDD, DVDD, and PVDD= 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.

Specifications guaranteed by characterization.

Table 4.

Parameter Symbol Min Typ Max Unit

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency 28.63636 MHz

Frequency Stability ±50 ppm

I2C PORT

SCLK Frequency 400 kHz

SCLK Minimum Pulse Width High t1 0.6 µs

SCLK Minimum Pulse Width Low t2 1.3 µs

Hold Time (Start Condition) t3 0.6 µs

Setup Time (Start Condition) t4 0.6 µs

SDATA Setup Time t5 100 ns

SCLK and SDATA Rise Times

t6 300 ns

SCLK and SDATA Fall Times

t7 300 ns

Setup Time (Stop Condition) t8 0.6 µs

RESET INPUT

RESET Pulse Width 5 ms

Figure 2. I2C Timing Diagram

SDATA

SCLK

t3t5t3

t4t8

12347-002

Data Sheet ADV7283

Rev. A | Page 7 of 21

PIXEL PORT TIMING SPECIFICATIONS

AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.

Specifications guaranteed by characterization.

Table 5.

Parameter Symbol Test Conditions/Comments Min Ty p Max Unit

CLOCK OUTPUTS

LLC Output Frequency 27 MHz

LLC Mark Space Ratio t16:t17 45:55 55:45 % duty cycle

DATA AND CONTROL OUTPUTS

Data Output Transitional Time t18

Negative clock edge to start of valid data

(tSETU P = t17 − t18)

3.8 ns

t19 End of valid data to negative clock edge

(tHOLD = t16 − t19)

6.9 ns

Figure 3. Pixel Port and Control Output Timing Diagram

OUTPUT LLC

P0 TO P7 OUTPUTS

12347-201

ADV7283 Data Sheet

Rev. A | Page 8 of 21

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter1

Rating

AVDD to GND 2.2 V

DVDD to GND 2.2 V

PVDD to GND 2.2 V

DVDDIO to GND 4 V

PVDD to DVDD −0.9 V to +0.9 V

AVDD to DVDD −0.9 V to +0.9 V

Digital Inputs (RESET, ALSB,

SDATA, SCLK, PWRDWN)

Voltage

GND − 0.3 V to DVDDIO + 0.3 V

Digital Outputs (P7 to P0,

INTRQ, LLC) Voltage

GND − 0.3 V to DVDDIO + 0.3 V

Analog Inputs (X TA LN , A

1 to

AIN6) to Ground

GND − 0.3 V to AVDD + 0.3 V

Maximum Junction Temperature

(TJ max)

140°C

Storage Temperature Range −65°C to +150°C

1 The absolute maximum ratings assume that the DGND pins and the exposed

pad of the ADV7283 are connected together to a common ground plane

(GND). This is part of the recommended layout scheme. See the PCB Layout

Recommendations section for more information. The absolute maximum

ratings are stated in relation to this common ground plane.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

The thermal resistance values in Table 7 are specified for the

device soldered onto a 4-layer printed circuit board (PCB) with

a common ground plane (GND) and with the exposed pad of

the device connected to DGND. The values in Table 7 are

maximum values.

Table 7. Thermal Resistance for the 32-Lead LFCSP

Thermal Characteristic Symbol Value Unit

Junction to Ambient Thermal

Resistance (Still Air)

θJA 32.5 °C/W

Junction to Case Thermal

Resistance

θJC 2.3 °C/W

ESD CAUTION

Data Sheet ADV7283

Rev. A | Page 9 of 21

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Ty p e Description

1, 4 DGND Ground

Ground for Digital Supply. The exposed pad and DGND pins must be connected together

to a common ground plane (GND).

2 DVDDIO Power Digital Input/Output Power Supply (1.8 V or 3.3 V).

3, 13 DVDD Power Digital Power Supply (1.8 V).

5 to 12 P7 to P0 Output Video Pixel Output Ports.

14 XTA L P Output Output for the External 28.63636 MHz Crystal. Connect this pin to the external

28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock

oscillator source is used to clock the ADV7283. The crystal used with the ADV7283 must be

a fundamental crystal.

15 XTA L N Input

Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7283 must

be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used

to clock the ADV7283, the output of the oscillator is fed into the XTALN pin.

16 PVDD Power

PLL Power Supply (1.8 V).

17,18, 22 to

AIN1 to AIN6 Input Analog Video Input Channels.

19 VREFP Output Internal Voltage Reference Output.

20 VREFN Output Internal Voltage Reference Output.

21 AVDD Power Analog Power Supply (1.8 V).

26 INTRQ Output

Interrupt Request Output. An interrupt occurs when certain signals are detected on the

input video.

27 RESET Input

System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to

reset the ADV7283 circuitry.

28 ALSB Input

Selector for the I2C Write Address. When ALSB is set to Logic 0, the write address is 0x40;

when ALSB is set to Logic 1, the write address is 0x42.

29 SDATA Input/output I2C Port Serial Data Input/Output.

30 SCLK Input I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.

31 PWRDWN Input Power-Down Pin. A logic low on this pin places the ADV7283 in power-down mode.

32 LLC Output Line-Locked Output Clock for Output Pixel Data. The clock output is typically 27 MHz, but it

increases or decreases according to the video line length.

EPAD (EP)

Exposed Pad. The exposed pad and DGND pins must be connected together to a common

ground plane (GND).

12347-057

DGND

DVDDIO

DVDD

DGND

VREFP

VREFN

VDD

PIN 1

INDICATOR

ADV7283

LFCSP

TOP VIEW

(No t t o Scale)

VDD

XTALN

XTALP

VDD

RESET

ALSB

SDATA

SCLK

PWRDWN

INTRQ

LLC

NOTES

1. T HE E X P OSED P AD AND DGND PI NS M US T BE

CONNECTED T OGE THER T O A COMM ON GROUND

PLANE ( GND).

ADV7283 Data Sheet

Rev. A | Page 10 of 21

THEORY OF OPERATION

The ADV7283 is a versatile one-chip, multiformat video

decoder. The device automatically detects standard analog

baseband video signals compatible with worldwide NTSC, PAL,

and SECAM standards in the form of composite, S-Video, and

component video.

The ADV7283 converts the analog video signals into an 8-bit

YCrCb 4:2:2 video data stream that is compatible with the 8-bit

ITU-R BT.656 interface standard.

The analog video inputs of the ADV7283 accept single-ended,

pseudo differential, and fully differential composite video signals,

as well as S-Video and YPrPb video signals, supporting a wide

range of consumer and automotive video sources.

In differential CVBS mode, the ADV7283, along with an

external resistor divider, provides a common-mode input range

of up to 4 V, enabling the removal of large signal, common-mode

transients present on the video lines.

The advanced I2P function allows the ADV7283 to convert an

interlaced video input into a progressive video output. This

function is performed without the need for external memory.

The ADV7283 uses edge adaptive technology to minimize

video defects on low angle lines.

The AGC and clamp restore circuitry allow an input video

signal peak-to-peak range of 1.0 V p-p at the analog video input

pins of the ADV7283. Alternatively, the AGC and clamp restore

circuitry can be bypassed for manual settings.

The external ac coupling capacitors protect the ADV7283 from

short-to-battery (STB) events on the analog video input pins.

The ADV7283 supports a number of other functions, including

8-bit to 6-bit down dither mode and ACE.

The ADV7283 is programmed via a 2-wire, serial bidirectional

port (I2C compatible) and is fabricated in a 1.8 V CMOS

process. The monolithic CMOS construction of the ADV7283

ensures greater functionality with lower power dissipation.

The ADV7283 is provided in a space-saving LFCSP surface-

mount, RoHS-compliant package.

The ADV7283 is available in an automotive grade that is rated

over the−40°C to +105°C temperature range, making the device

ideal for automotive applications.

The ADV7283 is also available in a −40°C to +85°C temperature

range, making it ideal for industrial applications.

ANALOG FRONT END

The analog front end (AFE) of the ADV7283 comprises a single

high speed, 10-bit ADC that digitizes the analog video signal

before applying it to the standard definition processor (SDP).

The AFE uses differential channels to the ADC to ensure high

performance in mixed-signal applications and to enable different ial

CVBS inputs to connect directly to the ADV7283.

The AFE also includes an input mux that enables the

application of multiple video signals to the ADV7283. The input

mux allows the application of up to six composite video signals to

the ADV7283.

Current clamps are positioned in front of the ADC to ensure

that the video signal remains within the range of the converter.

A resistor divider network is required before each analog input

channel to ensure that the input signal is kept within the range

of the ADC (see the Input Networks section). Fine clamping of

the video signal is performed downstream by digital fine

clamping within the ADV7283.

Table 9 lists the three ADC clock rates that are determined by

the video input format to be processed. These clock rates ensure

4× oversampling per channel for CVBS, Y/C, and YPrPb modes.

Table 9. ADC Clock Rates

Input Format

ADC Clock Rate

(MHz)1

Oversampling

Rate per

Channel

CVBS (Composite) 57.27 4×

Y/C (S-Video) 114 4×

YPrPb (Component) 172 4×

1 Based on a 28.63636 MHz crystal between the XTALP and XTALN pins.

The fully differential AFE of the ADV7283 provides inherent

small and large signal noise rejection, improved

electromagnetic interference (EMI) protection, and the ability

to absorb ground bounce. Support is provided for both true

differential and pseudo differential signals.

Data Sheet ADV7283

Rev. A | Page 11 of 21

STANDARD DEFINITION PROCESSOR

The ADV7283 can decode a large selection of baseband video

signals in composite (both single-ended and differential),

S-Video, and component formats. The video processor supports

the following standards:

• PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,

PAL Nc, PAL 60

• NTSC J, NTSC M, NTSC 4.43

• SECAM B, SECAM D, SECAM G, SECAM K, SECAM L

Using the SDP, the ADV7283 can automatically detect the video

standard and process it accordingly.

The ADV7283 has a five-line adaptive 2D comb filter that

provides superior chrominance and luminance separation when

decoding a composite video signal. This highly adaptive filter

automatically adjusts its processing mode according to the

video standard and signal quality without user intervention.

Video user controls such as brightness, contrast, saturation, and

hue are also available with the ADV7283.

The ADV7283 implements the patented Adaptive Digital Line

Length Tracking (ADLLT™) algorithm to track varying video line

lengths from sources such as VCRs. ADLLT enables the

ADV7283 to track and decode poor quality video sources such as

VCRs and noisy sources from tuner outputs and camcorders.

The ADV7283 contains a chroma transient improvement (CTI)

processor that sharpens the edge rate of chroma transitions,

resulting in sharper vertical transitions.

The ACE feature of the ADV7283 offers improved visual detail

using an algorithm that automatically varies contrast levels to

enhance picture detail. ACE increases the contrast in dark areas

of an image without saturating the bright areas of the image.

This feature is particularly useful in automotive applications,

where it can be important to discern objects in shaded areas.

Down dithering converts the output of the ADV7283 from an

8-bit to a 6-bit output, enabling ease of design for standard LCD

panels.

The I2P block converts the interlaced video input into a

progressive video output without the need for external memory.

The SDP can process a variety of VBI data services, such as closed

captioning (CCAP), wide screen signaling (WSS), copy generation

management systems (CGMS), and teletext data slicing for

world system teletext (WST).

The ADV7283 is fully Rovi® (Macrovision) compliant; detection

circuitry enables Type I, Ty pe II, and Type III protection levels

to be identified and reported to the user. The decoder is also

fully robust to all Rovi signal inputs.

ADV7283 Data Sheet

Rev. A | Page 12 of 21

POWER SUPPLY SEQUENCING

OPTIMAL POWER-UP SEQUENCE

The optimal power-up sequence for the ADV7283 is to first

power up the 3.3 V DVDDIO supply, followed by the 1.8 V supplies

(DVDD, PVDD, and AVDD).

When powering up the ADV7283, follow these steps (during

power-up, all supplies must adhere to the specifications listed in

the Absolute Maximum Ratings section):

1. Assert the

PWRDWN and RESET pins (pull the pins low).

2. Power up the DVDDIO supply.

3. After DVDDIO is fully asserted, power up the 1.8 V supplies.

4. After the 1.8 V supplies are fully asserted, pull

the PWRDWN pin high.

5. Wait 5 ms and then pull the RESET pin high.

6. After all power supplies and the PWRDWN and RESET

pins

are powered up and stable, wait an additional 5 ms before

initiating I2C communication with the ADV7283.

SIMPLIFIED POWER-UP SEQUENCE

Alternatively, the ADV7283 can be powered up by asserting all

supplies and the PWRDWN and RESET pins simultaneously.

After this operation, perform a software reset, then wait 10 ms

before initiating I2C communication with the ADV7283.

While the supplies are being established, ensure that a lower

rated supply does not go above a higher rated supply level.

During power-up, all supplies must adhere to the specifications

listed in the Absolute Maximum Ratings section.

POWER-DOWN SEQUENCE

The ADV7283 supplies can be deasserted simultaneously as

long as DVDDIO does not go below a lower rated supply.

DVDDIO SUPPLY VOLTAGE

Under normal operating conditions, the ADV7283 operates

with a nominal DVDDIO voltage of 3.3 V. The device can also

operate with a nominal DVDDIO voltage of 1.8 V. When operating

with a nominal voltage of 1.8 V, apply the power-up sequences

described in the Optimal Power-Up Sequence and Simplified

Power-Up Sequence sections. The only changes are that DVDDIO

is powered up to 1.8 V instead of 3.3 V, and the PWRDWN

and RESET pins of the ADV7283 are powered up to 1.8 V

instead of 3.3 V.

Note that when the ADV7283 operates with a nominal DVDDIO

voltage of 1.8 V, t h e n set the drive strength of all digital outputs

to a maximum.

Note that when DVDDIO is set to a nominal voltage of 1.8 V, no

pins can be pulled up to 3.3 V. For example, pull the I2C pins of

the ADV7283 (SCLK and SDATA) up to 1.8 V instead of

3.3 V.

POWER SUPPLY REQUIREMENTS

Table 10 shows the current rating recommendations for power

supply design. Use these values when designing a power supply

section to ensure that an adequate current is supplied to the

ADV7283.

Table 10. Current Rating Recommendations for Power

Supply Design

Current Rating

IDVDDIO 20 mA

IDVDD 110 mA

IAVDD 100 mA

IPVDD 20 mA

Figure 5. Optimal Power-Up Sequence

3.3V

1.8V

VOLTAGE

TIME3.3V SUPPLY

POWER-UP 1.8V SUPPLIES

POWER-UP

3.3V SUPPLY PWRDWN PIN

PWRDWN PIN

POWER-UP RESET PIN

POWER-UP

RESET PIN

1.8V SUPPLIES

5ms

RESET

OPERATION

5ms

WAIT

12347-005

Data Sheet ADV7283

Rev. A | Page 13 of 21

INPUT NETWORKS

An input network (external resistor and capacitor circuit) is

required on the AINx input pins of the ADV7283. The

components of the input network depend on the video format

selected for the analog input.

SINGLE-ENDED INPUT NETWORK

Figure 6 shows the input network to use on each AINx input pin

of the ADV7283 when any of the following video input formats

are used:

• Single-ended CVBS

• Y/C (S-Vide o)

• YPrPb

Figure 6. Single-Ended Input Network

The 24 Ω and 51 Ω resistors supply the 75 Ω end termination

required for the analog video input. These resistors also create a

resistor divider with a gain of 0.68. The resistor divider attenuates

the amplitude of the input analog video and scales the input to the

ADC range of the ADV7283. This allows an input range of up to

1.47 V p-p. Note that amplifiers within the ADC restore the

amplitude of the input signal so SNR performance is

maintained.

The 100 nF ac coupling capacitor removes the dc bias of the analog

input video before it is fed into the AINx pins of the ADV7283.

The clamping circuitry within the ADV7283 restores the dc bias

of the input signal to the optimal level before it is fed into the

ADC of the ADV7283.

DIFFERENTIAL INPUT NETWORK

Figure 7 shows the input network to use when differential

CVBS video is input on the AINx input pins of the ADV7283.

Figure 7. Differential Input Network

Fully differential video transmission involves transmitting two

complementary CVBS signals. Pseudo differential video

transmission involves transmitting a CVBS signal and a source

ground signal.

Differential video transmission has several key advantages over

single-ended transmission, including

• Inherent small signal and large signal noise rejection

• Improved EMI performance

• An ability to absorb ground bounce

Resistor R1 provides the RF end termination for the differential

CVBS input lines. For a pseudo differential CVBS input, a value

of 75 Ω is recommended for R1. For a fully differential CVBS

input, a value of 150 Ω is recommended for R1.

The 1.3 kΩ and 430 Ω resistors create a resistor divider with a

gain of 0.25. The resistor divider attenuates the amplitude of the

input analog video, but increases the input common-mode range

of the ADV7283 to 4 V p-p. Note that amplifiers within the

ADC restore the amplitude of the input signal so that SNR

performance is maintained.

The 100 nF ac coupling capacitors remove the dc bias of the

analog input video before it is fed into the AINx pins of the

ADV7283. The clamping circuitry within the ADV7283 restores

the dc bias of the input signal to the optimal level before it is fed

into the ADC of the ADV7283.

The combination of the 1.3 kΩ and 430 Ω resistors and the

100 nF ac coupling capacitors limits the current flow into the

ADV7283 during STB events (see the Short-to-Battery

Protection section).

To achieve optimal performance, the 1.3 kΩ and 430 Ω resistors

must be closely matched; that is, all 1.3 kΩ and 430 Ω resistors

must have the same resistance tolerance, and this tolerance must

be as low as possible.

SHORT-TO-BATTERY PROTECTION

In differential mode, the ADV7283 is protected against STB

events by the external 100 nF ac coupling capacitors (see

Figure 7). The external input network resistors are sized to be

large enough to reduce the current flow during an STB event,

but small enough to avoid affecting the operation of the

ADV7283.

The power rating of the input network resistors must be chosen

withstand the high voltages of STB events. Similarly, ensure that

the breakdown voltage of the ac coupling capacitors is robust

enough to handle STB events.

The R1 resistor is protected because no current or limited current

flows through it during an STB event.

51Ω

INPUT

CONNECTOR

VIDE O INP UT

FRO M SOURCE

24Ω 100nF

EXT

ESD

12347-006

POSITIVE

INPUT

CONNECTOR

NEGATIVE

INPUT

CONNECTOR

VIDE O INP UT

FRO M SOURCE EXT

ESD R1

1.3kΩ 100nF

430Ω

12347-007

ADV7283 Data Sheet

Rev. A | Page 14 of 21

APPLICATIONS INFORMATION

INPUT CONFIGURATION

The input format of the ADV7283 is specified using the

INSEL[4:0] bits (see Table 11). These bits also configure the SDP

core to process CVBS, differential CVBS, Y/C (S-Vide o ), or

component (YPrPb) format. The INSEL[4:0] bits are located in

the user sub map of the register space at Address 0x00[4:0]. For

more information about the registers, see the Register Maps

section.

The INSEL[4:0] bits specify predefined analog input routing

schemes, eliminating the need for manual mux programming

and allowing the user to route the various video signal types to

the decoder. For example, if the CVBS input is selected, the

remaining channels are powered down.

Table 11. Input Format Specified by the INSEL[4:0] Bits

INSEL[4:0] Bit Value

Video Format

Analog Inputs

00000 CVBS CVBS input on AIN1

00001 CVBS CVBS input on AIN2

00010 CVBS CVBS input on AIN3

00011 CVBS CVBS input on AIN4

00100 Reserved Reserved

00101 Reserved Reserved

00110 CVBS CVBS input on AIN5

00111 CVBS CVBS input on AIN6

01000 Y/C (S-Video) Y input on AIN1

C input on AIN2

01001 Y/C (S-Video) Y input on AIN3

C input on AIN4

01010 Reserved Reserved

01011 Y/C (S-Video)

Y input on A

IN5

C input on A

IN6

01100 YPrPb Y input on AIN1

Pb input on AIN2

Pr input on AIN3

01101 Reserved Reserved

01110 Differential CVBS Positive input on AIN1

Negative input on AIN2

01111 Differential CVBS Positive input on AIN3

Negative input on AIN4

10000 Reserved Reserved

10001 Differential CVBS Positive input on AIN5

Negative input on AIN6

10010 to 11111 Reserved Reserved

Data Sheet ADV7283

Rev. A | Page 15 of 21

ADAPTIVE CONTRAST ENHANCEMENT

The ADV7283 can increase the contrast of an image depending

on the content of the picture, making bright areas brighter and

dark areas darker. The optional ACE feature increases the

contrast within dark areas without significantly affecting the

bright areas. The ACE feature is particularly useful in

automotive applications, where it is important to discern objects

in shaded areas.

The ACE function is disabled by default. To enable the ACE

function, execute the following register writes:

1. Write 0x40 to Register 0x0E in User Sub Map (0x40 or

0x42). This enters User Sub Map 2.

2. Write 0x80 to Register 0x80 in User Sub Map 2 (0x40 or

0x42). This enables ACE.

3. Write 0x00 to Register 0x0E in User Sub Map 2 (0x40 or

0x42). This reenters User Sub Map.

To disable the ACE function, execute the following register

writes:

1. Write 0x40 to Register 0x0E in User Sub Map (0x40 or

0x42). This enters User Sub Map 2.

2. Write 0x00 to Register 0x80 in User Sub Map 2 (0x40 or

0x42). This disables ACE.

3. Write 0x00 to Register 0x0E in User Sub Map 2 (0x40 or

0x42). This reenters User Sub Map.

I2P FUNCTION

The I2P function of the ADV7283 allows the device to convert

an interlaced video input into a progressive video output. This

function is performed without the need for external memory.

The ADV7283 use edge adaptive technology to minimize video

defects on low angle lines.

The I2P function is disabled by default. To enable the I2P func-

tion, use the recommended scripts from Analog Devices, Inc.

ITU-R BT.656 TRANSMITTER CONFIGURATION

The ADV7283 receives analog video and outputs digital video

according to the ITU-R BT.656 specification. The ADV7283

outputs the ITU-R BT.656 video data stream over the P0 to P7

data pins, and has a line-locked clock (LLC) pin.

Video data is output over the P0 to P7 pins in YCrCb 4:2:2 format.

Synchronization signals are automatically embedded in the video

data signal in accordance with the ITU-R BT.656 specification.

The LLC output clocks the output data on the P0 to P7 pins at a

nominal frequency of 27 MHz.

Figure 8. ITU-R BT.656 Output Stage

ITU-R BT.656

DATA

STREAM

VIDEO

DECODER

ANALOG

VIDEO

INPUT

LLC

ADV7283

STANDARD

DEFINITION

PROCESSOR

ANALOG

FRONT

END

12347-018

ADV7283 Data Sheet

Rev. A | Page 16 of 21

I2C PORT DESCRIPTION

The ADV7283 supports a 2-wire, I2C-compatible serial

interface. Two inputs, serial data (SDATA) and serial clock

(SCLK), carry information between the ADV7283 and the

system I2C master controller. The I2C port of the ADV7283

allows the user to set up and configure the decoder and to read

back captured VBI data.

The ADV7283 has a number of possible I2C slave addresses and

subaddresses (see the Register Maps section). The main map of

the ADV7283 has four possible slave addresses for read and write

operations, depending on the logic level of the ALSB pin (see

Table 12).

Table 12. Main Map I2C Address

ALSB Pin R/W Bit Slave Address

0 0 0x40 (write)

0 1 0x41 (read)

1 0 0x42 (write)

1 1 0x43 (read)

The ALSB pin controls Bit 1 of the slave address. By changing

the logic level of the ALSB pin, it is possible to control two

ADV7283 devices in an application without using the same I2C

slave address. The LSB (Bit 0) specifies either a read or write

operation: Logic 1 corresponds to a read operation, and Logic 0

corresponds to a write operation.

To control the device on the bus, a specific protocol is followed.

1. The master initiates a data transfer by establishing a start

condition, which is defined as a high to low transition on

SDATA while SCLK remains high, and indicates that an

address/data stream follows.

2. All peripherals respond to the start condition and shift the

next eight bits (the 7-bit address plus the R/W bit). The bits

are transferred from MSB to LSB.

3. The peripheral that recognizes the transmitted address

responds by pulling the data line low during the ninth

clock pulse; this is known as an acknowledge (ACK) bit.

4. All other devices withdraw from the bus and maintain an

idle condition. In the idle condition, the device monitors

the SDATA and SCLK lines for the start condition and the

correct transmitted address.

The R/W bit determines the direction of the data. Logic 0 on the

LSB of the first byte means that the master writes information

to the peripheral. Logic 1 on the LSB of the first byte means that

the master reads information from the peripheral.

The ADV7283 acts as a standard I2C slave device on the bus.

The data on the SDATA pin is eight bits long, supporting the 7-bit

address plus the R/W bit. The device has subaddresses to enable

access to the internal registers; therefore, it interprets the first

byte as the device address and the second byte as the starting

subaddress. The subaddresses auto-increment, allowing data to

be written to or read from the starting subaddress. A data transfer

is always terminated by a stop condition. The user can also access

any unique subaddress register individually without updating

all the registers.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate jump

to the idle condition. During a given SCLK high period, issue

only one start condition, one stop condition, or a single stop

condition followed by a single start condition. If the user issues

an invalid subaddress, the ADV7283 does not issue an

acknowledge and returns to the idle condition.

If the highest subaddress is exceeded in auto-increment mode,

one of the following actions is taken:

• In read mode, the register contents of the highest sub-

address continue to be output until the master device issues

a no acknowledge, which indicates the end of a read. A no

acknowledge condition occurs when the SDATA line is not

pulled low on the ninth pulse.

• In write mode, the data for the invalid byte is not loaded into

a subaddress register. The ADV7283 issues a no

acknowledge, and the device returns to the idle condition.

Figure 9. Bus Data Transfer

Figure 10. Read and Write Sequence

SDATA

SCLK

START ADDR ACK ACK DATA ACK STOPSUBADDRESS

1–7 1–789 8 9 1–7 8 9

S P

R/W

12347-010

WRITE

SEQUENCE SL AV E ADDR A(S) SUBADDRESS A(S) DATA A(S) DATA A(S) P

READ

SEQUENCE SL AV E ADDR SLAV E ADDRA(S) SUBADDRESS A(S) S A(S) DATA A(M) DATA A(M) P

S = START BIT

P = STOP BIT A(S) = ACKNOWLEDG E BY S LAVE

A(M) = ACKNOWLEDGE BY MASTER A(S) = NO ACKNOWLEDG E BY S LAVE

A(M) = NO ACKNOW LEDG E BY M AS TER

LSB = 1LSB = 0

12347-011

Data Sheet ADV7283

Rev. A | Page 17 of 21

Figure 11. Register Map and Sub Map Access

The ADV7283 contains two register maps: the main register

map and the VPP register map.

Note that the main map of the ADV7283 contains three sub

maps: the user sub map, the interrupt/VDP map, and User Sub

Map 2.

Main Map

The ALSB pin sets the I2C slave address of the main map of the

ADV7283 (see Table 12). The main map allows the user to

program the I2C slave addresses of the VPP map. The main map

contains three sub maps: the user sub map, the interrupt/VDP

sub map, and User Sub Map 2. These three sub maps are accessed

by writing to the SUB_USR_EN bits (Address 0x0E[6:5]) within

the main map (see Figure 11 and Table 13).

Use r Sub Map

The user sub map contains registers that program the analog

front end and digital core of the ADV7283. The user sub map

has the same I2C slave address as the main map. To access the

user sub map, set the SUB_USR_EN bits in the main map

(Address 0x0E[6:5]) to 00.

Interrupt/VDP Sub Map

The interrupt/VDP sub map contains registers that can be used to

program internal interrupts, control the INTRQ pin, and decode

VBI data.

The interrupt/VDP sub map has the same I2C slave address as

the main map. To access the interrupt/VDP sub map, set the

SUB_USR_EN bits in the main map (Address 0x0E[6:5]) to 01.

Use r S ub M ap 2

User Sub Map 2 contains registers that control the ACE, down

dither, and fast lock functions. It also contains controls that set

the acceptable input luma and chroma limits before the

ADV7283 enters free run and color kill modes.

User Sub Map 2 has the same I2C slave address as the main map.

To access User Sub Map 2, set the SUB_USR_EN bits in the main

map (Address 0x0E[6:5]) to 10.

VPP Map

The video postprocessor (VPP) map contains registers that

control the I2P core (interlaced-to-progressive converter).

The VPP map has a programmable I2C slave address, which is

programmed using Register 0xFD in the user sub map of the

main map. The default value for the VPP map address is 0x00;

however, the VPP map cannot be accessed until the I2C slave

address is set. The recommended I2C slave address for the VPP

map is 0x84.

To set the I2C slave address of the VPP map, write to the

VPP_SLAVE_ADDRESS[7:1] bits of the user sub map (Address

0xFD[7:1]).

It is recommended to set the VPP_SLAVE_ADDRESS[7:1] bits

to a value of 0x84. This sets the VPP map I2C write address to

0x84 and the I2C read address to 0x85.

SUB_USR_EN Bits, Address 0x0E[6:5]

The ADV7283 main map contains three sub maps: the user sub

map, the interrupt/VDP sub map, and User Sub Map 2 (see

Figure 11). The user sub map is available by default. The other

two sub maps are accessed using the SUB_USR_EN bits. When

programming of the interrupt/VDP map or User Sub Map 2 is

completed, write to the SUB_USR_EN bits to return to the user

sub map.

VPP MAP

DEVICE ADDRESS

WRITE: 0x84

READ:0x85(RECOMMENDED

SETTINGS)

VPP MAP DEVICE ADDRESS IS

PROGRAMMABLEAND SET BY

SUB MAP

MAIN MAP

DEVICE ADDRESS

ALSB PIN HIGH

WRITE: 0x42

READ:0x43

ALSB PIN LOW

WRITE: 0x40

READ:0x41

0x0E[6:5] = 00

USER

SUB MAP

0x0E[6:5] = 01

INTERRUPT/VDP

SUB MAP

0x0E[6:5] =10

USER SUB

MAP 2

12347-012

ADV7283 Data Sheet

Rev. A | Page 18 of 21

Table 13. I2C Register Map and Sub Map Addresses

ALSB Pin R/W Bit Slave Address

SUB_USR_EN Bits

(Address 0x0E[6:5]) Register Map or Sub Map

0 0 (write) 0x40 00 User sub map

0 1 (read) 0x41 00 User sub map

0 0 (write) 0x40 01 Interrupt/VDP sub map

0 1 (read) 0x41 01 Interrupt/VDP sub map

0 0 (write) 0x40 10 User Sub Map 2

0 1 (read) 0x41 10 User Sub Map 2

1 0 (write) 0x42 00 User sub map

1 1 (read) 0x43 00 User sub map

1 0 (write) 0x42 01 Interrupt/VDP sub map

1 1 (read) 0x43 01 Interrupt/VDP sub map

1 0 (write) 0x42 10 User Sub Map 2

1 1 (read) 0x43 10 User Sub Map 2

X1 0 (write) 0x84 XX1 VPP map

X1 1 (read) 0x85 XX1 VPP map

1 X and XX mean don’t care .

PCB LAYOUT RECOMMENDATIONS

The ADV7283 is a high precision, high speed, mixed-signal

device. To achieve maximum performance from the device, it is

important to use a well designed PCB. This section provides

guidelines for designing a PCB for use with the ADV7283.

Analog Interface Inputs

When routing the analog interface inputs on the PCB, keep

track lengths to a minimum. Use 75 Ω trace impedances when

possible; trace impedances other than 75 Ω increase the chance

of reflections.

Power Supply Decoupling

It is recommended that each power supply pin be decoupled

with 100 nF and 10 nF capacitors. The basic principle is to place

a decoupling capacitor within approximately 0.5 cm of each

power pin. Avoid placing the decoupling capacitors on the

opposite side of the PCB from the ADV7283 because doing so

introduces inductive vias in the path.

Place the decoupling capacitors between the power plane and

the power pin. Current must flow from the power plane to the

capacitor and then to the power pin. Do not apply the power

connection between the capacitor and the power pin. The best

approach is to place a via close to or beneath the decoupling

capacitor pads down to the power plane (see Figure 12).

Figure 12. Recommended Power Supply Decoupling

It is especially important to maintain low noise and good

stability for the PVDD pin. Pay careful attention to regulation,

filtering, and decoupling. It is highly desirable to provide

separate regulated supplies for each circuit group (AVDD, DVDD,

DVDDIO, and PVDD).

Some graphic controllers use substantially different levels of

power when active (during active picture time) and when idle

(during horizontal and vertical sync periods). This disparity can

result in a measurable change in the voltage supplied to the analog

supply regulator, which can, in turn, produce changes in the

regulated analog supply voltage. To mitigate this problem,

regulate the analog supply, or at least the PVDD supply, from a

different, cleaner power source, for example, from a 12 V supply.

Using a single ground plane for the entire board is recommended.

Using multiple ground planes can be detrimental because each

separate ground plane is smaller, and can result in long ground

loops. Therefore, using a single ground plane can improve noise

performance.

VREFN and VREFP Pins

Place the circuit associated with the VREFN and VREFP pins as

close as possible to the ADV7283 and on the same side of the

PCB as the device.

Digital Outputs

The ADV7283 digital outputs are INTRQ, LLC, and P0 to P7.

Minimize the trace length that the digital outputs must drive.

Longer traces have higher capacitance, requiring more current

and, in turn, causing more internal digital noise. Shorter traces

reduce the possibility of reflections.

Adding a 30 Ω to 50 Ω series resistor can suppress reflections,

reduce EMI, and reduce current spikes inside the ADV7283. If

series resistors are used, place them as close as possible to the

SUPPLY

GROUND

10nF 100nF

VIA TO SUPPLY

VIA TO GND

12347-013

NOTES

1. G ND RE FERS TO THE COM M ON GROUND PL ANE

OF THE PCB.

Data Sheet ADV7283

Rev. A | Page 19 of 21

pins of the ADV7283. However, do not add vias or extra length

to the output trace in an attempt to place the resistors closer.

If possible, limit the capacitance that each digital output must

drive to less than 15 pF. This recommendation can be easily

accommodated by keeping traces short and by connecting the

outputs to only one device. Loading the outputs with excessive

capacitance increases the current transients inside the

ADV7283, creating more digital noise on the power supplies.

Exposed Metal Pad

The ADV7283 has an exposed metal pad on the bottom of the

package. This pad must be soldered to ground. The exposed

pad is used for proper heat dissipation, noise suppression, and

mechanical strength.

Digital Inputs

The digital inputs of the ADV7283 are designed to work with

1.8 V signals (3.3 V for DVDDIO) and are not tolerant of 5 V

signals. Extra components are required if 5 V logic signals must

be applied to the decoder.

ADV7283 Data Sheet

Rev. A | Page 20 of 21

TYPICAL CIRCUIT CONNECTION

Figure 13 provides an example of how to connect ADV7283. For detailed schematics of the ADV7283 evaluation board, contact a local

Analog Devices field applications engineer or an Analog Devices distributor.

Figure 13. Typical Connection Diagram

12347-203

SCLK

RESET

PWRDWN

SDATA

LLC 32 LLC

INTRQ 26 INTRQ

P0 12 P0

P1 11 P1

P2 10 P2

P3 9P3

P4 8P4

P5 7P5

P6 6P6

P7 5P7

P0 TO P7

28.63636MHz

47pF

XTALP

XTALN

0.1µF

VREFP

VREFN

ALSB

4kΩ

DGND

0.1µF 10nF

0.1µF10nF

ADV7283

VDD

_1.8V D

VDDIO

_3.3V A

VDD

_1.8V

VDDIO

_3.3V

VDD

_1.8V

VDD

_1.8V

VDD

_1.8V

YCrCb

8-BIT

IT U-R BT. 65 6 DATA

VDDIO

ALSB TI E D HIGH: I

C ADDRESS = 0x 4 2

ALSB TI E D LOW: I

C ADDRESS = 0x 4 0

VDD

VDDIO

LO CATE CL OSE TO, AND ON THE

SAME S IDE O F T HE PCB AS, THE ADV7 2 83

LO CATE V REFP AND VREF N CAPACITO R AS

CLO SE AS P OSSI BLE TO THE ADV7 28 3 AND ON

THE SAM E SIDE O F THE PCB AS T HE ADV7 2 83

0.1µF

430Ω

150Ω

430Ω

0.1µF

430Ω

75Ω

430Ω

FULLY

DIFFERENTIAL

CVBS I NPUT

PSEUDO

DIFFERENTIAL

CVBS I NPUT

1.3kΩ

DIFF1+

DIFF1–

DIFF2+

DIFF2–

0.1µF

51Ω

24kΩ

SINGLE-

ENDED

CVBS

INPUT

0.1µF

51Ω

24kΩ

SINGLE-

ENDED

CVBS

INPUT A

Data Sheet ADV7283

Rev. A | Page 21 of 21

OUTLINE DIMENSIONS

Figure 14. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model 1, 2 Temperature Range Package Description Package Option

ADV7283BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12

ADV7283BCPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12

ADV7283WBCPZ −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12

ADV7283WBCPZ-RL −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12

EVA L -ADV7283EBZ Evaluation Board for the ADV7283

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The ADV7283W model is available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should

review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive

applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific

Automotive Reliability reports for this model.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

0.50

0.40

0.30

01-26-2016-B

0.50

BSC

BOTTOM VIEWTOP VIEW

PIN 1

INDICATOR

2425

EXPOSED

PAD

PIN 1

INDICATOR

SEATING

PLANE

0.05 M AX

0.02 NO M

0.20 REF

COPLANARITY

0.08

0.30

0.25

0.18

5.10

5.00 SQ

4.90

0.80

0.75

0.70

FOR PROP E R CONNECT ION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTIO N DE S CRIPT IONS

SECTION OF THIS DATA SHEET.

0.25 M IN

3.75

3.60 SQ

3.55

COM P LIANT TO JE DE C S TANDARDS MO-220-WHHD-5.

PKG-004570

registered trademark s are the property of their respective owners.

D12347-0-10/16(A)