ispLSI® 2032/A
In-System Programmable High Density PLD
2032_10 1
USE ispLSI 2032E FOR NEW DESIGNS
Features
• ENHANCEMENTS
—ispLSI 2032A is Fully Form and Function Compatible
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging
—ispLSI 2032A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
•HIGH DENSITY PROGRAMMABLE LOGIC
—1000 PLD Gates
—32 I/O Pins, Two Dedicated Inputs
—32 Registers
—High Speed Global Interconnect
—Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
—Small Logic Block Size for Random Logic
•HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 180 MHz Maximum Operating Frequency
—tpd = 5.0 ns Propagation Delay
—TTL Compatible Inputs and Outputs
—Electrically Erasable and Reprogrammable
— Non-Volatile
—100% Tested at Time of Manufacture
—Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
—In-System Programmable (ISP™) 5V Only
—Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
•OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
—Complete Programmable Device Can Combine Glue
Logic and Structured Designs
—Enhanced Pin Locking Capability
—Three Dedicated Clock Input Pins
—Synchronous and Asynchronous Clocks
—Programmable Output Slew Rate Control to
Minimize Switching Noise
—Flexible Pin Placement
—Optimized Global Routing Pool Provides Global
Interconnectivity
Description
The ispLSI 2032 and 2032A are High Density Program-
mable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2032 and 2032A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2032 and 2032A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
(Figure 1). There are a total of eight GLBs in the ispLSI
2032 and 2032A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
GLB Logic
Array
DQ
DQ
DQ
DQ
0139Bisp/2000
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com January 2002
Specifications ispLSI 2032/A
2
USE ispLSI 2032E FOR NEW DESIGNS
Functional Block Diagram
Figure 1. ispLSI 2032/A Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
CLK 0
CLK 1
CLK 2
GOE 0
Notes:
*Y1 and RESET are multiplexed on the same pin
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
SDI/IN 0
SDO/IN 1
I/O 4
I/O 5
Y0
*Y1/RESET
SCLK/Y2
ispEN
MODE
0139B(1)isp/200
0
The devices also have 32 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032 and 2032A device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032 and 2032A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Specifications ispLSI 2032/A
3
USE ispLSI 2032E FOR NEW DESIGNS
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V
Input Voltage Applied........................ -2.5 to V CC +1.0V
Off-State Output Voltage Applied .....-2.5 to VCC +1.0V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
T
A
= 0°C to + 70°C
T
A
= -40°C to + 85°C
SYMBOL
Table 2 - 0005/2032
VCC
VIH
VIL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
4.75
4.5
2.0
0
5.25
5.5
V
cc
+1
0.8
V
V
V
V
Commercial
Industrial
Capacitance (TA=25°C, f=1.0 MHz)
CSYMBOL
Table 2-0006/2032
C
PARAMETER
I/O Capacitance 7
UNITSTYPICAL TEST CONDITIONS
1
2
6Dedicated Input Capacitance pf
pf V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC I/O
IN
CClock Capacitance 10
3
pf V = 5.0V, V = 2.0V
CC Y
Data Retention Specifications
Table 2-0008A-isp
PARAMETER
Data Retention MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 20
10000 –
– Years
Cycles
Specifications ispLSI 2032/A
4
USE ispLSI 2032E FOR NEW DESIGNS
Input Pulse Levels
Table 2-0003/2032
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
-135, -150, -180
-80, -110
≤ 1.5 ns
≤ 3 ns
Figure 2. Test Load
+ 5V
R1
R2CL*
Device
Output Test
Point
*CL includes Test Fixture and Probe Capacitance.
0213A
Switching Test Conditions
DC Electrical Characteristics
Over Recommended Operating Conditions
Output Load Conditions (see Figure 2)
TEST CONDITION R1 R2 CL
A 470Ω390Ω35pF
B∞390Ω35pF
470Ω390Ω35pF
Active High
Active Low
C470Ω390Ω5pF
∞390Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2 - 0004A
VOL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at V = 5V and T = 25°C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .
Table 2-0007/2032
1
VOH
IIH
IIL
IIL-isp
PARAMETER
IIL-PU
IOS
2, 4
ICC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
3.5V ≤ V ≤ V
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 5V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN CC
IN IL
IN IL
CC OUT
TOGGLE
IL IH
CONDITION MIN. TYP. MAX. UNITS
3
–
2.4
–
–
–
–
–
–
–
–
–
–
–
–
0.4
–
10
-10
-150
-150
-200
V
V
µA
µA
µA
µA
mA
CC A
OUT
–
–
40
40
mA
mA
–
–
–60 mA–-180, -150
Others
CC
CC
Comm.
Industrial
Specifications ispLSI 2032/A
5
USE ispLSI 2032E FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
-150
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B-180/2032
1
4
3
1
tsu2 + tco1
( )
-135
MIN.MAX. MAX.
DESCRIPTION#2
PARAMETER
A1Data Prop. Delay, 4PT Bypass, ORP Bypass – 5.5 – 7.5 ns
tpd2 A2Data Prop. Delay – – ns
fmax A3Clk Frequency with Internal Feedback 154 – 137 – MHz
fmax (Ext.) –4Clk Frequency with Ext. Feedback – – MHz
fmax (Tog.) –5Clk Frequency, Max. Toggle – – MHz
tsu1 –6GLB Reg Setup Time before Clk, 4 PT Bypass – – ns
tco1 A7GLB Reg. Clk to Output Delay, ORP Bypass – – ns
th1 –8GLB Reg. Hold Time after Clk, 4 PT Bypass 0.0 – ns
tsu2 –9GLB Reg. Setup Time before Clk 4.5 – ns
tco2 –10GLB Reg. Clk to Output Delay – – ns
th2 –11GLB Reg. Hold Time after Clk 0.0 – ns
tr1 A12Ext. Reset Pin to Output Delay – – ns
trw1 –13Ext. Reset Pulse Duration 4.5 – ns
tptoeen B14Input to Output Enable – – ns
tptoedis C15Input to Output Disable – – ns
tgoeen B16Global OE Output Enable – – ns
tgoedis C17Global OE Output Disable – – ns
twh –18Ext. Synchronous Clk Pulse Duration, High 3.0 – – ns
twl –19Ext. Synchronous Clk Pulse Duration, Low 3.0 – – ns
111
167
3.0 4.5
–
–
5.0
–
8.0
–
11.0
11.0
5.0
5.0
8.0
-180
MIN. MAX.
– 5.0
–
180 –
–
–
–
–
0.0
4.0
–
0.0
–
4.0
–
–
–
–
2.5 –
2.5 –
125
200
3.0 4.0
–
–
4.5
–
7.0
–
10.0
10.0
5.0
5.0
7.5
100
167
4.0
0.0
5.5
0.0
5.0
3.0
3.0
10.0
4.5
5.5
10.0
12.0
12.0
6.0
6.0
Specifications ispLSI 2032/A
6
USE ispLSI 2032E FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
-110
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B-110/2032
1
4
3
1
tsu2 + tco1
( )
-80
MIN.MAX. MAX.
DESCRIPTION#2
PARAMETER
A1Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 15.0 ns
tpd2 A2Data Propagation Delay – – ns
fmax A3Clock Frequency with Internal Feedback 111 – 84.0 – MHz
fmax (Ext.) – 4 Clock Frequency with External Feedback – – MHz
fmax (Tog.) – 5 Clock Frequency, Max. Toggle – – MHz
tsu1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns
tco1 A7GLB Reg. Clock to Output Delay, ORP Bypass – – ns
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns
tsu2 – 9 GLB Reg. Setup Time before Clock 7.5 – ns
tco2 – 10 GLB Reg. Clock to Output Delay – – ns
th2 – 11 GLB Reg. Hold Time after Clock 0.0 – ns
tr1 A12Ext. Reset Pin to Output Delay – – ns
trw1 – 13 Ext. Reset Pulse Duration 6.5 – ns
tptoeen B14Input to Output Enable – – ns
tptoedis C15Input to Output Disable – – ns
tgoeen B16Global OE Output Enable – – ns
tgoedis C17Global OE Output Disable – – ns
twh – 18 External Synchronous Clock Pulse Duration, High 4.0 – – ns
twl – 19 External Synchronous Clock Pulse Duration, Low 4.0 – – ns
77.0
125
5.5 5.5
–
–
6.5
–
13.5
–
14.5
14.5
7.0
7.0
13.0
57.0
83.0
7.5
0.0
9.5
0.0
10.0
6.0
6.0
18.5
8.0
9.5
19.5
24.0
24.0
12.0
12.0
Specifications ispLSI 2032/A
7
USE ispLSI 2032E FOR NEW DESIGNS
Over Recommended Operating Conditions
Internal Timing Parameters1
tio
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036C-180/2032
Inputs
UNITS
-150
MIN.
-135
MIN.MAX. MAX.
DESCRIPTION#2
PARAMETER
20 Input Buffer Delay – – 1.1 ns
tdin 21 Dedicated Input Delay – – 2.4 ns
tgrp 22 GRP Delay – – 1.3 ns
GLB
t1ptxor 25 1 Product Term/XOR Path Delay – – 5.0 ns
t20ptxor 26 20 Product Term/XOR Path Delay – – 5.1 ns
txoradj 27 XOR Adjacent Path Delay – – 5.6 ns
tgbp 28 GLB Register Bypass Delay – – 0.0 ns
tgsu 29 GLB Register Setup Time before Clock – 0.3 – ns
tgh 30 GLB Register Hold Time after Clock – 3.0 – ns
tgco 31 GLB Register Clock to Output Delay – – 0.7 ns
3
tgro 32 GLB Register Reset to Output Delay – – 1.1 ns
tptre 33 GLB Product Term Reset to Register Delay – – 4.4 ns
tptoe 34 GLB Product Term Output Enable to I/O Cell Delay – – 6.4 ns
tptck 35 GLB Product Term Clock Delay 2.9 5.2 ns
ORP
tob 38 Output Buffer Delay – – 1.2 ns
tsl 39 Output Slew Limited Delay Adder – – 10.0 ns
0.6
1.3
GRP
0.7
t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) – – 3.6 ns
t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) – – 3.6 ns
4.3
4.6
5.0
0.0
2.6
3.1
0.7
1.8
0.8
1.2
2.9
6.9
2.5 4.1
torp 36 ORP Delay – – 1.3 ns
torpbp 37 ORP Bypass Delay – – 0.3 ns
0.8
0.3
Outputs
1.3
10.0
toen 40 I/O Cell OE to Output Enabled – – 3.2 ns
todis 41 I/O Cell OE to Output Disabled – – 3.2 ns
2.8
2.8
tgoe 42 Global Output Enable – – 2.8 ns
2.2
tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.1 2.3 2.3 ns
tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.1 2.3 2.3 ns
Clocks
2.1
2.1
tgr 45 Global Reset to GLB – – 6.4 ns
Global Reset
4.7
-180
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.6
1.1
0.7
–
–
3.6
4.1
4.8
0.2
2.3
3.1
0.5
1.8
0.7
1.0
2.8
5.9
2.5 3.8
–
–0.7
0.2
1.2
10.0
–
–2.8
2.8
–2.2
1.9
1.9 1.9
1.9
–4.1
Specifications ispLSI 2032/A
8
USE ispLSI 2032E FOR NEW DESIGNS
Internal Timing Parameters1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036C-110/2032
Inputs
UNITS
-110
MIN.
-80
MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay – – 2.2 ns
t
din 21 Dedicated Input Delay – – 4.8 ns
t
grp 22 GRP Delay – – 2.6 ns
GLB
t
1ptxor 25 1 Product Term/XOR Path Delay – – 8.8 ns
t
20ptxor 26 20 Product Term/XOR Path Delay – – 9.2 ns
t
xoradj 27 XOR Adjacent Path Delay – – 10.2 ns
t
gbp 28 GLB Register Bypass Delay – – 0.0 ns
t
gsu 29 GLB Register Setup Time befor Clock – 0.1 – ns
t
gh 30 GLB Register Hold Time after Clock – 6.0 – ns
t
gco 31 GLB Register Clock to Output Delay – – 0.4 ns
3
t
gro 32 GLB Register Reset to Output Delay – – 2.2 ns
t
ptre 33 GLB Product Term Reset to Register Delay – – 8.8 ns
t
ptoe 34 GLB Product Term Output Enable to I/O Cell Delay – – 12.8 ns
t
ptck 35 GLB Product Term Clock Delay 5.5 9.5 ns
ORP
t
ob 38 Output Buffer Delay – – 2.4 ns
t
sl 39 Output Slew Limited Delay Adder – – 10.0 ns
1.7
3.4
GRP
1.7
t
4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) – – 7.2 ns
t
4ptbpr 24 4 Product Term Bypass Path Delay (Registered) – – 7.2 ns
6.2
6.8
7.5
0.1
4.9
4.8
0.5
4.0
0.6
1.8
5.9
7.1
4.0 7.0
t
orp 36 ORP Delay – – 2.1 ns
t
orpbp 37 ORP Bypass Delay – – 0.6 ns
1.5
0.5
Outputs
1.2
10.0
t
oen 40 I/O Cell OE to Output Enabled – – 6.4 ns
t
odis 41 I/O Cell OE to Output Disabled – – 6.4 ns
4.0
4.0
t
goe 42 Global Output Enable – – 5.6 ns
3.0
t
gy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 3.2 4.6 4.6 ns
t
gy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 3.2 4.6 4.6 ns
Clocks
3.2
3.2
t
gr 45 Global Reset to GLB – – 12.8 ns
Global Reset
9.0
Specifications ispLSI 2032/A
9
USE ispLSI 2032E FOR NEW DESIGNS
ispLSI 2032/A Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In #21
#20 #28
#29, 30,
31, 32
#38,
39
GOE 0 #42
#40, 41
0491/2000
#22
Comb 4 PT Bypass #23
#37
#45
Derivations of tsu, th and tco from the Product Term Clock1
=
=
=
=
tsu Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)
2.1 ns
=
=
=
=
th Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)
1.5 ns
=
=
=
=
tco Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)
7.7 ns
Table 2- 0042-16/2032
Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
Specifications ispLSI 2032/A
10
USE ispLSI 2032E FOR NEW DESIGNS
Power consumption in the ispLSI 2032 and 2032A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
60
80
100
120406080100 120 140 160 180
fmax (MHz)
ICC (mA)
Notes: Configuration of Two 16-bit Counters
Typical Current at 5V, 25° C
ispLSI 2032/A (-150, -180)
ispLSI 2032/A (-80, -110, -135)
90
70
40
50
0127A/2032A
ICC can be estimated for the ispLSI 2032/A using the following equation:
For 2032/A -150, -180: ICC(mA) = 30 + (# of PTs * 0.46) + (# of nets * Max freq * 0.012)
For 2032/A -135, -110, -80: ICC(mA) = 21 + (# of PTs * 0.30) + (# of nets * Max freq * 0.012)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
110
120
Power Consumption
Specifications ispLSI 2032/A
11
USE ispLSI 2032E FOR NEW DESIGNS
Pin Description
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Input/Output Pins — These are the general purpose
I/O pins used by the logic array.
NAME
Table 2-0002A-08isp/2032
44-PIN PLCC
PIN NUMBERS DESCRIPTION
15,
19,
25,
29,
37,
41,
3,
7,
16,
20,
26,
30,
38,
42,
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
18,
22,
28,
32,
40,
44,
6,
10
Global Output Enable input pin.2GOE 0
1, 23GND
V
CC
12, 34
17, 39
6, 28
18, 42
6, 30
VCC
No Connect.
12, 24, 36, 48
NC
1
Ground (GND)
Input — This pin performs two functions. When ispEN
is logic low, it functions as an input pin to load
programming data into the device. SDI/IN0 also is used
as one of the two control pins for the isp state machine.
When ispEN is high, it functions as a dedicated input
pin.
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
This pin performs two functions:
Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and SCLK
controls become active.
RESET/Y1
Y0
SDI/IN 0
2
ispEN
MODE Input — When in ISP Mode, controls operation of ISP
state machine.
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
Output/Input — This pin performs two functions. When
ispEN is logic low, it functions as an output pin to read
serial shift register data. When ispEN is high, it
functions as a dedicated input pin.
SDO/IN 1
2
Input — This pin performs two functions. When
ispEN is logic low, it functions as a clock pin for the
Serial Shift Register. When ispEN is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
SCLK/Y2
2
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
35
11
14
13
36
24
33
44-PIN TQFP
PIN NUMBERS 48-PIN TQFP
PIN NUMBERS
9,
13,
19,
23,
31
35,
41,
1,
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
40
5
29
7
8
30
18
27
9,
14,
20,
25,
33,
38,
44,
1,
10,
15,
21,
26,
34,
39,
45,
2,
11,
16,
22,
27,
35,
40,
46,
3,
13,
17,
23,
28,
37,
41,
47,
4
43
5
31
7
8
32
19
29
Specifications ispLSI 2032/A
12
USE ispLSI 2032E FOR NEW DESIGNS
Pin Configuration
ispLSI 2032/A 44-Pin PLCC Pinout Diagram
ispLSI 2032/A 44-Pin TQFP Pinout Diagram
I/O 18
I/O 17
I/O 16
MODE
RESET/Y1
VCC
SCLK/Y21
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
ispEN
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1SDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
7
8
9
10
12
11
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6
18
5
19
4
20
3
21
2
22
1
23
44
24
43
25
42
26
41
27
40
28
1. Pins have dual function capability.
ispLSI 2032/A
Top View
0123B/2032/A
I/O 18
I/O 17
I/O 16
MODE
RESET/Y1
VCC
SCLK/Y2
1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
ispEN
1
SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
SDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 2032/A
Top View
1
2
3
4
6
5
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
0851/2032/A
1. Pins have dual function capability.
Specifications ispLSI 2032/A
13
USE ispLSI 2032E FOR NEW DESIGNS
Pin Configuration
ispLSI 2032/A 48-Pin TQFP Pinout Diagram
I/O 18
I/O 17
I/O 16
MODE
RESET/Y12
VCC
SCLK/Y22
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
ispEN
2SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
2SDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 2032/A
Top View
1
2
3
4
6
5
7
8
9
10
11
35
34
33
32
31
30
29
28
27
26
25
47
13
46
14
45
15
44
16
43
17
42
18
41
19
40
20
39
21
38
22
37
23
48-Pin TQFP-2032/A
1NC 12
1NC
24
NC1
36
NC1
48
1. NC pins are not to be connected to any active signal, Vcc or GND.
2. Pins have dual function capability.
Specifications ispLSI 2032/A
14
USE ispLSI 2032E FOR NEW DESIGNS
ispLSI 2032/A Ordering Information
Part Number Description
Device Number
ispLSI XXXX XXX X XXX
Grade
Blank = Commercial
I = Industrial
X
Speed
180 = 180 MHz
f
max
150 = 154 MHz
f
max
135 = 137 MHz
f
max
110 = 111 MHz
f
max
80 = 84 MHz
f
max
2032
2032A
Power
L = Low
Package
J = PLCC
T44 = TQFP
T48 = TQFP
—
Device Family
0212A/2032
INDUSTRIAL
COMMERCIAL
YLIMAFf)zHM(xam t)sn(dp REBMUNGNIREDROEGAKCAP
ISLpsi 4851 CCLPniP-44
4851 PFQTniP-44
4851 PFQTniP-84
Table 2-0041B/2032A
ispLSI 2032A-80LJ44I
ispLSI 2032A-80LT44I
ispLSI 2032A-80LT48I
YLIMAFf)zHM(xam t)sn(dp REBMUNGNIREDROEGAKCAP
ISLpsi
0810.5 CCLPniP-44
0810.5 PFQTniP-44
0810.5 PFQTniP-84
4515.5 CCLPniP-44
4515.5 PFQTniP-44
4515.5 PFQTniP-84
7315.7 CCLPniP-44
7315.7 PFQTniP-44
7315.7 PFQTniP-84
11101 CCLPniP-44
11101 PFQTniP-44
11101 PFQTniP-84
4851 CCLPniP-44
4851 PFQTniP-44
4851 PFQTniP-84
2A302/A1400-2elbaT
ispLSI 2032A-180LJ44
ispLSI 2032A-180LT44
ispLSI 2032A-180LT48
ispLSI 2032A-150LJ44
ispLSI 2032A-150LT44
ispLSI 2032A-150LT48
ispLSI 2032A-135LJ44
ispLSI 2032A-135LT44
ispLSI 2032A-135LT48
ispLSI 2032A-110LJ44
ispLSI 2032A-110LT44
ispLSI 2032A-110LT48
ispLSI 2032A-80LJ44
ispLSI 2032A-80LT44
ispLSI 2032A-80LT48
Specifications ispLSI 2032/A
15
USE ispLSI 2032E FOR NEW DESIGNS
INDUSTRIAL
COMMERCIAL
f)zHM(xam t)sn(dp
PACKAGEORDERING NUMBERFAMILY
ispLSI
0810.5
0810.5
0810.5
4515.5
4515.5
4515.5
7315.7
7315.7
7315.7
11101
11101
11101
4851
4851
4851
2302/A1400-2elbaT
ispLSI 2032-180LJ
ispLSI 2032-135LJ
ispLSI 2032-110LJ
ispLSI 2032-80LJ
ispLSI 2032-150LJ
ispLSI 2032-180LT44
ispLSI 2032-110LT44
ispLSI 2032-80LT44
ispLSI 2032-110LT48
ispLSI 2032-80LT48
ispLSI 2032-135LT44
ispLSI 2032-135LT48
ispLSI 2032-150LT44
ispLSI 2032-180LT48
ispLSI 2032-150LT48
44-Pin PLCC
44-Pin PLCC
44-Pin PLCC
44-Pin PLCC
44-Pin PLCC
44-Pin TQFP
44-Pin TQFP
44-Pin TQFP
48-Pin TQFP
48-Pin TQFP
44-Pin TQFP
48-Pin TQFP
44-Pin TQFP
48-Pin TQFP
48-Pin TQFP
YLIMAFf)zHM(xam t)sn(dp REBMUNGNIREDROEGAKCAP
ISLpsi 4851 CCLPniP-44
4851 PFQTniP-44
4851 PFQTniP-84
Table 2-0041C/2032
ispLSI 2032-80LJI
ispLSI 2032-80LT44I
ispLSI 2032-80LT48I
