CS495002-CQZ - Cirrus Logic, Inc.

CONFIDENTIAL DS734F3

http://www.cirrus.com

CS485xx Family Data Sheet

CONFIDENTIAL DRAFT

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FEATURES

Cost-effective, High-performance 32-bit DSP

— 300,000,000 MAC/S (multiply accumulates per second)

— Dual MAC cycles per clock

— 72-bit accumulators are the most accurate in the industry

— 24k x 32 SRAM, 2k blocks - assignable to data or program

— Internal ROM contains a variety of configurable sound

enhancement feature sets

— 8-channel internal DMA

— Internal watch-dog DSP lock-up prevention

DSP Tool Set w/ Private Keys for Protecting Customer IP

Configurable Serial Audio Inputs/Outputs

— Configurable for all input/output types

— Maximum 32-bit @ 192 kHz

— Supports 32-bit audio sample I/O between DSP chips

— TDM input modes (multiple channels on same line)

— 192 kHz SPDIF transmitter

— Multi-channel DSD direct stream digital SACD input

Support s Two Diff eren t Input Fs Sam ple Rates

— Output can be master or slave

— Dual processing path capability

— Input supports dual domain slave clocking

— Hardware assist time sampling for sample rate conversion

Integrated Clock Manager/PLL

— Can operate from external crystal, external oscillator

Input Fs Auto Detection

Host & Boot via Serial Interface

Configurable GPIOs and External Interrupt Input

1.8V Core and a 3.3V I/O that is tolerant to 5V input

Low-power Mode

— “Energy Star® Ready” in low-power mode, 268 µW in standby

32-bit

DSP

P X Y

Serial

Control 1

12 Ch PCM

Audio Out

GPIO Debug

Watchdog

TMR1

TMR2

PLL

S/PDIF

12 Ch. Audio In /

6 Ch. SACD In

Differentiating from the legacy Cirrus multi-standard, multi-

channel decoders, this new CS485xx family is still based on

the same high-performance 32-bit fixed point Digital Signal

Processor core but instead is equipped with much less

memory, tailoring it for more cost-effective applications

associated with multi-channel and virtual-channel sound

enhancements. Target applications are:

— Digital Televisions

— Multimedia Peripherals

—iPod

® Docking Stations

— Automotive Head Units

— Automotive Outboard Amplifiers

— HD-DVD & Blu-ray Disc DVD Receivers

— PC Speak ers

There are are also a wide variety of licensable DSP codes

available today as seen by the following examples:

Cirrus also has developed, or is developing their own royalty-

free versions of popular features sets like Cirrus Bass

Manager, Cirrus Dynamic Volume Leveler, Cirrus Original

Multichannel Surround, Cirrus Virtual Speaker & Cirrus 3D-

Audio.

The CS485xx family is programmed using the Cirrus

proprietary DSP Composer™ GUI development tool.

Processing chains may be designed using a drag-and-drop

interface to place/utilize functional macro audio DSP

primitives. The end result is a software image that is down-

loaded to the DSP via serial host or serial boot modes.

Or dering Information:

See page 20 for ordering information

CS485xx Family Data Sheet

32-bit Audio Decoder DSP Family

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Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to

www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject t

change without noti ce and is provided “A S IS” witho ut warranty of any kind (express or imp lie d). Custome rs are advi sed to obtain the l atest versi on of relevant inf o

mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplie

at the ti m e of order acknowledg ment , i ncl udi ng t ho se pertaini n g t o warranty, indemnif ica ti on, and limit ati on of li ability. No responsibility is assumed by Cirrus for th

use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties

This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights

trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copie

to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not exten

to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCT OR PRODUCT S MAY INVOLVE POT ENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER

TY OR ENVIRONM ENTAL DAMAGE (“CRITICAL APPLICAT IO NS” ). CIRRUS PRO D UCT S ARE NO T DES IGNED, AUTHORIZED OR WARRANTED FOR USE IN

PRODUCTS S URGICALLY IMPLANTED INTO T HE BODY, AUTOMO TIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICA

APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRU

DISCLAIMS AND MAKES NO W ARRANTY, EX PRESS, ST ATUTORY OR IMPL IED, INCLUDING THE IMPLIED WARRAN TIES OF ME RCHAN TABILITY AND FIT

NESS FOR PARTICULAR PURPOSE, WITH REGA RD TO ANY CIRRUS PRODUCT THAT IS USED IN SUC H A M ANNER. IF THE C USTOMER OR CUST OMER'

CUSTOMER USES OR PERMIT S THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLIC ATIONS, CUSTOMER A GR EES, BY SUCH USE, TO FULLY INDE M

NIFY CIRRUS, ITS OFFICERS, DIRECTO RS, EMPLOYE ES, DISTRIBUTORS AND OTHER AG ENTS FROM A NY AND ALL LIABIL ITY, INCLUDING ATTORNEY S

FEES AND CO ST S, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names i

this document may be trademarks or service marks of their respective owners.

Dolby, Dolby Digital , Dol by Headph one, Dol by Virtual Speaker, Dolby Headphone, and Pro Logic are regi st ere d tradem arks of Dol by Laboratorie s, Inc. Supply of a

implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Lab

oratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Lab

oratories.

DTS is a reg ist ered tra demark of the Digital Theate r Systems, Inc. DTS Neo: 6 is a tradema rk of Di gital T heate r Systems, I nc. It is here by noti fied t hat a thir d-pa rt

license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product.

SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circle Surround II is a trademark of SRS Labs, Inc. The CIRCLE SURROUND

TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc.

Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND TECHNOLOGY® (i.e., CIRCLE SURROUND® LICENSEES) must first sign a license to pu

chase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passin

of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedul

may be made to cslicense @srsl abs.c om. SRS La bs, Inc. a nd V alence Technology, Ltd., re serve the righ t to de cli n e a use li cense for any submi ssi on tha t does n o

pass performance specifications or is not in the consumer electronics classification.

All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY must carry the Circle Surround® logo on the fron

panel i n a manner ap proved in wri t i ng by SRS Lab s, Inc., or Valence Te chnolog y Ltd. If the Circle Surr ound® logo i s printe d in use rs manuals, service manuals o

advertiseme nts, it must a ppear in a form approve d in writin g by SRS Labs, Inc. , or Va lence Technol ogy, Ltd. The rear pa nel of Circle Surr ound® products , user

manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademar

Usage Manual.

SPI is a trademark of Motorola, Inc.

C is a registered trademark of Philips Semiconductor.

iPod is a registered trademark of Apple Computer, Inc.

Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.

CS485xx Family Data Sheet

32-bit Audio Decoder DSP Family

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Table of Contents

1. Documentation S tr ategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Overv iew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3. Code Ove rlay s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4. Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1.1 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1.2 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 On-chip DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.1 Digital Audio Input Port (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.2 Digital Audio Output Port (DAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.3 Serial Control Port (I2C® or SPI™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.5 PLL-based Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.6 Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3 DSP I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.1 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.2 Termination Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.3 Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.4 Application Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5. Character istic s a nd Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.5 Thermal Data (48-Pin LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.6 Switching Characteristics— RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Switching Characteristics — XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.8 Switching Characteristics — Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.10 Switching Characteristics — Serial Control Port - SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.12 Switching Characteristics — Serial Control Port - I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.13 Switching Characteristics — Digital Audio Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.14 Switching Characteristics — DSD Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.15 Switching Characteristics — Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6. Ordering Informa ti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

7. Environmental, Manufacturing, & Handli ng Infor mation . . . . . . . . . . . . . . . . . . . . . . . . . .21

8. Device Pi nout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

8.1 CS48520, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.2 CS48540, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.3 CS48560,48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9. Pack age Me cha n ica l Draw ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

9.1 48-pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10. Revision His tory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

CS485xx Family Data Sheet

32-bit Audio Decoder DSP Family

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List of Figures

Figure 1. RESET Timing......................................................................................................................................... 12

Figure 2. XTI Timing ............................................................................................................................................... 12

Figure 3. Serial Control Port - SPI Slave Mode Timing........................................................................................... 14

Figure 4. Serial Control Port - SPI Master Mode Timing.........................................................................................15

Figure 5. Serial Control Port - I2C Slave Mode Timing ...........................................................................................16

Figure 6. Serial Control Port - I2C Master Mode Timing .........................................................................................17

Figure 7. Digital Audio Input (DAI) Port Timing Diagram ........................................................................................17

Figure 8. Direct Stream Digital - Serial Audio Input Timing.....................................................................................18

Figure 9. Digital Audio Output Port Timing, Master Mode.......................................................................................19

Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)............................................ 19

Figure 11. CS48520, 48-Pin LQFP Pinout..............................................................................................................22

Figure 12. CS48540, 48-Pin LQFP Pinout..............................................................................................................23

Figure 13. CS48560, 48-Pin LQFP Pinout..............................................................................................................24

Figure 14. 48-Pin LQFP Package Drawing............................................................................................................. 25

List of Tables

Table 1. CS485xx Family Related Documentation ................................................................................................5

Table 2. Device and Firmware Selection Guide.....................................................................................................7

Table 3. Ordering Information..............................................................................................................................20

Table 4. Environmental, Manufacturing, & Handling Information.........................................................................21

CS485xx Family Data Sheet

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1. Documentation Strategy

The CS485xx Family Data Sheet describes the CS485xx family of multichannel audio processors.

This document should be used in conjunction with the following documents when evaluating or

designing a syste m aro und the CS485xx family of processors.

The scope of the CS485xx Family Data Sheet is primarily the hardware specifications of the

CS485xx family of devices. This includes hardware functionality, characteristic data, pinout, and

packaging information.

The intended audience for the CS485xx Family Data Sheet is the system PCB designer, MCU

programmer, and the quality control engine er.

2. Overvi ew

The CS485xx DSP Family is designed to provide high-performance post-processing and mixing of

digital audio. The dual clock domain provided on the PCM inputs allows for the mixing of audio

streams with different sampling frequencies. The low-power standby preserves battery life for

applications which are always on, but not necessarily processing audio, such as automotive audio

systems.

There are three devices comprising the CS485xx family. The CS48520, CS48540 and CS48560 are

differentiated by the number of inputs and outputs available. All DSPs support dual input clock

domains and dual audio processing paths. All DSPs are available in a 48-pin QFP package. Please

refer to Table 2 on page 7 for the input, output, firmware features of each device.

2.1 Licensing

Licenses are required for all of the 3rd party audio processing algorithms listed in Section 3. Please

contact your local Cirrus Logic Sales representative for more information.

Table 1. CS485xx Family Related Documentation

Document Name Description

CS485xx Family Data Sheet This document

CS485xx Family Hardware User’s Manual Include s detailed system design information including

Typical Connection Diagrams, Boot-Procedures, Pin

Descriptions, etc.

AN298 - CS485xx Family Firmware User’s Manual Includes detailed firmware design information

includi ng signal processing flow diagram s and cont rol

API informatio n

DSP Composer User’s Manual Includes detailed configuration and usage

information for the GUI development tool.

CS485xx Family Data Sheet

32-bit Audio Decoder DSP Family

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3. Code Overlays

The suite of software available for the CS485xx family consists of an operating system (OS) and a

library of overlays. The overlays have been divided into three main groups called Matrix-processors,

Virtualizer-processors, and Post- processors. All soft ware components are defined below:

1. OS/Kernel - Encompasses all non-audio processing t asks, including loading data fr om external

memory, processing host messages, calling audio-processing subroutines, er ror concealment,

etc.

2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more

output channels than input chann els (2Ön channels ). Examples are Dolby ProLogi c IIx and DTS

Neo:6. Generally speaking, these modules increase the number of valid channels in the audio

I/O buffer.

3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than

input channe ls (nÖ2 channels) with the effect of providing “phantom” speakers to represent the

physical audio channels that were eliminated. Examples are Dolby Headphone® and Dolby

Vir tual S peaker®. Generally speak ing, these modules reduce the number of vali d channels in the

audio I/O buffer.

4. Post-processors - Any module that processes audio I/O buffer PCM data in-pl a ce after the

matrix- or v irtuali zer-pr ocess ors. Exampl es are bass manag ement, audi o manager, to ne contro l,

EQ, delay, customer-specif ic effects, etc.

The bulk of each overlay is stored in ROM within the CS485xx, but a small image is required to

configure the overlays and boot the DSP. This small image can either be stored in an external serial

FLASH/EEPROM, or downloaded via a host control ler through the SPI™/I2C® serial port.

The overlay st ructure r educes the time requi red to reconf igure the DSP when a pr ocessing change i s

requested. Each overlay can be reloaded independently without disturbing the other overlays. For

example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not

need to be reloaded — only the new matrix-processor (the same is true for the other overlays).

Table 2 below lists the firmware available based on device selection. Please refer AN298, CS485xx

Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules

available.

CS485xx Family Data Sheet

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4. Hardware Functional Description

4.1 DSP Core

The CS485xx family DSPs are single-core DSP with separate X and Y data and P code memory

spaces. The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is

capable of perfo rmin g two multiply-an d-acc umulate (MAC) operat ions per cl ock cycle. The DSP core

has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers.

The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between

peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output

(DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads

data move instructions from the DSP core, leaving more MIPS available for signal processing

instructions.

CS485xx family functionality is controlled by application codes that are stored in on-board ROM or

downloaded to the CS485xx from a host controller or external serial FLASH/EEPROM.

Users can develop their applications using DSP Composer to create the processing chain and then

compile the image into a series of commands that are sent to the CS485xx through the SCP. The

processing application can either load modules (matrix-processors, virtualizers, post-processors)

from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.

The CS485xx is suitable for a variety of audio post-processing applications such as automotive

head-ends, automotive amplifiers, and boom boxes.

4.1.1 DSP Memory

The DSP core has its own on-chip data and program RAM and ROM and does not require external

memory for post-processing applications.

The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P

equal in size, or more memory can be alloca ted for Y-RAM in 2kword blocks.

Table 2. Device and Firmware Selection Guide

Device Suggested

Application Chan nel Co unt

Input/Output Package

CS48520-CQZ

Digital TV

Portable Audio Docking Station

Portable DVD

DVD Mini / Receiver

Multimedia PC Speakers

Up to 4 channel in / 4

channel out 48-pin QFP

CS48540-CQZ

CS48540-DQZ

CS48520 features Plus

8 Channel Car Audio

DVD Receiver

Up to 8 channel in / 8

channel out 48-pin QFP

CS48560-CQZ

CS48560-DQZ

CS48540 features Plus

12 channel Car Audio

High-end Digital TV

Dual Source/Dual Zone

SACD

Up to 12 ch ann el in /12

channel out 48-pin QFP

CS485xx Family Data Sheet

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4.1.2 DMA Controller

The powerful 8-channel DMA con tr oller can move data between 8 on-chi p resources. Each resour ce

has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing

modes are supported, with flexible start address and increment controls. The service intervals for

each DMA channel, as well as up to 6 interrupt events, are programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

Each version of the CS485xx supports a different number of input channels. Refer to Table 2 on

page 7 for mo re details.

The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz.

The port is capable of accept ing PCM or DSD formats. Up to 32- bi t word l engths are supported. DSD

is supported and internally converted to PCM before processing. The DAI also supports a time

division multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line (the total

number possible depends on the ratio of SCLK to LRCLK and the version of chip. For example on

the CS48520 only 4 ch of PCM are supported in one line mode and on the CS48560 up to 8

channels are supported.).

The port has two independent slave-only clock domains. Each data input can be independently

assigned to a clock domain. The sample rate of the input clock domains can be determined

automatical ly by the DSP, of f-loadin g the ta sk of monitoring the SPDIF rec eiver fr om the host. A time-

stamping feature allows the input data to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

Each version of the CS485xx supports a different number of output channels. Refer to Table 2 on

page 7 for mo re details.

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as

192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a

clock slave if an external MCLK or SCLK/LRCLK source is available. One of the ser ial audio pins can

be re-configured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with

embedded clock on a single line) .

The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple

channels of PCM audio on a single data line.

4.2.3 Serial Contr ol Port (I2C® or SPI™)

The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C®

modes. Master/Slave operation is chosen by mode select pins when the CS485xx comes out of

Reset. The seri al clock pin can s upport frequenc ies as high as 25 MHz i n SPI mode (SPI clock speed

must always be ≤ (Fdclk/2)). The CS485xx serial cont ro l port also incl udes a pin fo r flow contr ol of the

communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the

host (SCP_IRQ).

4.2.4 GPIO

Many of the CS485xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as

an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising

edge, falling edge, active-low, or active-high.

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4.2.5 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used

to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock

domain can be out put on t he DAO port for drivi ng audio conv erters . The CS485xx defaults to running

from the external reference frequency and is switched to use the PLL output after overlays have

been loaded and configured, either through master boot from an external FLASH or through host

control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output

frequency ratio is selectable between 1:1 (default) or 2:1.

4.2.6 Hardware Watchdog Timer

The CS485xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The

watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This

peripheral ensures that the CS485xx will reset itself in the event of a temporary system failure. In

stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode

(that is, host MCU present) a GPIO will be used to signal the host th at the watc hdog has expired and

the DSP should be rebooted and re-configured.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS485xx family pins are multi-functional. For details on pin functionality please refer to

the CS485xx Hardware User ’s Manual.

4.3.2 Termination Requirements

Open-drain pins on the CS485xx must be pulled high for proper operation. Please refer to the

CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up

resistor is required for proper operation.

Mode select pins in the CS485xx family are used to select the boot mode upon the rising edge from

reset. A detailed explanation of termination requirements for each communication mode select pin

can be found in the CS485xx Hardware User’s Manual.

4.3.3 Pads

The CS485xx I/Os operate fr om the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

The external program code may be encry pted by the programmer to protect any intellectual property

it may contain. A secret, customer-specific key is used to encrypt the program code that is to be

stored external to the devic e. Please contact your local Cirrus representative for details.

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5. Characteristics and Specifications

Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and

temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C,

CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V)

Caution: Operati on at or beyon d these li mits may r esult in per manent dam age to the dev ice. Nor mal operatio n is

not guaranteed at these extremes.

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V)

Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.)

Parameter Symbol Min Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDDIO|

VDD

VDDA

VDDIO

–0.3

2.0

3.6

0.3

Input pin current, any pin except supplies Iin -+/- 10mA

Input voltage on PLL_REF_RES Vfilt -0.3 3.6 V

Input voltage on I/O pins Vinio -0.3 5.0 V

Storage temperature Tstg –65 150 °C

Parameter Symbol Min Typ Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDDIO|

VDD

VDDA

VDDIO

1.71

3.13

1.8

3.3

1.89

3.46

Ambient operating temperature - CQZ

- DQZ

TA0

- 40

-+ 70

+ 85

°C

Parameter Symbol Min Typ Max Unit

High-level input voltage VIH 2.0 - - V

Low-level input voltage, except XTI VIL --0.8V

Low-level input voltage, XTI VILXTI --0.6V

Input Hysteresis Vhys 0.4 V

High-level output voltage (IO = -2mA), except XTI VOH VDDIO * 0.9 - - V

Low-level output voltage (IO = 2mA), except XTI VOL - - VDDIO * 0.1 V

Input leakage XTI ILXTI --5μA

Input leakage current (all digital pins with internal

pul l-up re si st or s enab led) ILEAK --70μA

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5.4 Power Supply Characteristics

(Measurements performed under operating conditions)

5.5 Thermal Data (48-Pin LQFP)

1. Two-layer board is specified as a 76 mm X 114 mm , 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top &

bottom layers.

2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top &

bottom layers and 0.5-oz. copper covering 90 % of the internal power plane & ground plane layers.

3. To calculate the die temperature for a given power dissipation

Tj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]

4. To calculate the case temperature for a given power dissipation

Tc = Tj - [ (Power Dissipation in Watts) * ψjt ]

Parameter Min Typ Max Unit

Operational Power Supply Current:

VDD: Core and I/O operating1

VDDA: PLL operating

VDDIO: With most ports operating

Total Operational Power Dissipation:

Standby Power Supply Current:

VDD: Core and I/O not clocked

VDDA: PLL halted

VDDIO: All connected I/O pins 3-stated by other ICs in system

Total Standby Power Dissipation:

1. Dependent on application firmware and DSP clock speed.

203

480

100

348

μA

μW

Parameter Symbol Min Typ Max Unit

Junction Temperature Tj- - 125 °C

Thermal Resistance (Junction to Ambient)Two-layer Board1

Four-layer Board2θja -

-63.5

54 -

-°C / Watt

Thermal Resistance (Junction to Top of Package)

Two-layer Board3

Four-layer Board4ψjt -

-0.70

0.64 -

-°C / Watt

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5.6 Switching Characteristic s— RESET

Figure 1. RESET Timing

5.7 Switching Characteristi cs — XTI

Figure 2. XTI Timing

Parameter Symbol Min Max Unit

RESET# minimum pulse width low Trstl 1-ms

All bidirectional pins high-Z after RESET# low Trst2z -100ns

Configuration pins setup before RESET# high Trstsu 50 - ns

Configuration pins hold after RESET# high Trsthld 20 - ns

Parameter Symbol Min Max Unit

External Crystal operating frequency1

1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z

Fxtal 11.2896 27 MHz

XTI period Tclki 33.3 100 ns

XTI high time Tclkih 13.3 - ns

XTI low time Tclkil 13.3 - ns

External Crystal Load Capacitance (parallel resonant)2

2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should

be avoided. The crystal oscillator circuit design should follow the crystal manufacturer ’s recommendation for load capacitor

selection.

CL10 18 pF

External Crystal Equivalent Series Resistance ESR 50 Ω

RESET#

Trst2z

Trstl

Trstsu Trsthld

HS[3:0]

ll Bidirectional

Pins

tclkih tclkil

Tclki

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5.8 Switching Characteristics — Internal Clock

5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode.

Parameter Symbol Min Max Unit

Internal DCLK frequency1

CS4852x-CQZ

CS4854x-CQZ

CS4856x-CQZ

CS4854x-DQZ

CS4856x-DQZ

1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until

the next power-on reset.

Fdclk -

Fxtal

150

MHz

Internal DCLK period1

CS4852x-CQZ

CS4854x-CQZ

CS4856x-CQZ

CS4854x-DQZ

CS4856x-DQZ

DCLKP -

6.7

1/Fxtal

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin

should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.

fspisck -25MHz

SCP_CS# falling to SCP_ CLK rising tspicss 24 - ns

SCP_CLK low time tspickl 20 - ns

SCP_C LK high time tspickh 20 - ns

Setup time S CP_MOSI input tspidsu 5-ns

Hold time SC P_MOSI input tspidh 5-ns

SCP_CLK low to SCP_MISO output valid tspidov -11ns

SCP_CLK falling to SCP_IRQ# risin g tspiirqh -20ns

SCP_CS# rising to SCP_IRQ# falling tspiirql 0ns

SCP_CLK low to SCP_CS# rising tspicsh 24 - ns

SCP_CS# rising to SCP_MISO output high-Z tspicsdz -20 ns

SCP_CLK rising to SCP_BSY# falling tspicbsyl -3

*DCLKP+20 ns

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Figure 3. Serial Control Port - SPI Slave Mode Timing

5.10 Swi tching Characteristics — Serial Control Port - SPI Master Mode

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

fspisck -F

xtal/22

2. See Section 5.7.

MHz

SCP_CS# falling to SCP_ CLK rising 3

3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter

tspicss - 11*DCLKP +

(SCP_CLK PERIOD)/2 -ns

SCP_CLK low time tspickl 20 - ns

SCP_C LK high time tspickh 20 - ns

Setup time SCP_MISO input tspidsu 9-ns

Hold time SCP_MISO input tspidh 5-ns

SCP_CLK low to SCP_MOSI output valid tspidov -8ns

SCP_CLK low to SCP_CS# falling tspicsl 7-ns

SCP_CLK low to SCP_CS# rising tspicsh - 11*DCLKP +

(SCP_CLK PERIOD)/2 -ns

Bus free time between active SCP_CS# tspicsx 3*DCLKP - ns

SCP_CLK falling to SCP_MOSI output high-Z tspidz -20ns

CP_BSY#

SCP_CS#

SCP_CLK

CP_MOSI

CP_MISO

SCP_IRQ#

012670567

tspicss

tspickl

tspickh

tspidsu tspidh tspidov

A6 A5 A0 R/W MSB LSB

MSB LSB

tspicsh

tspibsyl

tspiirql

tspiirqh

fspisck

tspicsdz

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Figure 4. Serial Control Port - SPI Master Mode Timing

5.11 Switching Charac teristi cs — Seri al Control P ort - I2C Slave Mode

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin

should be implemented to prevent overflow of the input data buffer.

fiicck - 400 kHz

SCP_CLK low time tiicckl 1.25 - µs

SCP_C LK high time tiicckh 1.25 - µs

SCP_SCK rising to SCP_SDA rising or falling for

START or STOP condition tiicckcmd 1.25 µs

START condition to SCP_CLK falling tiicstscl 1.25 - µs

SCP_CLK falling to STOP condition tiicstp 2.5 - µs

Bus free time between STOP and START conditions tiicbft 3-µs

Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 ns

Hold time SCP_SDA input after SCP_CLK falling tiich 20 - ns

SCP_CLK low to SCP_SDA out valid tiicdov -18ns

SCP_CLK falling to SCP_IRQ# rising tiicirqh -3

*DCLKP + 40 ns

NAK condition to SCP_IRQ# low tiicirql 3*DCLKP + 20 ns

SCP_CLK rising to SCB_BSY# low tiicbsyl -3

*DCLKP + 20 ns

EE_CS#

SCP_CLK

CP_MISO

CP_MOSI

012670567

tspicss

tspickl

tspickh

tspidsu tspidh tspidov

A6 A5 A0 R/W MSB LSB

MSB LSB

tspicsh

tspicsx

fspisck

tspidz

tspicsl

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Figure 5. Serial Control Port - I2C Slave Mode Timing

5.12 Swi tching Characteristics — Serial Control Port - I2C Master Mode

Parameter Symbol Min Max Units

SCP_CLK frequency1

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

fiicck -400kHz

SCP_CLK low time tiicckl 1.25 - µs

SCP_C LK high time tiicckh 1.25 - µs

SCP_SCK risin g to SCP _SDA rising or falling for START or

STOP condition tiicckcmd 1.25 µs

START condition to SCP_CLK falling tiicstscl 1.25 - µs

SCP_CLK falling to STOP condition tiicstp 2.5 - µs

Bus free time between STOP and START conditions tiicbft 3-µs

Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 ns

Hold time SCP_SDA input after SCP_CLK falling tiich 20 - ns

SCP_CLK low to SCP_SDA out valid t iicdov -18ns

CP_BSY#

SCP_CLK

SCP_SDA

SCP_IRQ#

01 67801 7

tiicckl

tiicckh

tiicsu tiich

A6 A0 R/W ACK LSB

tiicirqh tiicirql

ACK

MSB

tiicstp

tiiccbsyl

tiicdov tiicb

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

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Figure 6. Serial Control Port - I2C Master Mode Timing

5.13 Swi tching Characteristics — Digital Audio Slave Input Port

Figure 7. Digital Audio Input (DAI) Port Timing Diagram

5.14 Switching Characteristics — DSD Slave Input Port

Parameter Symbol Min Max Unit

DAI_SCLK period Tdaiclkp 40 - ns

DAI_SCLK duty cycle - 45 55 %

Setup time DAI_DATAn tdaidsu 10 - ns

Hold time DAI_DATAn tdaidh 5-ns

Parameter Symbol Min Typ Max Unit

DSD_SCLK Pulse Width Low tsclkl 78 - - ns

DSD_SCLK Pulse Width High tsclkh 78 - - ns

DSD_SCLK Frequency (64x Oversampled) - 1.024 - 3.2 MHz

DSD_ A / _B vali d to DSD_SCL K risi ng se tup tim e tsdlrs 20 - - ns

DSD_SCLK rising to DSD_A or DSD_B hold time tsdh 20 - - ns

CP_CLK

CP_SDA

01 67801 7

tiicckl

tiicckh

tiicsu tiich

A6 A0 R/W ACK LSB

ACK

MSB

tiicstp

tiicdov tiic

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

DAI_SCLK

AI_DATAn

tdaidh

tdaidsu

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Figure 8. Direct Stream Digital - Serial Audio Input Timing

5.15 Swi tching Characteristics — Digital Audio Output Port

Parameter Symbol Min Max Unit

DAO_MCLK period Tdaomclk 40 - ns

DAO_MCLK duty cycle - 45 55 %

DAO_SCLK period for Master or Slave mode1

1. Master mode timing specifications are characte rized, not production tested.

Tdaosclk 40 - ns

DAO_SCLK duty cycle for Master or Slave mode1-4060%

Master Mode (Output A1 Mode)1,2

2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce

DAO_SCLK, DAO_LRCLK.

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input tdaomsck -19ns

DAO_LRCLK delay from DAO_SCLK transition, respectively3

3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the

data is valid.

tdaomstlr -8ns

DAO_SCLK delay from DAO_LRCLK transition, respectively3tdaomlrts -8ns

DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK transition3tdaomdv -10ns

Slave Mode (Output A0 Mode)4

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK transition3tdaosdv -15ns

DAO_LRCLK delay from DAO_SCLK transition, respectively3tdaosstlr -30ns

DAO_SCLK delay from DAO_LRCLK transition, respectively3tdaoslrts -15ns

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Figure 9. Digital Audio Output Port Timing, Master Mode

Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)

DAO_MCLK

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaomlclk

tdaomsck

tdaomdv

tdaomlrts

DAO_MCLK

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaomclk

tdaomsck

tdaomstlr

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaosstlr

tdaosclk

AO_SCLK

AO_LRCLK

tdaoslrts

tdaosd

tdaosclk

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

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6. Ordering Info rmation

The CS485xx family part number is described as follows:

CS485NI-XYZR

where

N - Product Number Variant

I - ROM ID Number

X - Product Grade

Y - Package Type

Z - Lead (Pb) Free

R - Tape and Reel Packaging

NOTE: Please contact the factory for availability of the -D (automotive grade) package.

Table 3. Ordering Information

Part No. Grade Temp. Range Package

CS48520-CQZ Commercial 0 to +70 °C

48-pin LQFP

CS48540-CQZ Commercial 0 to +70 °C

CS48540-DQZ Automotive -40 to +85 °C

CS48560-CQZ Commercial 0 to +70 °C

CS48560-DQZ Automotive -40 to +85 °C

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7. Environmental, Manufacturing, & Handling Information

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 4. Environmental, Manufacturing, & Handling Information

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

CS48520-CQZ

260 °C 3 7 Days

CS48540-CQZ

CS48540-DQZ

CS48560-CQZ

CS48560-DQZ

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8. Device Pinout Dia grams

8.1 CS48520, 48-pin LQFP Pinout Diagram

Figure 11. CS48520, 48-Pin LQFP Pinout

XTO

XTI

GNDA

PLL_REF_RES

VDDA (3.3V) GPIO1

GPIO2

GPIO16, DAI1_DATA0

GPIO0

GPIO13, SCP_BSY#, EE_CS#

GPOI12, SCP_IRQ#

GPIO10, SCP__MISO / SDA

GPIO9, SCP_MOSI

GPIO11, SCP_CLK

GND4

GNDIO4

VDD3

GND3

VDDIO3

GNDIO3

GPIO5, XMTA

GPIO3, HS1

DAO1_DATA0, HS0

DAO_LRCLK

DAI1_LRCLK

GPIO18, DAO_MCLK

DAI1_SCLK

VDD1

GND1

DAO_SCLK

GPIO4, HS2

RESET#

VDDIO1

GNDIO1

GPIO6, DAO2 _DATA0, HS3

GPIO7, HS4

VDD2

GND2

VDDIO2

GNDIO2

GPIO8, SCP_CS#

TEST

DBDA

DBCK

XTAL_OUT GPIO15, DAI2_SCLK

GPIO14, DAI2_LRCLK

GPIO17, DAI2_DATA0

CS48520

48-Pin LQFP

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8.2 CS48540, 48-pin LQFP Pinout Diagram

Figure 12. CS48540, 48-Pin LQFP Pinout

XTO

XTI

GNDA

PLL_REF_RES

VDDA (3.3V) GPIO1, DAI1_DATA2

GPIO2

GPIO16, DAI1_DATA0

GPIO0, DAI1_DATA1

GPIO13, SCP_BSY#, EE_CS#

GPOI12, SCP_IRQ#

GPIO10, SCP__MISO / SDA

GPIO9, SCP_MOSI

GPIO11, SCP_CLK

GND4

GNDIO4

VDD3

GND3

VDDIO3

GNDIO3

GPIO5, XMTA

GPIO3, DAO1_ DATA1, HS1

DAO1_DATA0, HS0

DAO_LRCLK

DAI1_LRCLK

GPIO18, DAO_MCLK

DAI1_SCLK

VDD1

GND1

DAO_SCLK

GPIO4, DAO1_ DATA2, HS2

RESET#

VDDIO1

GNDIO1

GPIO6, DAO2_DATA0, HS3

GPIO7, HS4

VDD2GND2

VDDIO2

GNDIO2

GPIO8, SCP_CS#

TEST

DBDA

DBCK

XTAL_OUT GPIO15, DAI2_SCLK

GPIO14, DAI2_LRCLK

GPIO17,

DAI2_DATA0

CS48540

48-Pin LQFP

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8.3 CS48560,48-pin LQFP Pinout Diagram

Figure 13. CS48560, 48-Pin LQFP Pinout

XTO

XTI

GNDA

PLL_REF_RES

VDDA (3.3V) GPIO1, DAI1_DATA2, TM2, DSD2

GPIO2, DAI1_DATA3, TM3, DSD3

GPIO16, DAI1_DATA0, TM0, DSD0

GPIO0, DAI1_DATA1, TM1, DSD1

GPIO13, SCP_BSY#, EE_CS#

GPOI12, SCP_IRQ#

GPIO10, SCP__MISO / SDA

GPIO9, SCP_MOSI

GPIO11, SCP_CLK

GND4

GNDIO4

VDD3

GND3

VDDIO3

GNDIO3

GPIO5, DAO1_DATA3, X MTA

GPIO3, DAO1_ DATA1, HS1

DAO1_DATA0, HS0

DAO_LRCLK

DAI1_LRCLK, DAI1_DATA4, DSD5

GPIO18, DAO_MCLK

DAI1_SCLK, DSD-CLK

VDD1

GND1

DAO_SCLK

GPIO4, DAO1_ DATA2, HS2

RESET#

VDDIO1

GNDIO1

GPIO6, DAO2 _DATA0, HS3

GPIO7, DAO2_D ATA1, HS4

VDD2GND2

VDDIO2

GNDIO2

GPIO8, SCP_CS#

TEST

DBDA

DBCK

XTAL_OUT GPIO15, DAI2_SCLK

GPIO14, DAI2_LRCLK

GPIO17, DAI2_DATA0, DSD4

CS48560

48-Pin LQFP

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9. Package Mechanical Drawings

9.1 48-pin LQFP Package Drawing

Figure 14. 48-Pin LQFP Package Drawing

48LDLQFP(7x7x1.4mmbody)

Number of Leads

MIN NOM MAX

A1.60

A1 0.05 0.15

A2 1.35 1.40 1.45

b 0.17 0.22 0.27

D9.00BSC

D1 7.00 BSC

e0.50BSC

E9.00BSC

E1 7.00 BSC

theta 0 7

L 0.45 0.60 0.75

L1 1.00 REF

NOTES:

1) Reference document: JEDEC MS-026

2) All dimensions are in millimeters and controlling dimension is in millimeters.

3) D1 and E1 do not include mold flash which is 0.25 mm max. per side.A1

4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.

CS485xx Family Data Sheet

32-bit Audio Decoder DSP Family

CONFIDENTIAL

CONFIDENTIAL DRAFT

DELPHI

10. Revision History

Revision Date Changes

A1 JUL 2006 Advance release.

A2 JUL 2006 Updated pinout definition for pins 26 and 27. Updated typical power

numbers.

A3 DEC 5 2006 Updated sections 2.0, 4.2.1, 5.8, Table 3, Table 4, to show new device

numbering scheme. Updated sections 8.1, 8.2, 8.3.

PP1 MAR 12 2007 Preliminary Release

PP2 December 18, 2007

Changed title of data sheet from CS48500 Data Sheet to CS485xx Fam-

ily Data Sheet to cover all CS485xx family products. Updated Standby

Power specification in Section . Updated DAO timing specifications and

timi ng diagrams in Section 5.15.

F1 April 21, 2007

Removed DSD Phase Modulation Mode from Se cti on 5.14. Removed

reference to MCLK in Section 5.14. Redefined Master mode clock

speed for SCP_CLK in Section 5.10. Redefined DC leakage character-

ization data in Section 5.3. Added typical crystal frequency values in

Table Footnote 1 under Section 5.7. Modified Footnote 1 under Section

5.9. Modified power supply characteristics in Section 5.4,

F2 July 14, 2008 Added reference to support for time division multiplexed (TDM) one-line

data mode for DAO port in Section 4.2.2.

F3 February 16, 2009 Updated Section 5.5, adding Junction Temperature specification.