1
HCTL-2032, HCTL-2032-SC, HCTL-2032-SCT, HCTL-2022
Quadrature Decoder/ Counter Interface ICs
Data Sheet
Description
The HCTL-20XX-XX is CMOS ICs that perform the quadra-
ture decoder, counter, and bus interface function. The
HCTL-20XX-XX is designed to improve system perfor-
mance in digital closed loop motion control systems and
digital data input systems. It does this by shifting time
intensive quadrature decoder functions to a cost eec-
tive hardware solution. The HCTL-20XX-XX consists of a
quadrature decoder logic, a binary up/down state coun-
ter, and an 8-bit bus interface. The use of Schmitt-trig-
gered CMOS inputs and input noise lters allows reliable
operation in noisy environments. The HCTL-20XX-XX
contains 32-bit counter and provides LSTLL compatible
tri-state output buers. Operation is specied for a tem-
perature range from -40 to +100°C at clock frequencies
up to 33MHz.
The HCTL-2032 and HCTL-2032-SC have dual-axis capa-
bility and index channel support. Both devices can be
programmed as 4x/2x/1x count mode. The HCTL-2032
and HCTL2032-SC also provides quadrature decoder out-
put signals and cascade signals for use with many stan-
dard computer ICs.
The HCTL-2022 has most of the HCTL-2032 features, but
it can only supports single axis and xed at 4x count
mode. The HCTL-2022 doesn’t provide decoder output
and cascade signals.
Features
• Interfaces Encoder to Microprocessor
• 33 MHz Clock Operation
• Programmable Count Modes (1x, 2x or 4x)
• Single or Dual Axis Support
• Index Channel Support
• High Noise Immunity:
• Schmitt Trigger Inputs and Digital Noise Filter
• 32-Bit Binary Up/Down Counter
• Latched Outputs
• 8-Bit Tristate Interface
• 8, 16, 24, or 32-Bit Operating Modes
• Quadrature Decoder Output Signals, Up/Down and
Count
• Cascade Output Signals, Up/Down and Count
• Substantially Reduced System Software
• 5V Operation (VDD - VSS)
• TTL/CMOS Compatible I/O
• Operating Temperature: -40°C to 100°C
• 32-Pin PDIP, 32-Pin SOIC, 20-Pin PDIP
Applications
• Interface Quadrature Incremental Encoders to
Microprocessors
• Interface Digital Potentiometers to Digital Data Input
Buses
ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-2032 family ICs.
2
Devices
Part Number Description Package Drawing
HCTL-2032 32-bit counter, dual axis, decoder and cascade outputs, index channel support,
programmable count modes, and 33 Mhz clock operation.
A
HCTL-2032-SC All features of HCTL-2032. B
HCTL-2022 Most of the HCTL-2032 features. The device supports single axis, and no decoder out-
put and cascade signals. The programmable count mode is set to 4x internally.
C
PINOUT A PINOUT B PINOUT C
HCTL-2032
VDD
EN1
EN2
D0
CLK
SEL1
OE
U/D
X
U/D
Y
D7
RST
Y
RST
X
CHB
Y
CHB
X
CHA
X
CHA
Y
X/Y
D3
D2
D1
CNTDEC
X
CNTDEC
Y
SEL2
CNTCAS
X
CNTCAS
Y
TEST
D4
D5
D6
CHI
Y
VSS
CHI
X
HCTL-2032-SC
VDD
EN1
EN2
D0
CLK
SEL1
OE
U/D
X
U/D
Y
D7
RST
Y
RST
X
CHB
Y
CHB
X
CHA
X
CHA
Y
X/Y
D3
D2
D1
CNTDEC
X
CNTDEC
Y
SEL2
CNTCAS
X
CNTCAS
Y
TEST
D4
D5
D6
CHI
Y
VSS
CHI
X
HCTL-2022
VDD
D0
CLK
SEL1
OE
U/D
D7
RST
CHA
CHB
D3
D2
D1
SEL2
TEST
D4
D5
D6
INDEX
VSS
Package Dimensions (dimensions in inches)
1) HCTL - 2032
3
2) HCTL - 2032 - SC
3) HCTL - 2022
4
4) HCTL-2032 –SCT (Tape and Reel Version of HCTL-2032-SC)
Notes:
1. 10 Sprocket hole pitch cumulative tolerance 0.2
2. Camber in compliance with EIA 481
3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole
4. All dimensions in mm
5
Notes
1. Free Air
2. In general, for any VDD between the allowable limits (+4.5V to +5.5V), VIL = 0.3VDD and VIH = 0.7VDD;
typical values are VOH = VDD - 0.5V and VOL = VSS + 0.2V
3. Including package capacitance
Operating Characteristics
Table 1. Absolute Maximum Ratings
(All voltages below are referenced to VSS)
Parameter Symbol Limits Units
DC Supply Voltage VDD -0.3 to +6.0 V
Input Voltage VIN -0.3 to
(VDD +0.3)
V
Storage Temperature TS-55 to +150 °C
Operating Temperature [1] TA-40 to +100 °C
Table 2. Recommended Operating Conditions
Parameter Symbol Limits Units
DC Supply Voltage VDD 4.5 to 5.5 V
Ambient Temperature [1] TA-40 to +100 °C
Table 3. DC Characteristics VDD = 5V ± 5%; TA = -40 to 100°C
Symbol Parameter Condition Min Typ Max Unit
VIL [2] Low-Level Input Voltage 1.5 V
VIH [2] High-Level Input Voltage 3.5 V
VT+ Schmitt-Trigger Positive-Going Threshold 3.5 4.0 V
VT- Schmitt-Trigger Negative-Going Thresh-
old
1.0 1.5 V
VHSchmitt-Trigger Hysteresis 1.0 2.0 V
IIN Input Current VIN=VSS or VDD -10 1 +10 µA
VOH [2] High-Level Output Voltage IOH = -3.75 mA 2.4 4.5 V
VOL [2] Low-Level Output Voltage IOL = +3.75mA 0.2 0.4 V
IOZ High-Z Output Leakage Current VO=VSS or VDD -10 1 +10 µA
IDD Quiescent Supply Current VIN=Vss or VDD 1 10 µA
CIN [3] Input Capacitance Any Input 5 pF
COUT [3] Output Capacitance Any Output 5 pF
6
Symbol
Pin
Description
HCTL
2032/
2032-SC
HCTL
2022
VDD 1 1 Power Supply
VSS 18 12 Ground
CLK 5 3 CLK is a Schmitt-trigger input for the external clock signal.
CHAX15 10 CHAX, CHAY, CHBX, and CHBY are Schmitt-trigger inputs that accept the outputs
from a quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required. CHAX and CHBX
are the 1st axis and CHAY and CHBY are the 2nd axis.
CHAY16 NC
CHBX14 9
CHBY13 NC
CHIX17 11 CHIX and CHIY are Schmitt-trigger inputs that accept the outputs of Index channel
from an incremental optical shaft encoder.
CHIY19 NC
RSTNX12 8 This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RSTX/ and RSTY/ are asynchronous with
respect to any other input signals. RSTX/ is to reset the 1st axis counter and RSTY/ is
to reset the 2nd axis counter.
RSTNY11 NC
OEN 7 5 This CMOS active low input enables the tri-state output buers. The OE/, SEL1, and
SEL2 inputs are sampled by the internal inhibit logic on the falling edge of the clock
to control the loading of the internal position data latch.
SEL16 4 These CMOS inputs directly controls which data byte from the position latch is en-
abled into the 8-bit tri-state output buer. As in OE/ above, SEL1 and SEL2 also con-
trol the internal inhibit logic.
BYTE SELECTED
SEL1 SEL2 MSB 2ND 3RD LSB
0 1 D4
1 1 D3
0 0 D2
1 0 D1
SEL226 17
EN12 NC These CMOS control pins are set to high or low to activate the selected count mode
before the decoding begins.
Count Modes
EN1 EN2 4x 2x 1x
0 0 Illegal Mode
1 0 On
0 1 On
1 1 On
EN23 NC
X/Y 32 NC Select the 1st or 2nd axis data to be read. Low bit enables the 1st axis data, while
high bit enables the 2nd axis data.
CNTDECX27 NC A pulse is presented on this LSTTL-compatible output when the quadrature decod-
er (4x/2x/1x) has detected a state transition. CNTDECX is for 1st axis and CNTDECY
is for 2nd axis.
CNTDECY28 NC
U/Dx 8 6 This LSTTL-compatible output allows the user to determine whether the IC is count-
ing up or down and is intended to be used with the CNTDEC and CNTCAS outputs.
The proper signal U (high level) or D/ (low level) will be present before the rising
edge of the CNTDEC and CNTCAS outputs.
U/Dy 9 NC
Functional Pin Description
Table 4. Functional Pin Descriptions
7
CNTCASX25 NC A pulse is presented on this LSTTL-compatible output when the HCTL-2032 / 2032-
SC internal counter overows or underows. The rising edge on this waveform may
be used to trigger an external counter.
CNTCASY24 NC
TEST 23 16 This pin is used for internal testing. Tied it to ground or leave it oating for normal
operation.
D0 4 2 These LSTTL-compatible tri-state outputs form an 8-bit output ports through which
the contents of the 32-bit position latch may be read in 4 sequential bytes. The MSB
is read rst followed by the rest of the bytes with the LSB is read last.
D1 31 20
D2 30 19
D3 29 18
D4 22 15
D5 21 14
D6 20 13
D7 10 7
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Notes
1. tclk - max delay (item 20/21) + min delay (item 22/23)
2. tclk - max delay (item 22/23) + min delay (item 20/21)
Switching Characteristics
Table 5. Switching Characteristics
Max/Min specications at VDD = 5V ± 5%; TA = -40 to 100°C, CL = 40 pf
Symbol Description Min. Max. Units
1 tCLK Clock Period 33 MHz
2 tCHH Pulse width, clock high 1/f ns
3 tCD Delay time, rising edge of clock to valid, updated count information on D0-7 31 ns
4 tODE Delay time, OEN fall to valid data 29 ns
5 tODZ Delay time, OEN rise to Hi-Z state on D0-7 29 ns
6 tSDV Delay time, SEL0~SEL1 valid to stable, selected data byte
(delay to High Byte = delay to Low Byte)
29 ns
7 tXNYDV Delay time, XNY valid to stable, selected data byte. 29 ns
8 tCLH Pulse width, clock low 15 ns
9 tSS Setup time, SEL1~SEL2 before clock fall 12 ns
10 tOS Setup time, OEN before clock fall 12 ns
11 tXNYS Setup time, XNY before clock fall 12 ns
12 tSH Hold time, SEL1~SEL2 after clock fall 0 ns
13 tOH Hold time, OEN after clock fall 0 ns
14 tXNYH Hold time, XNY after clock fall 0 ns
15 tRST Pulse width, RSTNX~RSTNY low 10 ns
16 tDCD Hold time, last position count stable on D0-7 after clock rise 2 ns
17 tDSD Hold time, last data byte stable after next SEL state change 2 ns
18 tDOD Hold time, data byte stable after OEN rise 2 ns
19 tDXNYD Hold time, data byte stable after XNY change 2 ns
20 tUDDX Delay time, U/DNX valid after clock rise 4 29 ns
21 tUDDY Delay time, U/DNY valid after clock rise 4 29 ns
22 tCHXD Delay time, CNTDECX or CNTCASX high after clock rise 4 31 ns
23 tCHYD Delay time, CNTDECY or CNTCASY high after clock rise 4 31 ns
24 tCLXD Delay time, CNTDECX or CNTCASX low after clock fall 4 31 ns
25 tCLYD Delay time, CNTDECY or CNTCASY low after clock fall 4 31 ns
26 tUDXH Hold time, U/DNX stable after clock rise 2 ns
27 tUDYH Hold time, U/DNY stable after clock rise 2 ns
28 tUDCXS Setup time, U/DNX valid before CNTDECX or CNTCASX rise Note 1 ns
29 tUDCYS Setup time, U/DNY valid before CNTDECY or CNTCASY rise Note 1 ns
30 tUDCXH Hold time, U/DNX stable after CNTDECX or CNTCASX rise Note 2 ns
31 tUDCYH Hold time, U/DNY stable after CNTDECY or CNTCASY: rise Note 2 ns
9
D0-D7
CLK
NEW
DATA
DATA NOT STABLE
OLD
DATA
tCLK
tCHH tCLH
tCD
tDCD tDCD
D0-D7
CLK
NEW
DATA
DATA NOT STABLE
OLD
DATA
tCLK
tCHH tCLH
tCD
tDCD tDCD
D0-D7
CLK
NEW
DATA
DATA NOT STABLE
OLD
DATA
tCLK
tCHH tCLH
tCD
tDCD tDCD
D0-D7
CLK
NEW
DATA
DATA NOT STABLE
OLD
DATA
tCLK
tCHH tCLH
tCD
tDCD tDCD
D0 -D7
OE
NOT STABLE
tODE
tDOD
STABLE DATANOT STABLE
tODZ
HIGH -ZHIGH -Z
Figure 1. Reset Waveform
Figure 3. Tri-State Output Timing
Figure 4. Bus Control Timing
Figure 2. Waveforms for Positive Clock Edge Related Delays
10
t UDXS / t UDYS t UDXH / t UDYH
t UDDX / t UDDY
t CHXD /
t CHYD
t CLXD /
t CLYD
t UDXH / t UDYH
CLK
U/DX
CNTDECX
CNTCASX
CNTDECY
CNTCASY
U/DY
t XNYS
t DXNYD
D0-D7 (1st-Axis) D0-D7 (2nd-Axis)
CLK
XNY
D0-D7
t XNYDV
CLK
CHA
CHB
D0-D7
CNTDEC
CNTCAS
H'FFFFFFFD H'00000001 H'00000002 H'00000003H'FFFFFFFE H'FFFFFFFF H'00000000
Figure 5. Decoder, Casade Output Timing
Figure 6. Output Data from 1st-axis and 2nd-axis
Figure 7. Quadrature decoder for 1st-axis/ 2nd-axis (4x count mode)
11
CLK
CHA
CHB
D0-D7
CNTDEC
CNTCAS
H'FFFFFFFF H'00000001 H'00000002H'00000000
CLK
CHA
CHB
D0-D7
CNTDEC
CNTCAS
H'FFFFFFFF H'00000001H'00000000
Figure 8. Quadrature decoder for 1st-axis/ 2nd-axis (2x count mode)
Figure 9. Quadrature decoder for 1st-axis/ 2nd-axis (1x count mode)
12
Operation
A block diagram of the HCTL-20XX-XX family is shown
in Figure 10. The operation of each major function is de-
scribed in the following sections.
RSTX
RSTY
Digital Filter
CHAX
CHBX
CHAY
CHBY
CHIX
CHIY
4x/2x/1x
Decode Logic
CNTX
UP/DN X
CNTY
UP/DN Y
CNTX
UP/DN X
CNTY
UP/DN Y
CLRX
CLRY
CLRX
CLRY
INHX INHYEN1 EN2
SEL1
SEL2
OE
QX0 - QX31
QY0 - QY31
DX0 - DX31
DY0 - DY31
DX0 - DX7
DX8 - DX15
DX16 - DX23
DX24 - DX31
32 Bits Binary
Counter
32 Bits Latch Octal 4 bit
Mux/Buffer
DY0 - DY7
DY8 - DY15
DY16 - DY23
DY24 - DY31
DX0 - DX7
DX8 - DX15
DX16 - DX23
DX24 - DX31
DY0 - DY7
DY8 - DY15
DY16 - DY23
DY24 - DY31
D0 - D7
XNY
32
32 8
8
8
8
8
8
8
8
8
CLK
EN1
EN2
SEL1
SEL2
OE
XNY
Inhibit Block
Decode / Cascade
Outputs (Y)
Decode / Cascade
Outputs (X)
U/DX
CNTDECX
CNTCASX
U/DY
CNTDECY
CNTCASY
CHAX filtered
CHBX filtered
CHAY filtered
CHBY filtered
CHIX filtered
CHIY filtered RX RY
CLRX
CLRY
SEL1 SEL2 OE
Figure 10. Simplied Logic Diagram
13
Digital Noise Filter
The digital noise lter section is responsible for rejecting
noise on the incoming quadrature signals. The input sec-
tion uses two techniques to implement improved noise
rejection. Schmitt-trigger inputs and a three-clock-cycle
delay lter combine to reject low level noise and large,
short duration noise spikes that typically occur in mo-
tor system applications. Both common mode and dif-
ferential mode noise are rejected. The user benets from
these techniques by improved integrity of the data in the
counter. False counts triggered by noise are avoided.
Figure 11 shows the simplied schematic of the input sec-
tion. The signals are rst passed through a Schmitt-trig-
ger buer to address the problem of input signals with
slow rise times and low-level noise (approximately < 1V).
The cleaned up signals are then passed to a four-bit delay
lter. The signals on each channel are sampled on rising
clock edges. A time history of the signals is stored in the
four-bit shift register. Any change on the input is tested
for a stable level being present for three consecutive ris-
ing clock edges. Therefore, the ltered output waveforms
can change only after an input level has the same value
for three consecutive rising clock edges.
Refer to Figure 12, which shows the timing diagram. The
result of this circuitry is that short noise spikes between
rising clock edges are ignored and pulses shorter than
two clock periods are rejected.
CHA
CHA
filtered
D Q D Q D Q D Q
CK
CK
J
K
Q
CHB
CHB
filtered
D Q D Q D Q D Q
CK
CK
J
K
Q
CHI
CHI
filtered
D Q D Q D Q D Q
CK
CK
J
K
Q
Figure 11. Simplied Digital Noise Filter Logic
14
CLK
CHA
CHB
CHA
filtered
CHB
filtered
CHI
CHI
filtered
t
E
t
E
t
ES
t
ES
t
ES
t
ES
t
E
t
E
3 t
CLK
Noise Spike
Figure 12. Signal Propagation through Digital Noise Filter
Quadrature Decoder
The quadrature decoder decodes the incoming ltered
signals into count information. This circuitry multiplies
the resolution of the input signals by a factor of one, two
or four (1X, 2X, 4X decoding) depending on the resolu-
tion mode. When using an encoder for motion sensing,
the user benets from the selectable resolution by being
able to provide better system control.
The quadrature decoder samples the outputs of the CHA
and CHB lters. Based on the past binary state of the two
signals and the present state, it outputs a count signal
and a direction signal to the integral position counter.
Figure 13 shows the quadrature states of Channel A and
Channel B signals. The?4x decoder mode will output
a count signal for every state transition (count up and
count down). Figure 14 shows the valid state transi-
tions for 2x and 1x decoder modes. The 2x/1x decoder
will output a count signal at respective state transition,
depending on the counting direction. Channel A lead-
ing channel B results in counting up. Channel B leading
channel A results in counting down. Illegal state transi-
tions, caused by faulty encoders or noise severe enough
to pass through the lter, will produce an erroneous
count.
1
2
3
4Valid State
Transitions
count up
count
down
12 3 4
clk
state
chA
chB
Tes
Te
Telp
15
CHA CHB STATE
4X Decoder
(Count Up & Count Down)
1 0 1 Pulse
1 1 2 Pulse
0 1 3 Pulse
0 0 4 Pulse
CHA CHB STATE
2x
Count Up
2x
Count Down
1x
Count Up
1x
Count Down
1 0 1 Pulse - Pulse -
1 1 2 - Pulse - Pulse
0 1 3 Pulse - - -
0 0 4 - Pulse - -
Figure 13. 4x Decoder Mode
Figure 14. 2x and 1x Decoder Modes
Design Considerations
The designer should be aware that the operation of the
digital lter places a timing constraint on the relationship
between incoming quadrature signals and the external
clock. Figure 12 shows the timing waveform with an in-
cremental encoder input. Since an input has to be stable
for three rising clock edges, the encoder pulse width (tE
- low or high) has to be greater than three clock periods
(3tCLK). This guarantees that the asynchronous input will
be stable during three consecutive rising clock edges. A
realistic design also has to take into account nite rise
time of the waveforms, asymmetry of the waveforms,
and noise. In the presence of large amounts of noise, tE
should be much greater than 3tCLK to allow for the inter-
ruption of the consecutive level sampling by the three-
bit delay lter. It should be noted that a change on the
inputs that is qualied by the lter will internally propa-
gate in a maximum of seven clock periods.
The quadrature decoder circuitry imposes a second tim-
ing constraint between the external clock and the input
signals. There must be at least one clock period between
consecutive quadrature states. As shown in Figure 13,
a quadrature state is dened by consecutive edges on
both channels. Therefore, tES (encoder state period) >
tCLK. The designer must account for deviations from the
nominal 90 degree phasing of input signals to guarantee
that tES > tCLK.
Position Counter
This section consists of a 32-bit (HCTL-20XX-XX) binary
up/down counter which counts on rising clock edges as
explained in the Quadrature Decoder Section. All 32 bits
of data are passed to the position data latch. The system
can use this count data in several ways:
A. System total range is 32 bits, so the count represents
“absolute” position.
B. The system is cyclic with 32 bits of count per cycle.
RST/ is used to reset the counter every cycle and the
system uses the data to interpolate within the cycle.
C. System count is >8, 16, 24, or 32 bits, so the count data
is used as a relative or incremental position input for a
system software computation of absolute position. In
this case counter rollover occurs. In order to prevent
loss of position information, the processor must read
the outputs of the IC before the count increments
one-half of the maximum count capability. Two’s-
complement arithmetic is normally used to compute
position from these periodic position updates.
D. The system count is >32 bits so the HCTL-2032 / 2032-
SC can be cascaded with other standard counter ICs to
give absolute position.
16
Quadrature Decoder Output (HCTL-2032 / 2032-SC only)
The quadrature decoder output section consists of count
and up/down outputs derived from the 4x/2x/1x decod-
er mode of the HCTL-2032 / 2032-SC. When the decoder
has detected a count, a pulse, one-half clock cycle long,
will be output on the CNTDCDR pin. This output will oc-
cur during the clock cycle in which the internal counter
is updated. The U/D pin will be set to the proper voltage
level one clock cycle before the rising edge of the CNT-
DCDR pulse, and held one clock cycle after the rising edge
of the CNTDCDR pulse. These outputs are not aected by
the inhibit logic.
Cascade Output (HCTL-2032 / 2032-SC only)
The cascade output also consists of count and up/down
outputs. When the HCTL-2032 / 2032-SC internal coun-
ter overows or underows, a pulse, one-half clock cycle
long, will be output on the CNTCAS pin. This output will
occur during the clock cycle in which the internal coun-
ter is updated. The U/D pin will be set to the proper volt-
age level one clock cycle before the rising edge of the
CNTCAS pulse, and held one clock cycle after the rising
edge of the CNTCAS pulse. These outputs are not aected
by the inhibit logic.
Step SEL1 SEL2 OE CLK Inhibit Signal Action
1 L H L 1 Set inhibit; Read MSB
2 H H L 1 Read 2nd Byte
3 L L L 1 Read 3rd Byte
4 H L L 1 Read LSB
5 X X H 0 Completes inhibit logic reset
Figure 15. Four Bytes Read Sequence
Position Data Latch
The position data latch is a 32-bit latch which captures
the position counter output data on each rising clock
edge, except when its inputs are disabled by the inhibit
logic section during four-byte read operations. The out-
put data is passed to the bus interface section. When ac-
tive, a signal from the inhibit logic section prevents new
data from being captured by the latch, keeping the data
stable while successive reads are made through the bus
section. The latch is automatically re-enabled at the end
of these reads. The latch is cleared to 0 asynchronously by
the RST signal.
Inhibit Logic
The Inhibit Logic Section samples the OE, SEL1 and SEL2
signals on the falling edge of the clock and, in response
to certain conditions (see Figure 15), inhibits the position
data latch. The RST signal asynchronously clears the in-
hibit logic, enabling the latch.
Bus Interface
The bus interface section consists of a 32 to 8 line multi-
plexer and an 8-bit, three-state output buer. The mul-
tiplexer allows independent access to the low and high
bytes of the position data latch. The SEL1, SEL2 and OE
signals determine which byte is output and whether or
not the output bus is in the high-Z state. In the HCTL-
20XX-XX, the data latch is 32 bit wide.
17
Cascade Considerations (HCTL-2032 / 2032-SC only)
The HCTL-2032 / 2032-SC ‘s cascading system allows for
position reads of more than four bytes. These reads can
be accomplished by latching all the bytes and then read-
ing the bytes sequentially over the 8-bit bus. It is assumed
here that, externally, a counter followed by a latch is used
to count any count that exceeds 32 bits. This congura-
tion is compatible with the HCTL-2032 / 2032-SC internal
counter/latch combination.
Consider the sequence of events for a read cycle that
starts as the HCTL-2032 / 2032-SC ‘s internal counter rolls
over. On the rising clock edge, count data is updated in
the internal counter, rolling it over. A count-cascade pulse
(CNTCAS) will be generated with some delay after the ris-
ing clock edge (tCHD). There will be additional propaga-
tion delays through the external counters and registers.
Meanwhile, with SEL and OE low to start the read, the in-
ternal latches are inhibited at the falling edge and do not
update again till the inhibit is reset.
If the CNTCAS pulse now toggles the external counter
and this count gets latched a major count error will oc-
cur. The count error is because the external latches get
updated when the internal latch is inhibited.
Valid data can be ensured by latching the external coun-
ter data when the high byte read is started (SEL and OE
low). This latched external byte corresponds to the count
in the inhibited internal latch. The cascade pulse that oc-
curs during the clock cycle when the read begins gets
counted by the external counter and is not lost.
For example, suppose the HCTL-2032 / 2032-SC count is
at FFFFFFFFh and an external counter is at F0h, with the
count going up. A count occurring in the HCTL-2032 /
2032-SC will cause the counter to roll over and a cascade
pulse will be generated. A read starting on this clock cy-
cle will show FFFFFFFFh from the HCTL-2032 / 2032-SC.
The external latch should read F0h, but if the host latches
the count after the cascade signal propagates through,
the external latch will read F1h.
FFFFFFFDh FFFFFFFEh FFFFFFFh 00000000h FFFFFFFEh FFFFFFFhCOUNT
CNT cas
CNT DCDR
U/Dbar
CHB FLT
CHA FLT
CLK
Figure 16. Decode and Casade Output Diagram (4x)
18
Interfacing the HCTL-2032 to an Atmel AVR 90S8535
The circuit shown in Figure 17 shows the connections be-
tween an HCTL-2032 and an Atmel AVR controller. Data
lines D0-D7 are connected to the Atmel AVR bus port.
The 8 MHz oscillators clock the Atmel AVR, whereas the
external 33 MHz oscillators clock the HCTL-2032. Figure
18 illustrates the program that interfaces with an Atmel
AVR 90S8535.
CHBX
CHAX
CHIX
CHBY
CHAY
CHIY
HCTL2032
D0
D1
D2
D3
D4
D5
D6
D7
SEL1
SEL2
EN1
EN2
OE
RSTX
RSTY
X/Y
PB1
AT90S8535
PB2
PC7
PB6
PB3
PB4
PB5
PB0
PA6
PA5
PA3
PA4
PA7
PA0
PA1
PA2
5
4
3
2
1
CHB
VCC
CHA
CHI
GND
+5v
RRR
R= 2.7kOHM
CHB
2
1
3
4
5
VCC
CHA
CHI
GND
RRR
+5v
R= 2.7kOHM
Figure 17. An HCTL-2032-to-Atmel AVR Interface
19
Figure 18. Typical Program for Reading HCTL-2032 with Atmel AVR
Set Portb.4 ‘EN1=1
Reset Portb.5 ‘EN2=0
Reset Portb.6 ‘Select X-axis
Result_new = 0
Result_old_x = 0
Result_old_y = 0
Do
Set Portb.0 ‘Disable OE
Waitms 25
Reset Portb.1 ‘SEL1=0 (MSB)
Set Portb.3 ‘SEL2=1 (MSB)
Reset Portb.0 ‘Enable OE
Gosub Get_hi ‘Get MSB
Set Portb.1 ‘SEL1=1 (2nd Byte)
Set Portb.3 ‘SEL2=1 (2nd Byte)
Gosub Get_2nd ‘Get 2nd Byte
Reset Portb.1 ‘SEL1=0 (3rd Byte)
Reset Portb.3 ‘SEL2=0 (3rd Byte)
Gosub Get_3rd ‘Get 3rd Byte
Set Portb.1 ‘SEL1=1 (LSB)
Reset Portb.3 ‘SEL2=0 (LSB)
Gosub Get_lo ‘Get LSB
Set Portb.0 ‘Disable OE
Waitms 25
Mult = 1
Temp = Result_lo * Mult ‘Assign LSB
Result = Temp
Mult = Mult * 256
Temp = Result_3rd * Mult ‘Assign 3rd Byte
Result = Result + Temp
Mult = Mult * 256
Temp = Result_2nd * Mult ‘Assign 2nd Byte
Result = Result + Temp
Mult = Mult * 256
Temp = Result_hi * Mult ‘Assign MSB
Result = Result + Temp
‘
Result = 32-bits Count Data
‘
Loop
20
Get_hi:
Hi_old = Pina ‘Get current data
Hi_new = Pina ‘Get 2nd Data
If Hi_new = Hi_old Then
Result_hi = Hi_new ‘Get stable data
Return
Else
Goto Get_2nd
End If
Get_2nd:
2nd_old = Pina ‘Get current data
2nd_new = Pina ‘Get 2nd Data
If 2nd_new = 2nd_old Then
Result_2nd = 2nd_new ‘Get stable data
Return
Else
Goto Get_2nd
End If
Get_3rd:
3rd_old = Pina ‘Get current data
3rd_new = Pina ‘Get 2nd Data
If 3rd_new = 3rd_old Then
Result_3rd = 3rd_new ‘Get stable data
Return
Else
Goto Get_3rd
End If
Get_lo:
Lo_old = Pina ‘Get current data
Lo_new = Pina ‘Get 2nd Data
If Lo_new = Lo_old Then
Result_lo = Lo_new ‘Get stable data
Return
Else
Goto Get_lo
End If
Figure 18 Cont. Typical Program for Reading HCTL-2032 with Atmel AVR
21
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-0060EN
AV02-0096EN - January 16, 2007
Actions
1. At rst, Port B4, B5, and B6 are setup for 4X encoding
and X/Y axis selection.
2. The HCTL-2032 detects that OE/ are low on the next
falling edge of the CLK and asserts the internal inhibit
signal. Data can be read without regard for the phase
of the CLK.
3. SEL1 and SEL2 are setup to select the appropriate
bytes. The “Get_hi” subroutine is called and the data is
read into the AVR.
4. Step 3 is repeated by changing the SEL1 and SEL2
combinations and specic subroutine is called to read
in the appropriate data.
5. The HCTL-2032 detects OE/ high on the next falling
edge of the CLK. The program set OE/ high by writing
the correct value to the respective Port. This causes
the data lines to be tristated. On the next rising CLK
edge new data is transferred from the counter to the
position data latch.
6. For displaying purposes, the data is arranged in 32-
bit data by shifting the MSB to the left through
multiplication.
Ordering Information
HCTL - 20 XX - XX
32-PDIP PackageBlank32
32-SOIC PackageSC32
20-PDIP PackageBlank22
32-SOIC Package in Tape and Reel (1000 Pcs / Reel)SCT32