November 2012
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
FR014H5JZ (14m, -30V)
High-Side Reverse Bias / Reverse Polarity Protector
With Integrated Over Voltage Transient Suppression
Features
Up to -30V Reverse-Bias Protection
Nano Seconds of Reverse-Bias Blocking
Response Time
+32V 24-Hour “Withstand” Rating
14m Typical Series Resistance at 5V
Integrated TVS Over Voltage Suppression
MLP 3.3x3.3 Package Size
RoHs Compliant
USB Tested and Compatible
Applications
USB 1.0, 2.0 and 3.0 Devices
USB Charging
Mobile Devices
Mobile Medical
POS Systems
Toys
Any DC Barrel Jack Powered Device
Any DC Devices subject to Negative Hot Plug or
Inductive Transients
Automotive Peripherals
Description
Reverse bias is an increasingly common fault event that
may be generated by user error, improperly installed
batteries, automotive environments, erroneous
connections to third-party chargers, negative “hot plug”
transients, inductive transients, and readily available
negatively biased rouge USB chargers.
Fairchild circuit protection is proud to offer a new type of
reverse bias protection devices. The FR devices are low
resistance, series switches that, in the event of a
reverse bias condition, shut off power and block the
negative voltage to help protect downstream circuits.
The FR devices are optimized for the application to offer
best in class reverse bias protection and voltage
capabilities while minimizing size, series voltage drop,
and normal operating power consumption.
In the event of a reverse bias application, FR014H5JZ
devices effectively provide a full voltage block and can
easily protect -0.3V rated silicon.
From a power perspective, in normal bias, a 14m FR
device in a 1.5A application will generate only 21mV of
voltage drop or 32mW of power loss. In reverse bias,
FR devices dissipate less then 20µW in a 16V reverse
bias event. This type of performance is not possible with
a diode solution.
Benefits extend beyond the device. Due to low power
dissipation, not only is the device small, but heat sinking
requirements and cost can be minimized as well.
Ordering Information
Part Number Top Mark Package Packing Method
FR014H5JZ 14H 8-Lead, Molded Leadless Package (MLP),
Dual, 3.3mm Square
3000 on Tape & Reel;
13-inch Reel, 12mm Tape
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 2
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Diagrams
CTL
NEGPOS
Startup Diode
Inrush Reducer
OV Bypass
Protection
Power
Switch
USB Device
Circuit
Power Source
(USB Connector)
FR014H5JZ
NEGPOS
CTL
V
IN
Protected USB Device Circuit
IIN
Figure 1. Block Diagram Figure 2. Typical Schematic
Pin Configuration
Figure 3. Pin Assignments
Pin Definitions
Name Pin Description
POS 5, 6, 7, 8 The positive terminal of the power source. Current flows into this pin during normal
operation.
CTL 4
The control pin of the device. A negative voltage to the POS pin turns the switch on and a
positive voltage turns the switch to a high-impedance state.
NEG 1, 2, 3 The positive terminal of the load circuit to be protected. Current flows out of this pin during
normal operation.
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 3
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Absolute Maximum Ratings
Values are at TA=25°C unless otherwise noted.
Symbol Parameter Value Unit
V+ MAX_OP Steady-State Normal Operating Voltage between POS and CTL Pins
(VIN = V+ MAX_OP, IIN = 1.5A, Switch On) +25
V
V+ 24 24-Hour Normal Operating Voltage Withstand Capability between POS
and CTL Pins (VIN = V+ 24, IIN = 1.5A, Switch On) (1) +32
V- MAX_OP Steady-State Reverse Bias Standoff Voltage between POS and CTL Pins
(VIN = V- MAX_OP) -30
IIN Input Current VIN = 5V, Continuous(2) (see Figur e 4) 8 A
TJ Operating Junction Temperature 150 °C
PD Power Dissipation TC = 25°C 36 W
TA = 25°C(2) (see Figure 4) 2.3
IDIODE_CONT Steady-State Diode Continuous Forward Current from POS to NEG(2)
(see Figure 4) 2
A
IDIODE_PULSE Pulsed Diode Forward Current from POS to NEG (300µs Pulse) (2) (see
Figure 5) 450
ESD
Electrostatic
Discharge
Capability
Human Body Model, JESD22-A114 8
kV
Charged Device Model, JESD22-C101 2
System Model,
IEC61000-4-2
NEG is shorted to CTL
and connected to GND
Contact 8
Air 15
No external connection
between NEG and CTL
Contact 3
Air 4
Notes:
1. The V+24 rating is NOT a survival guarantee. It is a statistically calculated survivability reference point taken on
qualification devices, where the predicted failure rate is less than 0.01% at the specified voltage for 24 hours. It is
intended to indicate the device’s ability to withstand transient events that exceed the recommended operating
voltage rating. Specification is based on qualification devices tested using accelerated destructive testing at
higher voltages, as well as production pulse testing at the V+24 level. Production device field life results may vary.
Results are also subject to variation based on implementation, environmental considerations, and circuit
dynamics. Systems should never be designed with the intent to normally operate at V+24 levels. Contact Fairchild
Semiconductor for additional information.
2. The device power dissipation and thermal resistance (R) are characterized with device mounted on the following
FR4 printed circuit boards, as shown in Figure 4 and Figure 5
Figure 4. 1 Square Inch of 2-ounce copper Figure 5. Minimum Pads of 2-ounce Copper
Thermal Characteristics
Symbol Parameter Value Unit
RJC Thermal Resistance, Junction to Case 3.4 °C/W
RJA Thermal Resistance, Junction to Ambient(2) (see Figure 4) 50
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 4
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Electrical Characteristics
Values are at TA = 25°C unless otherwise noted.
Symbol Parameter Conditions Min. Typ. Max. Unit
Positive Bias Characteristics
RON Device Resistance, Switch On
VIN = +4V, IIN = 1.5A 18 23
m
VIN = +5V, IIN = 1.5A 14 19
VIN = +5V, IIN = 1.5A,
TJ = 125°C 20
VIN = +12V, IIN = 1.5A 11 14
VON
Input Voltage, VIN, at which Voltage
at POS, VPOS, Reaches a Certain
Level at Given Current IIN = 100mA, VPOS - VNEG =
50mV, VCTL = 0V
2.0 2.4 3.0 V
VON / TJ Temperature Coefficient of VON -3.52 mV/°C
VF Diode Forward Voltage VCTL = VNEG, IDIODE = 0.1A,
Pulse width < 300µs 0.57 0.63 0.70 V
IBIAS Bias Current Flowing into POS Pin
during Normal Bias Operation
VPOS = 5V, VCTL = 0V,
No Load 30 nA
Negative Bias Characteristics
V- MAX_OP Reverse Bias Breakdown Voltage
IIN = -250µA, VCTL = VNEG =0V
-30 V
V- MAX_OP /
TJ
Reverse Bias Breakdown Voltage
Temperature Coefficient 22.5 mV/°C
I- Leakage Current from NEG to POS
in Reverse-Bias Condition
VPOS = -20V,
VCTL = VNEG = 0V 1 µA
tRN Time to Respond to Negative Bias
Condition
VCTL = 5V, VPOS = 0V, CLOAD =
10µF, Reverse Bias Startup
Inrush Current = 0.2A
50 ns
Integrated TVS Performance
VZ Breakdown Voltage @ IT I
T = 1mA, 300µs Pulse 28.5 30 31.2 V
IR Leakage Current from NEG to CTL VNEG = +25V, VCTL = 0V 1.5 10 µA
VNEG = -25V, VCTL = 0V -1.5 -10
IPPM
Max Pulse
Current from
NEG to CTL IEC61000-4-5
8x20µs pulse
VNEG > VCTL 0.8
A
VNEG < VCTL -0.9
VC
Clamping
Voltage form
NEG to CTL at
IPPM
VNEG > VCTL 34
V
VNEG < VCTL -34
Dynamic Characteristics
CI Input Capacitance between POS
and CTL
VIN = -5V, VCTL = VNEG = 0V, f
= 1MHz
2440
pF CS Switch Capacitance between POS
and NEG 564
CO Output Capacitance between NEG
and CTL 2526
RC Control Internal Resistance 3.6
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 5
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Typical Characteristics
TJ = 25°C unless otherwise specified.
02468101214161820
0
3
6
9
12
15
18
21
24
16V
12V
9V
5V
RON, SWITCH ON-RESISTANCE (mΩ)
IIN, INPUT CURRENT (A)
Input Voltage, VIN = 4V
0.00.30.60.91.21.51.82.1
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VON, MINIMUM INPUT VOLTAGE TURNING
ON THE SWITCH (V)
IIN, INPUT CURRENT (A)
Figure 6. Switch On Resistance vs. Switch Current Figure 7. Minimum Input Voltage to Turn On Switch
vs. Current at 50mV Switch Voltage Drop
13579111315171921
0.0
0.2
0.4
0.6
0.8
1.0
1.5A
0.9A
TJ = 25oC
RSW, EFFECTIVE SWITCH RESISTANCE (Ω)
VIN, INPUT VOLTAGE (V)
IIN = 0.1A
-75 -50 -25 0 25 50 75 100 125 150
0
3
6
9
12
15
18
21
24
IIN = 0.1A
12V
RON, SWITCH ON-RESISTANCE (mΩ)
TJ, JUNCTION TEMPERATURE (oC)
VIN = 5V
Figure 8. Effective Switch Resistance RSW vs.
Input Voltage VIN
Figure 9. Switch On Resistance vs. Junction
Temperature at 0.1A
-75 -50 -25 0 25 50 75 100 125 150
0
3
6
9
12
15
18
21
24
IIN = 1.5A
12V
RON, SWITCH ON-RESISTANCE (mΩ)
TJ, JUNCTION TEMPERATURE (oC)
VIN = 5V
1E-4 1E-3 0.01 0.1 1 10 100 1000
0.1
1
10
100
1000
PEAK PACKAGE POWER (W)
t, PULSE WIDTH (s)
Figure 10. Switch On Resistance vs. Junction
Temperature at 1.5A
Figure 11. Single-Pulse Maximum Power vs. Time
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 6
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Typical Characteristics
TJ = 25°C unless otherwise specified.
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
1E-3
0.01
0.1
1
10
100
-55oC
25oC
TJ = 125oC
IF, STARTUP DIODE FORWARD CURRENT (A)
VF, STARTUP DIODE FORWARD VOLTAGE (V)
VNEG = VCTL = 0V
Figure 12. Startup Diode Current vs. Forward Voltage
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 7
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Application Test Configurations
USB Device
Circuit
Power Source
(USB Connector)
FR014H5JZ
NEGPOS
CTL
VIN
Protected USB Device Circuit
I
IN
Figure 13. Typical Application Circuit for USB Applications
Pulse
Generator
DC Power
Supply
C1
C2
R1
R3
R2
Q1-1
FDS8858CZ
Q1-2
FDS8858CZ
i
IN
FR014H5JZ
NEG
POS
CTL
4 G2
1 S1
3 S2
5,6
D2
2 G1
7,8 D1
Figure 14. Startup Test Circuit – Normal Bias with FR014H5JZ
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 8
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Application Test Configurations (Continued)
C1 C2
R1
R3
R2
Q1-1
FDS8858CZ
Q1-2
FDS8858CZ
DC Power
Supply
Pulse
Generator
i
IN
FR014H5JZ
NEGPOS
CTL
4 G2
1 S1
3 S2 5,6 D2
2 G1
7,8 D1
Figure 15. Startup Test Circuit – Reverse Bias with FR014H5JZ
Pulse
Generator
DC Power
Supply
C1
C2
R1
R3
R2
Q1-1
FDS8858CZ
Q1-2
FDS8858CZ
i
IN
4 G2
1 S1
3 S2
5,6 D2
2 G1
7,8 D1
Figure 16. Startup Test Circuit – without FR014H5JZ
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 9
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Typical Application Waveforms
Typical USB3.0 conditions.
Figure 17. Normal Bias Startup Waveform, DC Power Source=5V, C1=100µF, C2=10µF, R1=R2=10k, R3=27
Figure 18. Reverse Bias Startup Waveform, DC Power Source=5V, C1=100µF, C2=10µF, R1=R2=10k, R3=27
VIN, 2V/div. The input voltage between POS and CTL
VOUT, 2V/div. The output voltage between NEG and CTL
VD, 1V/div. The startup diode voltage between POS and NEG
iIN, 5A/div. The input current flowing from POS to NEG
Time: 5
µ
s/div
VIN, 2V/div. The input voltage between POS and CTL
VD, 2V/div. The startup diode voltage between POS and NEG
VOUT, 1V/div. The output voltage between NEG and CTL
iIN, 0.1A/div. The input current flowing into POS
Time: 100ns/div
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FR014H5JZ • Rev. C2 10
FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression
Typical Application Waveforms (Continued)
Typical USB3.0 conditions.
Figure 19. Startup Waveform without FR014H5JZ, DC Power Source=5V, C1=100µF, C2=10uF,
R1=R2=10k, R3=27
Application Information
Figure 17 shows the voltage and current waveforms
when a virtual USB3.0 device is connected to a 5V
source. A USB application allows a maximum source
output capacitance of C1 = 120µF and a maximum
device-side input capacitance of C2 = 10µF plus a
maximum load (minimum resistance) of R3 = 27. C1 =
100µF, C2 = 10µF and R3 = 27 were used for testing.
When the DC power source is connected to the circuit
(refer to Figure 13), the built-in startup diode initially
conducts the current such that the USB device powers
up. Due to the initial diode voltage drop, the FR014H5JZ
effectively reduces the peak inrush current of a hot plug
event. Under these test conditions, the input inrush
current reaches about 6A peak. While the current flows,
the input voltage increases. The speed of this input
voltage increase depends on the time constant formed
by the load resistance R3 and load capacitance C2. The
larger the time constant, the slower the input voltage
increase. As the input voltage approaches a level equal
to the protector’s turn-on voltage, VON, the protector
turns on and operates in Low-Resistance Mode as
defined by VIN and operating current IIN.
In the event of a negative transient, or when the DC
power source is reversely connected to the circuit, the
device blocks the flow of current and holds off the
voltage, thereby protecting the USB device. Figure 18
shows the voltage and current waveforms when a virtual
USB3.0 device is reversely biased; the output voltage is
near 0 and response time is less than 50ns.
Figure 19 shows the voltage and current waveforms
when no reverse bias protection is implemented. In
Figure 17, while the reverse bias protector is present,
the input voltage, VIN, and the output voltage, VO, are
separated and look different. When this reverse bias
protector is removed, VIN and VO merge, as shown in
Figure 19 as VIN. This VIN is also the voltage applied to
the load circuit. It can be seen that, with reverse bias
protection, the voltage applied to the load and the
current flowing into the load look very much the same as
without reverse bias protection.
Benefits of Reverse Bias Protection
The most important benefit is to prevent accidently
reverse-biased voltage from damaging the USB load.
Another benefit is that the peak startup inrush current
can be reduced. How fast the input voltage rises, the
input/output capacitance, the input voltage, and how
heavy the load is determine how much the inrush
current can be reduced. In a 5V USB application, for
example, the inrush current can be 5% - 20% less with
different input voltage rising rate and other factors. This
can offer a system designer the option of increasing C2
while keeping “effective” USB device capacitance down.
VIN, 2V/div. The voltage applied on the load circuit
iIN, 2A/div. The input current
Time: 5
μ
s/div
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Rev. I77
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