FEATURES
APPLICATIONS
DESCRIPTION
PCM1850A
PCM1851A
SLES173 – MARCH 2006
24-BIT, 96-kHz STEREO A/D CONVERTERWITH 6 ×2-CHANNEL MUX AND PGAE
•PCM Audio Interface•Multiplexer and Programmable-Gain Amplifier – Master/Slave Mode Selectable(PGA)
– Data Formats: 24-Bit Left-Justified, 24-Bit– 6 ×2-Channel Single-Ended Inputs I
2
S, 16-, 24-Bit Right-Justified– Multiplexed Output •Mode Control by Serial Interface:– Maximum Input Level: 2.4 V rms – With SPI Control (PCM1850A)– Input Resistance: 50 k Ω, Minimum – With I
2
C Control (PCM1851A)– PGA Gain: 11-dB to –11-dB Range, 0.5 •Sampling Rate: 16–96 kHzdB/Step
•System Clock: 256 f
s
, 384 f
s
, 512 f
s
, 768 f
s•24-Bit Delta-Sigma Stereo A/D Converter
•Dual Power Supplies: 5 V for Analog, 3.3 V for•Antialiasing Filter Included Digital•Oversampling Decimation Filter •Package: 32-Pin TQFP– Oversampling Frequency: ×64– Pass-Band Ripple: ±0.05 dB
•DVD/HDD/DVD+HDD Recorder– Stop-Band Attenuation: –65 dB
•AV Amplifier Receiver– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)
•CD Recorder•High Performance
•MD Recorder– THD+N: 0.0023% (Typically)
•Multitrack Recorder– SNR: 101 dB (Typically)
•Electric Musical Instrument– Dynamic Range: 102 dB (Typically)
The PCM1850A/1851A is a high-performance, low-cost, single-chip stereo analog-to-digital converter with asingle-ended analog front end that consists of a 6-stereo-input multiplexer and wide-range PGA. ThePCM1850A/1851A includes a delta-sigma modulator with 64-times oversampling, a digital decimation filter and alow-cut filter that removes the dc component of the input signal. For various applications, the PCM1850A/1851Asupports two modes (master and slave) and four data formats through a serial control interface, SPI for thePCM1850A and I
2
C for the PCM1851A. The PCM1850A/1851A is suitable for a wide variety of cost-sensitiveDVD/CD/MD recorder and receiver applications where good performance and operation from a 5-V analogsupply and 3.3-V digital supply is required. The PCM1850A/1851A is fabricated using a highly advanced CMOSprocess and is available in a small 32-pin TQFP package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.System Two, Audio Precision are trademarks of Audio Precision, Inc.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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BLOCK DIAGRAM
Single-Ended
MUX and PGA
BCK
VINL1
Reference
VREF1
VREF2
Delta-Sigma
Modulator
Decimation
Filter
with
High-Pass Filter
Power Supply
AGNDVCC VDD
DGND
Clock and Timing Control
Audio
Data
Interface
Control
Data
Interface
LRCK
DOUT
OVER
TEST0
TEST1
RST
SCKI
VINL2
VINL3
VINL4
VINL5
VINL6
MOUTL
Single-Ended
MUX and PGA
VINR1
Delta-Sigma
Modulator
VINR2
VINR3
VINR4
VINR5
VINR6
MOUTR
VREFS
MS (ADR)(1)
MD (SDA)(1)
MC (SCL)(1)
(1) PCM1850A (PCM1851A) B0004-09
PIN ASSIGNMENTS
PCM1850A
(TOP VIEW)
23 22 21 20 19
1 2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VINR2
VINL2
VINR1
VINL1
MOUTL
MOUTR
RST
TEST1
VREFS
VREF1
VREF2
Vcc
AGND
MS
MC
MD
24 18
345678
17
VINR6
VINL6
VINR5
VINL5
VINR4
VINL4
VINR3
VINL3
LRCK
BCK
DOUT
OVER
DGND
VDD
SCKI
TEST0
PCM1851A
(TOP VIEW)
23 22 21 20 19
1 2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VINR2
VINL2
VINR1
VINL1
MOUTL
MOUTR
RST
TEST1
VREFS
VREF1
VREF2
Vcc
AGND
ADR
SCL
SDA
24 18
345678
17
VINR6
VINL6
VINR5
VINL5
VINR4
VINL4
VINR3
VINL3
LRCK
BCK
DOUT
OVER
DGND
VDD
SCKI
TEST0
P0040-01
PCM1850A
PCM1851A
SLES173 – MARCH 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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TERMINAL FUNCTIONS
PCM1850A
PCM1851A
SLES173 – MARCH 2006
PCM1850A
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 29 — Analog GNDBCK 2 I/O Bit clock input/output
(1)
DGND 5 — Digital GNDDOUT 3 O Audio data outputLRCK 1 I/O Sampling clock input/output
(1)
MC 31 I Mode-control clock input
(2)
MD 32 I Mode-control data input
(2)
MOUTL 12 O Multiplexer output, L-channelMOUTR 11 O Multiplexer output, R-channelMS 30 I Mode-control select input
(3)
OVER 4 O Overflow flagRST 10 I Reset, active-LOW
(3)
SCKI 7 I System clock input; 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
(2)
TEST0 8 I Test 0, must be connected to GND
(3)
TEST1 9 I Test 1, must be connected to GND
(3)
V
CC
28 — Analog power supply, 5-VV
DD
6 — Digital power supply, 3.3-VV
IN
L1 13 I Analog input 1, L-channelV
IN
L2 15 I Analog input 2, L-channelV
IN
L3 17 I Analog input 3, L-channelV
IN
L4 19 I Analog input 4, L-channelV
IN
L5 21 I Analog input 5, L-channelV
IN
L6 23 I Analog input 6, L-channelV
IN
R1 14 I Analog input 1, R-channelV
IN
R2 16 I Analog input 2, R-channelV
IN
R3 18 I Analog input 3, R-channelV
IN
R4 20 I Analog input 4, R-channelV
IN
R5 22 I Analog input 5, R-channelV
IN
R6 24 I Analog input 6, R-channelV
REF
S 25 — Reference S decoupling capacitor (= 0.5 V
CC
)V
REF
1 26 — Reference 1 decoupling capacitor (= 0.5 V
CC
)V
REF
2 27 — Reference 2 decoupling capacitor (= V
CC
)
(1) Schmitt-trigger input with internal pulldown resistor (50 k Ω, typically)(2) Schmitt-trigger input, 5-V tolerant(3) Schmitt-trigger input with internal pulldown resistor (50 k Ω, typically), 5-V tolerant
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PCM1850A
PCM1851A
SLES173 – MARCH 2006
PCM1851A
TERMINAL
I/O DESCRIPTIONNAME NO.
ADR 30 I Mode control address select input
(1)
AGND 29 — Analog GNDBCK 2 I/O Bit clock input/output
(2)
DGND 5 — Digital GNDDOUT 3 O Audio data outputLRCK 1 I/O Sampling clock input/output
(2)
MOUTL 12 O Multiplexer output, L-channelMOUTR 11 O Multiplexer output, R-channelOVER 4 O Overflow flagRST 10 I Reset, active-LOW
(1)
SCKI 7 I System clock input; 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
(3)
SCL 31 I Mode-control clock input
(3)
SDA 32 I/O Mode-control data input/output
(4)
TEST0 8 I Test 0, must be connected to GND
(1)
TEST1 9 I Test 1, must be connected to GND
(1)
V
CC
28 — Analog power supply, 5-VV
DD
6 — Digital power supply, 3.3-VV
IN
L1 13 I Analog input 1, L-channelV
IN
L2 15 I Analog input 2, L-channelV
IN
L3 17 I Analog input 3, L-channelV
IN
L4 19 I Analog input 4, L-channelV
IN
L5 21 I Analog input 5, L-channelV
IN
L6 23 I Analog input 6, L-channelV
IN
R1 14 I Analog input 1, R-channelV
IN
R2 16 I Analog input 2, R-channelV
IN
R3 18 I Analog input 3, R-channelV
IN
R4 20 I Analog input 4, R-channelV
IN
R5 22 I Analog input 5, R-channelV
IN
R6 24 I Analog input 6, R-channelV
REF
S 25 — Reference S decoupling capacitor (= 0.5 V
CC
)V
REF
1 26 — Reference 1 decoupling capacitor (= 0.5 V
CC
)V
REF
2 27 — Reference 2 decoupling capacitor (= V
CC
)
(1) Schmitt-trigger input with internal pulldown resistor (50 k Ω, typically), 5-V tolerant(2) Schmitt-trigger input with internal pulldown resistor (50 k Ω, typically)(3) Schmitt-trigger input, 5-V tolerant(4) Schmitt-trigger input/open-drain LOW output, 5-V tolerant
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
PCM1850A
PCM1851A
SLES173 – MARCH 2006
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
V
CC
–0.3 to 6.5 VSupply voltageV
DD
–0.3 to 4 VGround voltage differences: AGND, DGND ±0.1 VDigital input voltage: LRCK, BCK, DOUT, OVER –0.3 to (V
DD
+ 0.3) < 4 VDigital input voltage: RST, SCKI, MS (ADR)
(2)
, MC (SCL)
(2)
, MD (SDA)
(2)
, TEST0, TEST1 –0.3 to 6.5 VAnalog input voltage: V
IN
L1–6, V
IN
R1–6 –3 to (V
CC
+ 3) < 9 VAnalog input voltage: MOUTL, MOUTR, V
REF
1, V
REF
2, V
REF
S –0.3 to (V
CC
+ 0.3) < 6.5 VInput current (any pins except supplies) ±10 mAAmbient temperature under bias –40 to 125 °CStorage temperature –55 to 150 °CJunction temperature 150 °CLead temperature (soldering) 260 °C, 5 sPackage temperature (IR reflow, peak) 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) PCM1850A (PCM1851A)
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Analog supply voltage 4.5 5 5.5 VV
DD
Digital supply voltage 2.7 3.3 3.6 VAnalog input voltage, full scale (0 V
CC
= 5 V, PGA gain = 5.5 dB 2 VrmsdB)
Digital input logic family TTLSystem clock 4.096 49.152 MHzDigital input clock frequency
Sampling clock 16 96 kHzDigital output load capacitance 20 pFT
A
Operating free-air temperature 40 85 °C
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted)
PCM1850APJT, PCM1851APJTPARAMETER TEST CONDITIONS UNITMIN TYP MAX
DIGITAL INPUT/OUTPUT — DATA FORMAT
Audio data interface format Left-justified, I
2
S, right-justifiedAudio data bit length 16, 24 bitsAudio data format MSB-first, 2s complementf
S
Sampling frequency 16 48 96 kHz256 f
S
4.096 12.288 24.576384 f
S
6.144 18.432 36.864System clock frequency MHz512 f
S
8.192 24.576 49.152768 f
S
12.288 36.864 –
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ELECTRICAL CHARACTERISTICS (continued)
PCM1850A
PCM1851A
SLES173 – MARCH 2006
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted)
PCM1850APJT, PCM1851APJTPARAMETER TEST CONDITIONS UNITMIN TYP MAX
INPUT LOGIC
V
IH
(1)
2 V
DD
V
IL
(1)
0 0.8Input logic level VDCV
IH
(2) (3)
2 5.5V
IL
(2) (3)
0 0.8I
IH
(2)
V
IN
= V
DD
±10I
IL
(2)
V
IN
= 0 ±10Input logic current µAI
IH
(1) (3)
V
IN
= V
DD
65 100I
IL
(1) (3)
V
IN
= 0 ±10
OUTPUT LOGIC
V
OH
(4)
I
OUT
= –4 mA 2.8Output logic level VDCV
OL
(4) (5)
I
OUT
= 4 mA 0.5
AFE MULTPLEXER
Input channels 6Input level for full scale 2 2.4 VrmsCenter voltage (V
REF
1) Selected channel 0.5 V
CC
VCenter voltage (V
REF
S) Unselected channel 0.5 V
CC
VSelected channel 50 169Input impedance k ΩUnselected channel 50 57
AFE PGA
Gain range –11 0 11 dBGain step 0.5 dBMonotonicity SpecifiedAntialiasing filter frequency 300 kHz–3 dB, PGA gain = –5.5 dBresponse
MONITOR OUTPUT
Output level for full scale AC-coupled, >10 k Ω0.6 V
CC
Vp-pOutput load AC-coupled 10 k ΩTHD+N
(6) (7)
AC-coupled, 10 k Ω, 3 Vp-p output 0.0016%S/N Signal-to-noise ratio
(6) (7)
AC-coupled, 10 k Ω104 dBGain error
(6) (7)
AC-coupled, 10 k Ω–3 % of FSRCenter voltage 0.5 V
CC
V
ADC
Resolution 24 bitsFull-scale input voltage 0.6 V
CC
Vp-p
(1) Pins 1, 2: LRCK, BCK (In slave mode, Schmitt-trigger input, with 50-k Ωtypical pulldown resistor)(2) Pins 7, 31, 32: SCKI, MC/SCL (PCM1850A/1851A), MD/SDA (PCM1850A/1851A) (Schmitt-trigger input, 5-V tolerant)(3) Pins 8–10, 30: TEST0, TEST1, RST, MS/ADR (PCM1850A/1851A) (Schmitt-trigger input, with 50-k Ωtypical pulldown resistor, 5-Vtolerant)
(4) Pins 1–4: LRCK, BCK (in master mode), DOUT, OVER(5) Pin 32: SDA (PCM1851A) (open-drain LOW output)(6) Analog performance specifications are tested with the System Two™ audio measurement system by Audio Precision™, using a 400-HzHPF and 20-kHz LPF in the RMS mode at f
IN
= 1 kHz.(7) Reference level (0 dB) is specified as 2-V rms input on V
IN
L[1:6] and V
IN
R[1:6] pins with PGA gain of –5.5 dB.
6
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ELECTRICAL CHARACTERISTICS (continued)
PCM1850A
PCM1851A
SLES173 – MARCH 2006
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted)
PCM1850APJT, PCM1851APJTPARAMETER TEST CONDITIONS UNITMIN TYP MAX
ACCURACY
Gain mismatch, ±1±3 % of FSRchannel-to-channel
Gain error ±2±5 % of FSRBipolar zero error High-pass filter bypass ±2 % of FSR
DYANAMIC PERFORMANCE
(1) (2)
f
S
= 48 kHz, V
IN
= –0.5 dB (1.89 Vrms) 0.0023% 0.004%f
S
= 96 kHz
(4)
,
0.0027%Total harmonic distortion +
V
IN
= –0.5 dB (1.89 Vrms)THD+N
noise
(3)
f
S
= 48 kHz, V
IN
= –60 dB (2 mVrms) 1%f
S
= 96 kHz
(4)
, V
IN
= –60 dB (2 mVrms) 1%f
S
= 48 kHz, A-weighted 96 102Dynamic range
(3)
dBf
S
= 96 kHz
(4)
, A-weighted 102f
S
= 48 kHz, A-weighted 96 101S/N Signal-to-noise ratio
(3)
dBf
S
= 96 kHz
(4)
, A-weighted 102f
S
= 48 kHz 92 98Channel separation
dB(between L-ch and R-ch)
(3)
f
S
= 96 kHz
(4)
100f
S
= 48 kHz 90 96Channel separation (among
dBchannels)
(5)
f
S
= 96 kHz
(4)
96
DIGITAL FILTER PERFORMANCE
Pass band 0.454 f
S
HzStop band 0.583 f
S
HzPass-band ripple ±0.05 dBStop-band attenuation –65 dBDelay time 17.4/f
S
sHPF frequency response –3 dB 0.019 f
S
mHz
(1) Analog performance specifications are tested with the System Two™ audio measurement system by Audio Precision™, using a 400-HzHPF and 20-kHz LPF in the RMS mode at f
IN
= 1 kHz.(2) Reference level (0 dB) is specified as 2-V rms input on V
IN
L[1:6] and V
IN
R[1:6] pins with PGA gain of –5.5 dB.(3) Unselected channel inputs are terminated to AGND with 0.33 µF.(4) f
S
= 96 kHz, system clock = 256 f
S
.(5) 2-V rms input is applied to all unselected channels, and input of selected channel is terminated to AGND with 0.33 µF.
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ELECTRICAL CHARACTERISTICS (continued)
PCM1850A
PCM1851A
SLES173 – MARCH 2006
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted)
PCM1850APJT, PCM1851APJTPARAMETER TEST CONDITIONS UNITMIN TYP MAX
POWER-SUPPLY REQUIREMENTS
V
CC
4.5 5 5.5Voltage range VDCV
DD
2.7 3.3 3.6Operational 28 35 mAI
CC
Powered down
(2)
190 µAf
S
= 48 kHz 6 10Supply current
(1)
mAf
S
= 96 kHz
(3)
12I
DD
Powered down
(2)
, PCM1850A 80
µAPowered down
(2)
, PCM1851A 280Operating, f
S
= 48 kHz 160 208Operating, f
S
= 96 kHz
(3)
180Power dissipation mWPowered down
(2)
, PCM1850A 1.2Powered down
(2)
, PCM1851A 1.9
TEMPERATURE RANGE
Operation temperature –40 85 °CThermal resistance ( θ
JA
) 80 °C/W
(1) Minimum load on DOUT (pin 3), BCK (pin 2), LRCK (pin 1)(2) Halt SCKI, BCK, LRCK.(3) f
S
= 96 kHz, system clock = 256 f
S
.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
DIGITAL FILTER
Decimation Filter Frequency Response
−200
−150
−100
−50
0
50
0 8 16 24 32
Frequency [× fS]
Amplitude – dB
G001
Frequency [× fS]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.00 0.25 0.50 0.75 1.00
Amplitude – dB
G002
Frequency [× fS]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Amplitude – dB
G003
Frequency [× fS]
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0.45 0.47 0.49 0.51 0.53 0.55
Amplitude − dB
–4.13 dB at 0.5×
G004
PCM1850A
PCM1851A
SLES173 – MARCH 2006
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted).
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 1. Overall Characteristics Figure 2. Stop-Band Attenuation Characteristics
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 3. Pass-Band Ripple Characteristics Figure 4. Transition-Band Characteristics
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High-Pass Filter Frequency Response
Frequency [× fS/1000]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0 1 2 3 4
Amplitude – dB
G005
Frequency [× fS/1000]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.0 0.1 0.2 0.3 0.4
Amplitude – dB
G006
ANALOG FILTER
Antialiasing Filter Frequency Response (at PGA Gain = –5.5 dB)
−6.5
−6.4
−6.3
−6.2
−6.1
−6.0
−5.9
−5.8
−5.7
−5.6
−5.5
f – Frequency – kHz
Amplitude – dB
0.1 1 10 1k100
G007
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
f – Frequency – kHz
Amplitude – dB
110 100 10k1k
f–3dB = 300 kHz
G008
PCM1850A
PCM1851A
SLES173 – MARCH 2006
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted).
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 5. HPF Pass-Band Characteristics Figure 6. HPF Stop-Band Characteristics
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 7. Antialiasing Filter Pass-Band Figure 8. Antialiasing Filter Stop-BandCharacteritics Characteritics
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TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB
97
98
99
100
101
102
103
104
105
106
107
−40 −15 10 35 60 85
TA – Free-Air Temperature – °C
Dynamic Range and SNR – dB
SNR
Dynamic Range
G010
TA – Free-Air Temperature – °C
THD+N – Total Harmonic Distortion + Noise – %
0.001
0.002
0.003
0.004
−40 −15 10 35 60 85
G009
97
98
99
100
101
102
103
104
105
106
107
4.5 4.7 4.9 5.1 5.3 5.5
VCC – Supply V oltage – V
Dynamic Range and SNR – dB
SNR
Dynamic Range
G012
0.001
0.002
0.003
0.004
4.5 4.7 4.9 5.1 5.3 5.5
VCC – Supply V oltage – V
THD+N – Total Harmonic Distortion + Noise – %
G011
PCM1850A
PCM1851A
SLES173 – MARCH 2006
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted).
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SNRvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 9. Figure 10.
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SNRvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 11. Figure 12.
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97
98
99
100
101
102
103
104
105
106
107
16 36 56 76 96
Dynamic Range and SNR – dB
SNR
Dynamic Range
fSAMPLE Condition – kHz G014
0.001
0.002
0.003
0.004
16 36 56 76 96
fSAMPLE Condition – kHz
THD+N – Total Harmonic Distortion + Noise – %
G013
OUTPUT SPECTRUM
f – Frequency – kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
Amplitude – dB
Input Level = –60 dB
Data Points = 8192
G015
f – Frequency – kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
Input Level = –0.5 dB
Data Points = 8192
Amplitude – dB
G016
PCM1850A
PCM1851A
SLES173 – MARCH 2006
TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB (continued)All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted).
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SNRvs vsf
SAMPLE
CONDITION f
SAMPLE
CONDITION
Figure 13. Figure 14.
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 15. Figure 16.
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−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
Signal Level – dB
THD+N – Total Harmonic Distortion + Noise – %
100
1
0.1
0.01
0.001
10
G017
SUPPLY CURRENT PGA GAIN LINEARITY
0
5
10
15
20
25
30
16 36 56 76 96
ICC and IDD – Supply Current – mA
ICC
fSAMPLE Condition – kHz
IDD
G018
Gain Setting – dB
−11
−9
−7
−5
−3
−1
1
3
5
7
9
11
−11 −9 −7 −5 −3 −1 1 3 5 7 9 11
Overall Gain – dB
G019
PCM1850A
PCM1851A
SLES173 – MARCH 2006
TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB (continued)All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unlessotherwise noted).
TOTAL HARMONIC DISTORTION + NOISEvsSIGNAL LEVEL
Figure 17.
SUPPLY CURRENT OVERALL GAINvs vsf
SAMPLE
CONDITION GAIN SETTING
Figure 18. Figure 19.
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DETAILED DESCRIPTION
SYSTEM CLOCK
t(SCKH)
SCKI
t(SCKL)
2 V
0.8 V
H
L
T0005-11
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The PCM1850A/1851A supports 256 f
S
, 384 f
S
, 512 f
S
, and 768 f
S
as the system clock, where f
S
is the audiosampling frequency. The system clock must be supplied on SCKI (pin 7).
The PCM1850A/1851A has a system clock detection circuit which automatically senses if the system clock isoperating at 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
in slave mode. In master mode, the system clock frequency must beselected by mode control via the serial port. The 768-f
S
system clock is not available in master mode or for f
S
=88.2 kHz and 96 kHz in the slave mode. The system clock is divided into 128 f
S
and 64 f
S
automatically, andthese frequencies are used to operate the digital filter and the delta-sigma modulator, respectively.
Table 1 shows the relationship of typical sampling frequency to system clock frequency, and Figure 20 showssystem clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SYSTEM CLOCK FREQUENCY (MHz)SAMPLING RATE FREQUENCY
(kHz)
256 f
S
384 f
S
512 f
S
768 f
S
(1)
32 8.192 12.288 16.384 24.57644.1 11.2896 16.9344 22.5792 33.868848 12.288 18.432 24.576 36.86464 16.384 24.576 32.768 49.15288.2 22.5792 33.8688 45.1584 —96 24.576 36.864 49.152 —
(1) Slave mode only
SYMBOL PARAMETER MIN MAX UNIT
t
(SCKH)
System clock pulse duration, HIGH 8 nst
(SCKL)
System clock pulse duration, LOW 8 ns
Figure 20. System Clock Timing
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POWER-ON-RESET SEQUENCE
System Clock
2.6 V
2.2 V
1.8 V
Internal Reset
DOUT Zero Data Normal Data
Reset
VDD
Release From Reset
1024 System Clocks 4500/fS
T0014-10
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The PCM1850A/1851A has an internal power-on-reset circuit, and initialization (reset) is performed automaticallyat the time that the power supply (V
DD
) exceeds 2.2 V (typical). While V
DD
< 2.2 V (typical) and for 1024 systemclocks after V
DD
> 2.2 V (typical), the PCM1850A/1851A stays in the reset state and the digital output is forced tozero. The digital output is valid after the reset state is released and the time of 4500/f
S
has passed. At themoment of the power-on-reset release, the PCM1850A/1851A does not need a system clock. Figure 21illustrates the internal power-on-reset timing and the digital output for power-on reset.
Figure 21. Internal Power-On-Reset Timing
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ANALOG FRONT END
PGA
(11 dB to –1 1 dB)
with MUX G = –1
VREFS
(= 0.5 VCC)
LIN+
RVINL1
RVINL6
RVINL2
VREF1
(= 0.5 VCC)
R
R
MOUTL
LIN–
B0131−01
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The PCM1850A/1851A has a built-in analog front-end circuit, which is shown in the block diagram of Figure 22 .Selection of the multiplexer input and PGA gain is controlled by mode control via the serial port as shown inTable 2 and Table 3 . The change of the input selection and the gain selection is performed immediately after theserial control packet for the change is sent. A popping noise or other unexpected transient response could begenerated in the audio signal during channel and gain change. Because the PCM1850A/1851A has nozero-cross detection and no other buffering capability for channel and gain change, appropriate data handling inthe digital domain is recommended to control transients.
The PCM1850A/1851A analog front end permits only ac input via an input capacitor; dc input is prohibited. Asignal source resistance of less than 1 k Ωis recommended for the V
IN
xx pins.
All unselected channel inputs are terminated V
REF
S (= 0.5 V
CC
) using a resistor, typically 57 k Ω.
The PCM1850A/1851A employs MOUTL/R pins (pins 12 and 11) to monitor the multiplexer output. The load onthese pins must be ac-coupled and not less than 10 k Ω. The full-scale output level is typically 0.6 V
CC
.
Figure 22. Analog Front-End Block Diagram (L-Channel)
Table 2. Multiplexer Input Selection
CH2 CH1 CH0 CHANNEL
0 0 0 Mute0 0 1 Channel 1 (default)0 1 0 Channel 20 1 1 Channel 31 0 0 Channel 41 0 1 Channel 51 1 0 Channel 61 1 1 Mute
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PCM1850A
PCM1851A
SLES173 – MARCH 2006
Table 3. PGA Gain Selection
PG5 PG4 PG3 PG2 PG1 PG0 PGA GAIN [dB] R
IN
[k Ω, Typical]
(1)
0 0 1 0 1 0 –11 (default) 2010 0 1 0 1 1 –10.5 1990 0 1 1 0 0 –10 1960 0 1 1 0 1 –9.5 1930 0 1 1 1 0 –9 1900 0 1 1 1 1 –8.5 1880 1 0 0 0 0 –8 1850 1 0 0 0 1 –7.5 1810 1 0 0 1 0 –7 1780 1 0 0 1 1 –6.5 1750 1 0 1 0 0 –6 1720 1 0 1 0 1 –5.5 1690 1 0 1 1 0 –5 1650 1 0 1 1 1 –4.5 1620 1 1 0 0 0 –4 1580 1 1 0 0 1 –3.5 1550 1 1 0 1 0 –3 1510 1 1 0 1 1 –2.5 1470 1 1 1 0 0 –2 1440 1 1 1 0 1 –1.5 1400 1 1 1 1 0 –1 1360 1 1 1 1 1 –0.5 1331 0 0 0 0 0 0 1291 0 0 0 0 1 0.5 1251 0 0 0 1 0 1 1221 0 0 0 1 1 1.5 1181 0 0 1 0 0 2 1141 0 0 1 0 1 2.5 1111 0 0 1 1 0 3 1071 0 0 1 1 1 3.5 1031 0 1 0 0 0 4 1001 0 1 0 0 1 4.5 961 0 1 0 1 0 5 931 0 1 0 1 1 5.5 891 0 1 1 0 0 6 861 0 1 1 0 1 6.5 831 0 1 1 1 0 7 801 0 1 1 1 1 7.5 771 1 0 0 0 0 8 731 1 0 0 0 1 8.5 701 1 0 0 1 0 9 681 1 0 0 1 1 9.5 651 1 0 1 0 0 10 621 1 0 1 0 1 10.5 591 1 0 1 1 0 11 57
(1) R
IN
(k Ω, typical) = 258/(1 + 10
GAIN/20
)The PCM1850A/1851A becomes mute for PG[5:0] values other than those listed.
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SERIAL AUDIO DATA INTERFACE
Interface Mode
Data Format
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The PCM1850A/1851A interfaces with the audio system through BCK (pin 2), LRCK (pin 1), and DOUT (pin 3).
The PCM1850A/1851A supports both master and slave modes as interface modes, and they are selected bymode control via the serial port as shown in Table 4 .
In master mode, the PCM1850A/1851A provides the timing for serial audio data communications between thePCM1850A/1851A and the digital audio processor or external circuit. While in slave mode, the PCM1850A/1851Areceives the timing for data transfer from an external controller.
Table 4. Interface Mode
MD1 MD0 INTERFACE MODE
0 0 Slave mode (256 f
S
, 384 f
S
, 512 f
S
, 768 f
S
) (default)0 1 Master mode (256 f
S
)1 0 Master mode (384 f
S
)1 1 Master mode (512 f
S
)
Master Mode
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generatedin the clock and timing control circuit of the PCM1850A/1851A. The frequency of BCK is fixed at 64 ×LRCK. A768-f
S
system clock is not available in master mode.
Slave Mode
In slave mode, BCK and LRCK work as input pins. The PCM1850A/1851A accepts the 64 BCK/LRCK or 48BCK/LRCK (only for 384 f
S
SCKI) format. A 768-f
S
system clock is not available for f
S
= 88.2 kHz and 96 kHz inslave mode.
The PCM1850A/1851A supports four audio data formats in both master and slave modes, and they are selectedby mode control via the serial port as shown in Table 5 .Figure 23 illustrates the data formats in both slave andmaster modes.
Table 5. Data Format
FORMAT NO. FMT2 FMT1 FMT0 FORMAT
0 1 0 1 Left-justified, 24-bit1 1 0 0 I
2
S, 24-bit, (default)2 0 0 0 Right-justified, 24-bit3 0 1 1 Right-justified, 16-bit
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24-Bit, MSB-First, Left-Justified
BCK
LRCK Right-ChannelLeft-Channel
DOUT 122 23 24321
MSB LSB
22 23 24321
MSB LSB
FORMAT 0: FMT[2:0] = 101b
FORMAT 1: FMT[2:0] = 100b
FORMAT 2: FMT[2:0] = 000b
FORMAT 3: FMT[2:0] = 011b
24-Bit, MSB-First, I2S
LRCK Right-ChannelLeft-Channel
BCK
DOUT 22 23 24321
MSB LSB
22 23 24321
MSB LSB
24-Bit, MSB-First, Right-Justified
LRCK Right-ChannelLeft-Channel
BCK
DOUT 24 22 23 24321
MSB LSB
22 23 24321
MSB LSB
16-Bit, MSB-First, Right-Justified
LRCK Right-ChannelLeft-Channel
BCK
DOUT 16 14 15 16321
MSB LSB
14 15 16321
MSB LSB
T0016-16
PCM1850A
PCM1851A
SLES173 – MARCH 2006
Figure 23. Audio Data Format(LRCK, BCK Work as Inputs in Slave Mode and Outputs in Master Mode)
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Interface Timing
BCK
LRCK
DOUT
t(BCKH)
t(BCKL)
t(LRHD)
t(LRCP)
t(LRSU)
t(BCKP) t(CKDO) t(LRDO)
1.4 V
1.4 V
0.5 VDD
T0017-02
PCM1850A
PCM1851A
SLES173 – MARCH 2006
Figure 24 and Figure 25 illustrate the interface timing in slave and master modes, respectively.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
(BCKP)
BCK period 150 nst
(BCKH)
BCK pulse duration, HIGH 60 nst
(BCKL)
BCK pulse duration, LOW 60 nst
(LRSU)
LRCK setup time to BCK rising edge 20 nst
(LRHD)
LRCK hold time to BCK rising edge 20 nst
(LRCP)
LRCK period 10 µst
(CKDO)
Delay time, BCK falling edge to DOUT valid –10 20 nst
(LRDO)
Delay time, LRCK edge to DOUT valid –10 20 nst
r
Rise time of all signals 10 nst
f
Fall time of all signals 10 nsNOTE: Timing measurement reference level is 1.4 V for input and 0.5 V
DD
for output. Rise and fall times are measured from 10% to 90% ofIN/OUT signal swing. Load capacitance of DOUT is 20 pF.
Figure 24. Audio Data Interface Timing (Slave Mode: LRCK, BCK Work as Inputs)
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BCK
LRCK
DOUT
t(BCKH)
t(BCKL)
t(CKLR)
t(LRCP)
t(BCKP) t(CKDO) t(LRDO)
0.5 VDD
0.5 VDD
0.5 VDD
T0018-02
PCM1850A
PCM1851A
SLES173 – MARCH 2006
SYMBOL PARAMETER MIN TYP MAX UNIT
t
(BCKP)
BCK period 150 1/(64 f
S
) 1000 nst
(BCKH)
BCK pulse duration, HIGH 60 0.5 t
(BCKP)
400 nst
(BCKL)
BCK pulse duration, LOW 60 0.5 t
(BCKP)
400 nst
(CKLR)
Delay time, BCK falling edge to LRCK valid –10 20 nst
(LRCP)
LRCK period 10 1/f
S
60 µst
(CKDO)
Delay time, BCK falling edge to DOUT valid –10 20 nst
(LRDO)
Delay time, LRCK edge to DOUT valid –10 20 nst
r
Rise time of all signals 10 nst
f
Fall time of all signals 10 nsNOTE: Timing measurement reference level is 0.5 V
DD
. Rise and fall times are measured from 10% to 90% of IN/OUT signal swing. Loadcapacitance of all signals is 20 pF.
Figure 25. Audio Data Interface Timing (Master Mode: LRCK, BCK Work as Outputs)
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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
1/fS32/fS
NORMAL DATAZERO DATA
UNDEFINED
DATA
NORMAL DATA
SYNCHRONOUSASYNCHRONOUSSYNCHRONOUS
Resynchronization
Synchronization Lost
DOUT
State of Synchronization
T0020-05
Power-Down Control
Overflow Flag Output
HPF Bypass Control
PCM1850A
PCM1851A
SLES173 – MARCH 2006
In slave mode, the PCM1850A/1851A operates under LRCK, synchronized with system clock SCKI. ThePCM1850A/1851A does not need a specific phase relationship between LRCK and SCKI, but does require thesynchronization of LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCKs/frame ( ±5 BCKs for 48BCKs/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/f
Sand digital output is forced into the BPZ code until resynchronization between LRCK and SCKI is completed.
In the case of changes less than ±5 BCKs for 64 BCKs/frame ( ±4 BCKs for 48 BCKs/frame), resynchronizationwith simultaneous discontinuity in the digital output does not occur.
Figure 26 illustrates the digital output response for loss of synchronization and resynchronization. Duringundefined data, the PCM1850A/1851A might generate some noise in the audio signal. Also, the transition ofnormal to undefined data and undefined or zero data to normal creates a discontinuity of data in the digitaloutput, which could generate some noise in the audio signal.
It is recommended to set RST (pin 10) to LOW to get stable analog performance when the sampling rate,interface mode, or data format is changed.
Figure 26. ADC Digital Output for Loss of Synchronization and Resynchronization
RST (pin 10) controls the entire ADC operation. During reset mode, the supply current of the analog section isshut off and the digital section is initialized. DOUT (pin 3) is also disabled. Halting SCKI, BCK, and LRCK isrecommended to minimize power dissipation.
RST POWER-DOWN MODE
LOW Reset and power-down modesHIGH Normal operation mode
The PCM1850A/1851A has an output flag (pin 4) that indicates when overflow occurs in the L-channel orR-channel, and this flag remains HIGH at least during the 8192/f
S
time for a momentary overflow occurrence.
The built-in HPF function for dc component rejection can be bypassed via the serial port. In bypass mode, the dccomponent of the analog input signal, the internal dc offset, etc., are converted and included in the digital outputdata.
BYP HPF (HIGH-PASS FILTER) MODE
0 Normal (no dc component on DOUT) mode (default)1 Bypass (dc component on DOUT) mode
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System Reset Control
Mode Register Reset Control
SPI SERIAL CONTROL PORT FOR MODE CONTROL (PCM1850A)
MSB
0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D000
LSB
Register Index (or Address) Register Data
R0001-01
IDX0 D7 D6 D4D5 D3 D2 D1 D0
MS
MC
MD IDX1IDX2IDX3IDX4IDX5IDX60X X X 0 IDX6
T0048-04
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The system reset control is used to resynchronize the system via the serial port when the system clockfrequency, interface mode, and data format are changed. Change them while SRST = LOW. If they are changedduring normal operation, analog performance can be degraded.SRST SYSTEM RESET
0 Resynchronization
1 Normal operation (default)
The MRST bit is used to reset the mode control register to its default settings via the serial port.MRST MODE REGISTER RESET
0 Set default value1 Normal operation (default)
The user-programmable built-in functions of the PCM1850A can be controlled through a serial control port withthe SPI format. All operations for the serial control port use 16-bit data words. Figure 27 shows the control dataword format. The most-significant bit must be set to 0. Seven bits, labeled IDX[6:0], set the register index (oraddress) for write operations. The least-significant eight bits, D[7:0], contain the data to be written to the registerspecified by IDX[6:0].
Figure 28 shows the functional timing diagram for writing to the serial control port. MS (pin 30) is held at a logic-1state until a register needs to be written. To start the register write cycle, MS is set to logic-0. Sixteen clocks arethen provided on MC (pin 31), corresponding to the 16 bits of the control data word on MD (pin 32). After thesixteenth clock cycle has completed, the data is latched into the indexed mode control register in the writeoperation. To write the next data word, MS must be set to 1 once.
Figure 27. Control Data Word Format for MD
Figure 28. Serial Control Format
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CONTROL INTERFACE TIMING REQUIREMENTS (PCM1850A)
t(MCH)
1.4 V
MS
t(MSS)
LSB
1.4 V
1.4 V
t(MCL)
t(MHH)
t(MSH)
t(MCY)
t(MDH)
t(MDS)
MC
MD
T0013-06
I
2
C SERIAL CONTROL PORT FOR MODE CONTROL (PCM1851A)
Slave Address
Packet Protocol
PCM1850A
PCM1851A
SLES173 – MARCH 2006
Figure 29 shows a detailed timing diagram for the serial control interface of the PCM1850A. These timingparameters are critical for proper control port operation.
SYMBOL PARAMETER MIN MAX UNIT
t
(MCY)
MC pulse cycle time 100 nst
(MCL)
MC LOW-level time 40 nst
(MCH)
MC HIGH-level time 40 nst
(MHH)
MS HIGH-level time 80 nst
(MSS)
MS falling edge to MC rising edge 15 nst
(MSH)
MS hold time
(1)
15 nst
(MDH)
MD hold time 15 nst
(MDS)
MD setup time 15 ns
(1) MC rising edge for LSB to MS rising edge
Figure 29. PCM1850A Control Interface Timing
The user-programmable built-in function of the PCM1851A can be controlled through the I
2
C-format serial controlport, SDA (pin 32) and SCL (pin 31). The PCM1851A supports the I
2
C serial bus and the data transmissionprotocol for standard mode as a slave device. This protocol is explained in I
2
C specification 2.0.
MSB LSB
1 0 0 1 0 1 ADR R/nW
The PCM1851A has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factorypreset to 100101. The last bit of the address byte is the device select bit, which can be user-defined by the ADRpin (pin 30). A maximum of two PCM1851As can be connected on the same bus at one time. Each PCM1851Aresponds when it receives its own slave address.
A master device must control packet protocol, which consists of start condition, slave address with read/write bit,data if write or acknowledgement if read, and stop condition. The PCM1851A supports only slave receivers, sothe R/ W bit must be set to 0.
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9
SDA
SCL St 1−7 8 1−8 9 1−8 9 9 Sp
Slave Address ACK DATA ACK DATA ACK ACKR/W
R/W: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgement of a Byte if 0
DATA: 8 Bits (Byte)
Stop
Condition
Start
Condition
Transmitter M M M S M S M S S M
Data Type St Slave Address R/W ACK DATA ACK DATA ACK ACK Sp
M: Master Device S: Slave Device
St: Start Condition Sp: Stop Condition T0049-05
Write Operation
R0002-03
M: Master Device S: Slave Device
St: Start Condition ACK: Acknowledge W: Write Sp: Stop Condition
Transmitter M M M S
Data Type St Slave Address W ACK
M
Reg Address
M
Write Data 1
S
ACK
S
ACK
M
Sp
M
Write Data 2
S
ACK
S
ACK
PCM1850A
PCM1851A
SLES173 – MARCH 2006
Figure 30. Basic I
2
C Framework
The PCM1851A has only the write mode. A master can write to any PCM1851A registers using single or multipleaccesses. The master sends a PCM1851A slave address with a write bit, a register address, and the data. Ifmultiple access is required, the address is that of the starting register, followed by the data to be transferred.When the data are received properly, the index register is incremented by 1 automatically. When the indexregister reaches 33h, the next value is 31h. When undefined registers are accessed, the PCM1851A does notsend an acknowledgement. Figure 31 is a diagram of the write operation. The register address and the write dataare 8 bits and MSB-first format.
Figure 31. Framework for Write Operation
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TIMING DIAGRAM
SDA
SCL
t(BUF) t(D-SU)
t(D-HD)
Start
t(LOW)
t(S-HD) t(SCL-F)
t(SCL-R)
t(HI)
Repeated Start
t(RS-SU)
t(RS-HD)
t(SDA-F)
t(SDA-R) t(P-SU)
Stop
T0050-01
PCM1850A
PCM1851A
SLES173 – MARCH 2006
SYMBOL PARAMETER MIN MAX UNIT
f
(SCL)
SCL clock frequency 100 kHzt
(BUF)
Bus free time between STOP and START conditions 4.7 µst
(LOW)
Low period of the SCL clock 4.7 µst
(HI)
High period of the SCL clock 4 µst
(RS-SU)
Setup time for START/repeated START condition 4.7 µst
(S-HD)
, t
(RS-HD)
Hold time for START/repeated START condition 4 µst
(D-SU)
Data setup time 250 nst
(D-HD)
Data hold time 0 900 nst
(SCL-R)
Rise time of SCL signal 20 + 0.1 C
B
1000 nst
(SCL-F)
Fall time of SCL signal 20 + 0.1 C
B
1000 nst
(SDA-R)
Rise time of SDA signal 20 + 0.1 C
B
1000 nst
(SDA-F)
Fall time of SDA signal 20 + 0.1 C
B
1000 nst
(P-SU)
Setup time for STOP condition 4 µsC
B
Capacitive load for SDA and SCL lines 400 pFV
NH
Noise margin at HIGH level for each connected device (including hysteresis) 0.2 V
DD
V
Figure 32. PCM1851A Control Interface Timing Requirements
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MODE CONTROL REGISTERS
User-Programmable Mode Control Functions
Register Map
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The PCM1850A/1851A has several user-programmable functions which are accessed via control registers. Theregisters are programmed using the serial control port which is discussed in the SPI Serial Control Port for ModeControl (PCM1850A) and I
2
C Serial Control Port for Mode Control (PCM1851A) sections of this data sheet.Table 6 lists the available mode control functions, along with their reset default conditions and associated registerindex.
The mode control register map is shown in Table 7 . Each register includes an index (or address) indicated by theIDX[6:0] bits B[14:8].
Table 6. User-Programmable Mode Control Functions
FUNCTION RESET DEFAULT REGISTER BIT(S)
Mode register reset Normal operation 31 MRSTPGA gain control –11 dB 31 PG[5:0]Multiplexer input channel control Channel 1 32 CH[2:0]HPF bypass control HPF enable 33 BYPSystem reset Normal operation 33 SRSTAudio interface mode control Slave 33 MD[1:0]Audio interface format control I
2
S 33 FMT[2:0]
Table 7. Mode Control Register Map
HEX B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 31 0 0 1 1 0 0 0 1 RSV
(1)
MRST PG5 PG4 PG3 PG2 PG1 PG0Register 32 0 0 1 1 0 0 1 0 RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
CH2 CH1 CH0Register 33 0 0 1 1 0 0 1 1 BYP SRST RSV
(1)
MD1 MD0 FMT2 FMT1 FMT0
(1) RSV bits must be always written as 0. No values can be written in address 30h.
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APPLICATION INFORMATION
TYPICAL CIRCUIT CONNECTION DIAGRAM
23 22 21 20 19
1 2
VINR2
VINL2
VINR1
VINL1
MOUTL
MOUTR
RST
TEST1
VREFS
VREF1
VREF2
Vcc
AGND
MS (ADR)(1)
MC (SCL)(1)
MD (SDA)(1)
24 18
345678
17
VINR6
VINL6
VINR5
VINL5
VINR4
VINL4
VINR3
VINL3
LRCK
BCK
DOUT
OVER
DGND
VDD
SCKI
TEST0
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
+
C16
C17 C15 C14 C13 C12 C11 C10
+++++++
Analog Input/Output
+C9
+C8
+C7
+C6
+C19
+C18
+
C5+
C4+
C3
+C1
+5 V
0 V
C2
+
3.3 V
Control
Audio Data Processor
PCM1850A/1851A
(1) PCM1850A (PCM1851A)
S0181-01
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The following figure illustrates a typical circuit connection diagram for six stereo inputs and an analog monitor.
NOTE: C
1
, C
2
: 0.1- µF ceramic and 10- µF electrolytic capacitors are recommended, depending on layout and power supply.C
3
, C
4
, C
5
: 0.1- µF ceramic and 10- µF electrolytic capacitors are recommended.C
6
–C
17
: A 0.33- µF capacitor gives a 2.9-Hz ( τ= 0.33 µF×169 k Ω) typical cutoff frequency at the HPF input in normaloperation, and it requires power-on settling time with a 56-ms time constant in the power-on initialization period.Cutoff frequency and time constant depend on PGA gain. Cutoff frequency varies from 2.4 Hz to 8.5 Hz for 0.33 µF.DC-coupled input is inhibited for the analog input, V
IN
L[1:6] and V
IN
R[1:6].C
18
–C
19
: A 2.2- µF capacitor with a 10-k Ωload gives a 7.2-Hz cutoff frequency.
28
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BOARD DESIGN AND LAYOUT CONSIDERATIONS
V
CC
, V
DD
Pins
AGND, DGND Pins
V
IN
L[1:6], V
IN
R[1:6] Pins
MOUTL, MOUTR Pins
V
REF
1, V
REF
2, V
REF
S Pins
BCK and LRCK Pins (in Master Mode), DOUT Pin
System Clock
PCM1850A
PCM1851A
SLES173 – MARCH 2006
APPLICATION INFORMATION (continued)
The digital and analog power supply lines to the PCM1850A/1851A must be bypassed to the correspondingground pins with 0.1- µF ceramic and 10- µF electrolytic capacitors as close to the pins as possible to maximizethe dynamic performance of the ADC.
To maximize the dynamic performance of the PCM1850A/1851A, the analog and digital grounds are notconnected internally. These grounds must have low impedance to avoid digital noise feeding back into theanalog ground. Therefore, they should be connected directly to each other under the parts to reduce the potentialof a noise problem.
A 0.33- µF capacitor is recommended as the ac-coupling capacitor, which gives a 2.4- to 8.5-Hz cutoff frequency.If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to each V
IN
xxpin, but a signal source resistance less than 1 k Ωis recommended for these pins in order to keep accuracy ofthe gain control command and to maintain crosstalk performance.
An ac-coupled light load is recommended; a 2.2- µF capacitor with a 10-k Ωload gives a 7.2-Hz cutoff frequency.
Between V
REF
1 and AGND, V
REF
2 and AGND, and V
REF
S and AGND, 0.1- µF ceramic and 10- µF electrolyticcapacitors are recommended to ensure low source impedance of the ADC references. These capacitors shouldbe located as close as possible to the V
REF
1, V
REF
2, and V
REF
S pins to reduce dynamic errors on the ADCreferences. The differential voltage between V
REF
2 and AGND sets the analog input full-scale range.
These pins have enough load-driving capability. However, if the output line is long, locating a buffer near thePCM1850A/1851A and minimizing load capacitance is recommended in order to minimize the digital-analogcrosstalk and maximize the dynamic performance of the ADC.
Because the PCM1850A/1851A operates based on a system clock, the quality of the system clock can influencedynamic performance. Therefore, it is recommended to consider the system clock duty, jitter, and the timedifference between the system clock transition and the BCK or LRCK transition in slave mode.
29Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCM1850APJT ACTIVE TQFP PJT 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1850APJTG4 ACTIVE TQFP PJT 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1850APJTR ACTIVE TQFP PJT 32 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1850APJTRG4 ACTIVE TQFP PJT 32 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1851APJT ACTIVE TQFP PJT 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1851APJTG4 ACTIVE TQFP PJT 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1851APJTR ACTIVE TQFP PJT 32 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1851APJTRG4 ACTIVE TQFP PJT 32 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Oct-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1851APJTR TQFP PJT 32 1000 330.0 16.8 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1851APJTR TQFP PJT 32 1000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2008
Pack Materials-Page 2
MECHANICAL DATA
MPQF112 – NOVEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PJT (S-PQFP–N32) PLASTIC QUAD FLATPACK
4203540/A 11/01
1
0,45
0,30
32
7,00 SQ
0,95
1,05
Seating Plane
0,45
0,75
0,25
Gage Plane
0,80 0,20
SQ
9,00
1,00
1,20 0,10
0,05
0,15
0,20
0,09
M
0°– 7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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