© Semiconductor Components Industries, LLC, 2016
February, 2017 − Rev. 1 1Publication Order Number:
NCP4308/D
NCP4308
Synchronous Rectifier
Controller
The NCP4308 is a synchronous rectifier controller for switch mode
power supplies. The controller enables high efficiency designs for
flyback, quasi resonant flyback and LLC topologies.
Externally adjustable minimum off−time and on−time blanking
periods provides flexibility to drive various MOSFET package types
and PCB layout. A reliable and noise less operation of the S R system is
insured due to the Self Synchronization feature. The NCP4308 also
utilizes Kelvin connection of the driver to the MOSFET to achieve high
efficiency operation at full load.
The precise turn−off threshold, extremely low turn−off delay time
and high sink current capability of the driver allow the maximum
synchronous rectification MOSFET conduction time. The high
accuracy driver and 5 V gate clamp make it ideally suited for directly
driving GaN devices.
Features
•Self−Contained Control of Synchronous Rectifier in CCM, DCM and
QR for Flyback or LLC Applications
•Precise True Secondary Zero Current Detection
•Rugged Current Sense Pin (up to 150 V)
•Adjustable Minimum ON−Time
•Adjustable Minimum OFF-Time with Ringing Detection
•Adjustable Maximum ON−Time for CCM Controlling of Primary
QR Controller
•Improved Robust Self Synchronization Capability
•8 A / 4 A Peak Current Sink / Source Drive Capability
•Operating Voltage Range up to VCC = 35 V
•GaN Transistor Driving Capability (options A and C)
•Low Startup Current Consumption
•Maximum Operation Frequency up to 1 MHz
•SOIC-8, DFN−8 (4x4) and WDFN8 (2x2) Packages
•These are Pb−Free Devices
Typical Applications
•Notebook Adapters
•High Power Density AC/DC Power Supplies (Cell Phone Chargers)
•LCD TVs
•All SMPS with High Efficiency Requirements
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
4308x = Specific Device Code
x = A, B, C, D or Q
Ex = Specific Device Code
x = A or D
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G= Pb−Free Package
1
8NCP4308x
ALYW G
G
1
8
(Note: Microdot may be in either location)
4308x
ALYWG
G
1
DFN8
MN SUFFIX
CASE 488AF
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See detailed ordering and shipping information on page 26 o
f
this data sheet.
ORDERING INFORMATION
WDFN8
MT SUFFIX
CASE 511AT
ExMG
G
1
NCP4308
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Figure 3. Typical Application Example − Primary Side Flyback Converter
+
++
Vbulk
FLYBACK
SIDE
CONTROLLER
+Vout
GND
R1
R2
R7
R6
C1 C2
C3
C7
C10
D3
D4
TR1
M1
M2
PRIMARY
C4
C5
C6
R3
R4
R5
R8
VCC
DRV
COMP CS
ZCD
Figure 4. Typical Application Example − QR Converter − Capability to Force Primary into CCM Under Heavy
Loads utilizing MAX−TON
+
+
+
Vbulk
CIRCUITRY
+Vout
GND
OK1
R5
R2
R8
R9
R10
C1
C4
C7
D2
D3
D6
TR1
TR2
M1
M3
NCP4308
R7
D5
D1
R1
R11
R12
M2
D4
R3
R4
R6
C2
C5
C6
C3
VCC
DRV
FB CSZCD
CONTROL
QR
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PIN FUNCTION DESCRIPTION
ver. A, B, C, D ver. Q Pin Name Description
1 1 VCC Supply voltage pin
2 2 MIN_TOFF Adjust the minimum off time period by connecting resistor to ground.
3 3 MIN_TON Adjust the minimum on time period by connecting resistor to ground.
4 4 NC Leave this pin opened or tie it to ground.
5 − NC Leave this pin opened or tie it to ground.
6 6 CS Current sense pin detects if the current flows through the SR MOSFET and/or its body
diode. Basic turn−off detection threshold is 0 mV. A resistor in series with this pin can
decrease the turn off threshold if needed.
7 7 GND Ground connection for the SR MOSFET driver, VCC decoupling capacitor and for mini-
mum on and off time adjust resistors. GND pin should be wired directly to the SR
MOSFET source terminal/soldering point using Kelvin connection. DFN8 exposed flag
should be connected to GND
8 8 DRV Driver output for the SR MOSFET
− 5 MAX_TON Adjust the maximum on time period by connecting resistor to ground.
Minimum ON time
generator
MIN_TON
CS
detection
100mA
CS
MIN_TOFF
NC
CS_ON
CS_OFF
DRV
VCC
GND
VCC managment
UVLO
DRV Out
DRIVER
VDD
VDD
CS_RESET
NCADJ ELAPSED
EN
Minimum OFF
time generator
ADJ RESET
ELAPSED
Control logic
EN
Figure 5. Internal Circuit Architecture − NCP4308A, B, C, D
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Minimum ON time
generator
MIN_TON
CS
detection
100mA
CS
MIN_TOFF
MAX_TON
CS_ON
CS_OFF
DRV
VCC
GND
VCC managment
UVLO
DRV Out
DRIVER
VDD
VDD
CS_RESET
NC
ADJ
ELAPSED
EN
Minimum OFF
time generator
ADJ
RESET
ELAPSED
Control logic
EN
ELAPSED
Maximum ON time
generator EN
ADJ
Figure 6. Internal Circuit Architecture − NCP4308Q (CCM QR) with MAX_TON
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ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC −0.3 to 37.0 V
MIN_TON, MIN_TOFF, MAX_TON Input Voltage VMIN_TON,
VMIN_TOFF,
VMAX_TON
−0.3 to VCC V
Driver Output Voltage VDRV −0.3 to 17.0 V
Current Sense Input Voltage VCS −4 to 150 V
Current Sense Dynamic Input Voltage (tPW = 200 ns) VCS_DYN −10 to 150 V
MIN_TON, MIN_TOFF, MAX_TON, Input Current IMIN_TON, IMIN_TOFF,
IMAX_TON −10 to 10 mA
Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, SOIC8 RqJ−A_SOIC8 160 °C/W
Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, DFN8 RqJ−A_DFN8 80 °C/W
Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, WDFN8 RqJ−A_WDFN8 160 °C/W
Maximum Junction Temperature TJMAX 150 °C
Storage Temperature TSTG −60 to 150 °C
ESD Capability, Human Body Model, Except Pin 6, per JESD22−A114E ESDHBM 2000 V
ESD Capability, Human Body Model, Pin 6, per JESD22−A114E ESDHBM 1000 V
ESD Capability, Machine Model, per JESD22−A115−A ESDMM 200 V
ESD Capability, Charged Device Model, Except Pin 6, per JESD22−C101F ESDCDM 750 V
ESD Capability, Charged Device Model, Pin 6, per JESD22−C101F ESDCDM 250 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. This device meets latch−up tests defined by JEDEC Standard JESD78D Class I.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Maximum Operating Input Voltage VCC 35 V
Operating Junction Temperature TJ−40 125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VCS = −1 to
+4 V; fCS = 100 kHz, DCCS = 50%, unless otherwise noted. Typical values are at TJ = +25°C
Parameter Test Conditions Symbol Min Typ Max Unit
SUPPLY SECTION
VCC UVLO (ver. B & C) VCC rising, VCS = 0 V VCCON 8.3 8.8 9.4 V
VCC falling, VCS = 0 V VCCOFF 7.3 7.8 8.3
VCC UVLO Hysteresis (ver. B & C) VCCHYS 1.0 V
VCC UVLO (ver. A, D & Q) VCC rising, VCS = 0 V VCCON 4.20 4.45 4.80 V
VCC falling, VCS = 0 V VCCOFF 3.70 3.95 4.20
VCC UVLO Hysteresis
(ver. A, D & Q) VCCHYS 0.5 V
Start−up Delay VCC rising from 0 to VCCON + 1 V @ tr = 10 ms,
VCS = 0 V tSTART_DEL 75 125 ms
Current Consumption,
RMIN_TON = RMIN_TOFF = 0 kWCDRV = 0 nF, fCS = 500 kHz A, C ICC 3.0 4.0 5.6 mA
B, D, Q 3.5 4.5 6.0
CDRV = 1 nF, fCS = 500 kHz A, C 4.5 6.0 7.5
B, D, Q 7.7 9.0 10.7
CDRV = 10 nF, fCS = 500 kHz A, C 20 25 30
B, D, Q 40 50 60
Current Consumption No switching, VCS = 0 V, RMIN_TON = RMIN_TOFF
= 0 kWICC 1.5 2.0 2.5 mA
No switching, VCS = 0 V, RMIN_TON = RMIN_TOFF
= 0 kW, DFN8, WDFN8 ICC 1.0 2.0 2.5 mA
Current Consumption below UVLO No switching, VCC = VCCOFF – 0.1 V, VCS = 0 V ICC_UVLO 75 125 mA
DRIVER OUTPUT
Output Voltage Rise−Time CDRV = 10 nF, 10% to 90% VDRVMAX tr40 55 ns
Output Voltage Fall−Time CDRV = 10 nF, 90% to 10% VDRVMAX tf20 35 ns
Driver Source Resistance RDRV_SOURCE 1.2 W
Driver Sink Resistance RDRV_SINK 0.5 W
Output Peak Source Current IDRV_SOURCE 4 A
Output Peak Sink Current IDRV_SINK 8 A
Maximum Driver Output Voltage VCC = 35 V, CDRV > 1 nF (ver. B, D and Q) VDRVMAX 9.0 9.5 10.5 V
VCC = 35 V, CDRV > 1 nF (ver. A, C) 4.3 4.7 5.5
Minimum Driver Output Voltage VCC = VCCOFF + 200 mV (ver. B) VDRVMIN 7.2 7.8 8.5 V
VCC = VCCOFF + 200 mV (ver. C) 4.2 4.7 5.3
VCC = VCCOFF + 200 mV (ver. A, D and Q) 3.6 4.0 4.4
CS INPUT
Total Propagation Delay From CS
to DRV Output On VCS goes down from 4 to −1 V, tf_CS = 5 ns tPD_ON 35 60 ns
Total Propagation Delay From CS
to DRV Output Off VCS goes up from −1 to 4 V, tr_CS = 5 ns tPD_OFF 12 23 ns
CS Bias Current VCS = −20 mV ICS −105 −100 −95 mA
Turn On CS Threshold Voltage VTH_CS_ON −120 −75 −40 mV
Turn Off CS Threshold Voltage Guaranteed by Design VTH_CS_OFF −1 0 mV
Turn Off Timer Reset Threshold
Voltage VTH_CS_RESET 0.4 0.5 0.6 V
CS Leakage Current VCS = 150 V ICS_LEAKAGE 0.4 mA
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ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VCS = −1 to
+4 V; fCS = 100 kHz, DCCS = 50%, unless otherwise noted. Typical values are at TJ = +25°C
Parameter UnitMaxTypMinSymbolTest Conditions
MINIMUM tON and tOFF ADJUST
Minimum tON time RMIN_TON = 0 WtON_MIN 35 55 75 ns
RMIN_TON = 0 W, DFN8, WDFN8 tON_MIN 25 50 75 ns
Minimum tOFF time RMIN_TOFF = 0 WtOFF_MIN 190 245 290 ns
RMIN_TOFF = 0 W, DFN8, WDFN8 tOFF_MIN 160 245 290 ns
Minimum tON time RMIN_TON = 10 kWtON_MIN 0.92 1.00 1.08 ms
Minimum tOFF time RMIN_TOFF = 10 kWtOFF_MIN 0.92 1.00 1.08 ms
Minimum tON time RMIN_TON = 50 kWtON_MIN 4.62 5.00 5.38 ms
Minimum tOFF time RMIN_TOFF = 50 kWtOFF_MIN 4.62 5.00 5.38 ms
MAXIMUM tON ADJUST
Maximum tON Time VMAX_TON = 3 V tON_MAX 4.3 4.8 5.3 ms
Maximum tON Time VMAX_TON = 0.3 V tON_MAX 41 48 55 ms
Maximum tON Output Current VMAX_TON = 0.3 V IMAX_TON −105 −100 −95 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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TYPICAL CHARACTERISTICS
Figure 7. VCCON and VCCOFF Levels,
VCS = 0 V, ver. A, D, Q Figure 8. VCCON and VCCOFF Levels,
VCS = 0 V, ver. B, C
TJ (°C) TJ (°C)
100806040200−20−40
3.7
3.8
3.9
4.1
4.2
4.4
4.6
4.7
100806040200−20−40
7.3
7.5
7.7
8.1
8.3
8.7
8.9
9.3
VCC (V)
VCC (V)
120
4.0
4.3
4.5 VCCON
VCCOFF
VCCON
VCCOFF
120
7.9
8.5
9.1
Figure 9. Current Consumption, CDRV = 0 nF,
fCS = 500 kHz, ver. D Figure 10. Current Consumption, VCC =
VCCOFF − 0.1 V, VCS = 0 V, ver. D
VCC (V) TJ (°C)
3025 3520151050
0
1
2
3
4
5
6
1201006040200−20−40
0
20
40
60
80
100
120
Figure 11. Current Consumption, VCC = 12 V,
VCS = −1 to 4 V, fCS = 500 kHz, ver. A Figure 12. Current Consumption, VCC = 12 V,
VCS = −1 to 4 V, fCS = 500 kHz, ver. D
TJ (°C) TJ (°C)
100806040200−20−40
0
5
10
15
20
25
30
100806040200−20−40
0
10
20
30
40
50
60
ICC (mA)
ICC_UVLO (mA)
ICC (mA)
ICC (mA)
TJ = 85°CTJ = 55°CTJ = 125°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
80
120
CDRV = 0 nF
CDRV = 1 nF
CDRV = 10 nF
CDRV = 0 nF
CDRV = 1 nF
CDRV = 10 nF
120
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TYPICAL CHARACTERISTICS
Figure 13. CS Current, VCS = −20 mV Figure 14. CS Current, VCC = 12 V
TJ (°C) VCS (V)
100806040200−20−40
−110
−106
−104
−100
−98
−96
−94
−90
0.80.60.20−0.2−0.4−0.8−1.0
−1.4
−1.2
−1.0
−0.8
−0.6
−0.4
−0.2
0
Figure 15. Supply Current vs. CS Voltage,
VCC = 12 V Figure 16. CS Turn−on Threshold
VCS (V) TJ (°C)
3210−1−2−3−4
0
0.5
1.0
1.5
2.0
2.5
3.0
100806040200−20−40
−150
−130
−110
−90
−70
−50
−30
Figure 17. CS Turn−off Threshold Figure 18. CS Reset Threshold
TJ (°C) TJ (°C)
100806040200−20−40
−2.0
−1.5
−1.0
−0.5
0
0.5
1.0
0.40
0.45
0.50
0.55
0.60
ICS (mA)
ICS (mA)
ICC (mA)
VTH_CS_ON (mV)
VTH_CS_OFF (mV)
VTH_CS_RESET (V)
120
−92
−102
−108
−0.6 0.4 1.0
4
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
120
120 100806040200−20−40 120
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TYPICAL CHARACTERISTICS
Figure 19. CS Reset Threshold Figure 20. CS Leakage, VCS = 150 V
VCC (V) TJ (°C)
302520 35151050
0.30
0.35
0.45
0.50
0.60
0.65
0.70
0.80
100 1206040200−20−40
0
20
60
80
120
140
180
200
Figure 21. Propagation Delay from CS to DRV
Output On Figure 22. Propagation Delay from CS to DRV
Output Off
TJ (°C) TJ (°C)
100806040200−20−40
20
25
30
35
40
50
55
60
100806040200−20−40
4
6
10
12
16
18
22
24
VTH_CS_RESET (V)
ICS_LEAKAGE (nA)
tPD_ON (ns)
tPD_OFF (ns)
0.40
0.55
0.75
80
40
100
160
120
45
120
8
14
20
Figure 23. Minimum On−time RMIN_TON = 0 WFigure 24. Minimum On−time RMIN_TON = 10 kW
TJ (°C) TJ (°C)
100806040200−20−40
35
40
45
50
55
60
70
75
100806040200−20−40
0.92
0.94
0.96
0.98
1.00
1.04
1.06
1.08
tMIN_TON (ns)
tMIN_TON (ms)
120
65
120
1.02
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TYPICAL CHARACTERISTICS
Figure 25. Minimum On−time RMIN_TON = 50 kWFigure 26. Minimum Off−time RMIN_TOFF = 0 W
TJ (°C) TJ (°C)
100806040200−20−40
4.6
4.7
4.8
4.9
5.0
5.2
5.3
5.4
100806040200−20−40
190
200
220
230
240
260
270
290
Figure 27. Minimum Off−time RMIN_TOFF =
10 kW
Figure 28. Minimum Off−time RMIN_TOFF =
50 kW
TJ (°C) TJ (°C)
100806040200−20−40
0.92
0.94
0.96
1.00
1.02
1.04
1.06
1.08
100806040200−20−40
4.6
4.7
4.8
4.9
5.0
5.1
5.3
5.4
Figure 29. Minimum On−time RMIN_TON = 10 kWFigure 30. Minimum Off−time RMIN_TOFF =
10 kW
VCC (V) VCC (V)
302520 35151050
0.92
0.94
0.96
0.98
1.00
1.02
1.03
1.04
35302520151050
092
0.94
0.96
0.98
1.00
1.02
1.06
1.08
tMIN_TON (ms)
tMIN_TOFF (ns)
tMIN_TOFF (ms)
tMIN_TOFF (ms)
tMIN_TON (ms)
tMIN_TOFF (ms)
120
5.1
120
210
250
280
120
0.98
120
5.2
1.01
1.04
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TYPICAL CHARACTERISTICS
Figure 31. Driver and Output Voltage, ver. B, D
and Q Figure 32. Driver Output Voltage, ver. A and C
TJ (°C) TJ (°C)
100806040200−20−40
9.0
9.2
9.4
9.6
9.8
10.0
10.2
10.4
100806040200−20−40
4.3
4.5
4.7
4.9
5.1
5.3
5.5
Figure 33. Maximum On−time, ver. Q Figure 34. Maximum On−time, VMAX_TON = 3 V,
ver. Q
VMAX_TON (V) TJ (°C)
3.02.52.01.51.00.50
0
5
15
20
25
35
45
50
100806040200−20−40
4.3
4.4
4.6
4.7
4.8
5.0
5.1
5.3
Figure 35. Maximum On−time, VMAX_TON =
0.3 V, ver. Q
TJ (°C)
100806040200−20−40
41
43
45
47
49
51
53
55
VDRV (V)
VDRV (V)
tMAX_TON (ms)
tMAX_TON (ms)
tMAX_TON (ms)
120
VCC = 12 V, CDRV = 0 nF
VCC = 12 V, CDRV = 1 nF
VCC = 12 V, CDRV = 10 nF
VCC = 35 V, CDRV = 0 nF
VCC = 35 V, CDRV = 1 nF
VCC = 35 V, CDRV = 10 nF
VCC = 12 V, CDRV = 0 nF
VCC = 12 V, CDRV = 1 nF
VCC = 12 V, CDRV = 10 nF
VCC = 35 V, CDRV = 0 nF
VCC = 35 V, CDRV = 1 nF
VCC = 35 V, CDRV = 10 nF
120
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
10
30
40
120
4.5
4.9
5.2
120
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APPLICATION INFORMATION
General description
The NCP4308 is designed to operate either as a standalone
IC or as a companion IC to a primary side controller to help
achieve efficient synchronous rectification in switch mode
power supplies. This controller features a high current gate
driver along with high−speed logic circuitry to provide
appropriately timed drive signals to a synchronous
rectification MOSFET. With its novel architecture, the
NCP4308 has enough versatility to keep the synchronous
rectification system efficient under any operating mode.
The NCP4308 works from an available voltage with range
from 4 V (A, D & Q options) or 8 V (B & C options) to 35 V
(typical). The wide VCC range allows direct connection to
the SMPS output voltage of most adapters such as
notebooks, cell phone chargers and LCD TV adapters.
Precise turn-off threshold of the current sense comparator
together with an accurate offset current source allows the
user to adjust for any required turn-off current threshold of
the SR MOSFET switch using a single resistor. Compared
to other SR controllers that provide turn-off thresholds in t h e
range of −10 mV to −5 mV, the NCP4308 offers a turn-off
threshold of 0 mV. When using a low RDS(on) SR (1 mW)
MOSFET our competition, with a −10 mV turn of f, will turn
off with 10 A still flowing through the SR FET, while our
0 mV turn off turns off the FET at 0 A; significantly
reducing the turn-off current threshold and improving
efficiency. Many of the competitor parts maintain a drain
source voltage across the MOSFET causing the SR
MOSFET to operate in the linear region to reduce turn−off
time. Thanks to the 8 A sink current of the NCP4308
significantly reduces turn off time allowing for a minimal
drain source voltage to be utilized and efficiency
maximized.
To overcome false triggering issues after turn-on and
turn−off events, the NCP4308 provides adjustable minimum
on-time and off-time blanking periods. Blanking times can
be adjusted independently of IC VCC using external
resistors connected to GND. If needed, blanking periods can
be modulated using additional components.
An extremely fast turn−off comparator, implemented on
the current sense pin, allows for NCP4308 implementation
in CCM applications without any additional components or
external triggering.
An output driver features capability to keep SR transistor
closed even when there is no supply voltage for NCP4308.
SR transistor drain voltage goes up and down during SMPS
operation and this is transferred through drain gate
capacitance to gate and may turn on transistor. NCP4308
uses this pulsing voltage at SR transistor gate (DRV pin) and
uses it internally to provide enough supply to activate
internal driver sink transistor. DRV voltage is pulled low
(not to zero) thanks to this feature and eliminate the risk of
turned on SR transistor before enough VCC is applied to
NCP4308.
Some IC versions include a MAX_TON circuit that helps
a quasi resonant (QR) controller to work in CCM mode
when a heavy load is present like in the example of a
printer’s motor starting up.
Current Sense Input
Figure 36 shows the internal connection of the CS
circuitry on the current sense input. When the voltage on the
secondary winding of the SMPS reverses, the body diode o f
M1 starts to conduct current and the voltage of M1’s drain
drops approximately to −1 V. The CS pin sources current of
100 mA that creates a voltage drop on the RSHIFT_CS resistor
(resistor is optional, we recommend shorting this resistor).
Once the voltage on the CS pin is lower than VTH_CS_ON
threshold, M1 is turned−on. Because of parasitic
impedances, significant ringing can occur in the application.
To overcome false sudden turn−off due to mentioned
ringing, the minimum conduction time of the SR MOSFET
is activated. Minimum conduction time can be adjusted
using the RMIN_TON resistor.
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Figure 36. Current Sensing Circuitry Functionality
The SR MOSFET is turned-off as soon as the voltage on
the CS pin is higher than VTH_CS_OFF (typically −0.5 mV
minus any voltage dropped on the optional RSHIFT_CS). For
the same ringing reason, a minimum off-time timer is
asserted once the VCS goes above VTH_CS_RESET. The
minimum off-time can be externally adjusted using
RMIN_TOFF resistor. The minimum off−time generator can
be re−triggered by MIN_TOFF reset comparator if some
spurious ringing occurs on the CS input after SR MOSFET
turn−off event. This feature significantly simplifies SR
system implementation in flyback converters.
In an LLC converter the SR MOSFET M1 channel
conducts while secondary side current is decreasing (refer t o
Figure 37). Therefore the turn−off current depends on
MOSFET RDSON. The −0.5 mV threshold provides an
optimum switching period usage while keeping enough time
margin for the gate turn-off. The RSHIFT_CS resistor
provides the designer with the possibility to modify
(increase) the actual turn−on and turn−off secondary current
thresholds. To ensure proper switching, the min_tOFF timer
is reset, when the VDS of the MOSFET rings and falls down
past the VTH_CS_RESET. The minimum off−time needs to
expire before another drive pulse can be initiated. Minimum
off−time timer is started again when VDS rises above
VTH_CS_RESET.
NCP4308
www.onsemi.com
16
VDS =V
CS
VTH_CS_RESET –(R
SHIFT_CS*ICS)
VTH_CS_OFF–(R
SHIFT_CS*ICS)
VTH_CS_ON–(R
SHIFT_CS*ICS)
VDRV
Min ON−time
t
Min OFF−time
Min tOFF timer was
stopped here because
of VCS<VTH_CS_RESET
tMIN_TON
tMIN_TOFF
ISEC
The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors
Turn−on delay Turn−off delay
Figure 37. CS Input Comparators Thresholds and Blanking Periods Timing in LLC
VDS =V
CS
VTH_CS_RESET –(R
SHIFT_CS*ICS)
VTH_CS_OFF–(R
SHIFT_CS*ICS)
VTH_CS_ON–(R
SHIFT_CS*ICS)
VDRV
Min ON−time
t
Min OFF−time
tMIN_TON
tMIN_TOFF
ISEC
The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors
Turn−on delay Turn−off delay
Min tOFF timer was
stopped here because
of VCS<VTH_CS_RESET
Figure 38. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback
NCP4308
www.onsemi.com
17
If no RSHIFT_CS resistor is used, the turn-on, turn-off and
VTH_CS_RESET thresholds are fully given by the CS input
specification (please refer to electrical characteristics table).
The CS pin offset current causes a voltage drop that is equal
to:
VRSHIFT_CS +RSHIFT_CS *ICS (eq. 1)
Final turn−on and turn of f thresholds can be then calculated
as:
VCS_TURN_ON +VTH_CS_ON *ǒRSHIFT_CS *ICSǓ(eq. 2)
VCS_TURN_OFF +VTH_CS_OFF *ǒRSHIFT_CS *ICSǓ(eq. 3)
VCS_RESET +VTH_CS_RESET *ǒRSHIFT_CS *ICSǓ(eq. 4)
Note that RSHIFT_CS impact on turn-on and VTH_CS_RESET
thresholds is less critical than its effect on the turn−off
threshold.
It should be noted that when using a SR MOSFET in a
through hole package the parasitic inductance of the
MOSFET package leads (refer to Figure 39) causes a
turn−off current threshold increase. The current that flows
through the SR MOSFET experiences a high Di(t)/Dt that
induces an error voltage on the SR MOSFET leads due to
their parasitic inductance. This error voltage is proportional
to the derivative of the SR MOSFET current; and shifts the
CS input voltage to zero when significant current still flows
through the MOSFET channel. As a result, the SR MOSFET
is turned−off prematurely and the efficiency of the SMPS is
not optimized − refer to Figure 40 for a better understanding.
Figure 39. SR System Connection Including MOSFET and Layout Parasitic Inductances in LLC Application
NCP4308
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18
Figure 40. Waveforms From SR System Implemented in LLC Application and Using MOSFET in TO220 Package
With Long Leads − SR MOSFET channel Conduction Time is Reduced
Note that the efficiency impact caused by the error voltage
due to the parasitic inductance increases with lower
MOSFETs RDS(on) and/or higher operating frequency.
It is thus beneficial to minimize SR MOSFET package
leads length in order to maximize application efficiency. T h e
optimum solution for applications with high secondary
current Di/Dt and high operating frequency is to use
lead−less SR MOSFET i.e. SR MOSFET in SMT package.
The parasitic inductance of a SMT package is negligible
causing insignificant CS turn−off threshold shift and thus
minimum impact to efficiency (refer to Figure 41).
NCP4308
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19
Figure 41. Waveforms from SR System Implemented in LLC Application and Using MOSFET in SMT Package with
Minimized Parasitic Inductance − SR MOSFET Channel Conduction Time is Optimized
It can be deduced from the above paragraphs on the
induced error voltage and parameter tables that turn−off
threshold precision is quite critical. If we consider a SR
MOSFET with RDS(on) of 1 mW, the 1 mV error voltage on
the CS pin results in a 1 A turn-off current threshold
difference; thus the PCB layout is very critical when
implementing the SR system. Note that the CS turn-off
comparator is referred to the GND pin. Any parasitic
impedance (resistive or inductive − even on the magnitude
of mW and nH values) can cause a high error voltage that is
then evaluated by the CS comparator. Ideally the CS
turn−off comparator should detect voltage that is caused by
secondary current directly on the SR MOSFET channel
resistance. I n reality there will be small parasitic impedance
on the CS path due to the bonding wires, leads and soldering.
To assure the best efficiency results, a Kelvin connection of
the SR controller to the power circuitry should be
implemented. The GND pin should be connected to the SR
MOSFET source soldering point and current sense pin
should be connected to the SR MOSFET drain soldering
point − refer to Figure 39. Using a Kelvin connection will
avoid any impact of PCB layout parasitic elements on the SR
controller functionality; SR MOSFET parasitic elements
will still play a role in attaining an error voltage. Figure 42
and Figure 43 show examples of SR system layouts using
MOSFETs in TO220 and SMT packages. It is evident that
the MOSFET leads should be as short as possible to
minimize parasitic inductances when using packages with
leads (like TO220). Figure 43 shows how to layout design
with two SR MOSFETs in parallel. It has to be noted that it
is not easy task and designer has to paid lot of attention to do
symmetric Kelvin connection.
Figure 42. Recommended Layout When Using SR
MOSFET in TO220 Package
Figure 43. Recommended Layout When Using SR
MOSFET in SMT Package (2x SO8 FL)
NCP4308
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20
Figure 44. NCP4308 Operation after Start−Up Event
VDS = VCS
VTH_CS_RESET
VTH_CS_OFF
VTH_CS_ON
VCCON
Min OFF− time
VDRV
VCC
Min ON−time
tMIN_TOFF tMIN_TOFF
tMIN_TON
Not complete
tMIN_TOFF −
>IC
is not activated Complete
tMIN_TOFF
activates IC tMIN_TOFF is stopped
due to VDS drops
below VTH_CS_RESET
t1t2t3t4 t5t6t7 t8 t9 t10 t11t12
t13
t14
t15
Self Synchronization
Self synchronization feature during start−up can be seen
at Figure 44. Figure 44 shows how the minimum off−time
timer is reset when CS voltage is oscillating through
VTH_CS_RESET level. The NCP4308 starts operation at time
t1. Internal logic waits for one complete minimum off−time
period to expire before the NCP4308 can activate the driver
after a start−up event. The minimum of f−time timer starts t o
run at time t1, because VCS is higher than VTH_CS_RESET.
The timer is then reset, before its set minimum off−time
period expires, at time t2 thanks to CS voltage lower than
VTH_CS_RESET threshold. The aforementioned reset
situation can be seen again at time t3, t4, t5 and t6. A
complete minimum off−time period elapses between times
t7 and t8 allowing the IC to activate a driver output after time
t8.
Minimum tON and tOFF Adjustment
The NCP4308 offers an adjustable minimum on−time and
off−time blanking periods that ease the implementation of a
synchronous rectification system in any SMPS topology.
These timers avoid false triggering on the CS input after the
MOSFET is turned on or off.
The adjustment of minimum tON and tOFF periods are
done based on an internal timing capacitance and external
resistors connected to the GND pin − refer to Figure 45 for
a better understanding.
NCP4308
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21
Figure 45. Internal Connection of the MIN_TON Generator (the MIN_TOFF Works in the Same Way)
Current through the MIN_TON adjust resistor can be
calculated as:
IR_MIN_TON +Vref
RMIN_TON (eq. 5)
If the internal current mirror creates the same current
through R MIN_TON as used the internal timing capacitor (Ct)
charging, then the minimum on−time duration can be
calculated using this equation.
t
MIN_TON +CtVref
IR_MIN_TON +CtVref
Vref
R
MIN_TON
+Ct@RMIN_TO
N
(eq. 6)
The internal capacitor size would be too large if
IR_MIN_TON was used. The internal current mirror uses a
proportional current, given by the internal current mirror
ratio. One can then calculate the MIN_TON and
MIN_TOFF blanking periods using below equations:
tMIN_TON +1.00 * 10−4 *RMIN_TON [ms] (eq. 7)
tMIN_TOFF +1.00 * 10−4 *RMIN_TOFF [ms] (eq. 8)
Note that the internal timing comparator delay affects the
accuracy of Equations 7 and 8 when MIN_TON/
MIN_TOFF times are selected near to their minimum
possible values. Please refer to Figures 46 and 47 for
measured minimum on and off time charts.
Figure 46. MIN_TON Adjust Characteristics
RMIN_TON (kW)906050403020100
0
1
2
4
5
6
7
10
tMIN_TON (ms)
100
3
8070
8
9
Figure 47. MIN_TOFF Adjust Characteristics
RMIN_TOFF (kW)906050403020100
0
1
2
4
5
6
7
10
tMIN_TOFF (ms)
100
3
8070
8
9
NCP4308
www.onsemi.com
22
The absolute minimum tON duration is internally clamped
to 55 ns and minimum tOFF duration to 245 ns in order to
prevent any potential issues with the MIN_TON and/or
MIN_TOFF pins being shorted to GND.
The NCP4308 features dedicated anti−ringing protection
system that is implemented with a MIN_TOFF blank
generator. The minimum off−time one−shot generator is
restarted in the case when the CS pin voltage crosses
VTH_CS_RESET threshold and MIN_TOFF period is active.
The total off-time blanking period is prolonged due to the
ringing in the application (refer to Figure 37).
Some applications may require adaptive minimum on and
off time blanking periods. With NCP4308 it is possible to
modulate blanking periods by using an external NPN
transistor − refer to Figure 48. The modulation signal can be
derived based on the load current, feedback regulator
voltage or other application parameter.
Figure 48. Possible Connection for MIN_TON and MIN_TOFF Modulation
Maximum tON adjustment
The NCP4308Q offers an adjustable maximum on−time
(like the min_tON and min_tOFF settings shown above) that
can be very useful for QR controllers at high loads. Under
high load conditions the QR controller can operate in CCM
thanks t o this feature. The NCP4308Q version has the ability
to turn−off the DRV signal to the SR MOSFET before the
secondary side current reaches zero. The DRV signal from
the NCP4308Q can be fed to the primary side through a
pulse transformer (see Figure 4 for detail) to a transistor on
the primary side to emulate a ZCD event before an actual
ZCD event occurs. This feature helps to keep the minimum
switching frequency up so that there is better energy transfer
through the transformer (a smaller transformer core can be
used). Also another advantage is that the IC controls the SR
MOSFET and turns off from secondary side before the
primary side is turned on in CCM to ensure no cross
conduction. By controlling the SR MOSFET’s turn off
before the primary side turn off, producing a zero cross
conduction operation, this will improve efficiency.
The Internal connection of the MAX_TON feature is
shown in Figure 49. Figure 49 shows a method that allows
for a modification of the maximum on−time according to
output voltage. At a lower VOUT, caused by hard overload
or at startup, the maximum on−time should be longer than at
nominal voltage. Resistor RA can be used to modulate
maximum on−time according to VOUT or any other
parameter.
The operational waveforms at heavy load in QR type
SMPS are shown in Figure 50. After tMAX_TON time is
exceeded, the synchronous switch is turned off and the
secondary current is conducted by the diode. Information
about turned of f SR MOSFET is transferred by the DRV pin
through a sm a l l p u l s e t r a n s f o r m e r t o t h e p r im a r y s i d e w h e r e
it acts on the ZCD detection circuit to allow the primary
switch to be turned on. Secondary side current disappears
before the primary switch is turned on without a possibility
of cross current condition.
NCP4308
www.onsemi.com
23
Figure 49. Internal Connection of the MAX_TON Generator, NCP4308Q
VDS =V
CS
VTH_CS_RESET –(R
SHIFT_CS*ICS)
VTH_CS_OFF–(R
SHIFT_CS*ICS)
VTH_CS_ON–(R
SHIFT_CS*ICS)
VDRV
Min ON−time
t
Min OFF−time
tMIN_TON
tMIN_TOFF
ISEC
The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors, tMAX_TON is adjustable by RMAX_TON
Turn−on delay Turn−off delay
Primary virtual ZCD
detection delay
Max ON−time tMAX_TON
Figure 50. Function of MAX_TON Generator in Heavy Load Condition
NCP4308
www.onsemi.com
24
Power Dissipation Calculation
It is important to consider the power dissipation in the
MOSFET driver of a SR system. If no external gate resistor
is used and the internal gate resistance of the MOSFET is
very low, nearly all energy losses related to gate charge are
dissipated in the driver. Thus it is necessary to check the SR
driver power losses in the target application to avoid over
temperature and to optimize ef ficiency.
In SR systems the body diode of the SR MOSFET starts
conducting before SR MOSFET is turned−on, because there
is some delay from VTH_CS_ON detect to turn−on the driver .
On the other hand, the SR MOSFET turn off process always
starts before the drain to source voltage rises up
significantly. Therefore, the MOSFET switch always
operates under Zero Voltage Switching (ZVS) conditions
when in a synchronous rectification system.
The following steps show how to approximately calculate
the power dissipation and DIE temperature of the NCP4308
controller. Note that real results can vary due to the effects
of the PCB layout on the thermal resistance.
Step 1 − MOSFET Gate−to Source Capacitance:
During ZVS operation the gate to drain capacitance does
not have a Miller effect like in hard switching systems
because the drain to source voltage does not change (or its
change is negligible).
Figure 51. Typical MOSFET Capacitances
Dependency on VDS and VGS Voltages
Ciss +Cgs )Cgd
Crss +Cgd
Coss +Cds )Cgd
Therefore, the input capacitance of a MOSFET operating
in ZVS mode is given by the parallel combination of the gate
to source and gate to drain capacitances (i.e. Ciss capacitance
for given gate to source voltage). The total gate charge,
Qg_total, of most MOSFETs on the market is defined for hard
switching conditions. In order to accurately calculate the
driving losses in a SR system, it is necessary to determine the
gate charge of the MOSFET for operation specifically in a
ZVS system. Some manufacturers define this parameter as
Qg_ZVS. Unfortunately, most datasheets do not provide this
data. If the Ciss (or Qg_ZVS) parameter is not available then
it will need to be measured. Please note that the input
capacitance is not linear (as shown Figure 51) and it needs
to be characterized for a given gate voltage clamp level.
Step 2 − Gate Drive Losses Calculation:
Gate drive losses are affected by the gate driver clamp
voltage. Gate driver clamp voltage selection depends on the
type of MOSFET used (threshold voltage versus channel
resistance). The total power losses (driving loses and
conduction losses) should be considered when selecting the
gate driver clamp voltage. Most of today’s MOSFETs for SR
systems feature low RDS(on) for 5 V VGS voltage. The
NCP4308 offers both a 5 V gate clamp and a 10 V gate
clamp for those MOSFET that require higher gate to source
voltage.
The total driving loss can be calculated using the selected
gate driver clamp voltage and the input capacitance of the
MOSFET:
PDRV_total +VCC @VCLAMP @Cg_ZVS @fSW (eq. 9)
Where:
VCC is the NCP4308 supply voltage
VCLAMP is the driver clamp voltage
Cg_ZVS is the gate to source capacitance of the
MOSFET in ZVS mode
fsw is the switching frequency of the target
application
The total driving power loss won’t only be dissipated in
the IC, but also in external resistances like the external gate
resistor (if used) and the MOSFET internal gate resistance
(Figure 50). Because NCP4308 features a clamped driver,
it’s high side portion can be modeled as a regular driver
switch with equivalent resistance and a series voltage
source. The low side driver switch resistance does not drop
immediately at turn−off, thus it is necessary to use an
equivalent value (RDRV_SIN_EQ) for calculations. This
method simplifies power losses calculations and still
provides acceptable accuracy. Internal driver power
dissipation can then be calculated using Equation 10:
NCP4308
www.onsemi.com
25
Figure 52. Equivalent Schematic of Gate Drive Circuitry
PDRV_IC +1
2@Cg_ZVS @VCLAMP 2@fSW @ǒRDRV_SINK_EQ
RDRV_SINK_EQ )RG_EXT )Rg_intǓ)Cg_ZVS @VCLAMP @fSW @ǒVCC *VCLAMPǓ
)1
2@Cg_ZVS @VCLAMP 2@fSW @ǒRDRV_SOURCE_EQ
RDRV_SOURCE_EQ )RG_EXT )Rg_intǓ
(eq. 10)
Where:
RDRV_SINK_EQ is the NCP4308x driver low side switch
equivalent resistance (0.5 W)
RDRV_SOURCE_EQ is the NCP4308x driver high side switch
equivalent resistance (1.2 W)
RG_EXT is the external gate resistor (if used)
Rg_int is the internal gate resistance of the
MOSFET
Step 3 − IC Consumption Calculation:
In this step, power dissipation related to the internal IC
consumption is calculated. This power loss is given by the
ICC current and the IC supply voltage. The ICC current
depends o n switching frequency and also on the selected m in
tON and tOFF periods because there is current flowing out
from the min tON and tOFF pins. The most accurate method
for calculating these losses is to measure the ICC current
when CDRV = 0 nF and the IC is switching at the target
frequency with given MIN_TON and MIN_TOFF adjust
resistors. IC consumption losses can be calculated as:
PCC +VCC @ICC (eq. 11)
Step 4 − IC Die Temperature Arise Calculation:
The die temperature can be calculated now that the total
internal power losses have been determined (driver losses
plus internal IC consumption losses). The package thermal
resistance is specified in the maximum ratings table for a
35 mm thin copper layer with no extra copper plates on any
pin (i.e. just 0.5 mm trace to each pin with standard soldering
points are used).
The DIE temperature is calculated as:
TDIE +ǒPDRV_IC )PCCǓ@RqJ−A )TA(eq. 12)
Where:
PDRV_IC is the IC driver internal power dissipation
PCC is the IC control internal power
dissipation
RqJA is the thermal resistance from junction to
ambient
TAis the ambient temperature
NCP4308
www.onsemi.com
26
PRODUCT OPTIONS
OPN Package UVLO [V] DRV clamp [V] Pin 5 function Usage
NCP4308ADR2G SOIC8 4.5 4.7 NC
LLC, CCM flyback, DCM flyback, QR,
QR with primary side CCM control
NCP4308AMTTWG WDFN8 4.5 4.7 NC
NCP4308DDR2G SOIC8 4.5 9.5 NC
NCP4308DMNTWG DFN8 4.5 9.5 NC
NCP4308DMTTWG WDFN8 4.5 9.5 NC
NCP4308QDR2G SOIC8 4.5 9.5 MAX_TON QR with forced CCM from secondary side
ORDERING INFORMATION
Device Package Package marking Packing Shipping†
NCP4308ADR2G SOIC8 NCP4308A SOIC−8
(Pb−Free) 2500 /Tape & Reel
NCP4308DDR2G NCP4308D
NCP4308QDR2G NCP4308Q
NCP4308DMNTWG DFN8 4308D DFN−8
(Pb−Free) 4000 /Tape & Reel
NCP4308AMTTWG WDFN8 EA WDFN−8
(Pb−Free) 3000 /Tape & Reel
NCP4308DMTTWG ED
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ÉÉ
ÉÉ
ÉÉ
DFN8, 4x4
CASE 488AF−01
ISSUE C
DATE 15 JAN 2009
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL CON-
STRUCTIONS FOR TERMINALS.
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.25 0.35
D4.00 BSC
D2 1.91 2.21
E4.00 BSC
E2 2.09 2.39
e0.80 BSC
K0.20 −−−
L0.30 0.50
D
B
E
C0.15
A
C0.15
2X
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Ç
Ç
ÇÇ
ÇÇ
Ç
Ç
Ç
C
A
(A3)
A1
8X
SEATING
PLANE
C0.08
C0.10
Ç
ÇÇ
Ç
Ç
Ç
e
8X L
K
E2
D2
b
NOTE 3
14
58
8X
0.10 C
0.05 C
AB
1
SCALE 2:1
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
ALYWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
PIN ONE
REFERENCE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8X
0.63
2.21
2.39
8X
0.80
PITCH
4.30
0.35
(Note: Microdot may be in either location)
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÇÇÇ
A1
A3
L
ÇÇÇ
ÇÇÇ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
L1 −−− 0.15
DETAIL B
NOTE 4
DETAIL A
DIMENSIONS: MILLIMETERS
PACKAGE
OUTLINE
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON15232D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
DFN8, 4X4, 0.8P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
ÍÍ
ÍÍ
ÍÍ
C
A
SEATING
PLANE
D
E
0.10 C
A3
A
A1
0.10 C
WDFN8 2x2, 0.5P
CASE 511AT−01
ISSUE O
DATE 26 FEB 2010
SCALE 4:1
DIM
A
MIN MAX
MILLIMETERS
0.70 0.80
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D
E
e
L
PIN ONE
REFERENCE
0.05 C
0.05 C
A0.10 C
NOTE 3
L2
e
b
B
4
8
8X
1
5
0.05 C
L1
2.00 BSC
2.00 BSC
0.50 BSC
0.40 0.60
--- 0.15
BOTTOM VIEW
L
7X
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ÉÉÉ
ÉÉÉ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL B
DETAIL A
L2 0.50 0.70
B
TOP VIEW
SIDE VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.78
7X
DIMENSIONS: MILLIMETERS
0.30 PITCH
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
8X
1
PACKAGE
OUTLINE
RECOMMENDED
XX = Specific Device Code
M = Date Code
G= Pb−Free Device
XXMG
G
1
0.88
(Note: Microdot may be in either location)
2X
2X
8X
e/2
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON48654E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
WDFN8, 2X2, 0.5 P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
8
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(Pb−Free)
XXXXX
ALYWX
G
1
8
IC
(Pb−Free)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
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