von MAXKLMI Voltage-Output, 12-Bit DACs with Internal Reference __ CCGG al DeScrptiorn Features The MAX507/MAX508 are complete 12-bit, voitage- @ 12-Bit Voltage Output output digital-to-analog converters (DACs). The DAC @ Internal Voltage Reference output voltage and the reference have the same polarity, allowing single-supply operation. Both DACs include an @ Fast uP Interface internal buried-zener reference. integrating a DAC, @ 12 (MAX507) and 8+4 (MAX508) Data-Bus Widths voltage-output amplifier, and reference on one monolithic @ Single +12V to Dual +15V Supply Operation device greatly enhances reliability over multi-chip circuits. greally P @ 20- and 24-Pin DIP and Wide SO Packages Double-buffered logic inputs interface easily to micro- processors (uPs). Data is transferred into the input 8SOSXVIN/ZLOSXVIN register either from a 12-bit-wide data bus (MAX507) for ________. Ordering Information 16-bit wPs, or in a right-justified (8+4)-bit format (MAX508) for 8- or 16-bit uPs. All logic signals are level PART TEMP. RANGE PACKAGE ener triggered and are TTL and CMOS compatible. Interface (LSBs) timing specifications insure compatibility with all MAXSO7ACNG _0C to +70C 24 Narrow Plastic DIP 1/2 common pPs. MAXSO7BCNG = 0C: 10 +70C_ 24 Narrow Plastic DIP. 3/4 The DACs are specified and tested for both dual- and MAXS5O07ACWG = O ta +70C. 24 Wide SO +1/2 single-supply operation. Usable supplies range from X507BCW Ot i Wi + single +12V to dual +15V. MAX507BCWG = 0C to +70C_ 24 Wide SO +3/4 MAX507BC/D 0C to +70C Dice* +3/4 On-board gain-setting resistors allow three output- voltage ranges: OV to +5V and OV to +10V can be MAX507AENG -40C to +85C 24 Narrow Plastic DIP) +1/2 generated when using either single or dual supplies. MAX507BENG -40C to+85C 24 Narrow Plastic DIP +3/4 With dual supplies, 5V is also available. The output MAXSO07AEWG -40C to +85C 24 Wide SO +4/2 amplifier can drive a 2kQ load to +10V. . . MAX507BEWG -40C to +85C 24 Wide SO 43/4 Applications MAXS507AMRG -55C to +125C 924 Narrow CERDIP** 41/2 MAX507BMRG -55C to +125C 24 Narrow CERDIP** 43/4 Digital Offset and Gain Adjustment Industrial Controls Arbitrary Function Wavetorm Generators Ordering Information continued on page 12. ; . Contact factory for dice specifications. Automatic Test Equipment ** Contact factory for availability and processing to MIL-STD-883. Automated Calibration Machine and Motion Control Functional Diagram __ssCSCSCS:sC &Pinn. Ccornfigurattilorns Von REFOUT aE gy a TOP VIEW < 23 Vss L2 24) Vous Pre Rors C2] 23] Rig VREF od AEFOUT [3] [22} Vou \ Vout AGND La} ~WLAKIW [et] CLR - D1 MAX507 20] LDAC 4 pA 1, p10 =| Fis] wa AGND+ | i Vss 09 (7 a8] CS { 7 08 Ca 7] 00 18 a csH DAC LATCH CLR p7 [a] 16} 01 49 o6 (a 75] D2 WR CONTROL MAXIsvl RS Fool | LOGIC TF MAX507 D5 [11 14] D3 LDAGC 14 INPUT LATCH DGND [42 ria] D4 DIP/SO wl [st DO...D11 OGND MAX508 on last page MAKI VI Maxim Integrated Products 1 SWANK VI is a registered trademark of Maxim Integrated Products.MAX507/MAX508 Voltage-Output, 12-Bit DACs with Internal Reference ABSOLUTE MAXIMUM RATINGS Vppto AGND ...... cece eee eee eee eee -0.3V, +17V Vpp toDGND ........ cee ee eee ee eee -0.3V, +17V VDDtO VSS 2c. cece ee eee tee ee ee eens -0.3V, +34V AGNDtoDGND ...... ccc cece eee eee nee -0.3V, Vpp Digital Input Voltage to GND .......... -0.3V, Vop +0.3V Vout to AGND (Note 1) 2... 2... cc ee ee eee Vss, Vop VouT to Vsg (Note 1) 2... ee eee eee eee OV, +34V VouT to Vop (Note 1) REFOUT to AGND (Note 1) Continuous Power Dissipation (any package) to +76C derate above +75C Operating Temperature Ranges: MAX507_C__, MAX508_C_ ...........-. MAX507_E__, MAX508_E__ 0C to +70C cee eee eee -40C to +85C MAX507_M_, MAX508_M__ ......... -55C to +125C Storage Temperature Range ........... -65C to +150C Lead Temperature (soldering, 10sec) ........... +300C Note 1: The output can be shorted to either supply rail if the package power dissipation is not exceeded. Typical short-circuit current to AGND is 25mA. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Single Supply (Vop = +11.4V to +15.75V, Vss = AGND = DGND = OV, RL = 2kQ, Cr, = 100pF, REFOUT unloaded, all grades, Ta = TmIN to Tmax, unless otherwise noted.) PARAMETER SYMBOL L CONDITIONS MIN TYP MAX | UNITS STATIC PERFORMANCE Resolution N 12 Bits MAX507/508A +1/2 Ta = +25C MAX507/508B +3/4 Relative Accuracy INL LSB MAX507/508A +3/4 TA = TMIN to TMAX MAX507/508B +1 Differential Nonlinearity DNL +1 LSB Ta = +25C +3 Unipolar Offset Error LSB Ta = TMIN to TMAX +5 DAC Gain Error +2 LSB Ta = +25C +0.2 Full-Scale Output Voltage Error Vop = +12V or +15V %FSR Ta = TMIN to TMAXx +0.6 Ta = +25C +012 Full-Scale Output Voltage Change Vpp over full range %FSR/V Ta = TIN to TMAX +0.2 Full-Scale 7 MAX507/508_C/E +30 ppm ull-Scale Tempco 0 p MAX507/508_M +490 |FSR/C Unipolar Offset Error Change Vpp = +12V + 5% or +15V + 5% +1 mV MIA XKI/VIVoltage-Output, 12-Bit DACs with Internal Reference ELECTRICAL CHARACTERISTICS (continued) Single Supply (Vpp = +11.4V to +15.75V, Vgs = AGND = DGND = OV, RL = 2kQ, CL = 100pF, REFOUT unloaded, all grades, Ta = TMIN to Tmax, unless otherwise noted.) PARAMETER | symeot | CONDITIONS MIN TYP MAX | UNITS REFERENCE Reference Output Vop = +12V or +15V_ | Ta = +25C 4.99 5.01 Vv Reference Voltage Change VOD toe 5% or iL - *28C 2 mv/V A= TMIN to TMAX 6 Reference Temperature MAXS507/508_C/E +30 Coefficient MAX507/508_M +40 ppc Reference Load Sensitivity ILOAD = OvA to 100uA +1 mV ANALOG OUTPUT Ranges (Note 2) tos Vv 0 to 10 Output Range Resistors 15 30 kQ DC Output Impedance 0.5 Q Short-Circuit Current 40 mA DYNAMIC PERFORMANCE (Note 3) Voltage-Output Slew Rate 2 V/us Vout Settling Time To +1/2 LSB for full-scale change 5 us Digital Feedthrough 10 nv-s Digtal-to-Analog Glitch Impulse Major carry transition 30 nV-s Output Load Resistance (Note 2) Vout = OV to +10V 2 kQ POWER SUPPLIES Vpo Range For specified performance 11.4 15.75 Vv Ta = +25C 9 Ipp Outputs unloaded mA Ta = Ton to Tmax 12 MUA XKIvi 8OSXVW/ZOSXVNMAX507/MAX508 Voltage-Output, 12-Bit DACs with Internal Reference ELECTRICAL CHARACTERISTICS Dual Supply (Vpp = +11.4V to +15.75V, Vss =-11.4V to -15.75V, DGND = AGND = OV, Ri = 2kQ, CL = 100pF, REFOUT unloaded, all grades, Ta = TMIN to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX [units STATIC PERFORMANCE Resolution N 12 Bits MAX507/508A +1/2 Ta = +25C / MAX507/508B 43/4 Relative Accuracy INL LSB T tT tot MAX507/508A +3/4 = TMIN to TMAX A MAX507/508B +1 Differential Nonlinearity DNL +H LSB Ta = +25C +2 MAX507/508A T T tot 14 A= TMIN to TMAX + Bipolar Zero Offset Error BZOE LSB Ta = +285C +3 MAX507/508B Ta = TMIN to TMAX +5 DAC Gain Error +2 LSB Vpp = +15V, Ta = +25C +0.2 Vgg = -15V Ta = TmMIN to TMAX +0.6 Full-Scale Output Voltage Error %FSR Vpp = +12V, Ta = +25C +0.2 Vss = -12V Ta = Tmin to Tmax +0.6 Vppb = +12V + 5% or +15V + 5% Ta = +25C +012 fle. Vss = -12V or -15V Full-Scale Output Change Ss MF SR/V with Vpp Ta = TMIN to TMAX +0.2 Full-Scale Output Change Vss = -12V + 5% or -15V + 5% 6 with Vgs VSS | Vpp = +12V or +5V 0.01 |%FSR/V Full-Scale 7: MAX507/508_C/E +30 ppm ull-Scale Tempco P MAX507/508_M +40 |FSR/C Vpp = +12V + 5% or +15V + 5% +4 ; Vss = -12V or -15V ~ Bipolar Zero Offset Change mv Vss = -12V + 5% or -15V + 5% +4 Vop = +12V or +15V ~ REFERENCE Reference Output Vpp = +12V or +15V_ | Ta = +25C 4.99 .01 Vv Ta = +25C 2 Reference Output Change Vpp over full range mv/V Ta = TMIN to TMAx 6 Reference Temperature MAX507/508_C/E 30 ~ ppm/c Coefficient MAX507/508_M +40 Reference Load Sensitivity ILOAD = OA to 100uA H1 mV MIA KIWIVoltage-Output, 12-Bit DACs with Internal Reference ELECTRICAL CHARACTERISTICS (continued) Qual Supply (Vpp = +11.4V to +15.75V, Vgg = -11.4V to -15.75V, DGND = AGND = OV, RL = 2k, Cr = 100pF, REFOUT unloaded, all grades, Ta = TmIN to Tmax, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX | UNITS ANALOG OUTPUT Ranges (Notes 2, 4) 0 to ore Vv Output Range Resistors 15 30 kQ DC Output Impedance 0.5 Q Short-Circuit Current 40 mA DYNAMIC PERFORMANCE (Note 3) Voltage-Output Slew Rate 2 VWus Vout Settling Time to +1/2 LSB 5 us Digital Feedthrough 10 nV-s Digtal-to-Analog Glitch Impulse Major carry transition 30 nv-s Output Load Resistance VouT = -5V to +10V 2 kQ POWER SUPPLIES Vpp Range For specified performance 11.4 15.75 Vv Vss Range For specified performance -11.4 -15.75 Ta = +25C 9 IpD Outputs unloaded mA Ta = TmINn to TMAX 12 : Ta = +25C 3 Iss Outputs unloaded mA Ta = TmINn to TMAX 8 SVIA Ki svi 5 8OSXVAW/ZOSXVWMAX507/MAX508 Voltage-Output, 12-Bit DACs with Internal Reference ELECTRICAL CHARACTERISTICS Single or Dual Supply (Vpp = +11.4V to +15.75V, Vss = OV to -15.75V, DGND = AGND = OV, REFOUT unloaded, RL = 2kQ, CL = 100pF, all grades, Ta = TmIN to Tmax, unless otherwise noted.) PARAMETER | SYMBOL L CONDITIONS MIN TYP MAX | UNITS DIGITAL INPUTS VINH 2.4 Vv VINL 0.8 Ta = +25C + Input Current tN DO-D11 uA TA = TMIN to TMAX +10 _ ____ _ _ | Ta = +25C +1 HiNH CS, WR, LDAC, CLR uA Ta = TmIN to TMAX 410 _ ___ | Ta = +25C +150 TINE CS, WR, LDAC, CLR LA Ta = TMIN to TMAX +200 Digital Input Capacitance 8 pF TIMING CHARACTERISTICS (All grades, Ta = Twin to Tmax, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS | __ Ta = +25C 80 CS Pulse Width (Note 5) t ns Ta = TMIN to Tmax 100 _ Ta = +25C 80 WR Pulse Width te ns Ta = TmMIN to Tmax 100 CS to WR Setup Time (Note 5) tg 0 ns CS to WR Hold Time (Note 5) ta 0 ns ____ Ta = +25C 100 Data to WR Setup Time t5 ns Ta = TmINn to Tmax 110 Data to WR Hold Time te 10 ns a Ta = +25C 80 LDAC Pulse Width t7 ns Ta = TMIN to TMAX 100 __ Ta = +25C 80 CLR Pulse Width (MAX507) tg ns Ta = TMIN to Tmax 100 Note 2: Vout must be less than (Vpp - 2.5V). Note 3: Dynamic performance is included for design guidance, not subject to test. Note 4: The OV to +5V or +10V ranges can be used with Vss = -5V with no degradation. Note 5: CS = CSLSB and CSMSB for MAX508. IVA KiviVoltage-Output, 12-Bit DACs _ititCC@DS habit edd Description Digital-to-Analog Converters The MAX507/MAX508 are 12-bit, voltage-output DACs. The DAC output voltage has the same polarity as the reference, allowing single-supply operation. The basic DAC circuit consists of a laser-trimmed, thin- film, R-2R resistor array with NMOS voltage switches (Figure 1). Output-Buffer Amplifier The output amplifier is noninverting and configurable for a gain of 1 or 2. Three output voltage ranges can be configured for: OV to +5V, OV to +10V, and -5V to +5V. The output amplifier can drive 2kQ in parallel with 100pF connected to GND. with Internal Reference The MAX507/MAX508 can operate from a single supply with a OV to +5V or a OV to +10V output range by tying Vss to OV. However, the speed and current-sinking capability of the amplifier decreases as the output falls within 0.5V of Vss. Speed and current-sinking capability can be maintained by including a negative supply. Table 1 lists the allowable single and dual supplies for each range. The output amplifiers small-signal bandwidth is typically 2MHz. Output noise is approximately 25nW//Hz at 1kHz, and output broadband noise is approximately 25uVRMS. Rip VREF t AGND 55 Figure 1. Simplified MAX507 DAC Circuit Table 1. Output Voltage Range vs. Supply Voltage Single Supply Dual Supply Range Vpp Vpp Vss OV to +5V +11.4V to +15.75V +11.4V to +15.75V -4,.5V to -15.75V OV to +10V +14.25V to +15.75V +14.25V to +15.75V ~4.5V to -15.75V -5V to +5V +11.4V to +15.75V -11.4V to -15.75V SVWIA XI svi 7 8O0SXVN/ZLOSXVWMAX507/MAX508 Voitage-Output, 12-Bit DACs with Internal Reference Voltage Reference The voltage at REFOUT is 5V + 10mvV at +25C. The reference is internally connected to the DAC and is buffered to accommodate the DACs variable impedance. This buffer is capable of driving the DAC, the Rors resistor, and up to 500uA of external current. MAX507/ MAXS08 specifications are determined with the internal reference. The reference should be decoupled at REFOUT with 10Q in series with the recommended decoupling capacitors, 10uF in parallel with 0.1yF. Digital Inputs and Interface Logic All logic inputs are compatible with both TTL and 5V CMOS logic. Supply current is specified for TTL input levels, but is reduced by about 450uA when the data inputs are driven near DGND or Vop. The control inputs (CLR, LDAC, WR, CS, CSMSB, and CSLSB) each draw 100A from Ipp when low. MAX507 Interface Table 2 is the MAX507 truth table. The MAX507 accepts a 12-bit input word that can_be latched or transferred directly to the DAC. CS and WR control the input latch, and LDAC transfers information from the input latch to the DAC latch. Table 2. MAX507 Truth Table CLR |LDAC| WR cs Function 1 0 0 0 Both latches transparent 1 1 xX Both latches latched 1 1 x 1 Both latches latched 1 1 0 0 Input latch transparent 4 4 1 0 Input latch latched 1 0 1 1 DAC latch transparent 1 t 1 1 | DAC latch latched 0 X X X | DAC latch all Os 1 1 1 DAC latch latched with Os; output at OV or -5V t 0 0 | | Both latches transparent; output follows input data 1 = High State X = Dont Care 0 = Low State t = Rising Edge The input latch is transparent when CS and WR are low; the DAC latch is transparent when LDAC is low. Data is latched_within the input latch on the rising edge of WR when CS is low. The rising edge of LDAC latches data into the DAC when CS and WR are low. After CS and WR are high, LDAC must be held low for t7 or longer (Figure 2). 1 _. ~t ty CS | >| ty tomy WR 7 LDAC ts | te DATA VALID DATA NOTES: 1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V, t, - ty = 5ns. 2. TIMING MEASUREMENT REFERENCE LEVEL IS Vina + Vine _2 _ 3. IF LDAC 1S ACTIVATED WHILE WR IS LOW THEN LDAC MUST STAY LOW FOR t7 OR LONGER AFTER WR GOES HIGH Figure 2. MAX507 Timing Diagram The DAC latch is reset to zeros with CLRlow. CLRacts as a zero override when the input latch and DAC latch are transparent. Then, alow-to-high CLRtransition loads all zeros into the DAC latch, and the output remains low (OV to -5V). MAX5068 Interface The MAX508s 8-bit-wide data bus interfaces with 8-bit puPs. The MAX508 contains an input latch and a DAC latch. The data held in the DAC latch determines the output of the DAC. Table 3 is the MAX508 truth table, Figure 3 shows the input control logic, and Figure 4 shows the write-cycle timing. SVIA KI S/vIVoltage-Output, 12-Bit DACs Table 3. MAX508 Truth Table CSLSB | CSMSB/| WR |LDAC 0 1 Function 1 Loads LSBs to input latches 1 Locks LSBs in input latches Locks LSBs in input latches ala Loads MSBs to input latches = Locks MSBs in input latches oO;/oO1ol;| oO Locks MSBs in input latches | =a{s/lolo|alja = Loads input into DAC latch aialayalilwlo Locks input into DAC tatch = a oO;~7;o} Loads MSBs to input latches and loads input into DAC latch No data transfer 1 1 1 1 1 = High State 0 = Low State t = Rising Edge Right-justified data is loaded into the MAX508 using CSMSB, CSLSB, and WR. Data can be latched into the input latch on the rising edge of WR for the most significant bit (MSB) and least significant bit (LSB), or on the rising edge of CSMSB for the MSB and CSLSB for the LSB. Either the MSB or the LSB can be loaded first. The complete, 12-bit word loads into the DAC register when LDAC is tow, and latches on LDACs rising edge. LDAC is asynchronous and independent of WR, so it is ideal for simultaneously updating multiple MAX508 outputs. Because LDAC can occur during a write cycle, it must stay low for t7 (or longer) after WR goes high to ensure correct data is latched to the output. The MAX508 output can be updated in two write cycles by tying CSMSB and LDAC. In this automatic transfer mode, CSLSB and WR latch the lower 8 bits into the input latch; then CSMSB, WR, and LDAC load the upper 4 bits into the input latch and transfer the 12-bit word into the DAC latch. Alternatively, the MAX507 can be updated in two writes by tying CSLSB to LDAC if the upper 4 bits are input first, followed by the lower 8 bits. sVUlAKisvi with Internal Reference ioac[>o- DAC clR-_______| _ LATCH WR INPUT s yo LATCH D0-07 Figure 3a. MAX507 Input Control! Logic | LDAC DAC LATCH CSMSB J>4 nL WwR LOWER 8 BITS 4 OF DATA LATCH Po DO-D?7 Le Figure 3b. MAX508 Input Control Logic 8OSXVW/ZOSXVNMAX507/MAX508 Voltage-Output, 12-Bit DACs with Internal Reference |< t} _| +8V CSLSB ~ N fo , CSMSB. ty | ti} |<< tp | t3 Da |< tp >| ov ov ov +5V ov ey ty < DATA IN 2. TIMING MEASUREMENT REFERENCE LEVEL |S oY ts | ts VALID DATA NOTES: 1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V, t, = ty = Sns. <" >| +5y OV ts +5V VALID DATA ov Figure 4. MAX508 Timing Diagram Unipolar Configuration The MAX507/MAX508 are set up for a OV to +5V unipolar output range by connecting Rors, RrB, and Vout (Figure 5). The converters operate from either a single or a dual supply in this configuration. See Table 4 for the DAC-latch contents (input) vs. analog output (output). In this range, 1LSB = VREF (2-72). +15V 102 Yoo AWA REFOUT Ross 1QuF T oo O4ApF AGND Ree L L_| DGND = Vout Vout Ves OV TO -15V Figure 5. Unipolar Configuration (OV to +5V Output) 10 Table 4. Unipolar-Code Table (OV to +5V Output) INPUT OUTPUT 4095 1111 1111 4111 VREF) ( ) 4096 2049 1000 1 VREF) 0000 000 (VRE ) 4096 2048 F) = 1000 0000 0000 (VRE ) 4096 +VREF/2 4 0111 4411 1111 (ver) oo? 4096 1 0000 0000 0001 VREF) ( } 4096 0000 0000 0000 OV A OV to +10V unipolar output range is set up by connecting Rors to AGND and Rep to Vout (Figure 6). See Table 5 for the DAC-latch contents (input) vs. analog output (output). The MAX507/MAX508 operate from either a single or a dual supply in this configuration. tn this range, 1LSB = VREF (2-11). MVIA KI viVoltage-Output, 12-Bit DACs with Internal Reference Bipolar Configuration +15V A-5V to +5V bipolar range is set up by connecting ROFS | to REFOUT and Rpg to Vout, and operating from dual Voo power supplies (Table 1). See Table 6 for the DAC-latch 10Q i \ row REFOQUT contents (input) vs. analog output (output). In this O1uF = == 10uF range, 1LSB = (2) VREF (2-") = (VREF) 1/2048. c* Rors Rra : = Table 6. Bipolar-Code Table (-5V to +5V Output) AGND Vout Vour a DGND INPUT OUTPUT 2047 Vss 1111 1411 41 (+VREF) as OV TO -15V 1000 ~=0000~=-0001 (+VREF) sas Figure 6. Unipolar Configuration (OV to +10V Output) 1000-0000 0000 ov 1 Table 5. Unipolar-Code Table (OV to +10V Output) 0111 1111 1111 (-VREF) 3048 INPUT OUTPUT 2047 0000 0000 0001 (-VREF) _ 4095 2048 1111 4914 1111 +2 (VREF) 4096 2048 0000 0000 0000 (-VREF) 3048 = -VREF 2049 REF) 1000 0000 0001 +2 (VRE ) 7096 2048 _ 1000 0000 0000 +2 (VREF) 4096 =+VREF 0111 1114 1111 +2 VREF) 2247 ( 4096 1 0000 0000 0001 +2 (VREF) 4096 0000 0000 0000 OV SVIAN KI svI " 8OSXVW/ZOSXVNVoltage-Output, 12-Bit DACs with Internal Reference MAX507/MAX508 _____ Pin Configurations (continued) _ Ordering Information (continued) PIN- ERROR PART TEMP. RANGE PACKAGE (LSBs) TOP VIEW MAXS508ACPP ac to +70C 9 20 Narrow Plastic DIP _+1/2 Vs (4 Al P20] Voor MAX508BCPP 0C to +70C = 20 Narrow Plastic DIP} +3/4 Rors L2 19) Reg MAXS508ACWP 0C to +70C +=20 Wide SO +12 REFOUT (3 18} Voo._ MAX508BCWP 0C. to +70C_20 Wide SO +3/4 AGND C4] MAK IWI [97] LDAC o7 [3] MAX508 16] WR MAX508B8C/D OC to +70C Dice +3/4 06 (6 | 175] CSLSB MAX50BAEPP -40C to +85C 20 Narrow Plastic DIP. +1/2 os (Z] 14] CSMSB MAXSO8BEPP -40C to +85C 920 Narrow Plastic DIP +3/4 D4 [a] [43] DO/08 D3/D11 el 112] 01/D9 MAXS08AEWP -40C to +85C 920 Wide SO V/2 DEND [30] 47] 02/010 MAXS50BBEWP -40C to +85C 20 Wide SO +3/4 DIP/SO MAX508AMJP -55C to +125C 920 Narrow CERDIP** +1/2 MAXS508BMJP -55C to +125C 20 Narrow CERDIP** +3/4 * Contact factory for dice specifications. a oo o. ; . . ** Contact factory for availability and processing to MIL~STD-883. Maxim) cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1991 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products