AD9154 Data Sheet
Rev. C | Page 40 of 124
To avoid this common-mode current draw, use a 50% duty-
cycle periodic SYSREF± signal with ac coupling capacitors. If
ac-coupled, the ac coupling capacitors combine with the
resistors shown in Figure 50 to create a high-pass filter with an
RC time constant of τ = RC. Select C such that τ > 4/SYSREF
frequency. In addition, the edge rate must be sufficiently fast—
at least 1.3 V/ns is recommended per Table 5.
3kΩ ~600mV
1.2V
SYSREF+
SYSREF– 3kΩ
11389-014
Figure 50. SYSREF± Input Circuit
LMFC Synchronization Modes Overview
The AD9154 supports various LMFC sync processing modes.
These modes are one-shot, continuous, windowed continuous,
and monitor modes. All sync processing modes perform a
phase check to see that the LMFC is phase aligned to an
alignment edge. In Subclass 1, the SYSREF± pulse acts as the
alignment edge; in Subclass 0, an internal processing clock acts
as the alignment edge. If the signals are not in phase, a clock
rotation occurs to align the signals. The sync modes are described
in the following sections. See the LMFC Synchronization
Procedure section for details on the procedure for syncing the
LMFC signals.
One-Shot Sync Mode (SYNCMODE = 0x1)
In one-shot sync mode, a phase check occurs on only the first
alignment edge received after the sync machine is armed. If the
phase error is larger than a specified window error tolerance, a
phase adjustment occurs. Though an LMFC synchronization
occurs only once, the SYSREF± signal can still be continuous.
Continuous Sync Mode (SYNCMODE = 0x2)
Continuous mode must only be used in Subclass 1 with a
periodic SYSREF± signal. In continuous mode, a phase
check/alignment occurs on every alignment edge.
Continuous mode differs from the one-shot mode in two ways.
First, no SPI cycle is required to arm the device; the alignment
edge seen after continuous mode is enabled results in a phase
check. Second, a phase check (and when necessary, clock rotation)
occurs on every alignment edge in continuous mode. The one
caveat to the previous statement is that when a phase rotation cycle
is underway, subsequent alignment edges are ignored until the
logic lane is ready again.
The maximum acceptable phase error (in DAC clock cycles)
between the alignment edge and the LMFC edge is set in the
error window tolerance register. If continuous sync mode is
used with a nonzero error window tolerance, then a phase
check occurs on every SYSREF± pulse, but an alignment occurs
only if the phase error is greater than the specified error
window tolerance. If the jitter of the SYSREF± signal violates
the setup and hold time specifications given in Table 5, and
therefore causes phase error uncertainty, the error tolerance can
be increased to avoid constant clock rotations. Note that this
means that the latency is less deterministic by the size of the
window. If the error window tolerance must be set above 3,
Subclass 0 with a one-shot sync is recommended.
For debug purposes, SYNCARM (Register 0x03A, Bit 6)
informs the user that alignment edges are being received in
continuous mode. Because the SYNCARM bit is self cleared
after an alignment edge is received, the user can arm the sync
(SYNCARM (Register 0x03A, Bit 6) = 1), and then read back
SYNCARM. If SYNCARM = 0, the alignment edges are being
received and phase checks are occurring. Arming the sync
machine in this mode does not affect the operation of the device.
One-Shot Then Monitor Sync Mode (SYNCMODE = 0x9)
In one-shot then monitor mode, the user can monitor the phase
error in real time. Use this sync mode with a periodic SYSREF±
signal. A phase check and alignment occurs on the first alignment
edge received after the sync machine is armed. On all subsequent
alignment edges, the phase is monitored and reported, but no
clock phase adjustment occurs.
The phase error can be monitored on the CURRERR_L register,
(Register 0x03C, Bits[7:0]). Immediately after an alignment
occurs, CURRERRx = 0 to indicate that there is no difference
between the alignment edge and the LMFC edge. On every
subsequent alignment edge, the phase is checked. If the alignment
is lost, the phase error is reported in the CURRERR_L register in
DAC clock cycles. If the phase error is beyond the selected window
tolerance (Register 0x034, Bits[2:0]), one bit of Register 0x03D,
Bits[7:6] is set high, depending on whether the phase error is on
low or high side.
When an alignment occurs, snapshots of the last phase error
(Register 0x03C, Bits[3:0]) and the corresponding error flags
(Register 0x03D, Bit 7 and Bit 6]) are placed into readable
registers for reference (Register 0x038 and Register 0x039,
respectively).
LMFC Synchronization Procedure
The procedure for enabling the LMFC sync is as follows:
1. Set Register 0x008 to 0x03 to sync the LMFC for both DAC
duals (DAC0/DAC1 and DAC2/DAC3)
2. Set the desired sync processing mode. The sync processing
mode settings are listed in Table 40.
3. For Subclass 1, set the error window according to the
uncertainty of the SYSREF± signal relative to the DAC
clock and the tolerance of the application for deterministic
latency uncertainty. The sync window tolerance settings
are given in Table 41.
4. Enable sync by writing 1 to SYNCENABLE
(Register 0x03A, Bit 7).