AMIS-53050 Frequency Agile Transceiver Data Sheet
AMIS-53050 Frequency Agile Transceiver
Data Sheet
1
AMI Semiconductor – Jan. 07, M-20639-002
www.amis.com
AMIS-53050 Frequency Agile Transceiver Data Sheet
Table of Contents
1.0 Overview of the AMIS-53050..............................................................................................................................................................5
1.1 Typical Applications..........................................................................................................................................................................5
1.2 Key Features ....................................................................................................................................................................................5
1.3 Technical Features ...........................................................................................................................................................................5
1.4 Circuit Overview................................................................................................................................................................................6
1.4.1. Transmitter ..........................................................................................................................................................................................................6
1.4.2. Receiver...............................................................................................................................................................................................................6
2.0 Operational Specifications ................................................................................................................................................................8
2.1 Absolute Maximum Ratings..............................................................................................................................................................8
2.2 Recommended Operating Conditions...............................................................................................................................................8
2.2.1. Parametric Voltage and Current Levels............................................................................................................................................................8
2.3 Operational Specifications ................................................................................................................................................................9
3.0 Block Diagrams ................................................................................................................................................................................12
3.1 AMIS-53050 Overall Block Diagram...............................................................................................................................................12
3.2 Package..........................................................................................................................................................................................12
3.2.1. Pin Definition.....................................................................................................................................................................................................12
3.2.2. Block Diagram/Pin Definition...........................................................................................................................................................................13
3.2.3. Physical Characteristics...................................................................................................................................................................................14
4.0 Acronyms..........................................................................................................................................................................................15
5.0 Hardware Description ......................................................................................................................................................................16
5.1 Frequency.......................................................................................................................................................................................16
5.2 Receiver..........................................................................................................................................................................................19
5.2.1. Receiver Low Noise Amplifier (LNA)...............................................................................................................................................................20
5.2.2. IF Filter...............................................................................................................................................................................................................21
5.2.3. Data Filter...........................................................................................................................................................................................................21
5.3 Transmitter......................................................................................................................................................................................21
5.4 Single Antenna Option....................................................................................................................................................................22
5.5 Peak................................................................................................................................................................................................24
5.6 ADC................................................................................................................................................................................................25
5.7 Control Interface Serial Bus............................................................................................................................................................25
5.8 TX/RX Data Interface Serial Bus ....................................................................................................................................................26
5.9 System Clock..................................................................................................................................................................................28
5.10 Power and Grounds......................................................................................................................................................................29
5.11 Design Suggestions......................................................................................................................................................................29
6.0 User’s Guide .....................................................................................................................................................................................31
6.1 Control Serial Interface Bus Descripti on .........................................................................................................................................31
6.1.1. Control Interface Protocol................................................................................................................................................................................31
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.1.2. Serial Control Interface: Configuration...........................................................................................................................................................34
6.1.3. 3-Wire Interface Mode.......................................................................................................................................................................................35
6.1.4. I2C Interface .......................................................................................................................................................................................................37
6.2 Command Regist er.........................................................................................................................................................................40
6.3 Functional Flow Diagrams..............................................................................................................................................................41
6.4 Frequency.......................................................................................................................................................................................46
6.4.1. Frequency Control ............................................................................................................................................................................................46
6.4.2. 10kHz Oscillator................................................................................................................................................................................................50
6.4.3. System Clock .....................................................................................................................................................................................................50
6.4.4. Quick Start.........................................................................................................................................................................................................51
6.4.5. Self Calibration..................................................................................................................................................................................................51
6.5 Receiver..........................................................................................................................................................................................54
6.5.1. Receiver Circuit Brief Overview ......................................................................................................................................................................54
6.6 Transmitter.....................................................................................................................................................................................64
6.6.1. TX Config...........................................................................................................................................................................................................65
6.6.2. Output Power.....................................................................................................................................................................................................65
6.6.3. Preamble Length...............................................................................................................................................................................................66
6.6.4. FM Transmit Data Shaping...............................................................................................................................................................................66
6.7 Idle..................................................................................................................................................................................................66
6.7.1. Idle Config..........................................................................................................................................................................................................67
6.7.2. Sniff Mode Operation........................................................................................................................................................................................68
6.7.3. Burst Transmit Data..........................................................................................................................................................................................72
6.7.4. Housekeeping....................................................................................................................................................................................................74
6.8 Idle Return......................................................................................................................................................................................75
6.9 EE...................................................................................................................................................................................................76
6.9.1. Write EE .............................................................................................................................................................................................................76
6.9.2. Load EE..............................................................................................................................................................................................................76
6.10 Calibrate .......................................................................................................................................................................................76
6.10.1. Internal Trim ....................................................................................................................................................................................................77
6.10.2. Calibrate Quick Start Oscillator.....................................................................................................................................................................78
6.10.3. Calibrate 10kHz Oscillator..............................................................................................................................................................................78
6.10.4. Calibrate PLL...................................................................................................................................................................................................78
6.10.5. Calibrate LNA ..................................................................................................................................................................................................78
6.11 ROM 2 REGS ...............................................................................................................................................................................79
6.12 Chip Reset....................................................................................................................................................................................79
6.13 ADC Conversion...........................................................................................................................................................................79
6.13.1. ADC Conversion Results................................................................................................................................................................................80
6.13.2. Single ADC Conversion..................................................................................................................................................................................81
6.13.3. Continuous ADC Conversion.........................................................................................................................................................................81
7.0 Data Interface....................................................................................................................................................................................81
7.1.1. Chip Address MSB1..........................................................................................................................................................................................83
7.1.2. Chip Address LSB.............................................................................................................................................................................................83
7.1.3. Data Rate/Format ..............................................................................................................................................................................................83
7.1.4. General Options A.............................................................................................................................................................................................84
7.1.5. General Options B.............................................................................................................................................................................................85
7.1.6. Start of Frame....................................................................................................................................................................................................86
7.1.7. Data Rate 1.........................................................................................................................................................................................................86
7.1.8. Data Rate 0.........................................................................................................................................................................................................86
7.1.9. CRC Polynomial ................................................................................................................................................................................................87
7.1.10. Default Length of Packet................................................................................................................................................................................87
7.1.11. Broadcast ID 1.................................................................................................................................................................................................87
7.1.12. Broadcast ID 0.................................................................................................................................................................................................87
7.2 TX/RX Data Interface Protocol........................................................................................................................................................88
7.2.1. AMIS-53050 in Master Mode.............................................................................................................................................................................91
7.2.2. AMIS-53050 in Sla ve Mode...............................................................................................................................................................................92
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AMIS-53050 Frequency Agile Transceiver Data Sheet
7.2.3. Manchester Operation......................................................................................................................................................................................92
7.2.4. Packet Framing .................................................................................................................................................................................................93
7.2.5. Use ID.................................................................................................................................................................................................................93
7.2.6. Length of Packet Enable ..................................................................................................................................................................................94
7.2.7. CRC Enable........................................................................................................................................................................................................94
7.2.8. SOF Byte............................................................................................................................................................................................................94
7.2.9. Timing Diagrams for Various Packet Framing Modes...................................................................................................................................95
8.0 General System Functions..............................................................................................................................................................98
8.1 Pull-up Disable................................................................................................................................................................................98
8.2 Brown-Out POR..............................................................................................................................................................................98
8.3 Temperature Sensor.......................................................................................................................................................................98
8.3.1. Crystal Temperature Compensation...............................................................................................................................................................99
8.4 Software ..........................................................................................................................................................................................99
8.4.1. AMIS Part Revision Code.................................................................................................................................................................................99
9.0 Built-in Test Functions...................................................................................................................................................................100
9.1 TM Unlock Register ......................................................................................................................................................................100
9.2 Test Registers...............................................................................................................................................................................100
9.2.1. IF Amp Manual Trim A....................................................................................................................................................................................100
9.2.2. IF Amp Manual Trim B....................................................................................................................................................................................100
9.2.3. PLL Manual Trim.............................................................................................................................................................................................100
9.2.4. PLL Test Modes...............................................................................................................................................................................................100
9.2.5. Power Down RF Sections...............................................................................................................................................................................101
9.2.6. Analog Test Mode...........................................................................................................................................................................................101
9.2.7. RF Test Modes.................................................................................................................................................................................................101
9.2.8. Analog Test MUX.............................................................................................................................................................................................101
9.2.9. RF Test MUX....................................................................................................................................................................................................101
9.2.10. Digital Test MUX A........................................................................................................................................................................................102
9.2.11. Digital Test MUX B........................................................................................................................................................................................102
9.2.12. Digital Test MUX C........................................................................................................................................................................................103
9.2.13. Digital Test Mode A.......................................................................................................................................................................................103
9.2.14. Digital Test Mode B.......................................................................................................................................................................................103
9.2.15. Digital Test Mode C.......................................................................................................................................................................................103
9.2.16. Digital Test Mode D.......................................................................................................................................................................................103
9.2.17. Memory Test Mode Address........................................................................................................................................................................103
9.2.18. Memory Test Mode Data...............................................................................................................................................................................103
10.0 Register Definition........................................................................................................................................................................104
11.0 Applications..................................................................................................................................................................................106
12.0 Ordering Information....................................................................................................................................................................107
13.0 Company or Product Inquiries....................................................................................................................................................107
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AMIS-53050 Frequency Agile Transceiver Data Sheet
1.0 Overview of the AMIS-53050
The AMIS-53050 is a highly integrated and configurable single-chip wireless transceiver and is based on AMI Semiconductor’s
ASTRIC™ wireless solutions platform. It is ideally suited for multi-channel (sub-1GHz), low to moderate data rate, low power, narrow
band wireless applications in the automotive and industrial markets. The device provides for a number of data modulation schemes,
including frequency shift key (FSK), Gaussian FSK (GFSK) and on/off shift key (OOK) modulation, respectively. The AMIS-53050 can
be easily interfaced to a b aseband processor via a serial interface bus.
1.1 Typica l A pplica t ions
• Wireless sensors
• RFID
• Remote monitoring
• Access control and security
• Keyless entry
• Mobile wireless data terminals
• Tire pressure monitors
• Wireless toys
1.2 Key Features
• Very low power single-chip CMOS transceiver
• Patented Quick Start crystal oscillator
• Low power receive Sniff Mode™
• Periodic transmit using burst mode
• Internal low power 10kHz oscillator
• Internal self-calibration functions
• SPI/I2C interface bus
• 3-wire/4-wire serial data interface
• Two analog to digital conv erter channels
• Internal fractional N frequency synthesizer
• OOK / FSK / Gaussian FSK (BT = 1) modulation
• Internal temperature sensor
• Minimal external components
1.3 Technical Features
• Operating voltage range: 2.2 to 3.3V
• Operating temperature range: -40° to +85oC
• Operating frequency range: 300 – 960MHz
• Data rate:
o 1 to 19.2kbps (OOK)
o 2 to 128kbps (FSK/GFSK)
• Transmit output power:
o +15dBm max (high power mode)
o +0dBm max (low power mode)
• Transmit current: 50mA typical (15dBm)
• Receiver sensitivity
o –115dBm (OOK @ 1kbps)
o –105dBm (FSK @ 20kbps)
• Receiver current: 12mA (continuous)
• Minimum RX energy detect time: 130uS (sniff mode)
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AMIS-53050 Frequency Agile Transceiver Data Sheet
1.4 Circ uit Overvie w
1.4.1. Transmitter
In the AMIS-53050, a pre-driver and a class E power amplifier are used to output the OOK- or FSK-modulate d radio frequency signals .
The class E power amplifier has two output power ranges aimed at realizing high output power efficiency. The output power level is
programmable, the maximum value for these two ranges being 0dBm and + 15dBm, respectively. The class E p ower amplifier provid es
maximum output power of +12dBm to +15dBm in the frequency range of 300MHz to 915MHz.
The transmitted data can be NRZ or Manchester encode d. Data rates for OOK modulation can b e as high as 19.2k bps , while data rat es
for FSK/GFSK modulation can be as high as 128kbps. The deviation of the RF carrier frequency for the FSK modulation is
programmable, typically being one half to one times the data rate.
The transmit data output can be wave shaped with a Gaussian format. T his can reduce the occu pied ba nd width of the signal. Power to
the transmitter PA can be ramped during power-up and power-down transitions, respectively, in order to reduce signal frequency
splatter.
1.4.2. Receiver
The AMIS-53050 has single r eceive and tra nsmit channels , respectivel y, which can b e connected to i ndividua l antennas or alter natively
to a single antenna, using external components. A single antenna configuration will have reduced performance, receiver sensitivity
and/or transmit output power. The receiver uses four different methods to receive and recover data that has been on/off shift key or
frequency shift key modulated. The FSK/GFSK data is recovered using either a phase-locked loop (PLL) or a Fast Fourier transform
(FFT) circuit, in conjunction with a cl ock and data recovery (CDR) circuit. The OOK data is recovered using a receiv ed signal strength
indicator (RSSI) circuit. It is suggested that the CDR circuit be used when receiving OOK sign als as well.
1.4.2.1. On/Off Shift Key Modulation
The AMIS-53050 uses a logarithmic RSSI detector to recover the data from the on/off shift key modulated waveforms. Data rates can
be as high as 19.2kbps. The device has eight discrete data filters for common baud rates. The receiver can detect either NRZ or
Manchester encoded data. The sing le Byte command ROM2REGs will change the slice filt er settings and the CDR settings when one
of the standard data rates is selected.
1.4.2.2. Low Data Rate Frequency Shift Key Modulation
The AMIS-53050 uses a digital PLL detector to recover the received frequency shift key data below 20kbps. The recovered data
waveform is in turn a pplied to the CDR circuit to produce the digital d ata and a s ynchronized c lock. The r eceiver can de tect either NRZ
or Manchester encoded data. The single byte command ROM2REGs will change the CD R settings when one of the standard data rat es
is selected.
1.4.2.3. High Data Rate Frequency Shift Key Modulation
An integrated FFT circuit is used to recover the received frequency shift key modulated waveforms when the data rate is higher than
20kbps. The data rate can be as high as 128kbps. The demodulated data waveform is in turn applied to the clock and data recovery
circuit to produce the digital data and a synchronized clock. The receiver can detect either NRZ or Manchester encoded data. The
single byte command ROM2REGs will change the CDR settings when one of the standard data rates is selected.
1.4.2.4. Clock and Data Recovery
The AMIS-53050 uses a CDR circuit that is linked to the frequency shift key or on/off shift key data detector circuits to recover the data
stream. The CDR circuit synchronizes a clock with the data rate of the received data. The CDR function is a critical element for the
recovery of high data rate (>20kbps) FSK signals, while data can be recovered without the CDR function for low data rate FSK and
OOK signals, respectively. It is recommended, however, that the CDR function be used with all receive r data recovery methods.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
1.4.2.5. Manchester Data Encoding
The AMIS-53050 can encode the data as NRZ or Manchester. Manchester encoding can improve the communication link as the
encoding removes long time periods with the same level of multiple bits, without a data edge transition. Manchester encoding will
require that the data rate be half of the NRZ data rate.
1.4.2.6. Oscillators
The AMIS-53050 requires a single external crystal working with the internal VCO and PLL to generate frequencies from 300MHz to
960MHz. The AMIS-53050 has internal capacitors, which eliminate the need for external load capacitors when using a typical 24MHz
external crystal. The VCO requires an external inductor and capacitor (in conjunction with the internal capacitance) and user
programming of the device in order to produce the desired transmit or receive RF frequency. Due to parasitics associated with an
external capacitor, it is recommended that only a coil be used with the VCO unless the circuit cannot achieve the desired frequency
without a capacitor. A patented Quick Start circuit is used to force the cr ystal oscillator to the desir ed frequ ency in micros econds r ather
than in milliseconds.
A low power internal 10kHz oscillator pr ovides the timing for sniff, burst and housekeeping modes of operation. In this case, based on
integrated self-calibration circ uitry, a frequency tolerance of +/- 2% can be achieved.
Crystal frequencies other than 24MHz may be used; however, this option is not recomme nded because:
• The Quick Start feature will not function
• The algorithm for determining the frequency register values will change
• The algorithm for determining the data rate register values will change
• The algorithm for determining the FSK modul ation deviation register values will change
• The RF frequency operational range of the device will change
1.4.2.7. Interface Serial Bus
The AMIS-53050 has separate interfaces for dat a an d contr ol. T he transfer of TX/RX data between the transceiver and an e xternal host
controller is performed using a 3-wire serial interface or a 4-wire SPI compatible serial interface, respectively. Control information is
either written to or read from the appropriate register using either a 3-wire serial interface (only available with the AMIS-53050-002
version) or a 2-wire I2C compatible serial interface.
Once the data pertaining to the configuration of various modes of operation, such as transmit, receive, sniff, etc., is written to the
configuration register, placing the device into one of these specific modes is accomplished via a single write command .
TX/RX Data Interface
The transmit or receive data interface can be programmed to be either a proprietary 3-wire serial interface or a 4- wire SPI compatible
serial interface, respectively. The data interface can be set up for data transfer to a buffer or alternatively, for streaming data. In the
buffered data mode, the device can be configured as a master or a slave. However, it must be configured as a master in order to
process streaming data.
Control Interface
When the transceiver is first powered on, an external host controller can be used to configure the type of interface (3-wire or I2C) by
simply writing the desired protocol to the AMIS-53050. As long as power is not removed from the device, this configuration is
maintained. The AMIS-53050 is al ways a slave device for the control interface. The AMIS-5305 0-002 version does not bo nd the SSN
signal to an external pin of the AMIS-53050 pin. This version must use the I2C interface bus and the SSN line defaults to the correct
level to enable the I2C interface bus with the first write operation.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
2.0 Operational Specifications
2.1 Absolute Maximum Ratings
Table 1: Absolute Maximum Ratings
Symbol Parameter Min. Max. Units Notes
Vdd DC supply voltage -0.3 3.6 V
Vin Input pin voltage -0.3 Vdd+0.3 V
Iin Input pin current -10.0 10.0 mA 25C
Tstrg Storage temperature -55 150 C SSOP
Tlead Lead temperature 300 C 10 sec
ESDHBM Human body model 2.25 kV
ESDCDM Charged-device model 1000 V
ESDMM Machine model 175 V
2.2 Recommended Operating Conditions
Table 2: Operating Conditions
Symbol Parameter Min. Max. Units Notes
Vdd DC supply 2.2 3.3 V
Idds Standby current (off current) 0.8 uA (AMIS-53050-001) (1)(2)
Idds Standby current (off current) 0.2 uA (AMIS-53050-002) (1)(2)
Vss Ground 0.0 0.0 V
Ta Ambient temperature -40 85 C
Notes:
1. Stand-by current is specified at room temperature, with all analog cells in power-down mode, logic powered up with no clocks running, all outputs unloaded and
inputs set either high or low (no floating inputs).
2. The lowest receiver current is achieved when using the AMIS-53050-001 version with the internal digital regulator and a 100uF capacitor on Pin 22
(SSN/CoreReg).
2.2.1. Parametric Voltage and Current Levels
(Test data for various device currents assumes a static set-up, with measurements performed while static data is applied to the device)
2.2.1.1. Inputs
Table 3: Pin Input Parameters
Pin Vil Vih Iil
(1) Iih
(1) Notes (2)
Min.
(V) Max.
(V) Min.
(V) Max.
(V) Min.
uA Max.
uA Min.
uA Max.
uA
AI 0.0 1.0 -1.0 0.0 Analog input
DISU 0.0 0.3 0.8 1.0 0.0 1.0 -30 -90 CMOS with pull up Schmitt
DISC 0.0 0.3 0.8 1.0 0.0 1.0 -1.0 0.0 CMOS Schmitt
Notes:
1. Iil and Iih are tested at Vdd = VDDmax volts. Not tested at temperatures lower than room temperature
2. PU = pull-up, PD = pull-down, SC = Schmitt, SU = Schmitt & pull-up and SD = Schmitt and pull–down.
3. CMOS values are 'Vin * VDD' and TTL values are absolute voltages.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
2.2.1.2. Outputs
Table 4: Pin Output Parameters
Pin Vol
(1) Voh
(2) Iol
(1,3) Ioh
(2,3) Notes
Min.
(V) Max.
(V) Min.
(V) Max.
(V) Min.
mA Max.
mA Min.
mA Max.
mA
AO Analog outputs
DO 0 0.4 Vdd-.4 2 -2 CMOS
Notes:
1. Vol, Iol are tested at Vdd = VDDmin volts unless otherwise stated
2. Voh, Ioh are tested at Vdd = VDDmin volts unless otherwise stated
3. Polarity on currents indicates direction of current: (+) for sinking and (-) for sourcing
2.2.1.3. I/O Pins
Table 5: I/O Pin Parameters
Pin Vil
V
Min.
Vil
V
Max.
Vih
V
Min.
Vih
V
Max.
Vol
V
(1)
Vol
V
Max.
(1)
Voh
V
Min.
(2)
Voh
V
(2)
Iol
mA
Min.
(1)
Ioh
mA
Min.
(2)
Iozl
uA
Max.
(3)
Iozh
uA
Max.
(3)
Notes
AIO
DIO 0 0.3 0.8 1 0 0.4 Vdd-.4 Vdd 2 -2 1 -1 Schmitt
Notes:
1. Vol, Iol are tested at Vdd = 3.1V.
2. Voh, Ioh are tested at Vdd = 3.1V.
3. Ioz is tested with Vdd = 3.5V.
*** Leakage on I/O pins is typically checked for +/- 10 microamps with the output device turned off and no pull-up or pull-down device present.
2.3 Operational Specifications
Table 6: Operational Specifications
Parameter Min. Typ. Max
. Units Comment
Receiver
Frequency range 300 960 MHz Frequency is set by external VCO components & registers
-107 -114 dBm @ 10kHz data rate (FSK/GFSK modulation)
Sensitivity -104 -111 dBm @ 10kHz data rate (OOK modulation)
Noise figure 6.0 7.8 9.0 dB
IIP2 +60 dBm Dual tone test using RSSI
IIP3 +5 dBm Dual tone test using RSSI
Image rejection 30 40 50 dB Modulated desired, single tone interferer
Input impedance Figure 8 Receiver input impedance with given LNA input/output coils
RSSI gain 16 18 20 mV/dB
10 12 14 mA Receiver current consumption at 900MHz (AMIS-53050-001)
IIN 12 14 16 mA Receiver current consumption at 900MHz (AMIS-53050-002)
IDDS Crystal mode 2 mA Stand-by mode with crystal oscillator running
Ton 150 us Stand-by to receive mode transition time
TRX_TX/ TTX_RX 1500 us Transition time from RX to TX or TX to RX
IF bandwidth 300 kHz The receiver bandwidth is fixed
LNA
Input trim 1.2 4 pF Internal capacitor range for the receiver input
Output trim 0.32 0.91
2 pF Internal capacitor range for the output of the LNA in the receiver
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 6: Operational Specifications (Continued)
Parameter Min. Typ. Max. Units Comment
Transmitter
Frequency range 300 960 MHz
Ton 150 us Stand-by to transmit mode transition time
TTX_RX 150 us Transition time from TX to RX
OOK on/off ratio 60 dB
FSK frequency
separation 0 200 kHz Allowable transmit/receive peak deviation
-20 15 dBm Range of output power in the high power mode (dedicated TX port)
CW output power -25 0 dBm Range of output power in the low power mode (dedicated TX port)
PHARMONICS 35 dBc With complete matching network
TX PA
Output cap. 2 7.5 pF Internal capacitor range for the PA adjustable trim
Output switch R 5 18
On/Off ratio 60 dB
Output harmonics -35 dBc With typical 50 matching circuits
Operating current 50 68 mA 15dBm CW
Operating current 12 24 mA 0dBm CW
High
power 12.5 15 17 dBm
MAX
power Low
power -1 4.5 5.7 dBm
Matching network for 50Ω 928MHz high (dedicated TX port)
High
power 13.8 15.5 17 dBm
MAX
power Low
power 3 4 5 dBm Matching network for 50Ω 433MHz high (dedicated TX port)
Crystal Oscillator
Center frequency 24 MHz Trimmed
Tolerance 20 ppm Required crystal tolerance
Startup time 50 150 us Quick Start enabled
Startup time 2 5 ms Quick Start disabled
Trim cap 0 45 pF Internal trim capacitor (Self-calibration sets)
Trim resolution 145 160 175 fF
Idd 800 uA Normal operation
Idd 1.5 mA During Quick Start
10kHz Oscillator
Output frequency 9.8 10 10.2 kHz After trimming
Operating current 300 375 450 nA After trimming
Duty cycle 50 %
ADC
Resolution 8 Bits
FSR 2 V Full scale input range
Ci 1 pF Input capacitance
Reference offset 1 %FSR
fclk 0.01 2 MHz Clock frequency
Conversion rate 150 KSPS Clock rate = 2MHz
Conversion time 10 Tclk
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 6: Operational Specifications (Continued)
Parameter Min. Typ. Max. Units Comment
Data Filter
3dB Down point 110 120 130 %FDATA AM data filter bandwidth (relative to associated defined data rates)
Temperature Sensor
Output voltage 0.93 0.97 1.01 V At 27oC
Voltage range 0.61 0.97 1.4 V Output
Slope -5.24 mv/oC dV/dT
RSSI Buffer
Input range 0 Vdd V
Operating current 135 185 250 uA
Unity gain-BW 615 1000 1700 kHz 100k/100pF load
PLL 12 MHz Transmit mode (24MHz external crystal)
Reference input
frequency 16 MHz Receive mode (24MHz external crystal)
Resolution 91.55 Hz Frequency step size
9.62 12 14.4 MHz/V @ 400MHz
VCO gain constant 25.6 32 38.4 MHz/V @ 900MHz
@ 900MHz, although layout PCB
parasitics and component
placement will change this value
Settling time 100 us Internal loop filter
Phase noise -90 -80 dBc/Hz Internal loop filter @ 10kHz offset
Phase noise -120 -110 dBc/Hz Internal loop filter @ 3MHz offset
Max. spurious level -70 -50 dBc Internal loop filter
POR
Delay time 28 43 60 ms
Brown-out trip 1.2 1.6 1.8 V
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AMIS-53050 Frequency Agile Transceiver Data Sheet
3.0 Block Diagrams
3.1 AMIS-53050 Overall Block Diagram
Figure 1: AMIS-53050 Block Diagram
3.2 Package
3.2.1. Pin Defi
Tabl Pin De
nition
e 7: finitions
Pin# -001 -002 Pin Type Description
1 LNAvdd LNAvdd uctor) is connected to VDD from this pin Power A DC short (ind
2 RFin RFin Analog input The RF input to the receiver circuits
3 RFvss RFvss Ground Ground for the RF circuits
4 RFout RFout Analog output RF transmit output
5 RFpwr RFpwr Analog ut utput to power the RF transmitter (requires a DC short {inductor}
outp Variable DC voltage o
connection to RFout)
6 Avdd Avdd Power Vdd power for the analog circuits
7 ADC1 ADC1 Analog input Input to the analog to digital conversion circuit
8 ADC2 ADC2 Analog input Input to the analog to digital conversion circuit
9 RSSI RSSI Analog IO Analog voltage related to the strength of the received RF
10 PEAK PEAK Analog Analog voltage for external auto- slice capacitor
11 Avss Avss Ground Ground for the analog circuits
12 XTAL2 XTAL2 Analog Connection to an external crystal
13 XTAL1 XTAL1 Analog Connection to an external crystal
14 INT INT Digital output Interrupt to external controller
15 Dopt Dopt Digital input ta interface mode Optional data pin for the 4-wire da
16 Dssn Dssn Digital IO Active low select line for the data interface
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AMIS-53050 Frequency Agile Transceiver Data Sheet
able Pin DeT 7: finitions (Continued)
Pin# -001 -002 Pin Type Description
17 Drxtx Drxtx Digital IO Serial data input (Transmit) or output (Receive)
18 Dclk Dclk Digital IO Recovered clock output (Data interface clock)
19 SYSclk SYSclk Digital output System clock output
20 Dvss Dvss Ground Ground for the digital circuits
21 Dvdd Dvdd Power Vdd supply for the digital circuits
22 CoreReg SSN Digital -001 (pin bonded for a decoupling capacitor for the internal regulator)
-002 (pin is bonded to bring out the SSN bus enable for the control bus)
23 SCLK SCLK Digital Bi-directional clock for the 2-wire serial interface
24 SDATA SDATA Digital Bi-directional data for the 2-wire serial interface
25 xBURST xBURST Digital input Active low input interrupt that will immediately cause a Burst transmission
26 LOOPout LOOPout Analog Output to the optional external loop filter
27 LOOPin LOOPin Analog Input from the optional external loop filter
28 LOvss LOvss Ground Ground for the local oscillator circuits
29 LOn LOn Analog Negative side of the VCO tank
30 LOp LOp Analog Positive side of the VCO tank
31 LOvdd LOvdd Power Vdd supply for the local oscillator circuits
32 RFvdd RFvdd Power Vdd supply for the RF circuits
3.2.2. Block Diagram/Pin Definition
Figure 2: Block Diagram/Pin Definition *
* Not act u al package mar k ings. Please see marking format in 3.2.3.3.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
3.2.3. Physical Characteristics
3.2.3.1. Package Type
32 pin LQFP
3.2.3.2. Package Dimensions
Table 8: AMIS-53050 LQFP Package Dimensions
Symbol Min. Nom. Max. Units
Thickness - - 1.60 mm
D 9.00 BSC mm
D1 7.00 BSC mm
E 9.00 BSC mm
E1 7.00 BSC mm
e 0.80 BSC mm
Figure 3: Package
3.2.3.3. Package Marking Format
(AMIS Logo)
ion
XXXXYZZ is the date and tractability code**** is the country of origin (found on underside of chip).
The year in which the mask work was first fixed in a semiconductor chip pr oduct may also appear.
AMIS53050
19608-bbb
XXXXYZZ
Where:
bbb is the AMIS device vers
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AMIS-53050 Frequency Agile Transceiver Data Sheet
4.0 Acronyms
The following acronyms are used in this document.
ADPLL All digital phase lock loop
AM Amplitude modulated signal (AM/ASK/OOK are used interchangeably in this document)
ASIC Integrated circuit designed for a single customer requirement
ASK Amplitude shift key (AM/ASK/OOK are used interchangeably in this document)
ASSP A custom integrated circuit, that may be used in general designs
ASTRIC AMI Semiconductor’s family of wireless products
CCA Clear channel assessment
CDR Clock and data recovery, data is recovered from the received signal using a synchronous clock
CRC Cyclic redundancy checking; data error checking
CW Continuous wave, a single frequency or modulated signal carrier
DAC Digital to analog conversion
dB Decibels; a logarithmic measure of signal level
dBm Logarithmic measure of signal level above a milli-watt
DFFT Digital or discrete Fast Fourier transform (DFFT/DFT /FFT may be used in this document and mean the same)
DPLL Digital phase locked loop circuit to create a precise frequency
EE Electrical erasable memor y that can maintain data with power removed
FFT Fast Fourier transform; transform between time and frequency (DFFT/DFT/FFT may be used in this document and mean the
same)
FM Frequency modulated signal (FM/FSK are used interchangeably in this document)
FSK Frequency shift key (FM/FSK are used interchangeably in this document)
GFSK Gaussian data waveform modulated signal
IF Intermediate frequency
kbps Data rate in thousand bits per second
kHz Frequency in kilohertz per second
LO Local oscillator frequency; used to convert signals between RF frequency and IF freque ncy
LOP Byte indicating the length of a packet
MHz Fr equenc y in megahertz
mV Milli-volts
OOK On/off method of creating an amplitude modulated signal (AM/ASK/OOK are used interchangeably in this document)
OTA Transconductance amplifier
PLL Phase locked loop circuit to create a precise frequency
POR Power-on-reset is a threshold circuit for limiti ng operation at low voltages
RF Radio frequency
RSSI Received signal strength Indi cation; measurement of RF signal strength
SOF Byte indicating start of packet in data protocol
VCO Voltage controlled variable frequency oscillat or
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AMIS-53050 Frequency Agile Transceiver Data Sheet
5.0 Hardware Description
5.1 Frequency
The RF frequency for b oth TX an d RX mod es is determine d by the combi nation of inter nal VCO, PL L and trim c apacit ors, as well as an
external crystal oscillator. For the external crystal, it is recommended that a 24MHz parallel resonant mode crystal with 20ppm
tolerance be used, taking into account the interna l capacitors.
Figure 4: External Crystal Circuit
The internal VCO requires an external, parallel LC configuration in order to properly set the frequency for RX or TX modes. Operation of
the AMIS-53050 is sensitive to the pos itionin g of the LC compon ents in the PCB la yo ut. For this reaso n, the traces to the LC need to be
as symmetrical as is possibl e. T he loc ation of the LC c omp onents needs to be as close as poss ibl e to the transceiver pi n s as well. Any
layout changes will lead to a change in the V CO frequency, in turn requiring a chan ge in the val ues of the inductor, capacitor and/or the
values in the register(s) contr olling the RF frequenc y. The layout of the pri nted circuit board for the inductor and ca pacitor should route
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AMIS-53050 Frequency Agile Transceiver Data Sheet
traces connecting other components away from the inductor and capacitor pads. Furthermore, the values of the inductor and/or the
capacitor are to be optimized in order to properly calibrate the PLL for a given frequenc y of operation.
The AMIS-53050 has an internal l oop filter which is linked t o the PLL circu it to generate t he transceiver ’s output freq uency. T here is an
option to use an external loop filter.
Note: Using a capacitor in parallel with an inductor for the external VCO LC circuit will lower the VCO gain, reducing the frequency
overlap between the transmit frequency and the receive frequency. It is suggested that only a coil be us ed in the LC circuit, if possible.
Note: The PCB traces to the external LC components need to be as symmetrical as possible.
Note: The external L and C used to set the VCO frequency s hould be physically located as close to the AMIS-53050 Pins LOp, LOn a s
possible.
Figure 5: VCO External LC Circuit
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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Table 9: Internal Loop Parameters
Filter Component Value Units Comments
R1 60 k
C1 64 pF
Second order C2 3 pF
R 110 k
Additional pole C 1 pF
Frequency 24 MHz
Reference N N=(RF MHz)/(24 MHz)
KVCO 22 MHz/V VCO external coil inductance ~ 15 nH
VCO gain KVCO 10 MHz/V
VCO external coil inductance ~ 91 nH
ICP 25 µA The charge pump current is user selectable
CP current ICP 50 µA The charge pump current is user selectable
Figure 6: Optional External Loop Filter Circuit
AMIS-53050 Frequency Agile Transceiver Data Sheet
In the low power mode (idle/stand-by), an
functions, respectively. This oscillator requ internal 10kHz oscillator provides timing for the sniff, burst transmit and housekeeping
ires no external components. The 10kHz oscillator’s internal trim capacitor is trimmed by
eight bits of trim control via self-calibration. Once the trim is set, the oscillator frequency will be accurate to within two percent over
specified voltages and temperatures.
5.2 Receiver
The AMIS-53050 has a single channel receiver. T he LNA for the receiver inp ut requires a DC connection to gro und on the input (must
not be an RF ground connecti on). The LNA for the receiver input requires a DC connection to RFVDD on the output. T hese connections
are supplied through inductors, Lrx and LLNA, becoming part of the matching circuit for the receiver input.
Figure 7: Receiver Input Matching Circuit
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AMIS-53050 Frequency Agile Transceiver Data Sheet
5.2.1. Receiver Low Noise Amplifi er (LNA)
The receiver input of the AMIS-53050 is a sin e. The input is matched to 50 using an
ernal matching network, which provides a DC path to ground for biasing the receiver’s LNA. The output of the LNA is tuned to the
esired operating frequenc y using an e xternal inductor along with an on-chip ca pacitor. The output inductor also provides the LNA with
DC connection to the supply voltage. On-chip tun ing capacitors are binary weighted and digitally controlle d.
e internal input capacitance h as a range of 1. 2 - 4pF. T he corresponding r ange for the int ernal output ca pacitance is 0. 3
gle-ended input and single-ended output devic
ext
d
a
The value of th
- 0.9pF. The impedance of the receiver for three values of input coil inductance, with the input capacitance set to the middle of the
range (register set to 0X80), is sho wn in Figure 8. Here, the value of the output coil inductanc e is a function of the operating frequ ency,
nd is shown in Figure 9. a
Figure 8: RX Input Impedance
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 9: Receiver LNA Output Inductor Selection
5.2.2. IF Filter
A passive poly-phase filter and active filt ering are used to achieve frequenc y selectivity and rejection of the image frequency. The filter
is designed to provide an optimal image rejection of 50dB at 500kHz below the RF frequency.
5.2.3. Data Filter
he OOK low-pass data filter is used for additional post-de tection signal filtering in accordanc e with the OOK signal data rate (1.2, 1.8,
2.4, 4.8, 7.2, 9.6, 14.4, 19.2kHz).
5.3 Transmitter
The transmitter is a two-stage output amplif ier. When both stages are selected, the highest output po wer at frequencies from 300MHz
load, using the spreadsheet AMIS-
3RFMATCH.xls. This spreadsheet is provided by AMIS and is described in the Application Note “AMIS-53XXX Antenna Impedance
atching Considerations”.
T
to 960MHz is +15dBm, when matched into a 50 load. For output power levels up to 0dBm, single stage operation results in higher
power efficiency, as compared to t wo stage operation. The voltage output level on the RFPWR pin controls the RF output power level of
the device. A DC connection must be made between the RFOUT pin and the RFPWR pin. The non-linear output of the AMIS-53050
may require external components to match to a load an d to reduce the spurious harmonics.
he output impedance of the AMIS-53050 can be matched to the impedance of an external T
5
M
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 10: Transmitter Output Matching Circuit
5.4 Single Antenna Option
The AMIS-53050 is designed such that when the transmitter or the receiver is off, the respective pin is grounded. This provides a
known impedance for the off port (transmit or receive), in or der to allow the use of a single circuit topology com bining the receiver a nd
the transmitter into a s ingle an tenna. In th e AMIS-53050, a singl e r egister is use d to set the transm it and receive freque ncy, resultin g i n
the same transmit and receive frequency. Therefore, the simple method to combine the transmitter and the receiver into a single
antenna will lead to either a reduction in transmit output power or less sensitivity in the receiver.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Note: This se
receiver of ction offers a simple metho d to combine the transmitter and the receiver into a single antenna. The AMIS-53050 turns the
f and shorts the input to ground so that any transmit energy will not affect the receiver circuit s.
ypical T/R
Combining the transmitter and receiver is typically done in one of two ways:
1. A diplexer can be used if the transmit and receive frequenci es are different and far enoug h apart to allow bandpass filtering to
separate the signals. Typical diplexers have less than one dB path loss.
2. A T/R (transmit/receive) switch can be used when the transmitter and the receiver are at the same frequency. T
switches have 1 to 1.5 dB path loss and require a signal to control the direction of the switch.
The AMIS-53050 is not designed to provid e a T /R switch control signal.
Figure 11: Single Antenna Port T/R Matching Circuit
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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tion on proper selection of the capacitor values.
d. The time constant (corner frequency) for this filter is in turn
etermined by the value of the capacitor connected to the PEAK pin. A typical capacitor value would allow the average level to settle to
95 percent of the RSSI level in 2 bit intervals (remember that Manchester encoding may have transitions twice the data rate). The
chatter before a signal is rece ived and after the signal ends, which should b e considere d for proper
operation of the external host controller.
e swing on the RSSI for a typical 12dB signal to noise ratio at 10 BER is 240mV. The
apacitor value should not change the voltage by more than this 240mV during a string of zeros. The value is dependent on the
number o encoded.
In the AM er to accommodate cha nges in the e xternal
oise floor and/or the gain of the receiver due to temperature and voltage. This is done by setting a false wake-up value (number of
5.5 Peak
There are three methods for slicing the received OOK modulated signal to recover the data. The first method is based on setting a
threshold value that is fixed and to which the receiver compares th e recovered signal. The other two methods are based on automatic
setting of this threshold level. These automatic threshold methods require an external capacitor on the PEAK pin to operate. Please
efer to the Application Note “Setting up the Data Slicing Modes” for informar
In the averaging method, the transceiver’s low pass filter circuitry is enabled, with a cut-off frequency set below the data rate filter
setting. This filter extracts an average RSSI l evel as the data slice threshol
d
average threshold method will have
In the peak method, the peak detector circuitry is enabled, followed by detection of the maximum input signal level and setting of the
threshold level 6dB lo wer than the ma ximum level, r espectively. T he capacitor connected t o the PEAK pin is used to bleed or discharge
the peak voltage in the circuit. The voltag -3
cf zeros that are allowed in the chosen data protocol, NRZ or Manchester
IS-53050, the sniff function can be used t o adjust the thres hold energy lev el in ord
n
false wake-ups during a given number of sniff events).
Figure 12: Peak Capacitance Circuit
AMIS-53050 Frequency Agile Transceiver Data Sheet
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5.6 A DC
The ADC is a successive approximati on anal og to digital converter, using an inter nal 8-bi t DAC as the reference. T he ADC data for the
selected input channel(s) will be stored in the associ ated register, allo wing for external access to the conversion data throug h the serial
interface. Commands in the control register allo w for single or continuous oper ation of the ADC. T he ADC results can also be read and
automatically transmitted to another device using the burst transmit mode.
A voltage regulator generates the 2.0V reference for the ADC and DAC based up on an internal bandga p voltage source. The ADC ha s
six inputs, two of which are available for use in the designer’s application.
5.7 Control Interface Serial Bus
The internal registers of AMIS-53050 can be accessed via a 3-wire (requires the –002 version of the AMIS-53050) or 2-wire I2C
interface, respectively. In this case, the states of the three lines, SDATA, SCLK and SSN, and hence the type of interface are
automatically detected and configur ed b y the transceiver ’s control l ogic. T his configur atio n will b e valid as lon g as po wer is not remov ed
or a reset function is not initiated.
I2C: If SSN is high and an I2C start bit is detected, I2C mode is enabled
SPI: If SSN is low, and a negative edge on SCLK detected, SPI mode is enabled
The AMIS-53050 is designed to conform to the Philip Semiconductor I2C standard, with the AMIS-53050 as the slave device.
Figure 13: I2C Serial Bus Connections
AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 14: 3-Wire Control Bus Connections
.8 TX/RX Data Interface Serial Bus
Data transfer between AMIS-53050 and the external host controller is based on a 3-wire or 4-wire SPI serial data interface,
erface type is selected b y writing to the appropriate register. The DOPT line is undefin ed in the 3-wire interface.
(read or write) will determine the
efinition of the DRXTX and DOPT pins as outputs or inputs, respectively.
5
respectively. The int
The 4-wire interface of the AMIS-53050 is desig ned to be compatible with the definition of a standard SPI interface. T he device can be
configured as a master or a slave. The state of the device (master or slave) and the interface mode
d
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AMIS-53050 Frequency Agile Transceiver Data Sheet
AMIS-53050 Frequency Agile Transceiver Data Sheet
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Figure 15: SPI Compatible Serial Data Interface
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 16: 3-Wire Serial Data Interface
The system clock can be used as a clock for the external host controller. The clock frequency can be divided down from the 24MHz
can be output according to the following conditions:
output is off in general options B (Bit 1:0)
s received
T wi ck u the ee de i -up al h r is e ed in ekeeping configuration
(Bit 6).
Note: The SYSclk produ rm wh la the IS-53 er frequency and reduce the sensitivity of
the receiver.
For example, the 3 itiv of a system designed for
pplications not using this feature of the AM IS-53050.
• The PCB layout of an applic ation, which uses the SYSclk must use good isolation tec hniques for reducing the noise from the
5.9 System Cloc k
crystal frequency. In this case, the system clock
• Will be output in RX or TX, unless the
• The output will start back up in the idle mode after a packet i
he output ll start ba p in housek ping mo f wake extern ost controlle nabl the ho us
ces ha onics, ich may nd within AM 050 receiv may
• 0th harmonic of a 12MHz SYSclk is 360MHz and would affect receiver sens ity
360MHz operation.
• A suggestion is to disable the SYSclk output in a
SYSclk output in the AMIS-53050 receiver.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 10: System Clock Control
Mode Control Bits Outputs Comments
CLKout pin 0X0D General options B 1:0 Frequency: 12, 6, 3MHz or off
2:1 POR state: standby, idle, RX, TX
Standby General options A 0 Output in standby
Idle Idle config 4:3 Clock cycles before stop
5.10 Power and Grounds
The AMIS-53050 has four dist inct supply voltage inputs and t wo different ground nodes, respectively. This allows the separation of the
F, analog and digital power supply circuits to reduced coupled n ise in these circuits.. The same principle applies to the ground
nodes, where a separate gro und plane can reduce the amount of no e induced into the sensitive RF circuits.
.11 Design Suggestions
The foll ematics ayouts depict typical board-level solutions for the AM IS-53050:
R o
is
5
owing sch and board l
Figure 17: Typical Design Schematic
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 18: Typical Design Layout Suggestion
Figure 19: Minimum Design Schematic
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 20: Minimum Design Layout Suggestion
6.0 Us
er’s Guide
This user’s guide divides the description of the control registers into distinct functional areas; command register flow diagrams,
ata/control interfaces, and burst transmission, respectively.
Control Se
1: Contr
frequency generation, receiver, transmitter, idle, d
6.1 rial In terface Bus Description
Table 1 ol Interface Physical Configuration
Clock Data Power
Interface AMIS-
53050
Version Pin Source Output Input SSN AMIS-53050 RX Standby
-001 SCLK Master SDATA SDATA RegC Slave only Low Med.
I2C -002 SCLK Master SDATA SDATA NU Slave only Med. Low
3-Wire -002 SCLK Master SDATA SDATA Select Slave only Med. Low
Note: The I2C control bus interface can be used with either the –001 or the –002 version of the AMIS-53050, but the SPI can only be used with the –002 version. The
versions are different due to the receiver power requirements as shown.
The AMIS-53050 employs two different control interfaces. Communication with the AMIS-53050 control registers is through either a
3-wire bus or a 2-wire I2C compatible bus, respectively. The state of the control bus is detected by the device at the onset of
communication with the host controller, and is valid as long as po wer remains app lied to the part. In this case, the transceiver is always
a slave device.
6.1.1. Control Interface Protocol
The AMIS-53050 control interface allows an external host controller to write instructions to the registers. The external controller can
also read the register values. The control interface can be configured as either a 2-wire I2C interface bus or a 3-wire serial interface
(slave mode operation).
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AMIS-53050 Frequency Agile Transceiver Data Sheet
The 3-wire interface allows a single host controller to a ddress more than one transceiver using the single serial interface bus (requires a
each device). However, note that the 3-wire interface has only six register address bits and cannot
ace.
he I C interface requires a single host controller for each transceiver. The I2C interface allows the AMIS-53050 bonding option defining
e SSN/CoreReg pin as the external capacitor required for the low power digital regulator. The digital regulator reduces the receiver
power consumption.
different SSN control line for
address the entire register sp
2
T
th
Figure 21: Control I2C Protocol Format
able 12: I2C Addressing
TAddress Description
0110100X AMIS-53050 I2C address
01101000 AMIS-53050 Write command
01101001 AMIS-53050 Read command
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 22: 3-Wire Control Protocol Format
Table 13: 3-Wire Control (IN1 and IN0)
Control Word Bits
IN1 IN0 Description
0 0 Single register read
0 1 Single register write
1 0 Sequential register read
1 1 Sequential register write
I2C device address:
o 0x68 HEX for device write
o 0x69 HEX for device read
External controller can write registers
External controller can read registers
External controller ca n issue a immediate transmit via the xBURST input
External controller ca n receive an interrupt (xINT) from the AMIS-53050
Set-up registers descriptions:
I2C/3-wire select- First write to the interface sets the type of interface until AMIS-5305 0 is power cycled
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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6.1.2. Serial Control Interface: Configuration
The AMIS-53050’s control logic can automatically detect the type of interface used for the serial control bus. The interface pins are
then given the definitions as shown in Table 14. The detecti on scheme is based on the status of the device pi ns, as shown in Figure
23.
Table 14: Control Port Pin Definitions
Pin Name I2C Mode 3-Wire Mode
SCLK SCL SCLK
SDATA SDA R/W controlled
SSN Internal pull up SSN
Figure 23: Control Interface Selection
ddressing the part with the desired protocol will result in the configuration of the interface settings. After the first communication with
e device, the selection is lo cked until po wer is removed. The internal logic for determining which protocol to use on initial power-up is
he internal pull-ups on SCLK and SDATA can also be disabled for I2C applications using external pull-ups.
A
th
as follows:
I2C: If SSN is high and an I2C start bit is detected, I2C mode is enabled.
3-wire: If SSN is low, and a negative edge on SCLK detected, 3-wire mode is enabled.
T
Table 15: Control Interface Pull Up Control
Mode SCLK, SDATA Pull Ups SSN Pin Configuration
I2C Contr
options A register
olled by bit 3 of the general Not used (internal pull up)
3-wire Controlled by bit 3 of the general
options A register SSN: normal mode
AMIS-53050 Frequency Agile Transceiver Data Sheet
6.1.3. 3-Wire Interface Mode
he AMIS-53050 is always the slave device. T
Figure 24: Master/Slave for Bi-Directional 3-Wire Mode
Figure 24 illustrates the connections between the master SPI port and the slave 3-wire port in the AMIS-53050.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 25: Single Control Register Read/Write Using the 3-Wire I nterface
Figure 25 shows a single read or singl e write control data transfer. The operation starts with SSN trans itioning low to indicate a start of
ain active between successive read and write operations.
transfer. The first two bits transferred are the instruction for the slave interface of the AMIS-53050, namely IN1 and IN0, respectively.
Following the instruction are the si x address bits to specif y which address to read or write. If the instruction is to write to a register, the
register location is A<5:0> and the data is s pecified with the next eight bits, D<7:0>. If the operation is a read functi on, the slave output
buffer is enabled at the end of the address b its, and the data bits D<7:0> are buffered out of the part MSB first.
For single read/write, the SSN line can rem
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 26: Sequential Control Register Read/Write Using the 3-Wire Interface
F diagr or sequential re control data transfer. The format of the instruction and address is
identical t for a /write op r location to read or write. The first
eight bits of data tr correspond internally incremented after each data byte is
transferred. This ta for bles spanning over multiple address locations, such as the
fractiona word (
The SSN must b at the read/write in order for the slave SPI controller to correctly i nte rp ret
the next bits as a nd not
6.1.4. I2C Interface
T I2C e for the AMIS-53050 is with the AMIS-53050 as the slave
device.
defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is
elected. Following the start condition, the AMIS-53050 monitors the SDA bus checking the device type identifier being transmitted.
igure 26 is a am f ads or writes for 3-wire
to tha single read eration, with the addr ess corresponding to the first registe
ansferred to the address selected. The address is
sk is most useful
05). writing to or reading from varia
l PLL registers 03-
line e de-asserted completion of a sequential
eight a command data.
he interfac compatible with the Philip Semiconductor I2C standard,
6.1.4.1. I2C Device Addressing
A control byte is the first byte received follo wing the start condition from the Master device. The control byte consists of 7-bits for the
device address, and 1-bit for a read or write command. For the AMIS-53050, the devic e address is ‘0110 100’ binary. T he last bit of the
control byte
s
Upon receiving its device ad dr ess, the AM IS-530 50 outputs an acknowledg e signal on the SDA line. Dep end ing on th e state of the R/W
bit, the AMIS-53050 will select a read or write operation.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.1.4.2. Single Register Write
Figure 27: Single Control Data Read/Write with the I 2C Interface
The master device issues the start conditio n, then issu es the de vice addre ss, and then is sues the sing le R/W bit, a logic lo w state. This
indicates to the addressed slave receiver that a byte with a register address will follow after the slave has generated an acknowledge bit
during the ninth clock cycle. Therefore, the next byte transmitted by the master is the register address to be written with data. After
receiving another acknowledge signal from the AMIS-53050, the master device will transmit the data word to be written, and the
AMIS-53050 will ackno wledge again. The write cycle ends with the master generating a stop condition.
A similar approach is used to read a register value. The Master device issues the start condition, then issues the device address and
then issues the singl e R/W bit, a logic low state. This indicates to the add ressed slave receiver that a byte with a register address will
follow after the slave has ge nerated an ackno wledge bit during th e ninth clock c ycle. Therefore, the next byte transmitted by the master
is the register address to be read. After receiving anoth er ackno wledge signal from the AMIS-5305 0, the master device will immediately
follow with another start sequence, however, the R/W bit is no w set high, telling the slave devic e that the master wants the co ntents of
the register (addressed with the write command) to be placed on the SDA bus line. After the Master reads the eight bits of data, the
master does not acknowledge but sends the stop sequence.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.1.4.3. Sequential Register Write
Figure 28: Sequential Control Data Read/Write with the I2C Interface
When setting up the AMIS-53050 for an application, it is sometimes desirable to write the data to a number of registers sequentially.
The write control byte, register address and first data byte are transmitted to the AMIS-53050 in the same way as in a byte write.
However, instead of generating a stop condition, the master can continue to write register locations. Upon receipt of each word, the
address is internally incremented by ‘1’. Should the master transmit more words than the AMIS-53050 has address locations, the
address will roll over to the first address.
Reading a regi ster value is ba sed on a s imil ar ap proac h. T he writ e control byte and register a ddress ar e transmitted to t he AMI S-53050
in the same way as in a byte write. After receiving another acknowledge signal from the AMIS-53050, the master device will
immediately follo w with another start sequence, ho wever, the R/W bit is now set high telling the slave device that th e master wants the
contents of the register (addressed with the write command) to be placed on the SDA bus line. After the eight bits are read by the
master, the master acknowledges the reception. The AMIS-53050 will increment the register address and continue to output register
values. After the last register value is received by the master, the master does not respond with an acknowledgement but sends the
stop sequence.
6.1.4.4. Current Address Read
he internal address counter maintains the last address addressed, incremented by ‘1’. If the last instruction received was to access
register N, the current address read operation w 1. The timing for the current address read is to
send a start bit followed by the 7-bit device address, with the R/W he slave will acknowledge, after which the 8-bit
register contents will be transmitted. The master does not acknowl e the transmission, but does generate a stop bit.
Till read the contents from register N+
bit set to one. T
ged
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.1.4.5. Interface Options
Table 16: I2C Address Auto Increment
Register
Number (HEX) Name Bits Function
0X0C General options A 3 Disable the internal pull up resistors on SDATA and SSN lines
0X47 Analog test mode 4 I2C Auto increment disable*
*Note: To write to this register, the test registers must be unlocked by writing a special code to the UNLOCK KEY register (0X40).
6.1.4.6. Pull- Up Disable
The AMIS-53050 includes built in pull-up resistors for use with the I2C operation, in order to reduce the overall system component
count. The pull ups are asserted at POR until mode selection occurs. If the mode is determined to be 3-wire, the pull-up resistors are
removed. If the mode is determined to be I2C, this option bit determines whether the pull-up resistors ar e to be removed.
6.2 Command Register
The AMIS-53050 provides for single writes to an on-chip 8-bit register, in order to select different operat ing modes. It is very imp ort ant
to note that all registers associated with the desired mode are to be pre-programmed, for the single write to this register to operate
correctly.
The command register allows for the user application to issue a single write command to the device, in order to initiate the functions
listed in Table 17. Once a function is init i ated, the AMIS-53050 us es the register values associ ated with the selected function to perform
the desired operation(s). T hese register values will be the default values or the values the user app lication has written to the registers
before the function is called out in the command register. Most of the register values can be stored in the integrated E E memory so that
the transceiver can be powered up in the desired configuration.
Table 17: Command - 0X00 [0]
Bit Command Comment
[7:4] [3:0]
0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1111
Stand-by
Receive
Transmit
Idle
Idle Return
Write EE
Read EE
Calibrate QS Osc
Calibrate RC
Calibrate PLL
Calibrate LNA
ROM2Regs
Global Reset
Put the part into stand-by
Put the part into receive mode
Put the part into transmit mode
Put the part into idle mode
Use to return to idle after interrupt for HK or receive during sniff
Write the content of the working registers into EE
Read the contents of the EE
Calibrates the Quick Start oscillator
Calibrates the 10kHz RC oscillator
Calibrates the PLL
Calibrates the LNA matching
Write the content of the ROM into the shadow registers
Resets the part completely
[7:6] [5:0]
01 XXXXXX
100000 Single ADC
Conversion Do an ADC one time on the channel selected loop filter output
11 XXXXXX
100000 Continuous ADC
Conversions Do an ADC on the channel selected continuously loop filter output
With reference to Table 17, stand-by mode can be classifi power mode (where all internal circuitry except for the
ontrol bus interface are disabled), or a clock-only mode (where the crystal oscillator will be enabled to continue providing a system
ock for an external micropro cessor). A bit available in the general opti ons A register allows for selection of power-down or clock-only
peration.
Many of the instructions are finite in duration. In this case, the AMIS-53050 will return to the stand-by mode at the completion of the
task. Other instructions such as receive or transmit are indefinite in length and user-controlled, hence to return to the stand-by state, the
transceiver waits for the stand-by instruction.
ed as either a low
c
cl
o
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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AMI Semiconductor – Jan. 07, M-20639-002
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Note that there are two low-power modes for the AMIS-53050; stand-by and idle.
Stand-by allows the SYSCLK output
Idle is the very low power state without SYS ing, sniff or burst functions)
The device’s control logic m ay ignore a new instruction if it is busy or if it is not ready to receive the instruction. For example if a self-
calibration is in process and t he transceiver i s to transmit or receive a m essage, th e instruction m ay be i gnored. It is re commended th at
the host controller is configured to monitor the transceiver’s status registers listed below prior to issuing a new instruction:
Busy Status/Flag Register 2 bit 0 indicates that the AMIS-53050 is still performing a task
Instruction Enable Status/Flag Register 1 bit 1 indicates that the AMIS-53050 i s ready to receive a new instruction
Note: Instructions issued to the command r egister may be ignor ed b y the AMIS-5305 0 if it is bus y (bus y status bit) or it if is not read y to
receive a new instruction (instruction enable status bit). An application program should poll these status flags.
6.3 Functional Flow Diagrams
CLK output (allows for housekeep
Figure 29a: Receiver Flow Diagram
AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 29b: Receiver Flow Diagram (cont.)
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 30: Transmitter Flow Diagram
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 31: ROM 2 Regs
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 32: Idle State Flow Diagram
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 33: EE Flow Diagram
6.4 Frequency
s an internal PLL/VCO to generate the RF frequency for both trans mit and receive modes of operation. Only one
es. The self-calibration process is to be executed at least once following start-up or after a
gnificant change in the RF frequency.
The on-chip processor will calculate fo ur (30 0kHz) channel s above and four (300k Hz) ch ann els below the center frequency entered into
registers 0X05, 0X06, 0X07 and 0 X08, respectively. This occurs once a ROM2REGS ins truction is executed. Caution is advise d when
using any of the multi-channel features of the device, as the operating frequency could be altered.
6.4.1. Frequency Control
AMIS has developed an executable program (AMIS-53KF ractNCalc.exe), available fro m AMIS, which generates the register values for
the frequency divider a nd 24-bit fractional word to produce a desired frequency. First, the AMIS-53050 must have the correct LC for the
The AMIS-53050 use
set of registers needs to be programmed to generate the TX frequency and to generate the LO frequency to produce the mixing
frequency for converting the received signal to the low IF (about 500kHz). The self-calibration process will in turn trim internal
capacitance to tune the TX and RX frequenci
si
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
desired frequency connected to the VCO pins. There is internal capac itance, which is part of the capac itance for determining the valu e
o ctor. The following equation can be us ermine the approximate value of the LC components. Please note that the
V lacement of the o . The compon ents should be pl aced as close t o the AMIS-53050 as practic ally
possible (even short traces add sign ificant para to the components should be made symmetrical.
The V the A fferen ne illator (DNRO), com monly found in the literature. It uses an inter nal
voltag able c combina L and C to provid e the desired frequency. T he output frequenc y is
estimated by:
f the indu ed to det
mponentsCO is sensitive to the p LC c sitics) and the traces
CO in
e vari MIS-53050 is a di
(varactor) in tial gative resistance osc
apacitor tion with an exte rnal
Where: Ltot and Ctot are the total inductance and c his includes the internal capacitanc e of
approximately 2pF.
The RF PLL is a 24-bit sigma delta based fracti receive, and alternately a direct RF
utput for transmit.
nd second steps pertain
produced a program for
etermining the values for these registers, AMIS53KfractionalNCalculator)
ency- Program the three register fractional N word (AMI Semiconductor has pr oduc ed a progr am for determi ning th e
er
Setting the RF chan done ou ter, along with the RF frequency 2, 1 and 0 registers. The RF
vider register is used to specif y the integer portion of the divide value, and the RF Frequency 2, 1 and 0 registers are used to specify
s are calculated as follows:
apacitance respectively at the VCO pins. T
onal N synthesizer used to provi de the LO signal for
o
Register descriptions:
RF Divider- The RF frequency of th e receive r must be co nfigure d. T his is don e in two steps; the first a
o setting the RF divider and setting the fractional N word, respectively (AMI Semiconductor has t
d
RF Frequ
values for these registers, AMIS53KfractionalNCalculator)
Peak Deviation- When the data modulation is to be FSK, the two register peak deviation must also be set. The deviation
should be set to a value between one half and one times the data rate. Maximum d evi ation is about 200kHz for any data rate.
6.4.1.1. RF Divid
nel frequency is thr gh the RF divider regis
di
the fraction. The value
Where FChannel is the desired RF center frequency. The value for the RF divider register is found by,
Where integer is the value used for RF divider. The last step is to calculate the fractional value. This is done as,
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Fraction is the value to be used in the RF frequency 2, 1 and 0 registers. As an example, if the desired RF frequency channel is
9 ,
03.5MHz
For this example, the RF divider r r is w ency 2 is written to 0xFE, RF Frequency 1 to 0x95, and RF
requency 0 to 0x54.This value +/- 1 is fed directly to the PLL as N0 and N1. (i.e. if 63, send 64 and 65 to the PLL)
able 18: RF Divider - 0X05 [5]
egiste ritten to 0x26, RF Frequ
F
TBit Name Comment
7:0 The divider value is the rounded result of dividing the RF frequency by
RF_divide [7:0] 24MHz
6.4.1.2.
Table 19: RF Frequency 2 = 0X06 [6]
RF Frequency 2
Bit Name Comment
7:0 RF_FREQ [23:16] Upper 8 bits of the RF fraction
6.4.1.3. RF Frequency 1
Table 20: RF Frequency 1 - 0X07 [7]
Bit Name Comment
7:0 RF_FREQ [15:8] Center 8 bits of the RF fraction
6. 4. R 0
Table 21: RF Frequency 0 - 0X08 [8]
4.1. F Frequency
Bit Name Comm t en
7:0 :0] Lower 8 bits of the RF fraction
RF_FREQ [7
6.4.1.5. Peak Deviation 1
T pea FSK transmissions is determined by the peak dev iation 1 register and the peak deviation 0 register. T his value
is also used inside the DF the value for the peak deviation is straightforward:
he k deviation for T FSK detector. Calculation of
The result of this equation, converte eviation registers.
able 22: Peak Deviation 1 - 0X09 [9]
d to Hex, is entered into the peak d
TBit Name Comment
7:0 PEAK_DEV [15:8] Upper 8 bits of the peak deviation
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.4.1.6. Peak Deviation 0
0 - 0X0A [10] Table 23: Peak Deviation
Bit Name Comment
7:0 Lower 8 bits of the peak deviation
PEAK_DEV [7:0]
4.1.7.
Contains
able 24: RF PLL Options - 0X28 [40]
6. RF PLL Options
general options for the setup of the RF PLL.
TBit Name State Comment
1 The kicker has been calibrated
7 Kicker calibration status ted 0 The kicker has not been calibra
1 Use the Type 1 compensation for external crystal with curves similar to Type 1
6 Temperature
compensation curve 0 Use the Type 2 compensation for external crystal with curves similar to Type 2
5 Reserved
4 Reserved
1
3 Internal loop filter 0 Enable using the internal loop filter for the PLL (used for calibration)
1 50uA
2 Charge pump current 0 25uA
1 Iv 10
00 Ivco= 600uA
Ivco= auto level control
co[1:0]
11
01 Ivco= 1.2mA
Ivco= 800uA
Figure 34: Typical Crystal Temperature Curve for Crystal with Type 1 Characteristics
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 35: Typical Crystal Temperature Curve for Crystal with Type 2 Characteristics
6.4.2. 10kHz i
The AMIS-53 le modes. This very low po wer oscillator provides t he
clock for timing h as sniff receive, burst transmit or housekee ping. The oscillator is trimmed in the calibration instructions.
Register des i
10k r. (See Section 6.10.1.4)**
m Clock
Th ally 24MHz) as an output to an external host
control
Osc llator
050 has an internal 10kHz oscillator which is active in sta nd-by or id
functions suc
cript ons:
Oscillator Trim- The value of the calibration for the 10kHz oscill ato
6.4.3. Syste
e AMIS-53050 provides a divided version of the external reference oscillator (typic
ler or other circuits needing a clock.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 25: System Clock Control
Register
Number (HEX) Name Bits Function
11 POR starts in TX
10 POR starts in RX
01 POR starts in idle
2,1
00 POR starts in standby
0X0C
General options A
0 Standby mode with system clock output
11 External XTAL reference divided by 2 (12MHz)
10 External XTAL reference divided by 4 (6MHz)
01 External XTAL reference divided by 8 (3MHz)
0X0D General options B 1,0
00 System clock off
11 System clock continues for 1024 clock cycles
10 System clock continues for 512 clock cycles
01 System clock continues for 256 clock cycles
0X10 Idle config 3 4,
00 System clock shuts down after idle command ASAP
Regist ptions:
Crystal Oscillator Trim- The value of the calibration for the 10kHz oscillat or. (See Section 6.10.1.1)
.4.4. Qu
The AMIS-530 ker” to force the crystal oscillator
close to the RF frequenc y. Information on
the Quick Start circuit can be obtained in the following documents: QuickStart.doc, and AMIS-53XXX_QuickStartAppNote.pdf.
able 26: Kicker Calibration
er descri
6 ick Start
50 includes the ASTRIC family patented Quick Start oscillator. This circuit uses a “kic
the final desired frequenc y. T his reduces th e time required for th e cr ystal oscillator to settle to
T
Register
Number (HEX) Name Bits Function
0X28 RF PLL Options 7 Kicker calibration status
R e ons:
Q tart he value of ib
6.4.5. Self Cal on
T AMIS-53 0 has internal trim cti th ibration
is started by writing an instruction to the comman the AMIS-53050
has been pow efore the AMIS-530 e, the application
monitor the status registers and trim value registers to determine that the calibration was successful.
Note T
ew PLL for an
lication.
e LNA calibration, therefore this calibration is not typically
calibratio
egister d scripti
uick S Trim- T the cal ration for the kicker. (See Section 6.10.1.3)
ibrati
he 05 fun ons for e PLL, TX PLL, RX PLL, 10kHz oscillator, and kicker (Quick Start). A self cal
d register. This self calibration needs to be done at least once after
50 is placed into any mode such as transmit or receive. In this casered on and b
should
: he frequenc y of the AMIS-53050 can change a small amount (possibl y as much as +/- 10MHz at 91 5MHz) without requiring a
calibration. This tolerance depends on the frequency and VCO coil, so would have to be empirically determined n
app
ote: An RF signal input to the receiver is required when performing thN
performed. An application designed with the AMIS-53050 should consider the proper way to do an LNA calibration or even if an LNA
n is needed.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 27: Self Calibration Command
Register
Number (HEX) Name Code Function
0X07 Calibrate the Quick Start (kicker)
0X08 Calibrate the 10kHz oscillator
0X09 Calibrate the PLL
0X00 m
0X0A Calibrate the LNA
Co mand
Bit 2 Calibrate PLL during HK
Bit 1 Calibrate 10kHz oscillator during HK
0X1B Housekeeping
config Bit 0 Calibrate kicker during HK
Register
Status- C t
Softwar a
Instructi n Enable- Indicates that the AMIS-53050 is ready to receive a new instruction.
Busy- Indicates that the AMIS-53050 is still busy with internal tasks.
6.4.5.1. Status/Flag1
The purpose of the Status1 register is to provide information back to the host on the status of the part. T his register should be queried
at the completion of calibration sequ ences to ensure proper operation. The flags will be reset when the register is read.
CheckSum indicates whether an attempt to read or write the EE has failed due to an incorrect CheckSum.
Instruction Enable ndicates that the AMIS-53050 is ready to receive an instruction. This can be used to insure that the AMIS-53050
does not miss a command instruction due to the AMIS-53050 not being ready. Along with the busy flag, these status flags can police
the flow of commands to the AMIS-53050.
/Flag1 - 0X01 [1]
descriptions:
on ins the results of calibrations, instructions and activity in the AMIS-5a 3050.
e St te- Shows the current mode of the AMIS-53050.
o
i
Table 28: Status
Bit Name State Comment
1 PLL out of lock on startup (RX, TX, Sniff, Burst)
7 PLL xLock
0
1 PLL calibration for transmit failed
6 TX PLL cal 0
1 PLL calibration for receive failed
5 RX PLL cal 0
1 10kHz RC oscillator calibration failed
4 RC cal 0
1 Quick Start calibration failed
3 Quick Start cal 0
1 EE CheckSum failed
2 CheckSum 0
1 The AMIS-53050 is in a state of operation that can accept instructions
1 Instruction enable
0
1 ADC conversion complete
0 ADC done 0
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6. Status/Flag2
T S r prov s inform of the following reasons:
Calibration: The usy bit quence. Status2 can be repe atedly polled durin g
n sequence to dete
Read/Write EE: ile the ing from or writing to the E E, the busy bit will remain set.
: W in the nd a valid chip ID is found, the AMIS-53050 will begin the processing of this packet.
During the time t acket d, the busy bit will be set high.
X: A r the co enabled, the busy bit will remain high
until the part has complete mission of the packet.
Housekeeping: is a ousekeeping cycle.
ed during a burst transmission.
tatus2 also contains information on the reason a n interrupt was issued to the external host.
The CCA channel status b its provi de information back to t he host on which channel within the m ulti-chann els is bei ng used for
fter a CCA enabled transmission, these bits will be set to indicate which channel was used. For multi-
channel enabled receivers performing multi-channel sniff, these bits are us ed to indicate t he channel up on which either energy
When the CCA is enabled, Bit 0 (CCA failed) is used to indicate whether or not the channel is clear. The flags will be reset
T 29 - 0X02
4.5.2.
he tatus2 registe ide ation on the operating status of the part. The busy bit is asserted for any
b will remain high for the duration of a calibration se
rmine when it’s complete. a calibratio
Wh AMIS-53050 is read
Buffered RX hen receive mode a
he p is being processe
Buffered T fte mmand is given for transmit with the buffered packet option
d the actual trans
Busy sserted during a h
Burst TX: Busy is assert
S
communication. A
or an entire packet was found.
when the register is read.
able : Status/Flag2 [2]
Bit Name State Comment
7:4 CCA Channel Indicates channel selected during CCA
[3:0]
3:1 Interrupt type
111
110
101
100
011
010
001
000
RX CRC failed
Receive energy dwell timer timed out
CCA failed
Transmit complete
Buffer data for TX
Data has been received
Housekeeping
Low battery
1 AMIS-53050 is busy
0 Busy 0
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.4.5.3. Software State
Software state displays the current mode of the AMIS-530 n be used to monitor the activity of the AMIS-
53050.
ware State - 0X3C [60]
50. This status register ca
Table 30: Soft
Bit Name State Comment
7:0 tate
1111
010
010
0011
0010
0001
0000
Undetermined
Startup data to registers
A
Cali
Cali llato
Calibrati Start (kic cillator
ead da
riti dat
Idle
Transmitting
Receiving
Standb
1011
1010
1001 Copying ROM
Calibrating LN
1000
0111
0110
1
0 R
W
brating PLL
brating 10kHz osci
ng Quick r
ker) os
ing EE
ng EE ta
a
y
Software s
6.5 Receiver
The AMIS-53050 receiver is desi gned for eptio n/o key ( uency key (F odu ignals. The r eceiver
includes all the circu to re data fr lated signal carri he receiver operates on fixed
frequencies in the operating frequency ra e of 300 to 96 using l fracti ncy. The receiver
e incoming signal. T he rece iver can set a user defi ned fixed thr eshold
for d signal for determining the presence of signal and the state of the
reco and the data from the incoming signal
(FSK
ser defined
o
o Common data rates from 1.2kbps to 128kbps or user defined
he AMIS-53050 receiver is a low IF frequency single down conversion, sub-sampling, image rejection architecture with a common
AM/FM IF chain. Three demodulators are used for signal detection with additional post-detection and filtering capabilities for data
recovery.
A complex FFT demodulator is used for FSK signals with data rates > 20kbps.
A digital PLL demodulator is used for FSK signals with data rates less than 20kbps.
A logarithmic (RSSI) detector is used for OOK/ASK signals.
6.5.1. Receiver Circuit Brief Overview
Clock and Dat a Recovery: The AMIS-53050 c an extract a synchron ous clock signal from the received data. In this mode, the data in
the received signal is detecte d, filtered and then f ed into the clock and data recovery b lock where additional digital filtering is performed.
The waveform is sampled using a data clock in the AMIS-53050 to synchronously recover the data. Signal sensitivity is improved and
the recovered data jitter is reduced by this method.
rec
om eith
n of o
er the ff shift
OOK AM) or freq
SK modu shift M) m
er. T lated s
itry cover or the F
0MHz ng an interna onal N PLL to set the freque
can reduce power consumption us ing the Sniff Mode to acquire th
hold from the incomingata detection or it can form a thres
vered waveform. The receiver can use a synchronous data detector to extract the d ata clock
modulation always uses this method of data detection).
O K moduO lati on (AM)
o Manchester encoding option (600bps to 9.6kbps data rates)
o CDR data detection o
o ption (recommended that this be used)
Common data rates from 1.2kbps to 19.2kbps or u
FSK/GFSK modulation (FM)
o Manchester encoding (600bps to 64kbps data rates)
FFT or PLL demodulation (depen ds on data rate)
T
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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pling LO frequency architecture is implemented that down converts the incoming RF signal to the IF
oving image rejection and creating the signals
quired for the complex FFT FSK signal detection. The receiver uses this quadrature down-conversion and a combination of passive
niff Signal Acquisition: As with earlier ASTRIC devices, the AMIS-53050 can reduce the receiver power requirements by
Mode for RF signal detection. Sniff mode is a method using the Quick Start oscillator to quickly wake the
ceiver, check for signal ener gy and return to slee p or start the receive fu nction. T he Quick Start can start the receiver cr ystal oscillator
in as little
sleep in as little as 130 micro-secon ds. More information about this sniff mode is in Section 6.7.2.
Table 31:
LO Frequency: A sub-sam
frequency of about 500kHz. The LO frequency is produced from the internal VCO frequency. The frequency design of the LO signal
reduces the power consumption of the AMIS-53050 and simplifies the receiver, achieving reliable, quadrature LO signal generation.
IF Topology: The receiver implements a quadrature down-conversion architecture impr
re
and active poly-phase filtering to provide image suppression.
S
implementing the Sniff
re as 10 micro-seconds. Using this fast start time, the sniff mode can turn on the receiv er, check for sign al en ergy and return to
Receive Command
Register
Number (HEX) Name Code Function
0X01 (remember that all parameters for receive must be set before issuing
Instruction to place the AMIS-53050 into receive
this command)
0X00 Command
0X03 Instruction to set the AMIS-53050 into the Idle Mode
0X10 Idle config Bit 0 Enable sniff function when in Idle Mode
e
or the receiver must be set.
n 6.4.1.1)
6.5.1.1.
Regist r descriptions:
RX Config- Options f
RF Frequency- The RF frequency of the receiver must be configured. (See Sectio
RX Configuration
Figure 36: Receiver Timing Chart
AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 32: Receiver Timing
Timing
Symbol Min. Typ. Max. Units Comments
TPRE MOD1MOD1 should be made long enough to allow the receiver to
D Bits
acquire the signal
The TX preamble
TE0 255 D Bits The energy dwell timer should be set long enough to allow the receiver to
detect the energy2
TID 0 255 should be set long enough to allow the receiver to detect
the chip ID or global ID2
D Bits
The ID dwell timer
TLOP 1 Default 255 D Bits The length of packet will turn the receiver off after the number of data bits is
received
Notes:
1. Indicates the need for a a lation selected.
2. The dwell timers need to be long e er to stay active from the time it turns on due to energy and the time that the desired event occurs.
How set t case of false energy detection or signal corruption, excessive power dissipation results
he RX config register is used to set options for receive mode operatio n.
Wake on Energy: When ena bled, the CDR circuit is hel d i n reset until the ener g y threshol d is met. This option ca n be used to
make the normal receiver function to perform similar to sniff. The energy dwell timer is used to determine how long the
Gate on Energy: This option can be used in FM rec eive mode on ly, an d will gate th e data i nterface whil e th e energ y on RSSI
rformance:
1. Normal gain mode reduc es the current requirement for the LNA, but will loose some gain or sensitivity.
gain mode delivers the best sensitivity but increases the current requirement also.
3. Linear mode s ets the LNA to have less sens itivity than the high gai n mode and more sensitivity than the normal
orce Multi-Channel: When this bit is set, the bits in Status/Flag2 register (which usually show which channel the radio is on)
2. Write register 0X02 bits [7:4] to select the channel frequency to use
preamble nd the type of preamble is determined by the data modu
nough to allow the receiv
ever, if the dwell times are o their maximum value, in the
T
receiver will stay on checking for energy (with FF in the energy dwell time register, the receiver will stay on until the threshold
is met).
is below the energy threshold.
LNA Mode: The LNA can be configured for the following pe
2. High
gain mode while requiring less current than the high gain mode.
AM_FM_RX: Sets the mode of operation for receive
F
can be overwritten to force the AMIS-53050 to operate on a particular channel.
Typically the sequence should be to:
1. Write register 0X0E bit 3 to force the AMIS-53050 into force multi-channel channel mode
3. Command the AMIS-53050 to transmit or to receive
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 33: RX Config - 0X0E [14]
Bit Name State Comment
1 RSSI output during RX (this value can be overwritten by a test function if the test
registers are unlocked)
7 RS 0
SI active
1 Sniff cycle performed at multiple pre-defined channels
6 Multi channel 0
5
4 LNA mode[1:0]
11
10
01
00
No operation defined
Linear mode
High gain mode
Normal gain mode
3 Force channel 1
0 Force receive mode on a specific channel of the 9 defined channels
(status/Flag2)
1 AM receive mode
2 AM_FM_RX 0 FM receive mode
1 Clock and data outputs gated for RSSI<energy threshold
1 Gate on energy 0
0 Wake on energy 1 Clock and data disabled until energy threshold met
.5.1.2. E
n energy or sniff mode. If the automatic noise floor detection is enabled in sniff,
t MI 0 will overwr ents of this register each time a new threshold is calculated.
able 34: Energy Threshold - 0X15 [21]
6 nergy Threshold
Energy threshold sets the threshold for either wake o
he A S-5305 ite the cont
TBit Name Comment
7:0 E_Threshold Energy detect threshold in DAC mode = E_THRESHOLD*7.8125mV
6.5.1.3. Receiver Parameters
Figure 37: Receiver Sensitivity vs. Data Rate
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 38: RSSI Curve
6.5.1.4. Data Recovery
uration Table 35: Receiver Config
RX Configuration Registers
0X0E RX Config 0X1F CDR
Options A 0X0B Data Rate
Format
0X1E
Filter
Slice
Bit 2 Mod Bit 0 Demod Bit 3 Code Bit 1:0
Data Rage Preamble CDR SOF
0 NRZ SLICE >20k – 128k 10Pattern Yes No
1 2 3
0 FFT 2 3 No4
1 Man SLICE >20k – 128k 10Pattern Yes
0 NRZ1SLICE2<20k 10Pattern Yes3No
0 FM
1 PLL 1 Man SLICE2<20k All 1 or 0’s Yes30X55
0XAA
0 NRZ SLICE21k – 19.2k CW Opt70X55
0 NA61 Man SLICE21k – 19.2k CW Opt70X0A
0 NRZ SLICE21k – 19.2k CW Opt70X55
1 AM
1 NA61 Man SLICE21k – 19.2k CW Opt70X0A
Notes:
1. Long strings of 1’s or 0’s will degrade the
2. SLICE can use the parameters in Table 3performance of the CDR circuits.
7.
Y tes that CDR is detect the data. (See Table 41 and Table 42 for CDR parameters)
4. Manchester encoded data ster decoder to the recovered data.
0 ave th
owi
It is suggested that CDR with fast phase alignment be enabled
)
r CDR parameters)
3. es indica always used to
requires a SOF. A unique SOF (suggested 0x66) is used to bit-align the Manche
5. X55 or 0X0A SOF h
0x55 The foll e following requirements:
ng is suggested:
It is suggested that CDR with activity check be enabled with 8 or 16 bit times
It is suggested that the preamble be long enough to trigger activity check (10 or 20 bit times
0x0A The following is suggested:
It is suggested that CDR with fast phase alignment be enabled
It is suggested that CDR with activity check be enabled with 4 bit times
It is suggested that the preamble be long enough to trigger activity check
6. NA indicates that the parameter is not available for the AM/OOK modulated signals. and Table 42 fo7. OPT indicates that CDR is an option to detect the data however, it is recommended that CDR be used. (See Table 41
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
AM Data Recovery with RSSI
T og c AM detector, used ted signals, produces an RSSI output signal with approximately 18mV/dB
output level. A low pass filte pro additional filtering matched to the AM signal data rate (1.2, 1.8, 2.4, 4.8, 7.2, 9.6, 14.4,
19.2kbp gn sam an hold can be set
to a fixe n use gna king
The RSSI output signal ca n e lied to a clock and data r ecover y circuit, which sync hronizes an AMIS-530 50 internal cloc k with
the incoming data rate (see Op n).
Register descri
Slice Threshold- T slic utomatic. The value for the fixed threshold needs to be
Filter/Slice- Filter s gs
Slice Threshold
he l arithmi with OOK/ASK modula
r
al is vides
s). This filtered si
value or it ca pled
l trac d compared to the slice threshold to recover t he digita l data. T he slice thres
circuit to set a peak or average threshold. d a si
also b app
CDR eratio
ptions:
he e operation needs to be selected, fixed or a
set.
ettin and slice mode need to be selected.
S the level for rece . This threshold is used when the slice method sets in the AM data filter and slice options
register is set to DAC.
hold - 0X1D [29]
ets data slice AM ption
ThresTable 36: Slice
Bit Name Comment
7:0 SL_THRESH [7:0] AM slice threshold in DAC mode = SL_THRESH*7.8125mV
A ta d Slice OptM Da Filter an ions
This register contains settings for de thod of slicing for AM receive mod e.
_FILTER: Sets the post-detection filter bandwidth for RSSI during AM receive. These filter bandwidths are set for the
responding d a rates. hese filter settings can also be used with custom data rates.
AM_HYST: Sets the amount of hysteresis in the AM slice comparator.
AM_SLICE: Us elec ethod for providing a reference to the AM slice comparator.
DAC M This is a fixed threshold lev el programmed into the slice threshold register.
Averag e: n automatic threshol d level where the AMIS-53050 sets the threshold leve l to the average
l of SSI signal. A n external capacitor is required on the PEAK pin to set a bandwidth for the lo w pass filter
response of the a ging circuit. .
Peak M This is similar to the average mode, but only the highest level is determined from the incoming signal
and the AMIS-530 ts the threshold to a level 6dB lo wer than the peak valu e. An external capacitor on the PEAK
pin dete s a e) rate for the peak detector circuit. The value of this capacitor is discussed in
the application note “Setting up the AMIS-52100 Data Slicing Modes” which applies also to this AMIS-53050
parameter.
termining the me
AM
cor at T
ed to s t the m
ode:
e Mod This is a
leve the R vera
ode: 50 se
rmine bleed off (discharg
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 37: AM Data Filter and Slice Options - 0X1E [30]
Bit Name State Comment
[7:5] AM_FILTER[2:0]
000
001
010
011
100
101
110
111
RSSI filter bandwidth =300Hz
RSSI filter bandwidth = 600Hz
RSSI filter bandwidth = 1.2kHz
RSSI filter bandwidth = 2.4kHz
RSSI filter bandwidth = 4.8kHz
RSSI filter bandwidth = 9.6kHz
RSSI filter bandwidth = 19.2kHz
RSSI filter bandwidth = 38.4kHz
4 NU
[3:2] AM_SLICE[1:0]
00
01
10
11
DAC mode: Slice threshold set in register 1Bh
Average mode: AM threshold set using averaging filter
Peak detect mode: AM threshold set using peak detector
DAC mode: Slice threshold set in register 1Bh
[1:0] AM_HYST[1:0]
00
01
10
11
0mV slice hysteresis
25mV slice hysteresis
50mV slice hysteresis
100mV slice hysteresis
FM FFT
The AMIS-53050 receiver uses a FFT function to recover data from a FM/FSK modulated signal when the data rate is higher than
20kbps. The FFT detector uses a two-bit DFFT to demodulate the incoming IF signal. This circuit also uses the same clock recovery
ock (CDR) as the AM detector (see Section 6.1.4) to detect the data.
A pattern of 1’s and 0’s is re quired as a pr ded data is used, requiring a unique
preamble to bit-align the Manchester deco
Register descriptions:
Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate (see
eak Deviation- The peak deviatio n r res the value to be use d for both transmit and rec eive. In the FFT FM receive
th is used to the FFT bins (see Sections 6.4.1.5 and 6.4.1.6).
FM PLL oop Fi or the nts are pre-programmed (iss ue
the command ROM2REGs to have th ine these values). For user defined data rates, this value nee ds to
be calculated. (AMI Semiconductor provi des a program, he xe, which can help in determining the values for this register.)
M L
Th nction to recover the data from a FM/FSK modulated sign al with data rates 20kbps or lo wer. This circuit
us tion, the output of which is fed to the AM CDR circuit to rec over the cl ock, and add itional ly filter the output
da
h hen configured as NRZ FM is a repe ating sequence of 1’s and 0’s. T his gives the CDR circuit
ufficient edges to ac quire lock. H ence, for the NRZ case it is unnecessar y to include a SOF byte. In M anchester
specified as all 1’s (or 0’s). This gives the clock recovery circuit the most edges for lock acquisition. However,
ue to th
#55h or
bl
eamble. A SOF is not requir ed unless Manchester enco
der to the recovered data.
Section 7.1.3).
Pegister sto
mode, is value set-up
Detector L lter- F discrete data rates, the values for the loop filter coefficie
e AMIS-53050 determ
lper.e
CDR Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the
command ROM2REGs to have the AMIS-53050 determ ine these values). For user defined data rates, this value needs to be
calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
F PL (Low Data Rate FSK)
e AMIS-53050 uses a PLL fu
es an A DPLL for demodula
ta.
T
ane preamble sent by the AMIS-53050 w
d PLL demodulator s
mode, the preamble is
d e ambiguity of the preamble, a SOF byte is necess ar y for the Manchester d ecodi ng block. T he sugg ested SOF for this is either
#AAh. The length of preambl e necessary for this mode is dependant upon the loop band width f or the clock recovery PLL.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Register descriptions:
Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate (see
eive. In the FFT FM receive
mode, this value is used to set-up the FFT bins (see Sections 6.4.1.5 and 6.4.1.6).
PLL Detector Loop Filter- For the discrete data rates, the valu es for the loop filter c oeffi cients are pre- progr ammed (issue th e
s to have the AMIS-53050 determin e these values). For user defined data rates, this value n eeds to be
calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
CDR Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the
PLL Dete
Section 7.1.3).
Peak Deviation- The peak deviatio n register stores the value to be use d for both transmit and rec
command ROM2REG
command ROM2REGs to have the AMIS-53050 determ ine these values). For user defined data rates, this value needs to be
calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
ctor Loop Filter Setting
m (helper.exe avail ab le from AMIS) has been created to aid in the design of loop filter settings.
PLL Detector Loop
A progra
able 38: Filter Setting - 0X2B [43] TBit Name Comment
7:0 PLL_CO [7:0] PLL loop filter setting
Table 39: Clock Recovery Loop Filter Setting - 0X2C [44]
Bit Name Comment
7:0 CDR_CO [7:0] Clock recovery filter setting
6.5.1.5. lock and Data Recovery
a recovery for both AM/OOK/ASK and FM/FSK signals. An internal clock in the
AMIS-5305 s programmed o be same rate as the expected data rate in the incoming signal. This clock is then
s om data loop recovery method recovers data without much of
t jitter soci with w
Before l dlon to the operation of the detectors, and how to set them up, it is instructive to review the following related
r ster ns a their fu ctions.
Registe
Fast Phase Alig ent: In both the AM and PLL based FM modes (lower data rate), the AMIS-53050 can be configured to
kly acquire phase lock n incomi ng data. The pattern necessary for the fast phase alignment is simply ‘1010’. This function
can be enabled i CD bled, the CDR circuit will operate with minimum power
ntil the ‘1010 sed to not only recognize the 101 0 pattern, but al so
to instantaneousl de t allowing very fast (less than 4 b it) lock times locking
ming dat
eck: his func in conjunction with th e fast phase alignment to reset the cl ock and data recovery
into i inimal n mode when no transitions are detected on the data line for a specified period.
The check can be configured for 4, 8 or 16 bit times.
Clock (Ts Clock): Al l three detectors use the T s clock as the s ampling c lock for the transitio n from analog to
ase
is
generated come only from nois e. Small fractional values for the clamp can lead to
longer lock times since the clock recovery PLL may not be able to make as large of a correction as is necessary all at once.
C
T AM 50 device performs clock and dathe IS-530
0 i t nearly the
ynchronized to the inc
and noise as ing rate by extracting a clock from the data. This
he ated ireless communication links.
aunching hea
s, set-up optio g in
egi nd n
r descriptions:
nm
quic o
n the R options A register. With this function ena
consumption u ’ sequenc e is re ceived. A 32-bit correlati on is u
a phase correcti on to the clock recover y circuiy provi
the inco a.
Activity Ch
block back T tion can be used
ts m power consumptio
Over-Sampling
digital. This clock should be s et to the highe st rate possibl e , but not greate r than 400 x the data rate, to ensure a dequate ph
information. For the discrete data rates, this value is pre-programmed for those rates when the ROM2REGS command
issued.
Data Rate Clamp: The data rate clamp restricts the clock recovery circuit from wandering when an actual signal is not
present, and the phase error signals being
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Channel Clamp: This clamping circuit is used to hold the low data rate FSK PLL detect or within the specified lim its to preve nt
L from wand absence of signal.
C p
his circuit utilizes an all digital PLL (ADPLL) to recover the clock from the raw sliced data. The slicer output is integrated over a bit time
to provide a phase error, and the sign of the integrati on is used to determine the data symbol.
When using the AMIS-53050 in AM mode with any of the packet framing options enabled, it is necessary to have the SOF byte for
fast phase alignment
atures enabled for the packet framing modes. The preamble that the AMIS-53050 will transmit in AM mode is CW, hence the SOF
ent feature in the CDR to acquire lock. The suggested SOF for AM NRZ format is #55h. This will
p e st transitions covery circuit to acquire lock prior to the incoming packet. For Manchester operation, the
suggest hi anchester decode.
ecause there are no transitions during the preamble in AM mode, the CDR relies on the fast phase alignment for acquiring lock. As
amble can be quite short as long as the activity check is enabled. The preamble should be long
e p the activity d rcuit at the fast phase alignment circuit is reset at the beginning of the SOF. This
g fast phas w gested length for the preamble is 4 BT’s for Manchester
w et to 4 B nd 10 or to 8 or 16 respective ly. Note in the NRZ case, enablin g
a the be forma sition in the data during the length of activity check (i.e.
e 16 BT’s).
R escriptions:
a time R
ified as a 16-bit word for a user defined data rate (see
Section 7.1.3).
d to tell the AMIS-53050 receiver that data will start (see Section 7.1.6)
the PL ering in the
DR O eration
T
proper start-up of the AM CDR circuit. It is recommended that the CDR is set up with the activity check, and
fe
byte is used by the fast phase alignm
rovid the mo for the clock re
ed SOF is #0A. T s will provide early transitions for phase lock, and 4 bits to align the M
B
this is the case, the length of the pre
nough to tri etection ci
nment ry such th
uarantees that the
ith activity check s e alig
T’s, a ill kick in during the SOF. The sug
20 for NRZ, with activity check set
ctivity check will require data tted to guarantee at least one tran
very 8 or
egister d
ID Dwell- Set that the CD circuit will continue to search for the chip ID.
CDR Config- Set the parameters for the clock and data recovery circuits.
Data Rate- Can be specified in the discrete data rate register, or spec
Start of Frame- Byte use
CDR Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the
command ROM2REGs to have the AMIS-53050 determ ine these values). For user defined data rates, this value needs to be
calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
hip ID Dwell TimerC
Used to specify ho w long the clock and data recovery circ uit will stay active after energy has bee n detected, looking for a val id chip ID.
will look for either the chip ID or the global broadcast ID.
0X14 [20]
The part
Table 40: Chip ID Dwell Timer -
Bit Name Comment
7:0 C_DWELL 00h: Code or standard receive wake on code)
01h – FF e dwell time = C_DWELL*bit time * 8
[7:0] dwell timer disabled (f
h: Cod
CDR Options A
his register contains settings for determining t ecovery parameters.
DR_clamp: Limits the CDR frequenc y drift between data packets
Channel_clam p: Restricts the bandwidth to the channel bandwidth
Activity check: Sets a number of bit times that the CDR circuit will shut down if there is no data present
Fast phase alignment: Forces the CDR circuit to quickly synchronize to the incomi ng data
FM mode: The FM detector used in the receiver depends on the data rate of the incomi ng signal
The clock and data r
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 41: CDR OptionsA - 0X1F [31]
Bit Name State Comment
1/64
1/32
1/16
7,6
DR Clamp
1/8
The clamp restricts the clock recovery PLL to +- the fraction selected
of prevents clock
wa
<1> 11
10
01
00 the frequency selected by the BaudCLK which
ndering between data packets
11 +-150
10 +-100
01 +-50
5,4
Channel clamp
00 +-16
Th y lock on signals that are e clamp restricts the PLL detector to onl
wi e IF frequency thin the specified window, centered +-500kHz of th
3,2
Activity check <1>
10
01
00
Reset after 8 bit times of no activity
Re
Activity
11 Reset after 16 bit times of no activity
set after 4 bit times of no activity
check disabled, clock recovery will always run
1 The CDR circuit will perform fast phase alignment
1 FPA enable 0 CDR always running
1 PLL
0 FM mode 0 FFT
CDR Options B
T le clock rate should be as fast as possible
eeding 4
he samp
ithout exc values are written from ROM with the discrete data rate selected. The sample
00 samples per bit time. w
Table 42: CDR OptionsB - 0X20 [32]
Bit Name State Comment
1 CDR is held reset
7 CDR reset 0
6 NU
5 NU
4 NU
3:0 Sample clock
1011
1010
1000
0111
0110
0101
0100
0000
45kHz
90kHz
375kHz
750kHz
1.5M
3M
6M
24M
1001 187.5kHz
0011
0010
0001
8M
12M
16M
Clock Recovery Loop Filter Setting
A progra
Table 43: Clock Recovery Loop Filter Setting - 0X2C [44]
m (AMIS-53CDRPLLCalc.exe available from AMIS) has been created to aid in the design of the CDR loop filter settings.
Bit Name Comment
7:0 CDR_CO [7:0] Clock recovery filter setting
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AMI Semiconductor – Jan. 07, M-20639-002
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.6 Transmitter
Figur
e 39: Typical Output Power vs. Power Register Setting*
*Note: Curve is for output matched to 50.
able 44: Transmit Command TRegister
Number (HEX) Name Code Function
0X00 Command 0X02
Instruction to place the AMIS-53050 into transmit
(Remember that all parameters for tr
command) ansmit must be set before
issuing this
The AMIS-53050 uses a switching class E power amplifier as the high power output driver. The high power PA can be bypassed to
allow a high efficiency at a lower output power. The output drivers are turned on and off directly in AM/OOK/ASK data modulation. A
direct modulation PLL is used to form the FM/FSK signal for transmission. The PLL lo op runs at half of the desired transmit frequency
to provide excellent On/Off ratio for AM, and to lower current consumption in the PLL.
OOK modulation (AM)
FSK modulation (FM)
Burst mode transmit
FM wave shaping
High power and low power range
Register descriptions:
Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate (see
Section 7.1.3)
RF Frequency- The RF frequency of the transmitter must be configured (see section 6.4.1)
Output Power- Sets the RF output level for the AMIS-53050
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Peak Deviation- The FM deviation must be set for F M operation (se e section 6.4.1.5 and 6.4.1.6)
TX Config- Options for the transmitter must be set.
he receiver can detect the signal.
6.6.1. TX Config
General options for transmit.
Sha tional N PLL with a pre-programmed sequence.
T waveform that
modu
ID for TX: This option specifies which ID the AMIS-53050 will transmit when the use ID bit in gen eral options A is enabled.
to transmit from one node to all devices. Chip ID will transmit from one node to only those devices that have
the same chip ID
Buffered TX: When this option is enabled in conjunction with use ID and LOP enable, the packet for transmission is loaded
er to operate on a
specific channel of the nine c hannels defi ned b y the multi-c han nel confi gur ation (this fe ature ca n oper ate on a n y RF frequ ency
able 45:
Preamble- Set a reasonable length of pream ble to insure that t
AM_FM_TX: Used to set the mode for transmit
ping: When enabled, the FSK transitions are digitally shaped in the frac
he filter for the shaping is Gaussian with a BT=1. This reduces the high frequency content of the data
lates the carrier.
Global is used
into internal RAM prior to the RF being enabled.
Force Multi-Channel: When this bit is set to 1, bits[7:4] of Status2 can be written to force the transmitt
if the ROM2REGS command has been used to create nine channels).
Clear Channel Assessment: W hen one of the CCA modes of operation ar e enabled, the AMIS-5305 0 will enable its receiver
to first check for the presence of energy on the specified channel before transmitting.
T TX Config - 0X0F [15]
Bit Name State Comment
7,6
Clear channel
assessment
11
10
01
00
Not allowed
Multi-channel assessment (pre-defined channels)
Single clear channel assessment prior to transmit (any frequency)
No clear channel assessment performed, normal operation
1
5 Force channel 0
1 Enable smooth power up of PA (reduces the spurious response of the TX on
power up)
4 Smooth turn on 0
3 NU
1 Use the defined chip ID from the chip ID register
2 ID for TX 0 Use the defined global ID from the chip ID register
1 Gaussian FM data shaping enabled
1 Shaping 0 FM data shaping disabled
1 AM transmit mode
0 AM_FM_TX 0 FM transmit mode
6.6.2. Output Power
C_POWER: Coarse output power control for the power amplifier. When set high, the max out is 15dBm - when set low, the
max output is 0dBm.
F_POWER: Fine output power control for the PA. These seven bits control the voltage on the RFPWR pin via an internal
DAC.F_POWER conversion output voltage.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
T 46 t Power - 0X able : Outpu 18 [24]
Bit Name Comment
7 C_POWER arse o Co utput power selection sent to PA
6:0 F_POWER [6:0] Fine out f the DAC, LSB of DAC=0) put power control (upper 7 bits o
6.6.3. Preamble Length
This byte is used to define gth of preamb it.
T 47 gth A [26]
the len le to send prior to data in both transmit and burst mode transm
able : Preamble Len - 0X1
Bit Name Comment
7 PreambleLen [7:0] ength, i s, oL n bit time f CW (AM), or ’10 (FM) sent prior to preamble in burst
Table 48: Suggested Preambles
Modulation Preamble Comment
AM NR CW
Z with CDR SOF required and suggested as 0X 551
AM Ma th CDR nchester wi CW SOF required and suggested as 0x0A2
FM FFT 1/0 pattern No SOF is required
FM PLL
(NRZ) 1/0 pattern No SOF is required
FM PLL (Manchester) All 1s or 0s SOF is required and suggested to be 55(Hex) or AA(Hex)3
Notes:
3. The length of this preamble is dependent on the loop bandwidth of the recovery clock PLL.
6.6.4. F S
he AMIS-53050 allows the user to enable data shaping of the data waveform to improve the RF spectral efficiency. When enabled,
recovery NCO is used to provide an internal clock at 16 times the selected data rate. This clock is used to cycle through a pre-
a transition is detected on the TX input. The shaping pattern is Gaussian with a BT=1. The intermediate
ermined from the peak deviation re gister when an external host controller writes the ‘RO M 2 REGS’ to the
.7 Idle
T 49 ommand
1. When using SOF with NRZ data, it is suggested that fast phase alignment is enabled, activity check is set to 8 or 16 and preamble length is 10 or 20 bit times.
2. When using SOF with Manchester coded data, it is suggested that fast phase alignment is enabled, activity check is set to 4 bit times and preamble length is set
long enough to trigger the activi ty check.
M Transmit Data haping
T
the clock
defined pattern whenever
values for the shaping are det
AMIS-53050 command register.
6
able : Idle C
Register
Number (HEX) Name Code Function
0X03 Enable the idle state
0X00 Command
0X04 Return to idle state
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 50: Idle Configuration
Register
Number (HEX) Name Bits Function
0X02 Status/Flag2 0 AMIS-53050 is busy
2:1 Select state that AMIS-53050 enters on POR
0X0C General options A 0 Output system clock in standby mode
0X0D ency General options B 1, 0 Select the system clock frequ
2 Enable housekeeping during Idle state
1 Enable burst transmit operation during Idle state
0X10 Idle config 0 Enable sniff receive operation during Idle state
Note that there are two low-po wer modes for AMIS-53050 – standby and idle. Stan dby allows the SYSCLK output. Idle is the very low
power state without SYSCLK output.
Table 51: Idle Modes
Idle Tasks Description
Sniff Receiver periodic wake-up and RF energy detection check
Burst transmit Periodic wake and transmit function
Housekeeping Used to perform periodic temperatur alibration or to wake external host controller e correction, c
Standby Low-power mode with no activity ma rogrammed to continue to output system clock y be p
T IS-53050 allo ws for a lo w-po wer mode. Po w irements are reduced when the ver y lo w po wer 10kHz osci llator is the clock
f ns the timers for ei timer, the burst transmit timer or the housekeeping wake-up
ti low power 10kHz e AMIS-53050 can still provide a clock signal output to an
h as a microproc of a valid data packet or a Housekeeping cycle where the
MIS-53050 has been programmed to issue a wake up to the external host controller.
he options for idle mode must be set.
is the time between the AMIS-53050 issuing an interrupt to indicate that data is ready and the time
e assertion of the DSSN signal.
Idle to System Clo ommand, the system clock
e additi
he AM er requ
or the device. This oscillator ru ther the sniff wake-up
mer. However, even when the
xternal host controller device suc oscillator is running, th
essor after receptione
A
The AMIS-53050 will return t o this low power idle state after activities such as transmit, receiv e or the various timers are done and the
external host controller writes the ‘Return to Idle’ instruction to the AMIS-53050 comm and register.
egister descriptions: R
Idle Config- T
6.7.1. Idle Config
The idle configuration register is used to specify which periodic tasks are performed once the idle comm and is given in register 0. Any
combination of sniff, burst and housekeeping can be enabled.
INT to DSSN Timing: This
ata transfer sthat d tarts with th
ck Stop: Once the AMIS-53050 has completed a task and is issued the idle c
onal clock cycles to allow the external host controller to finish its tasks. can produc
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 52: Idle Config - 0X10 [16]
Bit Name State Comment
DSSN going active is delayed 8 bit times from INT
7:5 Wait timing between
ff receive
111
000 DSSN is immediately active after INT
INT and DSSN for …
sni 11 System ts 1024 clock cycles before shutdown after idle command clock outpu
10 System clock outputs 512 clock cycles before shutdown after idle command
01 System clock outputs 256 clock cycles before shutdown after idle command
4,3
Wait timing n betwee
idle instruction and
system clock shutoff
time 00 System clock immediately shuts down after idle command
1 Periodic housekeeping enabled (HK settings must be set)
2 Housekeeping
Enable 0
1 Periodic burst mode enabled (burst settings must be set)
1 Burst enable 0
1 Periodic Sniff mode enabled (sniff settings must be set)
0 Sniff enable 0
6.7.2. Sn
Table 53:
iff Mode Operation
Sniff Mode Configuration
Register
Number (HEX) Name Bits Function
1 Force the receiver to not output Clk&Data < energy level
0X0E RX Config 0 Set the receiver to wak when at energy level threshold e
0X10 Idle Config 2 Enable periodic sniff mode
The Quick Start technology enables t d sniff mode. As implemented in the
AMIS-53050, this sniff mode can wake the receiver and acquire the transmitted message in as little as 130 microseconds.
he AMIS-53050 to operate its receiver in a mode calle
Figure 40: Sniff Waveform
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AMIS-53050 Frequency Agile Transceiver Data Sheet
The sniff mode of operation puts the AMIS-53050 rece iver into a cyclic mode of sleeping and peri odically waking to check for received
gnal energy. When energy is detected the receiver is placed in receive mode and the AMIS-53050 attempts to recover data. The
receiver i
sleep.
The AMI
si n sniff mode can be configured to check for a valid ID. The failure to receive a valid ID will cause the receiver to go back to
S-53050 receiver average supply c urrent can b e estimated as:
Where, is receiver current consumption in continuous receive mode, equal to or less than 12mA;
is receiver current consumption in sleep mod e, equa l to or less than 2uA;
is programmable receiver energy scan impulse on time (sniff time), approximately equal to 130µs minimum;
is programmable receiver off time period length between receiver energy scan impulses (sniff mode interval).
Config-Thi the mode.
al- Set the time interval between receiver wakeups in the sniff mode.
hresho - The threshold for detecting the incomi ng RF energy must be set (see Section 6.5.1.2).
ll T - Set th receiver will rema ing for RF energy detection.
Code Dwell Tim nce R the receiver can determine if the message has the unique ID for that
he time interval e Chip ID Dwell Timer).
The number be monitored for false wake ups and the energy threshold
ccount for the no
6 2.1.
SNIFF_FILTER: Setting for the energy detection filter. This all o ws for different settings of the AM data filter between sniff and
receive. The energy dwell timer needs to be extended long enough to allow for this filter t o settle duri ng the sniff cycle.
his bit enable the AMIS-53050 to scan th e nine pre-d efined c hannels d efined by the multi-channel f eature of
Sniff Interval Resolu rmines the clock for the sniff interval timer.
Register descriptions:
Sniff s sets options in the sniff
Sniff Interv
Energy T ld
Energy Dwe ime e time interval that the in active look
e- O F ener gy has been detected
receiver. T for looking for this ID must be set (se
Threshold-
to a of times a wake up is received can
ise level. adjusted
.7. Sniff Config
The Sniff config register is used to s on of the part during a sniff cycle, be yond those set in the RX
config register. et additional options for the operati
Auto-Threshold Count Value: Number of sniff cycles used to determine whether to raise or lower the energy threshold for
sniff. Any value other than 0x00 in this register will enable the auto-threshold function.
Multi Channel: T
the AMIS-53050.
tion: Dete
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 54: Sniff Config - 0X11 [17]
Bit Name State Comment
7:5 SNIFF_FILTER
01
01
100
101
110
width =300Hz
I filter bandwidth = 600Hz
SI filter bandwidth = 1.2kHz
RSSI filter bandwidth = 9.6kHz
RSSI filter bandwidth = 19.2kHz
RSSI filter bandwidth = 38.4kHz
000
001 RSSI filter band
RSS
0 RS
1 RSSI filter bandwidth = 2.4kHz
RSSI filter bandwidth = 4.8kHz
111
11 100
10 500
01 100
4,3
Auto-threshold
count value
00 Disable
This is the number of Sniff cycles to count false wake ups due to the
noise level, so that the threshold level can be adjusted. It is
adjusted higher when the number of false wake ups exceeds the
wake up target number. It is adjusted down when there are fewer
false wake ups than the target number. Entering a number other
than 00 in this register will enable the auto-threshold.
2 NU
1 NU
1 Sniff interval timer resolution is 100ms (interval between sniff signal detection
events is (sniff interval) times (sniff resolution)
0 Sniff interval
resolution 0 Sniff interval timer resolution is 500us (interval between sniff signal detection
ev (sn times (sniff resolution) ents is iff interval)
0X12 [18]
6.7.2.2. Sniff Interval Timer
This is used to specify the period (time between sniff events) of the sniff operation. The sniff interval is this value times the sniff interval
resolution value (set in the sniff config register).
Table 55: Sniff Interval Timer -
Bit Name Comment
7:0 Sn
NIFF_INT [7:0] Sniff interval timer =SNIFF_INT* S niff interval timer resolutio
6.7.2.3. Energy Dwell Timer
receiver will stay on in a sniff cycle, checking for the presence of a signal. It is also used for a receive
ake the CCA compatible with a market or government standard.
able 56: Energy Dwell Timer - 0X13 [19]
This is the length of time the
command when the wake on energy bit is asserted in RX config. This may need be set to a fixed value, such as 10 milli-seconds, to
m
TBit Name Comment
7:0 E00h: Energy dwell timer not used, energy determined by an impulse sample
_DWELL[7:0] 01h – FEh: Energy dwell time = E_DWELL * 100us
FFh: Receiver remains on until energy threshold is met
.7.2.4. Energy Threshold
his sets d in
niff, the ulated.
6
T
s the threshold for either wake on energy or sniff mode signal acquisition. If the automatic noise floor detection is enable
AMIS-53050 will overwrite the contents of this register each time a new threshold is calc
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Automatic Threshold Optimization in Sniff Mod e
A ailable in th m will enable the AMIS-53050 to automatically adjust the energy threshold of the
AMIS- timize sensi target number of wake-ups (register 0X2F) allows the user to specify a
value for the number of false wake wed with the selected configur ation of the sniff mode (by bits [4:3] in the
SNIFF register) mber
As an example:
umber of sniff cycl
rget num of fal wake-ups is set to 50 (target number wake-ups),
Then over the course of the next 5 ely by energy:
0 times, the threshol ity,
mes, the threshold will be decrease d to increase the sensitivity.
U ng et th resho ergy detection can h ave a dra matic impact on the life of battery powered devices. The AMIS-
53050 ust to cha ng lev ng maximum sensitivity and will not waste power by
continu ing and pr ssing background noise.
Additio e energy thr shold setting ca ller. The amount the threshold will increase or
decrease is based on Table 57, wi the order of the rows in the same order as the AMIS-53050 will evaluate the c onditions.
able 57: Auto Threshold Adjust
n option av e sniff ode config register
53050 to op the tivity of the sniff mode. The
-ups the AMIS-53050 is allo
of sniff cycles. _CONFIG nu
If the n
If the ta es is set to 500 (sniff config [Bit 4:3]),
ber se
00 sniff cycles the radio is triggered fals
d will be increased to reduce the sensitivMore than 5
Less than 50 ti
si this option to s e th ld for en
will adj
ally wak ngi els of background noise while still maintaini
oce
nally, th e n be monitored by an external host contro
th
T
Condition Adjustment
Select the number of sniff cycles as the test period
Enter the desired number of false wake ups per
period Note: a false wake up is when the receiver detects energy but fails to detect the ID in the
packet
Then if wake ups/period > target Threshold is increased
Then if wake ups/period < target Threshold is decreased
hre AMIS e next, due to design, manufacturing tolerances, and
nvironment changes; such as temperature and voltage. This automatic threshold optimization can be used to adjust the threshold by
onitoring the level of false wake ups due to background noise. The adjustment in this fashion can reduce the effects of design and
hold setting of the AMIS-53050.
Register descriptions:
arget- Set a value for the allowed nu lse wake-ups desired.
Target Threshold
The t shold of the -53050 can var y over a wide range from one device to th
e
m
manufacturing on the thres
Tmber of fa
he number of false wake ups occurring during a period of time is used to automatically adjust the energy threshold in the sniff
peration. This allows the AMIS-53050 to automatically adjust its input level to compensate for, manufacturing, components,
able 58: Target Wake Ups - 0X2F [47]
T
o
environment, temperature an d/or voltage.
TBit Name Comment
7:0 Target [7:0]
The number of wake-ups that the sniff circuit will try to adjust the threshold to not have
more false wake-ups or less missed signal detections. This register allows the number to
be 0 to 255, but this number should always be less than the number of sniff count (sniff
config bit 4:3).
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.7.3. Burst Transmit Data
Table 59: Burst Transmission Configuration
Register
Number (HEX) Name Bits Function
0X10 Idle Config 1 Enable burst transmissions
mode of tra a functio can ca essage at a programmed time interval or by
g the xBURST ctive (the -5 ST mode), causing the AMIS-53050 to immediatel y transmit
sage. The o e star burst mode in the idle register and then writing to the command
r to set the to idle ode. T ister values (a message)
ersio .
egister descriptions:
onfig- Set the burst transmission parameters
User DataB- Message for xBURST initiated transmissions.
Burst nsmission is n that
AMIS use the AMIS-53050 to transmit a m
3050 must be in the xBURassertin
a mes pin to a
burst mode can als b ted by enabling the
registe AMIS-5305 0 in
n values m he xBURST mode sets a timed automatic transmiss ion of reg
or ADC conv
R
Burst C
Burst Interval- Set the time interval between burst transmissions
User DataA- Message for timer initiated transmissions
Figure 41: Data Packet Format Showing Order for Burst TX Content
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Used to set the options for the burst mode of operation:
R_BURST: These bits set the number of times the pack et is to be repeated eac h burst interval. This can b e used to increase
y that all packets will get through when several burst transmitters are located in the same area.
option is included to allow for the operating case of having multiple transmitters sending to a single
er or for one to send to on e receiver. The multiple transmitters will need to be configur ed to send the global
X c smitter’s packet. Sending the chip ID as part of the
e transmitter to send to only that receiver which has the same Chip ID.
Send Internal ADC Data: When enabled, the AMIS-53050 will perform conversions on the battery voltage and temperature
includes these conversions as part of the packet payload.
Send External ADC Data: When enabled, the AMIS-53050 will perform conversions on the two external ADC inputs and
the probabilit
Send Chip ID: This
receiv transmitter
chip ID in the T
payload allows a singl
onfig options so that the receiver will wake on all tran
sensor and
includes these conversions as part of the packet payload.
Burst Interval Resolution: Used to define the clock frequency for the burst interval timer .
Table 60: Burst Config - 0X16 [22]
Bit Name State Comment
1
7 Reserved 0
1
6 Reserved 0
5:4 R_BURST[1:0]
00
01
10
11 Packet is repeated two times
Packet is repeated three times
Packet is sent one time
Packet is repeated once Repeat interval*
1 Chip ID is included as part of the packet
3 Send dhip ID 0
1 Data for temperature and battery is sent
2 Send Internal
ADC Data 0
1 Data for EXT1, EXT2 is sent
1 Send external
ADC data 0
1 Burst interval timer resolution is 15s
0 Bs
urst interval
resolution 0 Burst interval timer resolution is 50m
Note: When the burst transmission is repeated, the interval between transmissions is a random time period produced in a random number generator with the chip ID value
.7.3.1. B
urst interval defines the period for the normal burst trans mission to occur. This is a cyclic mode and the AMIS-53050 will transmit th e
end of each interval. This interval is fixed by the register value unlike the random time interval when the
d.
used to seed the random number generator.
6 urst Interval
B
contents of a register at the
transmission is repeate
Table 61: Burst Interval - 0X17 [23]
Bit Name Comment
7:0 BURST_INT [7:0] Burst interval= (BURST_INT+1)*Burst interval resolution
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.7.3.2. User Defined Data A
Table 62: User Defined Data A - 0X2D [45]
Bit Name Comment
7:0 USE_DATAA [7:0] Optional data to be sent in normal burst mode if non-zero
6. 3. User Defined Data B
Table 63: User Defined Data B = 0X2E
7.3.
[46]
Bit Name Comment
7:0 USE_DATAB [7:0] onal on-zero Opti data to be sent in interrupt triggered burst if n
6 H ng
able 64: Housekeeping Enable
.7.4. ousekeepi
TRegister
Number (HEX) Name Bits Function
0X10 Idle config 0 Enable housekeeping timed functions
Housekeeping is anoth er periodic oper ation mode, which can be used to periodic ally perform operati ons such as oscillator calibr ations,
re compens ation. It can also be us ed to periodical ly wake an ext ernal host cont roller to allo w it
to perform whatever tasks it may need to. The housekeeping configuration register contains the options to specify what is to occur
Housekeeping Co n fig- Sets the tasks for the housekeeping function
ets the time interval between times the AMIS-53050 wakes to perform the housekee ping function
during a Housekeepin g cycle.
HK Interval Resolution: Used to specify the clock frequency for the housekeeping interval timer
Wake: enabled, the AMIS-53050 will enable the syst em clock output, and issue an interrupt to an external controller.
Read INT ADC Channels: The AMIS-53050 will do conversions on the battery voltage and temperatu re sensor. This can be
used as a method to periodically update the temperature compensation loop.
C Channels: When enabled, the t wo extern al ADC inputs will be converted during a housekeeping cycle.
PLL calibration, EE refresh or temperatu
during a housekeeping cycle, and the housekeeping interval timer is used to control how frequently the wake-up occurs.
Register descriptions:
Housekeeping In terval- S
6.7.4.1. Housekeeping Config
The Housekeeping configuration register is used to specify which tasks the AMIS-53050 should perform
When
Write EE: This option is used to store the values of any calibrations that may have been performed during housekeeping.
The entire working register bank will be written to EE.
Read EXT AD
Cal PLL, RC, Kicker: Allows periodic calibration of the oscillators of the AMIS-53050.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 65: Housekeeping Config - 0X1B [27]
Bit Name State Comment
1 Five minute resolution setting
7 resolution 0 One second resolution setting
HK interval
1 Issue interrupt and enable clock to external host controller
6 Wake 0
1 Current register data written to EE (performed after all cal’s complete)*
5 Write EE 0
1 Temp sensor and battery inputs converted
4 Read INT
ADC channels 0
1 EXT1 and EXT2 ADC inputs converted
3 Re
ADad EXT
C channels 0
1 PLL calibration performed during housekeeping
2 Cal PLL 0
1 RC oscillator calibration performed during housekeeping
1 Cal RC 0
1 Kicker calibration performed during housekeeping
0 Cal kicker 0
Note: * Bit 5 is set high to allow the EE to be automati cally written after a calibration is complete.
terval (time that the AMIS-53050 is ode) for the h ousekeeping routine.
66: Housekeeping Interval - 0X1C [2
6.7.4.2. Housekeeping Interval
This sets the in
in sleep m
Table 8]
Bit Name Comment
7:0 HK_INT [ sekeepin terval = (H
7:0] Hou g in K_INT+1)* (HK interval resolution)
6.8 Idle Return
Table 67: Idle Return
Register
Number (HEX) Name Code Function
0X00 Command 0X04
In most conditions, the AMIS-53050 must be returned to idle mode at
the end of a task by this command
his command is used to put the p art back into idle mode. It should b e used by the host to place th e AMIS-53050 back into idle mode
after the ing cycle.
T AMIS-53050 has interrupted the host for reception of a packet in s niff, or to end a housekeep
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.9 EE
EE memory to store register settings (either default factory settings or user defined settings).
T 68 ation Results
The AMIS-53050 uses internal
able : Calibr
Register
Number (HEX) Name Bits Function
0X05 Write the register contents to EE
0X00 Command
0X06 Read the contents of the EE
0X01 Status/Flag1 2 EE checksum status
0X1B Housekeep a to EE (automatic after calibration complete)
ing
Config 5 Write register dat
6.9.1. Write EE
The serial interface provides a means to read and write the working registers of the AMIS-53050. To retain the information held by
t re , on-board E store all of the register contents needed for operation. The write EE command copies the
current c worki g with a CheckSum. The CheckSum is used to ve rify that the content of the EE is
wh pe
ontents of the working regi sters with the values st ored i n EE, if the EE Ch eckS um is valid. If the
EE CheckSum fails an error et in the Status2 register.
.10 Calibrate
hese gisters E is provided to
ontents of the
en the EE is dum ng registers i nto EE, alon
d back into the registers. v
alid
6.9.2. Load EE
The load EE command will refresh the c
bit will be s
6
Table 69: Calibration Results
Register
Number (HEX) Name Bits Function
0X07 Perform a Quick Start oscillator calibration
0X08 Perform a 10kHz RC oscillator calibration
0X09 Perform a PLL calibration
0X00 Command
0X0A Perform a Quick Start oscillator calibration
6 TX PLL calibration status
5 RX PLL calibration status
4 10kHz RC oscillator calibration status
0X01 Status/Flag1
3 Quick Start oscillator calibration status
2 Perform the PLL calibration
1 Perform the 10kHz RC oscillator calibration
0X1B Housekeeping
config 0 Perform the kicker calibration
0X33 Kicker slope
0ptions 4 Kicker calibration status
Register descriptions:
Trim- Shows the trim value for the circuit
PLL Trim Target- Set a value that the PLL trim tries to achieve in calibration
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.10.1. Internal Trim
6.10.1.1. Crystal Trim
Table 70: Crystal Trim - 0X21 [33]
Bit Name Comment
7:0 XTAL 7:0] 2 inte m cap x capacitance, 00 is min
_TRIM [ 4MHz rnal tri s; FF is ma
6. LNA Trim
The LNA trim requires that own e a r. Once a known signal is applied, the LNA self-
calibration can be run to dete e the r t e higher than minimum sensitivity. The LNA calibration
ses this signal to trim the input and output as well as gain parameters to maximize the gain of the L NA.
10.1.2.
a kn signal b pplied to the AMIS-53050 receive
rmin value fo his register. The signal should b
u
Table 71: LNA Trim - 0X22 [34]
Bit Name Comment
7:4 LNA_OUT[3:0} LNA output tank cap trim F is max cap
3:0 LNA_IN [3:0] LNA input shunt capacitor trim, F is max, 0 is min
6. Quick Start Oscillator Tr
This register contains the val the th
T : Quic lator - 0X2
10.1.3. im
ue of trim from e self cali bration.
able 72 k Start Oscil Trim 3 [35]
Bit Name C ment om
7:0 QS_TRIM [7:0] Trim for the art on circuit Quick St (kicker), this register is written to by the calibrati
6.10.1.4. 10K Oscillator Trim
This register contains the value of the trim from the self calibration.
Table 73: 10kHz Oscillator Trim - 0X24 [36]
Bit Name Comment
7:0 RC_TRI Trim f Hz oscillator, this register y cior the 10k is written b the calibration rcuit
M [7:0]
6.10.1.5. Analog Trim1
his is an internal use r wi er m . Th te e fa ing the value will cause the
MIS-53050 to not operate.
.10.1.6. Analog Trim2
his is an internal use register with no user-defined me aning. This register valu e is set at the factory and changing th e value will cause
e AMIS-53050 to not operate.
T
Aegister th no us -defined eaning is regis r is set at th ctory and chang
6
T
th
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.10.1.7. RF PLL Trim
This register contains the val ue of the trim from the s elf cali br ation. The values written to this register by t he P LL c alibration can provide
some indication of the quality of the frequency selection. Values at the maximum or minimum allowed for the TX or RX trim function,
even when calibration p asses, ma y indicate (althoug h not necessar il y) that a different val ue for the VCO external LC c ompon ents coul d
provide better performance or that a slightly different frequency should be used.
Table 74: RF PLL Trim - 0X27 [39]
Bit Name State Comment
7
6:4 TX Mode PLL
trim value 111
--000
Max. VCO trim value from the self calibration
Min. VCO trim value from the self calibration
3
2:0 RX Mode PLL
trim value
111
--
000
Max. VCO trim value from the self calibration
Min. VCO trim value from the self calibration
6.10.1.8. PLL Target Value
This register is used by the AMIS-53050 during sel register with no user-defined fu nction.
.10.2. Calibrate Quick Start Oscillator
he Quick Start oscillator must be calibrated prior to operations such as sniff or burst transmit. This command will perform an internal
calibration of the oscillator, write the result to the Quick Start trim register, issue a calibration complete flag, as well as a calibration
good/bad indicator. This command can be issued from any valid state that accepts changes in the instructions.
6.10.3. Calibrate 10kHz Oscillator
and then perform the calibration and store the result. A cal done and status flag will be issued upon completion of the
alibratio ed from any valid state that accepts changes in the instructions.
10.4.
rms a calibration for the PLL in both trans mit and receive mode. T he PLL status register reports the calibration
alue for changes
the in (before a
ansmit
.10.5. Cali
This com oth the LNA outp ut tuning structure and the LNA input matching trim for
maximum on typically performed at board assembly in the presence of a known RF signal. The
AMIS-53 ize gain, compensating for the
tolerance of exter c
ote: O level should be h igh enough to be above the nois e)
put to
f calibration. This is an internal use
6
T
In any of the idle modes of operation, an internal 10kHz oscillator is used as the timekeeping reference for the interval timers. The
calibrate 10kHz oscillator command will enable the crystal oscillator to create an accurate time base to use for the calibration of this
scillator, o
c n. This command can be issu
6. Calibrate PLL
C
valibrate the PLL perfo
both modes, as well as the status for the calibration. T his command can be issued from any v alid state that accepts
structions. This calibration is required when the AMIS-53050 is first powered on or returned from a device reset in
tr or receive instruction is issued).
6 brate LNA
mand turns on the RF receiver chain and optimizes b
signal level on RS SI. This is a calibrati
050 will auto-tune both the input and output internal variable capacitances of the LNA to optim
nal omponents for the match.
Nnly perform this calibration with a known, non-modulated, signal input (the
the AMIS-53050 receiver. in
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.11 ROM 2 REGS
his command as:
a rate selected.
s: Calculates all the parameters for the selected d ata rate (selected from the defined data rates).
X/RX frequency
arameters for the filter defined by the data rate selection (defined data rates).
6
his resets the entire chip, similar to a POR. This operation will reset the unlock test MUX register.
T 75
T starts internal AMIS-53050 processes such
Multi-Channel: Calculates the frequency i nformation to form nine channels of 300kHz bandwidth. Four of these ch annels are
at higher frequencies than the programmed RF frequency and four channels are at lower frequenc ies.
Wave Shaping: Calculates the voltage steps to form the Gaussian wave shaping of the data for the dat
Defined Data Rate
RF Frequency: Calculates the parameters needed to set the T
AM Filters: Calculates p
.12 Chip Reset
T
6.13 ADC Conversi on
able : ADC Configuration
Register
Number (HEX) Name Bits Function
010xxxxx Perform a single ADC conversion (see Table 84)
0X00 Command 110xxxxx Perform continuous ADC conversions (see Table 85)
0X01 Status/Flag1 0 The ADC conversion has completed
4 Do an ADC conversion for the internal measurements
0X1B Housekeeping
Config 3 Do an ADC conversion for the external measurements
The AMIS-53050 contains an 8 bit analog to digital converter. This ADC can measure the voltage on a number of internal functions,
such as battery voltage, temperature, received signal strength indication voltage, and loop filter voltage. The results of these
from the last ADC of the internal battery voltage (divided b y 2).
ontains the value from the last ADC of the loop filter voltage.
conversions are available through reading the registers where that data is stored or by using the feature of the burst transmission to
send that information to another node. The AMIS-53050 also contains two ADC channels available on the device pins. The ADC can
convert signals at a conversion rate up to 128k samples/se cond.
Register descriptions:
Temp- Contains the value from the last ADC of the internal temperature sensor.
Battery- Contains the value
RSSI- Contains the value from the last ADC of the signal level sample in the receiver.
ADC1- Contains the value from the last ADC of the external analog input.
ADC2- Contains the value from the last ADC of the external analog input.
Loop Filter- C
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.13.1. ADC Co on Results
6.13.1.1. Temp ADC
Table 76: T X34 ]
nversi
emp ADC - 0 [52
Bit Name Comment
7:0 TEMP_ADC [7:0] mpe sor ADC reading Te rature sen
6.13.1.2. Battery ADC
Table 77: Battery ADC - 0X3 ] 5 [53
Bit Name Comment
7:0 BATT_ADC [7:0] Battery voltage ADC reading (Vbatt/2)
6.13.1.3. RSSI
Table 78: RSSI - 0X36 [54]
Bit Name Comment
7:0 RSSI_ADC [7:0] RSSI voltage ADC reading
6.13.1.4.
able 79:
External Input 1 ADC
T Extern al Input1 ADC - 0X37 [55]
Bit Name Comment
7:0 EXT1_ADC [7:0] External input 1 ADC reading
6.13.1.5.
Table 80:
External Input 2 ADC
External Input2 ADC - 0X38 [56]
Bit Name Comment
7:0 EXT2_ADC [7:0] External input 2 ADC reading
6 .6. L r
T e 81: L
.13.1 oop Filte
abl oop Filter - 0X39 [57]
Bit Name Com t men
7:0 LO Intern loop filal ter
OP_FILT [7:0]
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AMIS-53050 Frequency Agile Transceiver Data Sheet
6.13.2. Single ADC Conversion
he single conversion comm and performs an ADC c onversi on on th e cha nnel spec ified as part of the co mmand. Once complete, a flag
r the conversion is available in its associated register.
T
is set, and the 8 bit data fo
Table 82: Single ADC Conversions
Register
Number
(HEX) Name Bits
(7:6) Bits
(5:0) Function
01 000001 Perform an ADC on the external input 1
01 000010 Perform an ADC on the external input 2
01 000100 Perform an ADC on the internal temperature sensor
01 001000 Perform an ADC on the Internal battery voltage
01 010000 Perform an ADC on the receiver RSSI
0X00
r
Command
01 100000 Perform an ADC on the loop filte
6.13.3. C
his com d into from an
le state ver written.
Table 83:
ontinuous ADC Conversion
T mand can be given to the radio and operate in parallel with transmit or receive. This mode can also be entere
. In this mode the specified ADC channel is continuous ly converted, and its associated register is continuously oid
Single ADC Conversions
Register
Number
(HEX) Name Bits
(7:6) Bits
(5:0) Function
11 000001 Perform continuous ADC on the external input 1
11 000010 Perform continuous ADC on the external input 2
11 000100 Perform continuous ADC on the internal temperature sensor
11 001000 Perform continuous ADC on the internal battery voltage
11 010000 Perform continuous ADC on the receiver RSSI
0X00 Command
11 100000 Perform continuous ADC on the loop filter
7.0 Data Interface
Table 84: Control/Data Interface Physical Configuration
Clock Data
Interface Function Pin Source Output Input Select AMIS-53050 Data Buffering
DCLK Master DRXTX DRXTX DSSN Master Optional
3-wire Data DCLK Master DRXTX DRXTX DSSN Slave Buffered only
DCLK Master DRXTX DOPT DSSN Master Optional
4-Wire Data DCLK Master DRXTX DOPT DSSN Slave Buffered only
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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Figure 42: 3-Wire Serial Data Interface
Figure 43: 4-Wire SPI Compatible Serial Data Interface
AMIS-53050
AMIS-53050
AMIS-53050 Frequency Agile Transceiver Data Sheet
The AMIS-53050 employs two different data interfaces. Transmit and receive data is exchanged with an external controller through
re SPI like interface. Selecting th e interface, 3-wire or 4- wire is done b y writing to Bit 7 of the gener al options B either a 3-wire or a 4- wi
register.
SPI serial data interface
3-wire serial data interface
AMIS-53050 can be the sla
ve or master
Register
tted and received with the data packet to identify a unique ra dio.
Configure the interface options.
ral Options B e the interface options.
Idle Config- Sets a wait time between:
1. The INT signals a data transfer is ready a nd the DSSN line starts that transfer.
2. The Idle command and the S YSclk clock stops (allows for the external HOST controller to finish tasks).
Start of Frame- Set a code value that indicates the start of a data packet.
gth- Select a type of preamble and set the length in bits. (see Section 6.6.3)
onfigures parameters for data rates that are not one of the fixed data rates.
Va
Default Length o f Packet- Set a default length for packets. Note: when the LOP or the default LOP (and the defa ult LOP is
enabled, bit 3 of the general optionsB reg ister) is anything other than zero, the AMIS-53050 is in packet mode.
- A general chip ID allowing for transmissions to be received b y all radios.
several purposes in the AMIS-53050 .
Table 85: Chip Address1 - 0X03 [3]
descriptions:
Chip Address- Allows a unique value to be transmi
Fixed Data Rates- Select the options for one of several fixed data rates.
General Options A-
Gene - Configur
Preamble Len
Custom Data Rates- C
CRC Polynomial- lue of the CRC polynomial.
Broad Cast ID
7.1.1. Chip Address MSB1
The 16 bit ID that can be used for
Bit Name Comment
7:0 Chip_Add [15:8] Upper byte of chip address
Table 86: Chip Address0 - 0X04 [4]
7.1.2. Chip Address LSB
Bit Name Comment
7:0 Chip_Add [7:0] Lower byte of chip address
7.1.3. Data Rate/Format
The data rate/format register is used to select the data rate and format for both receive and transmit. The DDRATE[2:0} option bits
allow selection of one of eight pre-pr ogramm ed data rat es. When one of the discrete d ata rates is select ed, the ROM2 REGS command
is used to load clock and data recovery settings for the desired data rate into their associated registers.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
The Manchester option bit configures the AMIS-53050 to transmit and receive in the Manchester encoded format, while the data
, set clock recovery loop filter settings, and if using the PLL based FSK
detector,
Note: For data ar one of the pre-defined data rates, a discrete data rate could first be chosen, the ROM2REGS
command given to data rate and then the custom data rate option enabled and the
new data rate info
For example, if the desire bps, set DDRATE to 110 for 96kbps operation. Next, issue the ROM2REGS command in
e command register. All of the proper settings for the cloc k and data recovery circuit for a 96k d ata rate will be loaded into the working
gisters from ROM (sample clock frequency, clock recovery loop filter settings). Finally, enable the use custom option, and program
d 0 with the value for a 100k data rate.
Custom frequency is set in data rate 1 and d ata rate 0. If custom is 0, ROM contents for selected discr e te data rate ar e loaded into data
rate 1 and data rate 0.
Table 87: Data Rate/Format - 0X0B [11]
interface remains NRZ.
If a data rate other than one of the available discrete rates is desired, the user should set the use custom bit, and then program the
custom data rate register for the desired data rate. When the use custom data rate option is enabled, it is up to the user to set the
correct sample clock frequency in the CDR options B register
ilter. set the PLL detector loop f
rates that are ne
load all of the settings for the various blocks for that
rmation entered.
d data rate is 100k
th
re
data rate 1, an
Bit Name State Comment
7 NU
6 NU
5 NU
1 Enables user programmable data rate
4 Use custom 0
1 Manchester encoding selected
3 Manchester
0 NRZ encoding selected
2:0 DDRATE [2:0]
000
001
010
011
100
101
110
111
1.2kbps
2.4kbps
4.8kbps
9.6kbps
19.2kbps
57.6kbps
96kbps
128kbps
7.1.4. General Options A
The general options A register contains a number of options that specify the operation of the part in its various modes.
Standby Mode: Determines whether the crystal oscillator is enabled during standby. For applications relying on the
AMIS-53050 to provide and external h ost controll er with a system clock, this bit should be enabled, and is the default state.
POR State: Specifies the power on state of the device. Once this has been stored into EE, the device will power up in the
chosen state after the EE has been shadowed into the working registers.
Pull up Disable: For applications not using an open drain type driver to drive the r egister interface pins (SDATA, SCLK and
SSN) the pull-ups on these pins can be disabled via this option bit to save power.
Temperature Compensation: When enabled, the ADC output for the temperature sensor is used to compensate the RF
center frequency for crystal frequency error. A new correction factor is calculated each time the ADC performs a new
conversion on the temperature sensor.
CRC Enable: Enables internal CRC checking in RX, and appends a CRC in TX.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Length of Packet Enable: Allows buffering of packets, also allows CRC when enabled. The number of bytes to be sent is
(N-1), where (N) corresponds to the value i n the Default L ength of P acket register. Not e: When the default LOP or L OP valu e
is anything other than zero (along with the Default LOP option bit enabled), the AMIS-53050 is in Packet mode.
Use ID in RX and TX: When enabled, in receive mode the part will not output data until a valid ID is fou nd, and in TX, the part
will automatically send preamble and chip ID before enabling the data interf ace.
Table 88: General OptionsA - 0X0C [12]
Bit Name State Comment
1 Wake on ID in RX, send ID in TX
7 Use ID in RX and TX 0
1 Enables the part to frame packets
6 Length of packet
enable 0
1 Enables CRC (packet length must be enabled)
5 CRC enable 0
1 R F center frequency temperature compensation enabled
4 Temperature
compensation 0 Temperature compensation is disabled
1 Pull ups on IIC clock and data and SSN pins disabled
3 Pull-up disable 0
[2:1] POR state
00
01
10
11
Standby
Idle
RX
TX
1 Crystal only mode, system clock output active
0 Standby mode 0 Low-power standby mode
7.1.5. General
option ore option bits for the general set-up and operation of the AMIS
Specifies which edge of DCLK should be used to sample the RXTX pin.
Length of Packet Enable: This register d efines the default LOP (register 0X31) so that the LOP does not have to be part of
the data packet. This needs to be set to the same valu in both the transmitting AMIS-53050 device and the receiving
AMIS-53050 device, respectively. Note: When the defa LOP value is anything other than zero (along with the
Default LOP option bit enabled), the AMIS-53050 is in Packet mode.
Data Interface Clock Frequency: Sets the clock freque y for the data interface when the AMIS-53050 is configured to be
the master of the data interface. For modes in which the AMIS-53050 does not buffer the packet, the interface speed will
always be the data rate, regardless of this setting.
Data Interface Slave/Master: Specifies whether the AMIS-53050 is the master or slave for the data interface.
4-Wire Data Interface: Enables the 4-wire SPI data interface. When low, RXTX is bi-dir ectional.
Options B
General s B contains m -53050.
System Clock Output Frequency: Sets the frequency of the output clock on the SYSclk pin when enabled.
RXTX Sampling Edge:
e
t LOP orul
nc
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 89: General OptionsB - 0X0D [13]
Bit Name State Comment
1 Enabled
7 4-Wire data interface 0
1 AMIS-53050 is slave
6 Data interface slave master 0 AMIS-53050 is Master, clock speed determined by bits 5, 4
5,4
Data interface clock frequency
11
10
01
00
1MHz
500kHz
100kHz
Baud clock
1 Data packet length is defined by the value of the default LOP
register
3 Default LOP 0 LOP must be sent with the data packet
1 Data bits are sampled on the rising edge of DCLK on the interface
2 RXTX sampling edge 0 Data bits are sampled on the falling edge of DCLK on the interface
11 12MHz (24MHz external crystal)
10 6MHz (24MHz external crystal)
01 3MHz (24MHz external crystal)
1,0
System clock output frequency
00 Off
7.1.6. Start of Frame
The start of frame byte is transmitted when this register is non-zero. It’s used as an aid for the receiver clock and data recovery circuit in
modes where the fast phase alignment feature is enabled. The data pattern required is different for different data modulations as
discussed in Table 35.
Table 90: Start of Frame - 0X19 [25]
Bit Name Comment
7:0 SOF [7:0] 8-bit code sent prior to chip ID in TX and burst
7.1.7. Data Rate 1
The data rate 1 and data rate 0 registers are used to set user defined data rates. These registers are loaded from ROM when a
discrete data rate is selected. The following equatio n is used to calculate the value for CUST_DR:
where DataRate is the desired data rate, and Fsample_clock is the frequency selected for the sample clock. This register is
loaded with the discrete rate if selected.
Table 91: Data Rate1 - 0X29 [41]
Bit Name Comment
7:0 CUST_DR [15:8] Upper byte of user defined data rate/discrete data rate
7.1.8. Data Rate 0
Table 92: Data Rate0 - 0X2A [42]
Bit Name Comment
7:0 CUST_DR [7:0] Lower byte of user defined data rate/discrete data rate
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AMIS-53050 Frequency Agile Transceiver Data Sheet
7.1.9. CRC Polyn
T egister allo desig to change the CR olyn used the . The register represents the presence of the
p uation ex
ynomial x8+ x2+x+1 is encoded by assuming the polynomial will always have a high order bit.
This is set as the value 0X27 (HEX) in the register
ty, T., “ Ccylic Redundanc y Code (CRC) Polynomial Sel ection For Embedded Net works” DSN04, June
Table 93: C 8]
omial
his r ws a ner C p omial in AMIS-53050
owers in the CRC eq . For ample:
The pol x5+
So the binary representation is: 1 0010 0111
(See “Koopman, P. & Chakravar
2004.” for more information.)
RC Poly - 0X30 [4
Bit Name Comment
7:0 C_POLY CRC p value
CR [7:0] olynomial
7.1.10. ault Len cket
his register allows a default value for the L OP (register value plus 1 byte) such that the AMIS-53050 does not hav e to send the LOP
ith a buffered packet.
able 94: Default LOP - 0X31 [49]
Def gth of Pa
T
w
TBit Name Comment
7:0 D of packet to be used in buffered TX/RX
EFAULT_LOP [7:0] Default value for the length
.1.11. Broadcast ID 1
Man e wireless market make use of a e Master note in a system can transmit to all
wireless nodes in the network ut addressing each n dually, but s odes in another network.
Table 95: Bro ast X3A
7
y applications in th broadcast function where th
witho
[58]
ode indivi till not broadcasting to n
adc ID1 - 0
Bit Name Comment
7:0 Global_ID1 [7:0] Lower byt global address e of the
7.1.12. Broadcast ID 0
e 96: B adcast - 0X3BTabl ro ID0 [59]
Bit Name Comment
7:0 Global_ID0 [7:0] Upper byte of the global address
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AMIS-53050 Frequency Agile Transceiver Data Sheet
7.2 TX/RX Data Interface Protocol
The AMIS-53050 TX/RX data format can be streaming data where the transmitter transmits each bit of data as it is received or it can be
acketized. p Packetize d data can be in packets up to 256 bytes.
Packetized data can add:
a preamble,
start of frame,
identification code (Chip ID or Broadcast Global ID)
length of packet,
CRC error CheckSum.
Figure 44: Data Protocol Format
• Streaming or packetized data
• Buffer size is 256 byte maximum
• Packet overhead
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AMIS-53050 Frequency Agile Transceiver Data Sheet
Figure 45: Data Protocol Timing ( 50 as
Table 97: Serial Data Timing
AMIS-530 Master)
Symbols Description Typical Units
TIN Interrupt to the exte hos ller to in ate data pa uS T rnal t contro dic cket received 5
Td ssn Dela me fr the interrupt N is actiy ti om to the time that DSS ve low Register (Idle Config) Bit times
TCLK Time from DSSN going active and the start of the data clock Immediate
TData Time from DSSN going active and the first bit of the data appears Immediate
TCend Time from the last clock pulse and DSSN goes inactive Immediate
TDend Time from the last data bit e the DSSN signal goends and s inactive Immediate
Data Bit Data bit period k period Register (gen opts B) Cloc
Note: These times are when the AMIS-530 50 contro ls the timing as the master. When the externa troller is configur ed as th e
master, these times will change.
l Host con
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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Figure 46: 3-Wire Data Transfer Protocol
Figure 47: 4-Wire Data Transfer Protocol
AMIS-53050 Frequency Agile Transceiver Data Sheet
Table 98: TX/RX Data Protocols
Modulation Detector CDR Preamble SOF ID/LOP/CRC Slice
AM RSSI Opt1CW Yes2See Table 99 Fixed/Auto
FM (<20kbps) PLL Yes 1 0 pattern ------- See Table 99 -------------
FM (>20kbps 3 4 e 99 ------------- ) FFT Yes See Tabl
Notes:
1. The u ended for AM/OOK modulation.
he S for NRZ and 0A (HEX) for Manchester encoded data.
3. The preamble for FM (FFT) with NRZ data is a 1 0 repeating pattern. The preamble for FM (FFT) with Manchester encoded data is all 1s or all 0s.
SO gested SOF is a pattern of 55 (HEX) or AA (HEX).
ta Protocols
se of the CDR function to recover the data is recomm
OF for AM modulation is suggested to be 55 (HEX) 2. T
4. A F is only required for FM (FFT) when the data is Manchester encoded. The sug
Table 99: Interface Da
TX/RX Data Protocol Interface Data
Protocol Comments
LOP CRC Interface Data
N N e interface as it is received Active Stream1Data is streamed out th
N N Active* Stream * Data is streamed out the interface starting with the wake-up on ID
Y N lete Interrupt Buffered An interrupt is issued when data reception is comp
Y Y Interrupt Buffered An interrupt is issued when data reception is complete
Note:
1. When the interface uses streaming data, the AMIS-53050 must be the master.
The serial data interface for the AMIS-53050 can be configured to be:
• A 3-wire interface or a 4-wire SPI interface
• A master or a slave for both receive and transmit operation.
• Data can be sampled on the rising, or falling edge of DCLK. The setting for the sampling polarity applies to all modes.
Table 100: Serial Data Interface Configuration
General Options B Data Port Configuration
Pin Function Definition
Bit 7 Bit 6 Bit 2 # Port
Pins AMIS-53050 Edge
Sample DCLK DSSN DRXTX DOPT
0 0 X 3 Master X Output Output I/O X
0 1 X 3 Slave X Input Input I/O X
1 0 X 4 Master X Output Output Output Input
1 1 X 4 Slave X Input Input Output Input
X X 0 X X Falling
X X 1 X X Rising
7.2.1. AMIS-53050 in Master Mode
receive mode, the DSSN pin will transition low when the AMIS-53050 has received data. Immediately following the transition of
SSN, the AMIS-53050 will provide a synchronized bit clock on DCLK, and the received data will appear on DRXTX.
transmit mode, the transition of DSSN is used to s ign al an exter nal ho st controll er th at the AMIS-53050 is rea dy for transmit data and
ready to receive that data on the DRXTX pin. Immediately following the transition of DSSN, the AMIS-53050 will provide a
ynchronous clock on DCLK for the host controller to use for loading tra nsmit data into th e AMIS-53050.
In
D
In
is
s
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AMIS-53050 Frequency Agile Transceiver Data Sheet
7.2.2. AMIS-53050 in Slave Mode
The A S-53050 cMI annot be the slave for streaming data. The requirements of adding header information such as preamble or SOF
r t the 3050 be in control of the data interface transfer. The receiver has similar requirements with removing the
h ormatio
As the slave for t rrupt to the external host indicating that data is available
after a data packe
F r buffered transmit operation, the AMIS-53050 will issue an interrupt indicating it is ready to load the packet. After the packet is
r y the A ing is done and the packet is sent.
tion
equires tha AMIS-5
eader inf n.
he data interface, the AMIS-53050 will simply issue an inte
t has been received.
o
eceived b MIS-53050 and the transmitter is enabled, any packet formatt
7.2.3. Manchester Opera
Figure 48: Manchester Coded Data
If the Manche ted in the data rate and format register, the AMIS-53050 will internally encode and decode both
t nsmit and r ace remains NRZ in this mode.
ster option is selec
ra eceive data respectively. The format for the signal interf
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AMIS-53050 Frequency Agile Transceiver Data Sheet
7.2.4. Packet Framin
T ree options bits lo ill process packets: use
ID, length of packet (LOP) enable and cyclic redundancy check (CRC) enable. An additional bit in the TX config register enables the
buffered TX mode of operation.
Table 101: Register Configuration Bits
g
h cated in the general options A re gister determi e the method with which the transceiver wn
General Options A TX Config SOF Default
LOP
Bit
7 Bit 6 Bit 5 Bit 3 Bit 2 All All Protocol Comments
0 0 0 0 X 0X00 X Streaming data
The preamble is transmitted and then data
is transmitted as it is received
0 0 0 0 X non
0X00 X Streaming data The preamble and SOF are transmitted
and then data is transmitted as it is
received
1 0 0 0 opt10X00 X Streaming data
Preamble, ID is transmitted and then data
is transmitted as received
1 0 0 0 opt1non
0X00 X Streaming data Preamble, ID, SOF is transmitted and then
data is transmitted as received
1 1 0 0 opt10X00 X Data packet
Packet is formed with Preamble, ID, LOP
and data, then it is transmitted
1 1 0 0 opt1non
0X00 X Data packet Packet is formed with Preamble, ID, SOF,
LOP and data, then it is transmitted
1 1 0 1 opt10X00 Value Data packet Packet is formed with Preamble, ID and
data, then it is transmitted
1 1 0 1 opt1non
0X00 Value Data packet Packet is formed with Preamble, ID, SOF
and data, then it is transmitted
1 1 1 opt1opt10X00 X Data packet Packet is formed with preamble, I
and data, then it is transmitted wi CRC
at the end
D, LOP
th
1 1 1 opt1opt1non
0X00 X Data packet Packet is formed with preamble, ID, SOF,
LOP and data, then it is transmitted with
CRC at the end
1 1 1 opt1opt10x00 Value Data packet Packet is formed with preamble, ID and
data, then it is transmitted with CRC at the
end
1 1 1 opt1opt1non
0X00 Value Data packet Packet is formed with preamble, ID, SOF
and data, then it is transmitted with CRC
at the end
Notes:
X means that the register value is ignored (suggest setting the register to 0X00).
Value means that the TX and the RX device will use default packets of length of this register plus 1 Byte.
Optional means:
ions B; 1 means that LOP will not be transmitted but the Default LOP will be used
0 means that the LOP will be transmitted
; 1 means that the ID
0 means that t al ill be transmitted
7.2.5. Use ID
General Opt
TX Config Chip
he Glob is transmitted
Broadcast ID w
Table 102: ID
Register
Number (HEX) Name Bits Function
0X0C General options A 7 Wake on ID in RX/send ID with TX
0X0F TX config 2 Select either the chip ID or global ID to be used in transmissions
0X16 Burst config 3 Send ID with burst packet
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AMIS-53050 Frequency Agile Transceiver Data Sheet
T ord which can ro in registers three and four. In receive mode, when the use ID bit in general
o t -53050 will no r buffering data until a valid ID matching the valu e stored in the chip ad dress
registers is received. The ID is used in more a des of operation for byte alignm ent. In addition to waking on its own unique
ID, the AMIS-530 n a -de al chip ID. T he default v alue f or the gl obal ID is in the register tabl e. This value
can be overwritten, but is not st care must be taken when overwriting the value.
ith the use ID bit enabled i n transmit mode, the AMIS-53 050 will transm it the chip ID pr ior to enab ling the data interface. An ad dition al
option bit in the TX config register allows selection of either the chip ID or global ID value for transmit.
e, when the use ID bit is enabled without LOP enabled, the AMIS-53050 will not buffer data. Hence when
ata interface must be configured with the AMIS-53050 as the master.
D bit must
53050 will interpre t the first b yte following either a val id chip ID, or global ID to be the
ngth of the incoming packet. This byte specifies the number of b es following the LOP to be received (non-inclusive of the CRC if
enabled). When ena bled, the AMIS-5305 0 will buffer the i ncoming cket into internal RA M. Follo wing reception of the last byte of the
packet, an interrupt is issued on the interrupt pin, and depe ndi ng on the c onfig uration of the data interfa ce, the packet will e ither be s ent
out of the data interface by the AMIS-53050 as master, or it will wait for the external host controller to stream the packet out as the
master.
, enables the buffering of the T X packet. Once the DSSN is pulled lo w by the AMIS-53050, the first byte received
to the that all bytes have been
received, at ding of the data packet
depends on the data interface setup as to whether the AMIS-53050 is master or slave.
7.2.7. CRC Enable
The CRC enable l ocated in general options A is the final tier of intelligenc e for the AMIS-53050 packet handling c apability. In order for
the AMIS-53050 to do CRC checking, this option must be used in conjunction with both use ID and LOP enable. Operation of the
interface for both receiv e and transmit with the CRC enabled is no different from that explained under the LOP enabled section. With
the CRC enabled, the AMIS-53050 will append the calculated CRC in transmit as the last byte. In receive mode, interrupts to the
external controller will only be issued for packets passing the CRC.
7.2.8. SOF Byte
Table 103: Suggested SOF
he chip ID is a
ptions A is set, 16-bit w
he AMIS be p
t begin e
grammed
xporting o
dvanced mo
50 will also wake o
ored in EE so
pre fin ed glob
W
In either transmit or receiv
enabled stand alone, the d
7.2.6. Length of Packet Enable
The length of the packet ena ble (LOP) bit located in gener al options A, enables the AMI S-53050 to buffer packets. The use I
e used in conjunction with LOP to allow the receiver to byte align on incoming data. b
n receive mode with the LOP enabled, the AMIS-I
le yt
a p
OP, in transmit modeL
in part is expected to be the LOP byte. Transmission continues until the AMIS-53050 has determined
which point the data interface is disabled and the AMIS-53050 will return to standby. T he actual loa
Modulation Detector Coding Preamble SOF
NRZ CW 55 (HEX)
AM RSSI
Manchester CW 0A (HEX)
FM (<20kbps) PLL 1 0 pattern 1 0 pattern Not required
NRZ Repeating 1/0 Not required
FM (>20kbps) FFT Manchester All 1’s or 0’s 55 (HEX) o r AA (HEX)
Depending on whether the mode of operation is AM or FM, NRZ or Manchester, it may be necessary for a SOF byte to precede the
chip ID. This byte is user programmable, a nd is used to ensure proper CDR operation and bit alignment prior to reception of the chip
ID. When the contents of the SOF byte register are loaded to any non-zero valu e, this byte will be transmitted prior to the chip ID. For
modes not requiring the SOF byte, setting this register to 00h will prohibit transmission of this byte. Mor e information on when the SOF
byte is required is in the clock and data recovery section.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
7.2.9. Timing Diagra ms for Various Packet Framing Modes
7.2.9.1. Use ID Enabled, No CRC, No Packet Length
Table 104: Receive
Parameter Action
ID Data interface immediately ready after ID detected
Radio stays in RX until instructed to change
No LOP Data is shifted out data port as received
No CRC Error checking is not performed and CRC is not attached to packet
T iable 105: Transm t
Parameter Action
Transmit command immediately powers the transmitter on
Transmits preamble
Transmit returns to standby after Transmission completes AMIS-53050
ID Transmits the ID
DSSN Starts data interface and uses a synchronous clock to clock in the TX data (Master only)
Figure 49: Data Interface Protocol (ID only)
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AMIS-53050 Frequency Agile Transceiver Data Sheet
7.2.9.2. Use ID Enabled, No CRC, LOP Enabled
Table 106: Receive
Parameter Action
ID Data interface immediately ready after ID detected
LOP Receiver loads rest of packet into buffer memory
After last data byte is received, radio returns to the previous state
An interrupt is issued to the external controller/microprocessor
ler as Master Data is transferred out the port with the AMIS-53050 as Master or the external control
No CRC Error checking is not performed and CRC is not attached to packet
Transmit
Table 107:
Parameter Action
Buffered If buffered t
Transmit into memory with AMIS-53050 as Master or external controller as master
ransmit is selected, the AMIS-53050 will open the data interface and transfer all TX data
Transmit Transmit command (or end of TX data transfer) immediately powers the transmitter on
Transmits preamble (length of preamble as specified)
ID Transmits the SOF and the ID
or clo
Starts data interface and uses a synchronous clock to clock in the TX data (master only)
cks data out of memory (buffered TX)
After the packet is transmitted, the transmitter returns to standby state
Figure 50: Data Interface Protocol (ID and LOP)
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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, LOP Enabled 7.2.9.3. Use ID Enabled, CRC Enabled
Table 108: Receive
Parameter Action
ID Data interface immediately ready after ID detected
CRC As soon as the ID is validated, the CRC starts processing the data
LOP The LOP is received
The rest of the received data packet is buffered into memory
CRC
invalid r waits for a command from the external host controller, or if the receiver
came from idle it will return to receive
The last byte is the CRC and if invalid, the receive
CRC valid Receiver returns to previous state and an interrupt is issued to the external controller
RC The data interface is started and the data is sent to the controller, except for the C
Table 109: Transmit
Parameter Action
Buffered transmit If buffered transmit is sele a into memory with
AMIS-53050 as m cted, the AMIS-53050 will open the data interface and transfer all TX dat
aster or external controller as master
Transmit Transmit command (or end of TX data transfer) immediately powers the transmitter on
Transm preamble (length of preamble as specified) its
ID Transmits the SOF and the ID
CRC The CR egins C b processing the data with the ID
Starts data interface and uses a synchronous clock to clock in the TX data (Master only)
or clock ata ous d t of memory (buffered TX)
LOP The firs te is defined to be the LOP of the packet t by
CRC byte At the end of the sent packet, the data stops and the CRC value is
th acket is rom the external host controller After e p transmitted, the transmitter waits for a command f
Figure 51: Data Interface Protocol (ID, LOP and CRC)
AMIS-53050 Frequency Agile Transceiver Data Sheet
8.0 General System Functions
8.1 Pull-up Disable
The AMIS-53050 includes built in pull-
pull-up are asserted at POR until m ode
up resistors for use with the I2C operation to reduce the overall system component count. The
s selection occurs. If the mo de is d et ermined to be 3- wire, the pul l-ups ar e r emov ed. If the m ode
is er 2C, this et mines whether the pull-ups are to be removed.
Table 110: I2C Pull Up Control
det mined to be I option bit d er
Register
Number (HEX) Name Bits Function
0X0C General O Disable internal pull up resistors on I2C busptions A 3
8.2 Brown-Out POR
The brown-out POR serv es two purposes firs R sig hen po wer is initially applie d to the
part. The second is to provid e a POR should the ly drift n range to prevent the AMIS-53050
from being placed in an unknown conditio
T 11 eset St
. The t is to provide a PO n al to reset the digital w
ormal operatingvoltage on the su pp below
n.
able 1: Power-on-R art Up State
Register
Number (HEX) Name Bits Function
00 Standby
01 Idle
10 RX
0X0C General options A 2,1
11 TX
8.3 Temperature Sensor
The temperature sensor is cr eated by usin
be se an analog t o g a Darlington p air of PNP transistors. T he two transistors cr eate a 5mV/oC slop e, which can
nsed with nvert r. Without amplification, an 8 bit ADC with a 2V reference voltage will have a resolution
better than two degrees.
The temperature sensor can be trimmed to an accuracy of 3°C. As the trim i t voltage also increa ses.
The temperature voltage relationship is given by:
o digital c e
s increased, the outpu
Where V is the output voltage and T is the te
Register descriptions:
ADC Temperature- Register show alu perature se D
mperature in celsius.
s the v e of the tem nsor A C (see Section 6.13.1.1)
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AMIS-53050 Frequency Agile Transceiver Data Sheet
8.3.1. Crystal Temperature Compensation
ature sensor storage regist er is updated with a new value. Therefore, it is possible to update the compens ation value either
eke cycle or as controlle d external ly by issuin g the instruction to perform an A DC measurement
Table 112: RF Frequency Temperature Comp n
An on-chip temperature sensor combined with an on-chip A/D and a look-up table enable the part to maintain RF frequency accurac y
within ± 2.5ppm over all operating voltages and temperatures (-45°C to 85°C). This function can be enabled via configuration Bit 4
located in general options A. When this function is enabled, a new calculation for the center frequency word will be performed w henever
the temper
in hous epi ng, as part of a burst transmit
of the temp sensor.
ensatio
Register
Number (HEX) Name Bits Function
0X0C General options A 4 En y temperatur penable RF frequenc e com sation
8.4 Software
The version of the AMIS-53050 is writte re e end of the m ctu ss. This code can help AMIS wireless
product support when there is an issue wi AM
Register descriptions:
- Register contains a co wi ion of the AMIS-53050.
8.4.1. AMIS Part Revision Code
Table 113: AMIS Part Revision Code - 0X41 [65]
n to a gister at th anufa ring proce
th the IS-53050.
AMIS ID de sho ng the vers
Bit Name Comment
7:0 AMIS_ID [7:0] Revision status of the AMIS-53050
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AMIS-53050 Frequency Agile Transceiver Data Sheet
9.0 Built-in Test Functions
The AMIS-53050 has a number of test registers. These registers are not available to the general user of the AMIS-53050. However,
:
Test Unlock- A special code is required to unlock the functions of the test registers.
Test- Registers that route signals to pi ns for monitori ng or turn internal circuits
9.1 Un Re ter
T velop er desi ing t 0 m a est modes to monitor the rati he AMIS-5305 0 or to
determine ctiv of r. These registers are locked from use by a o nlock the test registers contact
A wire t su tain th e c ock register to access t test registers. This register will
be reset with a rese f th will lo t registers.
R er d tions:
T nlo - Re cod -53050 is ope
** Registe ith be d
Table 114: nlo od
many of these registers control test features are useful in the development of applications using the AMIS-53050.
Register descriptions
off for test.
TM lock gis
he de gn he AMIS-5305 y desire t o use some of the t ope on of t
the a ity some paramete code word. T u
MIS less produc ppor t to ob ode. Enter this code in the unl he
t o e part and thus ck the user out of the tes
egist escrip
est U ck gister contai ns a e about the state the AMIS rating in.
rs w the ** mark can trimmed if the test registers are unlocke .
Test U ck C e - 0X40 [64]
Bit Name Comment
7:0 U [7 Code to unlock operation of the test registers (contact AMIS for the code to unlock th st re
NLOCK :0] e te gister
functions)
9.2 Test R ers
T llow all be monitoring. They also the AMIS-53050 on and off for
measuring nal e A
9.2.1. IF A an rim
T gis se r fa f the A
9.2.2. IF A an rim
T gis se r fa g of the A ions.
9 LL al
T gis se r fa the A ctions.
9.2.4. PLL Test Mo
his register is used for factory testing of the AMIS-53050 and has n o user functions.
egist
he fo ing registers ow for signals to routed to pins for turn functions in
the operatio parameters of th MIS-53050.
mp M ual T A
his re ter is u d fo ctory testing o MIS-53050 and has no user functions.
mp M ual T B
his re ter is u d fo ctory testin MIS-53050 and has no user funct
.2.3. P Manu Trim
his re ter is u d fo ctory testing of MIS-53050 and has n o user fun
des
T
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AMIS-53050 Frequency Agile Transceiver Data Sheet
9.2.5. Power Down RF Sections
This regis used for fa the A nd has no user functions.
9.2.6. Anal st Mode
Dig ad t: exc errupt are 1mA I/O with pull up chmitt triggers. The
SYSclock and xInt 2mA
Au rem t D abl e I2C dre s. I low repeated writes
to e ste djustin
Table 115: Anal
ter is ctory testing of MIS-53050 a
og Te
ital P Tes All digital pads
are ept system clock out, and xInt s and S
errupt pads outputs.
to Inc en isable: This dis es the automatic incrementing of th
lue. register ad sse t can al
the sam regi r, useful for a g a parameter to optimize its va
og Test Mode - 0X47 [71]
Bit Name State Comment
1 Enable th apacitance t value e test mode for determination of c rim
7 CA P_TRIM 0
1 Enable the ADC1 input channel as a direct input to the data filter
6 Pip 1 to e ADC data
filter 0 Normal op ration e
1 Override t voltage he brown-out POR to allow test at any
5 Bro po
dowwn-out
n wer 0
1 Address increment disabled (IIC only)
4 Aut meo incre nt
Disable 0
1 Dither is a e PLL pplied to the sigma-delta circuits in th
3 Dith e
er mod 0
1 Ignore crystal control (digital clock gating)
2 Ignore XTAL control 0
1
bled:
Ena
1 Dig st A
abled
pad te
0 Dis
1
Enabled:
0 Dig st B pad te
0 Disabled
9.2.7. RF od
T is regis se r fa e A ns.
9.2.8. Anal st MUX
T is regis se r fa f the AMIS-53050 and has no user functions.
.9. RF UX
This register is used for factory testing of the AMIS-5305 0 and has no user functions.
Test M es
h ter is u d fo ctory testing of th MIS-53050 and has no user functio
og Te
h ter is u d fo ctory testing o
9.2 Test M
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AMIS-53050 Frequency Agile Transceiver Data Sheet
9.2.10. Digital Test MUX A
nals to be routed to the indicate d pins of the AMIS-53050. These signals can help in the d evelopment of an
application using the AMIS-53050. The test unlock register code must be written, then this test register is written and then the test
function will be enabled until either is changed or there is a reset of the AMIS-53050, even if the test unlock register code value is
al Test MUX A - 0X4B [75]
This register allows test sig
changed.
Table 116: Digit
Bit Test Pin Comment
1111 Space Q channel CLK 0111 Energy dwell enable
1110 Mark Q channel CLK 0110 PLL increment
1101 NC 0101 TX enable
1100 Data Q channel 0100 10kHz clock
1011 PN code from Σ∆ 0011 Software state [3]
1010 Start 0010 Bandgap ready
1001 Analog data out 0001 ADC CLK
7:4 MUX to SCLK 1111 - 0000
1000 PLL detect/data out 0000 Normal/system clock
1111 Space I channel CLK 0111 Code dwell enable
1110 Mark I channel CLK 0110 PLL decrement
1101 PLL detect/NCO out 0101 Kicker
1100 Energ y detected 0100 PLL Z
1011 Data I channel 0011 Software state [2]
1010 RF PLL CLK feedback 0010 PLL xReset
1001 Is locked (encoder) 0001 ADC power down
3:0 MUX to Dopt 1111 - 0000
1000 TX data 0000 D optional
9.2.11. Digital Test MUX B
This register allows test signals to be r outed to the indicated pins of the AMIS-53050. These sign als can help in the dev elopment of an
application using the AMIS-53050. The test unlock register code must be written, then this test register is written and then the test
function will be enabled until either is changed or there is a reset of the AMIS-53050, even if the test unlock register code value is
changed.
Table 117: Digital Test MUX B - 0X4C [76]
Bit Test Pin Comment
1111 Encoder in 0111 Cal done kicker
1110 Decoder in 0110 PLL in range
1101 Sniff 0101 INT0
1100 Σ∆ output 0100 Transmit done
1011 RF PLL (reference
CLK) 0011 Software state [1]
1010 Brown-out output 0010 Xtal on
1001 Receive done 0001 ADC done
7:4 MUX to xINT 1111 - 0000
1000 TS CLK 0000 xInterrupt
1111 Recovered clock 0111 PA enable
1110 Decoder out 0110 PLL cal timer
overflow
1101 Encoder out 0101 PLL cal enable
1100 CDR enable 0100 xtal PD
1011 Baud clock (CDR out) 0011 Software state [0]
1010 CRC failed 0010 isStopMode
1001 RX enable 0001 Watch dog reset
3:0 MUX to xBurst 1111- 0000
1000 NC 0000 xBurst
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AMIS-53050 Frequency Agile Transceiver Data Sheet
9.2.12. Digital Test MUX C
This register allows test signals to be routed to the indic ated pins of the AMIS-53050. These signals ca n help in the development of an
application using the AMIS-53050. The test unlock register code must be written, then this test register is written and then the test
n changed or there is a reset of the AMIS-53050, even if the test unlock register code value is
d.
Table 118: Digital Test MUX C - 0X4D [77]
functio will be enabled until either is
change
Bit Test Pin Comment
1111 ed 0 BIST d Undefin 111 RAM ba
1110 Undefined 0110 EE BIST done
1101 goo 0 ISTEE BIST d 101 EE B bad
1100 Clock 0100 Busy
AM Filter
1011 A 0uctio able CPEN 011 Instr n en
1010 ROM done 0010 Bandgap BIST power down
1001 T b 0 L ROM BIS ad 001 XTA
7:4 MUX to 1111 - 00
1000 BIST done 0 DSSN
Data SSN 00
RAM 000
1111 Undefined 0111 Undefined
1110 Undefined 0110 Undefined
1101 Undefined 0101 Undefined
1100 Undefined 0100 Undefined
1011 Undefined 0011 Undefined
1010 Undefined 0010 Undefined
1001 Undefined 0001 Undefined
3:0 Reserved 1111- 0000
1000 Undefined 0000 Undefined
9.2.13. Digital Test Mode A
ster is used for factory testing of the AMIS-53050 and has no user functions.
.2.14. Digital Test Mode B
his register is used for factory testing of the AMIS-53050 and has n o user functions.
.2.15. Digital Test Mode C
his register is used for factory testing of the AMIS-53050 and has n o user functions.
9.2.16. Digital Test Mode D
This register is used for factory testing of the AMIS-5305 0 and has no user functions.
9.2.17. Memory Test Mode Address
This register is used for factory testing of the AMIS-53050 and has no user functions.
9
T
This regi
9
T
9
T
.2.18. Memory Test Mode Data
his register is used for factory testing of the AMIS-53050 and has n o user functions.
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AMIS-53050 Frequency Agile Transceiver Data Sheet
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10.0 Register Definition
Table 118 contains the addresses for all of the internal registers. Once the EE has been written, the POR states for the registers
become the data last written. Should the C heckSum fail, all registers will return to the POR state shown and an error flag will be written
to a status register.
Table 119: Register List
Address
R/W Hex Dec Register Name Description POR State EE Section
R/W 0x00 0 Command Instruction register 0000_0000 6.2
R/W 0x01 1 Status/Flag1 Part status, flags 0000_0000 6.4.5.1
R/W 0x02 2 Status/Flag2 Part status, flags 0000_0000 6.4.5.2
R/W 0x03 3 Chip address 1 Upper 8 bits of chip address 0000_0000 X 7.1.1
R/W 0x04 4 Chip address 0 Lower 8 bits of chip address 0000_0000 X 7.1.2
R/W 0x05 5 RF divider Integer portion of RF frequency 0000_0000 X 6.4.1.1
R/W 0x06 6 RF frequency 2 Upper 8 bits of RF fraction 0000_0000 X 6.4.1.2
R/W 0x07 7 RF frequency 1 Center 8 bits of RF fraction 0000_0000 X 6.4.1.3
R/W 0x08 8 RF frequency 0 Lower 8 bits of RF fraction 0000_0000 X 6.4.1.4
R/W 0x09 9 Peak deviation 1 Upper 8 bits of FM deviation 0000_0000 X 6.4.1.5
R/W 0X0A 10 Peak deviation 0 Lower 8 bits of FM deviation 0000_0000 X 6.4.1.6
R/W 0x0B 11 Data rate / format Set discrete data rate and encoding option 0000_0000 X 7.1.3
R/W 0x0C 12 General options A General options for interface, POR state,
etc. 0000_0000 X 7.1.4
R/W 0x0D 13 General options B General options for interface, POR state,
etc. 0000_0000 X 7.1.5
R/W 0x0E 14 RX config Receiver options 0000_0000 X 6.5.1.1
R/W 0x0F 15 TX config Transmit options 0000_0000 X 6.6.1
R/W 0x10 16 Idle config Idle mode options X 6.7.1
R/W 0x11 17 Sniff config Sniff mode options 1011_0100 X 6.7.2.1
R/W 0x12 18 Sniff interval Interval between Sniff cycles 0000_1010 X 6.7.2.2
R/W 0x13 19 Energy dwell time Length of time to dwell in sniff mode 0000_0000 X 6.7.2.3
R/W 0x14 20 Code dwell timer Number of bit times to wait for code
after energy detect 0000_0000 X 6.5.1.5
R/W 0x15 21 Energ y threshold Threshold for wake on RSSI, sniff
and CCA 0000_0000 X 6.5.1.2
R/W 0x16 22 Burst config Burst transmit options 0000_0000 X 6.7.3
R/W 0x17 23 Burst interval Interval timer for burst transmit 0001_1000 X 6.7.3.1
R/W 0x18 24 Output power Output power 0001_0000 X 6.6.2
R/W 0x19 25 Start of frame Byte used for burst transmit/CDR wake up 0001_0000 X 7.1.6
R/W 0x1A 26 Preamble length Length of CW, or ‘10’
repeated in Burst/TX (BT’s) 0001_0000 X 6.6.3
R/W 0x1B 27 HK config Housekeeping options register X 6.7.4.1
R/W 0x1C 28 HK interval Interval timer for Housekeeping X 6.7.4.2
R/W 0x1D 29 Slice threshold Energy threshold for AM DAC mode
data slice X 6.5.1.4
R/W 0x1E 30 Filter/slice AM/RSSI filter setting and AM slice mode X 6.5.1.4
R/W 0x1F 31 CDR options A Clock and data recovery options A X 6.5.1.5
R/W 0x20 32 CDR options B Clock and data recovery options B 1000_0000 X 6.5.1.5
R/W 0x21 33 Crystal trim Crystal trim 0000_0000 X 6.10.1.1
R/W 0x22 34 LNA trim LNA input and output matching trim 0000_0000 X 6.10.1.2
R/W 0x23 35 Quick Start trim Quick Start oscillator trim 0000_0000 X 6.10.1.3
AMIS-53050 Frequency Agile Transceiver Data Sheet
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Table 118: Register List (Continued)
Address
R/W Hex Dec Register Name Description POR State EE Section
R/W 0x24 36 10k Osc trim 10kHz oscillator trim 0000_0000 X 6.10.1.4
0x25 37 Analog trim 1 Bandgap and temp sensor trim 0000_0000 X 6.10.1.5
0x26 38 Analog trim 2 Capacitance trim 0010_0100 X 6.10.1.6
0x27 39 RF PLL trim PLL calibration storage register 0100_0100 X 6.10.1.7
0x28 40 RF PLL options RF PLL options register 0000_0000 X 6.4.1.7
0x29 41 Data rate 1 User defined data rate upper bits 0000_0000 X 7.1.7
0x2A 42 Data rate 0 User defined data rate lower bits 0000_0000 X 7.1.8
0x2B 43 PLL loop co User defined PLL detector bandwidth 0000_0000 X 6.5.1.4
0x2C 44 CDR loop co User defined clock recovery loop 0000_0000 X 6.5.1.5
0x2D 45 User data Transmitted on normal interval burst 0000_0000 X 6.7.3.2
0x2E 46 User data Transmitted on interrupt triggered Burst X 6.7.3.3
0x2F 47 TargNumWakeUps Target number of wake ups for X 6.7.2.4
0x30 48 CRCPoly CRC polynomial register X 7.1.9
0x31 49 DefaultLOP Default LOP register X 7.1.10
0x32 50 Checksum EEPROM checksum X 6.9.1
0x33 51
0x34 52 Temp ADC Storage register for the temp sensor
reading 0000_0000 6.13.1.1
0x35 53 Battery ADC Storage register for the battery reading 0000_0000 6.13.1.2
0x36 54 RSSI ADC Storage register for the RSSI reading 0000_0000 6.13.1.3
0x37 55 EXT1 ADC Storage register for the EXT1 input 0000_0000 6.13.1.4
0x38 56 EXT2 ADC Storage register for the EXT2 input 0000_0000 6.13.1.5
0x39 57 Loop filter
Error!
0x3A 58 Broascast ID1 7.1.11
0x3B 59 Broadcast ID0 7.1.12
0x3C 60 Software state 6.4.5.3
0x3D 61
0x3E 62
0x3F 63
0x40 64 Unlock reg 1010_0101 9.1
0x41 65 AMIS ID code 0011_0001 8.4.1
0x42 66 IF Amp trim A 9.2.1
0x43 67 IF Amp trim B 9.2.2
0x44 68 Manual PLL trim 9.2.3
0x45 69 PLL Test Mode 9.2.4
0x46 70 PDtestRF 9.2.5
0x47 71 Analog test mode 9.2.6
0x48 72 RFTM 9.2.7
0x49 73 Analog test mux 9.2.8
0x4A 74 RF test mux 9.2.9
0x4B 75 Digital test mux A Configure external pins as test signal 0000_0000 9.2.10
0x4C 76 Digital test mux B Configure external pins as test signal 0000_0000 9.2.11
0x4D 77 Digital test mux C Configure external pins as test signal 0000_0000 9.2.12
0x4E 78 DTM A 0000_0000 9.2.13
0x4F 79 DTM B 0000_0000 9.2.14
0x50 80 DTM C 0000_0000 9.2.15
0x51 81 DTM D 9.2.16
0x52 82 MTM address 9.2.17
0x53 83 MTM data 9.2.18
0x54 84 PLLCalTarget PLL calibration target value 0000_0000 6.10.1.8
AMIS-53050 Frequency Agile Transceiver Data Sheet
106
AMI Semiconductor – Jan. 07, M-20639-002
www.amis.com
11.0 Applications
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AMIS-53050 Frequency Agile Transceiver Data Sheet
107
AMI Semiconductor – Jan. 07, M-20639-002
www.amis.com
12.0 Ordering Information
Table 120: Ordering Information
Ordering Code Product Name Package
Type
Operating
Temperature
Range
Industry
Application Differentiating
Feature Shipping
Configuration
19608-001-XTP (or –XTD)* AMIS-53050-I/A 32 LQFP -40C to 85C Industrial,
automotive,
other
Extra low power
RX Tape & Reel (-XTP);
Tubes (-XTD)
19608-002-XTP (or –XTD)** AMIS-53050-I/A 32 LQFP -40C to 85C Industrial,
automotive,
other
SPI interface;
Ganged
transceivers
Tape & Reel (-XTP);
Tubes (-XTD)
19608-003-XTP (or –XTD)* AMIS-53050-I/A 32 LQFP,
green/
RoHS -40C to 85C Industrial,
automotive,
other
Extra low power
RX Tape & Reel (-XTP);
Tubes (-XTD)
19608-004-XTP (or –XTD)** AMIS-53050-I/A 32 LQFP,
green/
RoHS -40C to 85C Industrial,
automotive,
other
SPI interface;
Ganged
transceivers
Tape & Reel (-XTP);
Tubes (-XTD)
* 19608-001 device will be deactivated and replaced by green/RoHS version 19608-003.
** 19608-002 device will be deactivated and replaced by green/RoHS version 19608-004.
13.0 Company or Product Inquiries
For more information about AMI Semiconductor, our technolog y and our products, visit our Web site at: HTUhttp://www.amis.comUTH.
North America
Tel: +1.208.233.4690
Fax: +1.208.234.6795
Europe
Tel: +32 (0) 55.33.22.11
Fax: +32 (0) 55.31.81.12
Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory,
implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of
merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI
Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high
reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMIS for such
applications. Copyright ©2007 AMI Semiconductor, Inc.
