M48T37V-70MH6TR - STMicroelectronics, Inc.

August 2007 Rev 7 1/29

M48T37Y

M48T37V

5.0 or 3.3V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM

Features

■Integrated ultra-low power SRAM, real time

clock, power-fail control circuit, and battery

■Frequency test output for real time clock

software calibration

■Year 2000 compliant

■Automatic power-fail chip deselect and WRITE

protection

■Watchdog timer

■WRITE protect voltage

(VPFD = Power-Fail Deselect Voltage):

–M48T37Y:V

CC = 4.5 to 5.5V

4.2V ≤ VPFD ≤ 4.5V

–M48T37V: V

CC = 3.0 to 3.6V

2.7V ≤ VPFD ≤ 3.0V

■Packaging includes a 44-lead SOIC and

SNAPHAT® top (to be ordered separately)

■SOIC package provides direct connection for a

SNAPHAT® top which contains the battery and

crystal

■Microprocessor power-on reset (valid even

during battery back-up mode)

■Programmable alarm output active in the

battery back-up mode

■Battery low flag

■RoHS compliant

– Lead-free second level interconnect

SNAPHAT (SH)

Battery/Crystal

SOH44 (MH)

44-pin SOIC

www.st.com

Contents M48T37Y, M48T37V
2/29   
Contents
Summary description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
2 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
Clock operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
3 Stopping and starting the oscillator   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
4 Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
5 Calibrating the clock  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
6 Watchdog timer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
7 Power-on reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
8 Programmable Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
9 Battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
10 Initial power-on defaults  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
11 VCC noise and negative going transients  . . . . . . . . . . . . . . . . . . . . . . . . .  18
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Part numbering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M48T37Y, M48T37V List of tables
 3/29
List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Register map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Capacitance  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Power down/up trip points DC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. SOH44 – 44-lead plastic small outline, 4-socket SNAPHAT, package mechanical data . . 24
Table 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data  . . 25
Table 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mechanical data  . 26
Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. SNAPHAT battery table  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

List of figures M48T37Y, M48T37V
4/29   
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Write enable controlled, write AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Chip enable controlled, write AC waveforms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Back-up mode alarm waveforms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. SOH44 – 44-lead plastic small outline, 4-socket SNAPHAT outline. . . . . . . . . . . . . . . . . . 24
Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 25
Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 26

M48T37Y, M48T37V Summary description

5/29

1 Summary description

The M48T37Y/V TIMEKEEPER® RAM is a 32 Kb x8 non-volatile static RAM and real time

clock. The monolithic chip is available in a special package which provides a highly

integrated battery backed-up memory and real time clock solution.

The 44-lead, 330mil SOIC package provides sockets with gold-plated contacts at both ends

for direct connection to a separate SNAPHAT housing containing the battery and crystal.

The unique design allows the SNAPHAT® battery/crystal package to be mounted on top of

the SOIC package after the completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal

damage due to the high temperatures required for device surface-mounting. The SNAPHAT

housing is keyed to prevent reverse insertion.

The SOIC and battery packages are shipped separately in plastic anti-static tubes or in

Tape &Reel form. For the 44-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part

number is “M4T28-BR12SH” or “M4T32-BR12SH” (see Table 18 on page 27).

Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the

lithium button-cell battery.

Figure 1. Logic diagram

AI02172

DQ0-DQ7

VCC

M48T37Y

M48T37V

VSS

WDI

RST

IRQ/FT

A0-A14

Summary description M48T37Y, M48T37V

6/29

Table 1. Signal names

Figure 2. SOIC connections

A0-A14 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

RST Reset Output (Open Drain)

IRQ/FT Interrupt / Frequency Test Output (Open Drain)

WDI Watchdog Input

E Chip Enable

G Output Enable

WWRITE Enable

VCC Supply Voltage

VSS Ground

NC Not connected Internally

AI02174

VSS

A13

A11

VCC

M48T37Y

M48T37V

A12

A14 IRQ/FT

DQ0

DQ7

DQ5DQ1

DQ2

DQ3

DQ4

DQ6

WDI

RST

A10

M48T37Y, M48T37V Summary description

7/29

Figure 3. Block diagram

AI03253

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

RSTVCC VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

16 x 8 BiPORT

SRAM ARRAY

32,752 x 8

SRAM ARRAY

A0-A14

DQ0-DQ7

POWER

IRQ/FT WDI

Operation modes M48T37Y, M48T37V

8/29

2 Operation modes

As Figure 3 on page 7 shows, the static memory array and the quartz controlled clock

oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that

provide user accessible BYTEWIDE™ clock information are in the bytes with addresses

7FF1 and 7FF9h-7FFFh (located in Table 5 on page 13). The clock locations contain the

century, year, month, date, day, hour, minute, and second in 24 hour BCD format.

Corrections for 28, 29 (leap year - valid until the year 2100), 30, and 31 day months are

made automatically.

Byte 7FF8h is the clock control register. This byte controls user access to the clock

information and also stores the clock calibration setting.

Byte 7FF7h contains the watchdog timer setting. The watchdog timer redirects an out-of-

control microprocessor and provides a reset or interrupt to it. Bytes 7FF2h-7FF5h are

reserved for clock alarm programming. These bytes can be used to set the alarm. This will

generate an active low signal on the IRQ/FT pin when the alarm bytes match the date,

hours, minutes, and seconds of the clock. The eight clock bytes are not the actual clock

counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE

memory cells. The M48T37Y/V includes a clock control circuit which updates the clock

bytes with current information once per second. The information can be accessed by the

user in the same manner as any other location in the static memory array.

The M48T37Y/V also has its own Power-fail Detect circuit. The control circuitry constantly

monitors the single VCC supply for an out of tolerance condition. When VCC is out of

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

midst of unpredictable system operation brought on by low VCC. As VCC falls below the

Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which

maintains data and clock operation until valid power returns.

Table 2. Operating modes

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

2.1 Read mode

The M48T37Y/V is in the READ Mode whenever WRITE Enable (W) is high and Chip

Enable (E) is low. The unique address specified by the 15 Address Inputs defines which one

of the 32,752 bytes of data is to be accessed. Valid data will be available at the Data I/O

pins within Address Access time (tAVQV) after the last address input signal is stable,

Mode VCC E G W DQ0-DQ7 Power

Deselect

4.5 to 5.5V

3.0 to 3.6V

VIH X X High Z Standby

WRITE VIL XV

IL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High Z Active

Deselect VSO to VPFD (min)(1)

1. See Table 13 on page 23 for details.

X X X High Z CMOS Standby

Deselect ≤ VSO(1) X X X High Z Battery Back-up

Mode

M48T37Y, M48T37V Operation modes

9/29

providing that the E and Output Enable (G) access times are also satisfied. If the E and G

access times are not met, valid data will be available after the latter of the Chip Enable

Access time (tELQV) or Output Enable Access time (tGLQV).

The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are

activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV.

If the Address Inputs are changed while E and G remain active, output data will remain valid

for Output Data Hold time (tAXQX) but will be indeterminate until the next Address Access.

Figure 4. Read mode AC waveforms

Note: WRITE Enable (W) = High.

Table 3. Read mode AC characteristics

AI00925

tAVAV

tAVQV tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A14

DQ0-DQ7

VALID

Symbol Parameter(1)

1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V

(except where noted).

M48T37Y M48T37V

Unit–70 –100

Min Max Min Max

tAVAV READ Cycle Time 70 100 ns

tAVQV Address Valid to Output Valid 70 100 ns

tELQV Chip Enable Low to Output Valid 70 100 ns

tGLQV Output Enable Low to Output Valid 35 50 ns

tELQX(2)

2. CL = 5pF.

Chip Enable Low to Output Transition 5 10 ns

tGLQX(2) Output Enable Low to Output Transition 5 5 ns

tEHQZ(2) Chip Enable High to Output Hi-Z 25 50 ns

tGHQZ(2) Output Enable High to Output Hi-Z 25 40 ns

tAXQX Address Transition to Output Transition 10 10 ns

Operation modes M48T37Y, M48T37V

10/29

2.2 Write mode

The M48T37Y/V is in the WRITE Mode whenever W and E are low. The start of a WRITE is

referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the

earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W

must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable

prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to

the end of WRITE and remain valid for tWHDX afterward. G should be kept high during

WRITE cycles to avoid bus contention; however, if the output bus has been activated by a

low on E and G, a low on W will disable the outputs tWLQZ after W falls.

Figure 5. Write enable controlled, write AC waveform

Figure 6. Chip enable controlled, write AC waveforms

AI00926

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A14

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI00927

tAVAV

tEHAX

tDVEH

A0-A14

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

M48T37Y, M48T37V Operation modes

11/29

Table 4. Write mode AC characteristics

2.3 Data retention mode

With valid VCC applied, the M48T37Y/V operates as a conventional BYTEWIDE™ static

RAM. Should the Supply Voltage decay, the RAM will automatically power-fail deselect,

write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs

become high impedance, and all inputs are treated as “Don't care.”

Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the

user can be assured the memory will be in a write protected state, provided the VCC fall time

is not less than tF

The M48T37Y/V may respond to transient noise spikes on VCC that reach into the deselect

window during the time the device is sampling VCC. Therefore, decoupling of the power

supply lines is recommended. When VCC drops below VSO, the control circuit switches

power to the internal battery which preserves data and powers the clock. The internal button

cell will maintain data in the M48T37Y/V for an accumulated period of at least 7 years at

room temperature when VCC is less than VSO. As system power returns and VCC rises

above VSO, the battery is disconnected and the power supply is switched to external VCC.

Normal RAM operation can resume tREC after VCC reaches VPFD (max).

For more information on Battery Storage Life refer to the Application Note AN1012.

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where

noted).

M48T37Y M48T37V

Unit–70 –100

Min Max Min Max

tAVAV WRITE Cycle Time 70 100 ns

tAVWL Address Valid to WRITE Enable Low 0 0 ns

tAVEL Address Valid to Chip Enable Low 0 0 ns

tWLWH WRITE Enable Pulse Width 50 80 ns

tELEH Chip Enable Low to Chip Enable High 55 80 ns

tWHAX WRITE Enable High to Address Transition 0 10 ns

tEHAX Chip Enable High to Address Transition 0 10 ns

tDVWH Input Valid to WRITE Enable High 30 50 ns

tDVEH Input Valid to Chip Enable High 30 50 ns

tWHDX WRITE Enable High to Input Transition 5 5 ns

tEHDX Chip Enable High to Input Transition 5 5 ns

tWLQZ(2)(3)

2. CL = 5pF.

3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE Enable Low to Output Hi-Z 25 50 ns

tAVWH Address Valid to WRITE Enable High 60 80 ns

tAVEH Address Valid to Chip Enable High 60 80 ns

tWHQX(2)(3) WRITE Enable High to Output Transition 5 10 ns

Clock operations M48T37Y, M48T37V

12/29

3 Clock operations

3.1 Reading the clock

Updates to the TIMEKEEPER® registers should be halted before clock data is read to

prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are

only data registers and not the actual clock counters, so updating the registers can be

halted without disturbing the clock itself.

Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 7FF8h.

As long as a '1' remains in that position, updating is halted. After a halt is issued, the

registers reflect the count; that is, the day, date, and the time that were current at the

moment the halt command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an

update in progress. Updating will resume within a second after the bit is reset to a '0.'

3.2 Setting the clock

Bit D7 of the Control Register (7FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like

the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them

with the correct day, date, and time data in 24 hour BCD format (see Table 5 on page 13).

Resetting the WRITE Bit to a '0' then transfers the values of all time registers (7FF1h,

7FF9h-7FFFh) to the actual TIMEKEEPER counters and allows normal operation to

resume. After the WRITE Bit is reset, the next clock update will occur in approximately one

second.

Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset

to '0.'

3.3 Stopping and starting the oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant

amount of time on the shelf, the oscillator can be turned off to minimize current drain on the

battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the

oscillator. When reset to a '0,' the M48T37Y/V oscillator starts within one second.

Note: It is not necessary to set the WRITE Bit when setting or resetting the FREQUENCY TEST

Bit (FT) or the STOP Bit (ST).

M48T37Y, M48T37V Clock operations

13/29

Table 5. Register map

KEYS:

S = Sign Bit

FT = Frequency Test Bit

R = READ Bit

W = WRITE Bit

ST = Stop Bit

0 = Must be set to '0'

BL = Battery Low Flag (Read only)

BMB0-BMB4 = Watchdog Multiplier Bits

AFE = Alarm Flag Enable Flag

RB0-RB1 = Watchdog Resolution Bits

WDS = Watchdog Steering Bit

ABE = Alarm in Battery Back-Up Mode Enable Bit

RPT1-RPT4 = Alarm Repeat Mode Bits

WDF = Watchdog Flag (Read only)

AF = Alarm Flag (Read only)

Z = '0' and are Read only

Address

Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

7FFFh 10 Years Year Year 00-99

7FFEh 0 0 0 10 M Month Month 01-12

7FFDh 0 0 10 Date Date: Day of Month Date 01-31

7FFCh 0 FT 0 0 0 Day of Week Day 01-7

7FFBh 0 0 10 Hours Hours Hours 00-23

7FFAh 0 10 Minutes Minutes Min 00-59

7FF9h ST 10 Seconds Seconds Sec 00-59

7FF8h W R S Calibration Control

7FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

7FF6h AFE 0 ABE 0 0 0 0 0 Interrupts

7FF5h RPT4 0 AIarm 10 Date Alarm Date Alarm Date 01-31

7FF4h RPT3 0 AIarm 10

Hours Alarm Hours Alarm Hour 00-23

7FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Min 00-59

7FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm Sec 00-59

7FF1h 1000 Year 100 Year Century 00-99

7FF0h WDF AF Z BL Z Z Z Z Flags

Clock operations M48T37Y, M48T37V

14/29

3.4 Setting the alarm clock

Registers 7FF5h-7FF2h contain the alarm settings. The alarm can be configured to go off at

a predetermined time on a specific day of the month or repeat every day, hour, minute, or

second. It can also be programmed to go off while the M48T37Y/V is in the battery back-up

mode of operation to serve as a system wake-up call.

RPT1-RPT4 put the alarm in the repeat mode of operation. Ta b l e 6 shows the possible

configurations. Codes not listed in the table default to the once per second mode to quickly

alert the user of an incorrect alarm setting.

Note: User must transition address (or toggle chip enable) to see Flag Bit change.

When the clock information matches the alarm clock settings based on the match criteria

defined by RPT1-RPT4, AF is set. If AFE is also set, the alarm condition activates the

IRQ/FT pin. To disable alarm, write '0' to the Alarm Date registers and RPT1-4. The alarm

flag and the IRQ/FT output are cleared by a READ to the Flags Register as shown in

Figure 7. A subsequent READ of the Flags Register is necessary to see that the value of the

Alarm Flag has been reset to '0.'

The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if

an alarm occurs and both the Alarm in Battery Back-up Mode Enable (ABE) and the AFE

are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated

during power-up will only set AF. The user can read the Flag Register at system boot-up to

determine if an alarm was generated while the M48T37Y/V was in the deselect mode during

power-up. Figure 8 illustrates the back-up mode alarm timing.

Figure 7. Alarm interrupt reset waveform

Table 6. Alarm repeat modes

RPT4 RPT3 RPT2 RPT1 Alarm Activated

1111 Once per Second

1 1 1 0 Once per Minute

1 1 0 0 Once per Hour

1000 Once per Day

0 0 0 0 Once per Month

AI01677B

A0-A14

ACTIVE FLAG BIT

ADDRESS 7FF0h

IRQ/FT

15ns Min

M48T37Y, M48T37V Clock operations

15/29

Figure 8. Back-up mode alarm waveforms

3.5 Calibrating the clock

The M48T37Y/V is driven by a quartz controlled oscillator with a nominal frequency of

32,768 Hz. The devices are tested not to exceed ±35 PPM (parts per million) oscillator

frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the

calibration bits properly set, the accuracy of each M48T37Y/V improves to better than +1/–2

PPM at 25 °C.

The oscillation rate of any crystal changes with temperature (see Figure 10 on page 19).

Most clock chips compensate for crystal frequency and temperature shift error with

cumbersome trim capacitors. The M48T37Y/V design, however, employs periodic counter

correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure 11 on page 19. The number of times pulses

are blanked (subtracted, negative calibration) or split (added, positive calibration) depends

upon the value loaded into the five-bit Calibration byte found in the Control Register. Adding

counts speeds the clock up, subtracting counts slows the clock down.

The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register

7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit

D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.

Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per

minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If

a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be

modified; if a binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125, 829, 120 (64 minutes x 60 seconds/minute x 32,768 cycles/second)

actual oscillator cycles, that is +4.068 or –2.034 PPM of adjustment per calibration step in

the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz,

AI03254B

VCC

IRQ/FT

tREC

VPFD (max)

VPFD (min)

ABE, AFE bit in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

HIGH-Z

Clock operations M48T37Y, M48T37V

16/29

each of the 31 increments in the Calibration Byte would represent +10.7 or –5.35 seconds

per month which corresponds to a total range of +5.5 or –2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M48T37Y/V may

require. The first involves simply setting the clock, letting it run for a month and comparing it

to a known accurate reference (like WWW broadcasts). While that may seem crude, it

allows the designer to give the end user the ability to calibrate his clock as his environment

may require, even after the final product is packaged in a non-user serviceable enclosure.

All the designer has to do is provide a simple utility that accesses the Calibration Byte.

The second approach is better suited to a manufacturing environment, and involves the use

of the IRQ/FT pin. The pin will toggle at 512 Hz when the Stop Bit (ST, D7 of 7FF9h) is '0'

the Frequency Test Bit (FT, D6 of 7FFCh) is '1,' the Alarm Flag Enable Bit (AFE, D7 of

7FF6h) is '0,' and the Watchdog Steering Bit (WDS, D7 of 7FF7h) is '1' or the Watchdog

Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at

the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 PPM

oscillator frequency error, requiring a –10(WR001010) to be loaded into the Calibration Byte

for correction.

Note: Setting or changing the Calibration Byte does not affect the Frequency Test output

frequency.

The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper

operation. A 500-10kΩ resistor is recommended in order to control the rise time. The FT Bit

is cleared on power-down.

For more information on calibration, see the Application Note AN934, “TIMEKEEPER

Calibration.”

3.6 Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the eight-bit

Watchdog Register, address 7FF7h. The five bits (BMB4-BMB0) that store a binary

multiplier and the two lower order bits (RB1-RB0) select the resolution, where 00 = 1/16

second, 01 = 1/4second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is

then determined to be the multiplication of the five-bit multiplier value with the resolution.

(For example: writing 00001110 in the Watchdog Register = 3x1, or 3 seconds).

Note: Accuracy of timer is within ± the selected resolution.

If the processor does not reset the timer within the specified period, the M48T37Y/V sets the

Watchdog Flag (WDF) and generates a watchdog interrupt or a microprocessor reset. WDF

is reset by reading the Flags Register (Address 7FF0h).

Note: User must transition address (or toggle chip enable) to see Flag Bit change.

Reset will not occur unless the addresses are stable at the flag location for at least 15ns

while the device is in the READ Mode as shown in Figure 9 on page 19.

The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to

a '0,' the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a '1,'

the watchdog will output a negative pulse on the RST pin for a duration of tREC. The

Watchdog Register, the FT Bit, AFE Bit, and ABE Bit will reset to a '0' at the end of a

Watchdog time-out when the WDS bit is set to a '1.'

M48T37Y, M48T37V Clock operations

17/29

The watchdog timer resets when the microprocessor performs a re-write of the Watchdog

period then starts over.

The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the

Watchdog Register. Should the watchdog timer time-out, a value of 00h needs to be written

to the Watchdog Register in order to clear the IRQ/FT pin.

The watchdog function is automatically disabled upon power-down and the Watchdog

frequency test function is activated, the watchdog or alarm function prevails and the

frequency test function is denied. The WDI pin should be connected to VSS if not used.

3.7 Power-on reset

The M48T37Y/V continuously monitors VCC. When VCC falls to the power fail detect trip

point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC

passes VPFD. RST is valid for all VCC conditions. The RST pin is an open drain output and

an appropriate resistor to VCC should be chosen to control rise time (see Figure 13 on

page 22).

3.8 Programmable Interrupts

The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an

interrupt condition occurs, the M48T37Y/V sets the appropriate flag bit in the Flag Register

7FF0h. The interrupt enable bits (AFE and ABE) in 7FF6h and the Watchdog Steering

(WDS) Bit in 7FF7h allow the interrupt to activate the IRQ/FT pin.

The Alarm flag and the IRQ/FT output are cleared by a READ to the Flags Register. An

interrupt condition reset will not occur unless the addresses are stable at the flag location for

at least 15ns while the device is in the READ Mode as shown in Figure 7 on page 14.

The IRQ/FT pin is an open drain output and requires a pull-up resistor (10kΩ

recommended) to VCC. The pin remains in the high impedance state unless an interrupt

occurs or the Frequency Test Mode is enabled.

3.9 Battery low flag

The M48T37Y/V automatically performs periodic battery voltage monitoring upon power-up.

The Battery Low Flag (BL), Bit D4 of the Flags Register 7FF0h, will be asserted high if the

SNAPHAT® battery is found to be less than approximately 2.5V. The BL Flag will remain

active until completion of battery replacement and subsequent battery low monitoring tests

during the next power-up sequence.

If a battery low is generated during a power-up sequence, this indicates the battery voltage

is below 2.5V (approximately), which may be insufficient to maintain data integrity. Data

should be considered suspect and verified as correct. A fresh battery should be installed.

The SNAPHAT top may be replaced while VCC is applied to the device.

Note: This will cause the clock to lose time during the interval the battery/crystal is removed.

Note: Battery monitoring is a useful technique only when performed periodically. The M48T37Y/V

only monitors the battery when a nominal VCC is applied to the device. Thus applications

Clock operations M48T37Y, M48T37V

18/29

which require extensive durations in the battery back-up mode should be powered-up

periodically (at least once every few months) in order for this technique to be beneficial.

Additionally, if a battery low is indicated, data integrity should be verified upon power-up via

a checksum or other technique.

3.10 Initial power-on defaults

Upon application of power to the device, the following register bits are set to a '0' state:

WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT (see Ta b l e 7 ).

Table 7. Default values

3.11 VCC noise and negative going transients

ICC transients, including those produced by output switching, can produce voltage

fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if

capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the

bypass capacitors will be released as low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in

Figure 9) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can

generate negative voltage spikes on VCC that drive it to values below VSS by as much as

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, it is recommended to connect a

schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface

mount.

Condition W R FT AFE ABE WATCHDOG

1. WDS, BMB0-BMB4, RBO, RB1.

Initial Power-up

(Battery Attach for SNAPHAT)(2)

2. State of other control bits undefined.

00000 0

Subsequent Power-up / RESET(3)

3. State of other control bits remains unchanged.

00000 0

Power-down(4)

4. Assuming these bits set to '1' prior to power-down.

00011 0

M48T37Y, M48T37V Clock operations

19/29

Figure 9. Supply voltage protection

Figure 10. Crystal accuracy across temperature

Figure 11. Clock calibration

AI02169

VCC

0.1μF DEVICE

VCC

VSS

AI00999

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

ΔF= -0.038 (T - T0)2 ± 10%

ppm

T0 = 25 °C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

Maximum rating M48T37Y, M48T37V

20/29

4 Maximum rating

Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 8. Absolute maximum ratings

Caution: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up

mode.

Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Symbol Parameter Value Unit

TAAmbient Operating Temperature Grade 1 0 to 70 °C

Grade 6 –40 to 85 °C

TSTG

Storage Temperature (VCC Off,

Oscillator Off)

SNAPHAT®–40 to 85 °C

SOIC –55 to 150 °C

TSLD(1)(2)

1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget

not to exceed 180°C for between 90 to 150 seconds).

2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal

budget not to exceed 245°C for greater than 30 seconds).

Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltages M48T37Y –0.3 to 7 V

M48T37V –0.3 to 4.6 V

VCC Supply Voltage M48T37Y –0.3 to 7 V

M48T37V –0.3 to 4.6 V

IOOutput Current 10 mA

PDPower Dissipation 1 W

M48T37Y, M48T37V DC and AC parameters

21/29

5 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC Characteristic

tables are derived from tests performed under the Measurement Conditions listed in the

relevant tables. Designers should check that the operating conditions in their projects match

the measurement conditions when using the quoted parameters.

Table 9. Operating and AC measurement conditions

Note: Output Hi-Z is defined as the point where data is no longer driven.

Figure 12. AC testing load circuit

1. 50pF for M48T37V.

Note: Excluding open-drain output pins

Table 10. Capacitance

Parameter M48T37Y M48T37V Unit

Supply Voltage (VCC) 4.5 to 5.5 3.0 to 3.6 V

Ambient Operating Temperature

(TA)

Grade 1 0 to 70 0 to 70 °C

Grade 6 –40 to 85 –40 to 85 °C

Load Capacitance (CL) 100 50 pF

Input Rise and Fall Times ≤ 10 ≤ 10 ns

Input Pulse Voltages 0 to 3 0 to 3 V

Input and Output Timing Ref. Voltages 1.5 1.5 V

AI02325

CL = 100pF(1)

CL includes JIG capacitance

645Ω

DEVICE

UNDER

TEST

1.75V

Symbol Parameter(1)(2)

1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.

2. At 25°C, f = 1MHz.

Min Max Unit

CIN Input Capacitance 10 pF

CIO(3)

3. Outputs deselected.

Input / Output Capacitance 10 pF

DC and AC parameters M48T37Y, M48T37V

22/29

Table 11. DC characteristics

Figure 13. Power down/up mode AC waveforms

Symbol Parameter Test condition(1)

1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where

noted).

M48T37Y M48T37V

Unit–70 –100

MinMaxMinMax

ILI(2)

2. WDI internally pulled down to VSS through a 100kΩ resistor.

Input Leakage Current 0V ≤ VIN ≤ VCC ±1 ±1 µA

ILO(3)

3. Outputs deselected.

Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA

ICC Supply Current Outputs open 50 33 mA

ICC1 Supply Current (Standby) TTL E = VIH 32mA

ICC2

Supply Current (Standby)

CMOS E = VCC – 0.2V 3 2 mA

VIL Input Low Voltage –0.3 0.8 –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V

VOL

Output Low Voltage

(standard) IOL = 2.1mA 0.4 0.4 V

Output Low Voltage

(open drain) IOL = 10mA 0.4 0.4 V

VOH Output High Voltage IOH = –1mA 2.4 2.4 V

AI03078

VCC

INPUTS

RST

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tREC

tRB

tDR

VALID VALID

VPFD (max)

VPFD (min)

VSO

VALID VALID

M48T37Y, M48T37V DC and AC parameters

23/29

Table 12. Power down/up AC characteristics

Table 13. Power down/up trip points DC characteristics

Note: All voltages referenced to VSS.

Symbol Parameter(1)

1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where

noted).

Min Max Unit

tF(2)

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after

VCC passes VPFD (min).

VPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB(3)

3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data

VPFD (min) to VSS VCC Fall Time 10 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1 µs

tREC(4)(4)

4. tREC (min) = 20ms for Industrial Temperature Range - Grade 6 device.

VPFD (max) to RST High 40 200 ms

Symbol Parameter(1)

1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where

noted).

Min Typ Max Unit

VPFD Power-fail Deselect Voltage M48T37Y 4.2 4.4 4.5 V

M48T37V 2.7 2.9 3.0 V

VSO Battery Back-up Switchover Voltage M48T37Y VBAT V

M48T37V VPFD –100mV V

tDR(2)

2. At 25°C, VCC = 0V.

Expected Data Retention Time Grade 1 5 7 YEARS

Grade 6 10(3)

3. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - Grade 6 device).

YEARS

Package mechanical data M48T37Y, M48T37V

24/29

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 14. SOH44 – 44-lead plastic small outline, 4-socket SNAPHAT outline

Note: Drawing is not to scale.

Table 14. SOH44 – 44-lead plastic small outline, 4-socket SNAPHAT, package mechanical data

Symbol

mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

a 0°8° 0°8°

N44 44

CP 0.10 0.004

SOH-A

LA1 α

M48T37Y, M48T37V Package mechanical data

25/29

Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline

Note: Drawing is not to scale.

Table 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package

mechanical data

SHTK-A

A1 A

Symbol

mm inches

Typ Min Max Typ Min Max

A9.780.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

Package mechanical data M48T37Y, M48T37V

26/29

Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package

outline

Note: Drawing is not to scale.

SHTK-A

A1 A

Table 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package

mechanical data

Symbol

mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 .0335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 .0710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

M48T37Y, M48T37V Part numbering

27/29

7 Part numbering

Table 17. Ordering information scheme

Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will

drain the lithium button-cell battery.

For other options, or for more information on any aspect of this device, please contact the

ST sales office nearest you.

Table 18. SNAPHAT battery table

Example: M48T 37Y –70 MH 1 E

Device type

M48T

Supply voltage and write protect voltage

37Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V

37V = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V

Speed

–70 = 70ns (37Y)

–10 = 100ns (37V)

Package

MH(1) = SOH44

1. The SOIC package (SOH44) requires the SNAPHAT® battery package which is ordered

separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in

Tape & Reel form (see Table 18).

Temperature range

1 = 0 to 70°C

6 = –40 to 85°C

Shipping method

blank = tubes (not for new design - use E)

E = ECOPACK package, tubes

F = ECOPACK package, tape & reel

TR = tape & reel (not for new design - use F)

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

Revision history M48T37Y, M48T37V
28/29   
8 Revision history
Table 19. Document revision history
         
Date Version Changes
Dec-1999 1.0 First Issue
07-Feb-2000 2.0 From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns 
speed class identifier changed (Ta b le 3 , 4)
11-Jul-2000 2.1 tFB changed (Ta bl e 1 2 ); watchdog timer paragraph changed
19-Jun-2001 3.0 Reformatted; added temp./voltage info. to tables (Ta bl e 1 0 , 11, 3, 4, 12, 13)
06-Aug-2001 3.1 Fix text for Setting the Alarm Clock (Figure 7)
15-Jan-2002 3.2 Fix footnote numbering (Ta b l e 1 7)
20-May-2002 3.3 Modify reflow time and temperature footnote (Ta b le 8)
31-Mar-2003 4.0 v2.2 template applied; data retention condition updated (Ta b l e 1 3 )
01-Apr-2004 5.0 Reformatted; updated with Lead-free package information (Ta b l e 8 , 17)
08-Feb-2006 6.0 New template; updated Lead-free text; fixed DC Characteristics (Ta b le 8 , 11, 17)
03-Aug-2007 7.0 Reformatted; added lead-free second level interconnect information to cover page 
and Section 6: Package mechanical data.

M48T37Y, M48T37V

29/29

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