AOZ1022DI - Alpha & Omega Semiconductor

Rev. 1.6 December 2010 www.aosmd.com Page 1 of 17

AOZ1022

EZBuck™ 3A Synchronous Buck Regulator

General Description

The AOZ1022 is a synchro nous high efficiency, simple

to use, 3A buck regulator. The AOZ1022 works from a

4.5V to 16V input voltage range, and provides up to 3A

of continuous output current with an output voltage

adjustable down to 0.8V.

The AOZ1022 comes in a DFN 5x4 and an EPAD SO-8

package and is rated over a -40°C to +85°C ambient

temperature range.

Features

●4.5V to 16V operating input voltage range

●Synchronous rectification: 100mΩ internal high-side

switch and 20mΩ Internal low-side switch

●High efficiency: up to 95%

●Internal soft start

●Active high power good state

●Output voltage adjustable to 0.8V

●3A continuous output current

●Fixed 500kHz PWM operatio n

●Cycle-by-cycle current limit

●Pre-bias start-up

●Short-circuit protection

●Thermal shutdown

●Small size DFN 5x4 and EPAD SO-8 package

Applications

●Point of load DC-DC conversion

●PCIe graphics cards

●Set top boxes

●DVD drives and HDD

●LCD panels

●Cable modems

●Telecom/networking/datacom equipment

Typical Application

Figure 1. 3.3V/3A Synchronous Buck Regulator

PGOOD

VIN

VOUT

5V DC

PGND

COMP

AGND

C2, C3

22µF Ceramic

22µF

Ceramic

L1 4.7µH

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 2 of 17

Ordering Information

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional informatio n.

Pin Configuration

Pin Description

Part Number Ambient Temperature Range Package Environmental

AOZ1022DI -40°C to +85°C DFN 5x4

AOZ1022 -40°C to +85°C EPAD S0-8 Green

PGND

VIN

AGND

PGOOD

COMP

5x4 DFN-8

(Top View)

GND

PGND

VIN

AGND

Exposed Pad SO-8

(Top View)

PAD

(LX)

PGOOD

COMP

Pin Number

Pin Name Pin Function5x4 DFN-8 Exposed

Pad SO-8

1 1 PGND Power ground. PGND needs to be electrical ly connected to AGND.

22V

IN Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,

the device starts up.

3 3 AGND Analog ground. AGND is the reference point for controller section. AGND needs to

be electrically connected to PGND.

4 4 FB Feedback input. The FB pin is used to set the output voltage via a resistor divider

between the output and AGND.

5 5 COMP External loop compensation pin. Connect a RC network between COMP and AGND

to compensate the control loop.

6 6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable

the device. if on/off control is not needed, connect it to VIN and do not leave it open.

7 Pad LX Switching node. LX is the drain of the internal PFET. LX is used as the thermal pad of

the power stage.

8 7 PGOOD Power Good Output. PGOOD is an open-drain output that indicates the status of out-

put voltage. PGOOD is pulled low when output is below 90% of the normal regula-

tion.

8 NC No Connect. Pin 8 is not internally connected.

Rev. 1.6 December 2010 www.aosmd.com Page 3 of 17

AOZ1022

Block Diagram

Absolute Maximum Ratings

Exceeding the Absolute Maximum Ratings may damage the

device.

Note:

1. Devices are inherently ESD sensitive, handling precautions are

required. Human body model rating: 1.5kΩ in series with 100pF.

Recommended Operating Conditions

The device is not guaranteed to operate beyond the Maximum

Recommended Operating Conditions.

Note:

2. The value of ΘJA is measured with the device mounted on

1-in2 FR-4 board with 2oz. Copper, in a still air environment with

TA = 25°C. The value in any given application depends on the

user's specific board design.

Oscillator

AGND PGND

VIN

COMP

PGOOD

OTP

Internal

+5V

ILimit

PWM

Control

Logic

5V LDO

Regulator

UVLO

& POR

Softstart

Reference

& Bias

0.8V

PWM

Comp

Level

Shifter

FET

Driver

ISen

EAmp

0.2V

–

0.72V

–

Frequency

Foldback

Comparator

Parameter Rating

Supply Voltage (VIN) 18V

LX to AGND -0.7V to VIN+0.3V

EN to AGND -0.3V to VIN+0.3V

FB to AGND -0.3V to 6V

COMP to AGND -0.3V to 6V

PGND to AGND -0.3V to 0.3V

PGOOD to AGND -0.3V to 6V

Junction Temperature (TJ) +150°C

Storage Temperature (TS) -65°C to +150°C

ESD Rating(1) 2.0kV

Parameter Rating

Supply Voltage (VIN) 4.5V to 18V

Output Voltage Range 0.8V to VIN

Ambient Temperature (TA) -40°C to +85°C

Package Thermal Resistance

Exposed Pad SO-8 (ΘJA)(2) 50°C/W

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 4 of 17

Electrical Characteristics

TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3)

Note:

3. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.

Symbol Parameter Conditions Min. Typ. Max. Units

VIN Supply Voltage 4.5 16 V

VUVLO Input Under-Voltage Lockout Threshold VIN Rising

VIN Falling

4.1

3.7 V

IIN Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 1.2V 1.6 2.5 mA

IOFF Shutdown Supply Current VEN = 0V 320µA

VFB Feedback Voltage TA = 25°C 0.788 0.8 0.812 V

Load Regulation 0.5 %

Line Regulation 1%

IFB Feedback Voltage Input Current 200 nA

ENABLE

VEN EN Input Threshold Off Threshold

On Threshold 2

0.6 V

VHYS EN Input Hysteresis 100 mV

MODULATOR

fOFrequency 350 500 600 kHz

DMAX Maximum Duty Cycle 100 %

DMIN Minimum Duty Cycle 6%

GVEA Error Amplifier Voltage Gain 500 V / V

GEA Error Amplifier T r ansconductance 200 µA / V

PROTECTION

ILIM Current Limit 4.0 5.0 A

Over-Temperature Shutdown Limit TJ Rising

TJ Falling 150

100 °C

tSS Soft Start Interva l 3 5 7 ms

POWER GOOD

VOLPG PGOOD LOW Voltage IOL = 1mA 0.5 V

PGOOD Leakage 1µA

VPGL PGOOD Threshold Voltage 87 90 92 %VO

PGOOD Threshold Voltage Hysteresis 3 %

tPG PGOOD Delay Time 128 µs

PWM OUTPUT STAGE

High-Side Switch On-Resistance VIN = 12V

VIN = 5V 97

166 130

200 mΩ

Low-Side Switch On-Resistance VIN = 12V

VIN = 5V 18

30 23

36 mΩ

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 5 of 17

Light Load Operation Full Load (CCM) Operation

Startup to Full Load Short Circuit Protection

50% to 100% Load Transient Short Circuit Recovery

1s/div1s/div

1ms/div

100s/div

Vin ripple

0.1V/div

Vo ripple

20mV/div

2V/div

Vin

10V/div

lin

1A/div

Vo Ripple

100mV/div

1A/div

VLX

10V/div

Vin ripple

0.1V/div

Vo ripple

20mV/div

1A/div

VLX

10V/div

50µs/div

10V/div

2V/div

2A/div

1ms/div

10V/div

2V/div

2A/div

Typical Performance Characteristics

Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 6 of 17

Efficiency

Thermal Derating Curves

AOZ1022 Efficiency

Efficiency (V

= 12V) vs. Load Current

95 5.0V OUTPUT

3.3V OUTPUT

1.8V OUTPUT

1.2V OUTPUT

1.8V

3.3V OUTPUT

100

00.5 1.0 1.5 2.0 2.5 3.0

Load Current (A)

Efficieny (%)

AOZ1022 Efficiency

Efficiency (V

= 5V) vs. Load Current

100

00.5 1.0 1.5 2.0 2.5 3.0

Load Current (A)

Efficieny (%)

Derating Curve at 5V/6V Input

1.2V, 1.8V OUTPUT

3.3V

OUTPUT

Ambient Temperature (T

)

Output Current (I

)

25 35 45 55 65 75 85

Derating Curve at 12 Input

1.2V, 1.8V, 3.3V, 5.0V OUTPUT

Ambient Temperature (T

)

Output Current (I

)

3.3

3.2

3.1

3.0

2.9

2.8

25 35 45 55 65 75 85

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 7 of 17

Detailed Description

The AOZ1022 is a current-mode step down regulator

with integrated high-side PMOS switch and a low-side

NMOS switch. It operates from a 4.5V to 16V input

voltage range and supplies up to 3A of load curre nt.

The duty cycle can be adjusted from 6% to 100%

allowing a wide range of output voltage. Features include

enable control, Power-On Reset, input under voltage

lockout, output over voltage protection, active high power

good state, fixed internal soft-start and thermal shut

down.

Enable and Soft Start

The AOZ1022 has an internal soft start feature to limit

in-rush current and ensure the output voltage ramps up

smoothly to regulation voltage. A soft start process

begins when the input voltage rises to 4.1V and voltage

on EN pin is HIGH. In the soft start process, the output

voltage is typically ramped to regulation voltage in 4ms.

The 4ms soft start time is set internally.

The EN pin of the AOZ1022 is active HIGH. Connect the

EN pin to VIN if the enable function is not used.

Pulling EN to ground will disable the AOZ1022. Do not

leave it open. The voltage on the EN pin must be above

2V to enable the AOZ1022. When vo ltage on the EN

pin falls below 0.6V, the AOZ1022 is disabled . If an appli-

cation circuit requires the AOZ1022 to be disabled, an

open drain or open collector circuit should be used to

interface to the EN pin.

Power Good

The output of Power-Good is an open drain N-channel

MOSFET which supplies an active high power good

stage. A pull- up r esistor (R 3) should connect this pin to a

DC power trail with maximum voltage of 6V. The

AOZ1022 monitors the FB voltage. When FB voltage is

lower than 90% of the norma l voltage, N-channel

MOSFET turns on and the Power-Good pin is pulle d low.

This indicates the power is abno rmal.

Steady-State Operation

Under steady-state conditions, the converter operates in

fixed frequency and Continuous-Conduction Mode

(CCM).

The AOZ1022 integrates an internal P-MOSFET as the

high-side switch. In ductor current is sensed by amplifying

the voltage drop acro ss the drain to source of the high

side power MOSFET. Output voltage is divided down by

the external voltage divider at the FB pin. The difference

of the FB pin voltage and reference is amplified by the

internal tran sconductance error amplifier. The error

voltage, which shows on the COMP pin, is compared

against the current signal, which is sum of indu ctor

current signal and ramp compensation signal, at the

PWM comparator input. If the current signal is less than

the error voltage, the internal high-side switch is on. The

inductor current fl ows from the input thro ugh the in ductor

to the output. When the current signal exceeds the error

voltage, the high-side switch is off. The inductor current

is freewheeling through the inter nal low-side N-M OSFET

switch to output. The internal adaptive FET driver

guarantees no turn on overlap of both high-side and

low-side switch.

Comparing with regulators using freewheeling Schottky

diodes, the AOZ1022 uses freewheeling NMOSFET to

realize synchronous rectification. It greatly improves the

converter efficien cy and reduces power loss in the

low-side switch.

The AOZ1022 uses a P-Channel MOSFET as the high-

side switch. It saves the bootstrap capacitor normally

seen in a circuit which is using an NMOS switch. It allows

100% turn-on of the high-side switch to achieve linear

regulation mode of operatio n. The minimum volt age drop

from VIN to VO is the load current x DC resistance of

MOSFET + DC resistance of buck inductor. It can be

calculated by the equation below:

where;

VO_MAX is the maximum output voltage,

VIN is the input voltage from 4.5V to 16V,

IO is the output current from 0A to 3A, and

RDS(ON) is the on resi stance of internal MOSFET, the value is

between 97mΩ and 200mΩ depe nding on input voltage and

junction temperature.

Switching Frequency

The AOZ1022 switching frequency is fixed and set by

an internal oscillator. The practical switching frequency

could range from 350kHz to 600kHz due to device

variation.

Output Voltage Programming

Output voltage can be set by feeding back the output to

the FB pin by using a resistor divider network. See the

application circuit shown in Figure 1. The resistor divider

network includes R1 and R2. Usually, a design is started

by picking a fixed R2 value and calculating the required

R1 with equation on the next page:

VO_MAX VIN IORDS ON()

×–=

VO0.8 1 R1

-------

⎝⎠

⎜⎟

⎛⎞

×=

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 8 of 17

Some standard value of R1, R2 and most used output

voltage values ar e listed in Table 1.

The combination of R1 and R2 should be large enough to

avoid drawing excessive current from the output, which

will cause power loss.

Since the switch duty cycle can be as high as 100%, the

maximum output voltage can be set as high as the input

voltage minus the voltage drop on upper PMOS and

inductor.

Protection Features

The AOZ1022 has multip le protection features to preven t

system circuit damage under abnormal conditions.

Over Current Protection (OCP)

The sensed inductor current signal is also used for

over current pr ot ect i on . Sinc e the A OZ 1 02 2 em p loys

peak current mode control, the COMP pin voltage is

proportional to the peak inductor current. The COMP pin

voltage is limited to be betwee n 0.4V and 2.5V intern ally.

The peak inductor current is automatically limited cycle

by cycle.

When the output is shorted to ground under fault

conditions, the inductor current decays very slow during

a switching cycle beca us e of VO = 0V. To prevent cata-

strophic failure, a secondary current limit is designed

inside the AOZ1022. The measured inductor current is

compared against a preset voltage which represents the

current limit, between 3.5A and 5.0A. When the output

current is more than current limit, the high side switch will

be turned off. The converter will initiate a soft start once

the over-current condition is resolved.

Power-On Reset (POR)

A power-on reset circuit monitors the input voltage.

When the input voltage exceeds 4.1V, the converter

starts operation. When input voltage falls below 3.7V,

the converter shuts down.

Thermal Protection

An internal temperature sensor monitors the junction

temperature. It shut s down the inter nal control circuit and

high side PMOS if the junction temperature exceeds

150°C. The regulator will restart automatically under the

control of soft-start circui t when the junction temperature

decreases to 100°C.

Application Information

The basic AOZ1022 application circuit is show in

Figure 1. Component selection is explained below.

Input Capacitor

The input cap acitor must be connected to the VIN pin and

PGND pin of AOZ1022 to maintain steady input voltage

and filter out the pulsing inp ut curr ent. The vo ltage rating

of input capacitor must be greater than maximum input

voltage plus ripple voltage.

The input ripple voltage can be approximated by equa-

tion below:

Since the input current is discontinuous in a buck

converter, the current stress on the input capacitor is

another conc er n wh en sele ctin g th e ca pacitor. For a

buck circuit, the RMS value of input capacitor current

can be calculated by:

if we let m equal the conversion ratio:

The relation between the input capacitor RMS current

and voltage conversion ratio is calculated and shown in

Figure 2 on the next p age. It can be seen that when VO is

half of VIN, CIN is under the worst current stress. The

worst current stress on CIN is 0.5 x IO.

For reliable operation and best performance, the input

capacitors must have current rating higher than ICIN_RMS

at worst operating conditions. Ceramic capacitors are

preferred for input capacitors because of their low ESR

and high current rating. Depend ing on the application

circuits, other low ESR tantalum capacitor may also be

used. When selecting ceramic capacitors, X5R or X7R

type dielectric ceramic capacitors should be used for

their better temp er ature and voltage charac te ristics.

VO (V) R1 (kΩ) R2 (kΩ)

0.8 1.0 open

1.2 4.99 10

1.5 10 11.5

1.8 12.7 10.2

2.5 21.5 10

3.3 31.1 10

5.0 52.3 10

ΔVIN

----------------- 1VO

VIN

---------

–

⎝⎠

⎜⎟

⎛⎞

VIN

---------

××=

ICIN_RMS IO

VIN

---------1VO

VIN

---------

–

⎝⎠

⎜⎟

⎛⎞

×=

VIN

---------m=

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 9 of 17

Figure 2. ICIN vs. Voltage Conversion Ratio

Note that the ripple current rating from capacitor manu-

factures are based on certain amount of life time.

Further de-rating may be necessary in practical design.

Inductor

The inductor is used to supply constant current to output

when it is driven by a switching voltage. For given input

and output voltage, induct ance and switching frequency

together decide the inductor ripple current, which is:

The peak inductor current is:

High inductance gives low inductor ripple current but

requires larger size inductor to avoid saturation. Low

ripple current reduces inductor core losses. It also

reduces RMS current through inductor and switches,

which results in less conduction loss. Usually, peak to

peak ripple current on inductor is designed to be 20%

to 30% of output current.

When selecting the inductor, make sure it is able to

handle the peak current without saturation even at the

highest operating temperature.

The inductor takes the highest current in a buck circuit.

The conduction loss on inductor need to be checked for

thermal and efficiency requ ire m en ts.

Surface mount in ductors in diff erent shape and style s are

available from Coilcraft, Elytone and Murata. Shielded

inductors are small and radiate less EMI noise. But they

cost more than unshielded inductors. The choice

depends on EMI requirement, price and size.

Output Capacitor

The output cap acitor is selected based on the DC output

voltage rating, output ripple voltage specification and

ripple current rating.

The selected output capacitor must have a higher rated

voltage specification than the maximum desired output

voltage including ripple. De-rating needs to be consid-

ered for long term reliability.

Output ripple voltage specification is another important

factor for selecting the output capacitor. In a buck con-

verter circuit, ou tp ut ripple voltage is determi ne d by

inductor value, switching frequency, output capacitor

value and ESR. It can be calculated by the equation

below:

where,

CO is output capacitor value, and

ESRCO is the equivalent series resistance of the output

capacitor.

When low ESR ceramic capacitor is used as output

capacitor , th e impedance of the capacitor at the switchin g

frequency dominates. Output ripple is mainly caused by

capacitor value and inductor ripple current. The output

ripple voltage calculation can be simplified to:

If the impedance of ESR at switching frequency

dominates, the output ripple voltage is mainly decided

by capacitor ESR and inductor ripple current. The output

ripple voltage calculation can be further simplified to :

For lower output ripple voltage across the entire operat-

ing temperature range, X5R or X7R dielectric type of

ceramic, or other low ESR t antalu m are recommended to

be used as output capacitors.

In a buck converter , output capacitor current is continuous.

The RMS current of output capacitor is decided by the

peak to peak inductor ripple current. It can be calculated

by:

Usually, the ripple current rating of the output cap acitor is

a smaller issue because of the low current stress. When

the buck inductor is selected to be very small and induc-

0.1

0.2

0.3

0.4

0.5

0 0.5 1

CIN_RMS

(m)

ΔIL

fL×

-----------1VO

VIN

---------

–

⎝⎠

⎜⎟

⎛⎞

×=

ILpeak IO

ΔIL

--------

ΔVOΔILESRCO

8fC

××

-------------------------

⎝⎠

⎛⎞

×=

ΔVOΔIL

8fC

××

-------------------------

⎝⎠

⎛⎞

×=

ΔVOΔILESRCO

×=

ICO_RMS

ΔIL

----------

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 10 of 17

tor ripple current is high, the output capacitor could be

overstressed.

Loop Compensation

The AOZ1022 employs peak current mode control for

easy use and fast tr ansient response. Peak current mode

control eliminates the double pole effect of the output

L&C filter. It greatly simplifies the compensation loop

design.

With peak current mode control, the buck power stage

can be simplified to be a one-pole and one-zero system

in frequency domain. The pole is the dominant pole can

be calculated by:

The zero is an ESR zero due to output capacitor and its

ESR. It is can be calculated by:

where;

CO is the output filter capacitor,

RL is load resistor value, and

ESRCO is the equivalent series resistance of output capacitor.

The compensation design is actually to shape th e

converter control loop transfer function to get the desired

gain and phase. Several different types of compensation

network can be used for the AOZ1022. In most cases, a

series capacitor and resistor network connected to the

COMP pin set s the pole-zero and is adequate for a stable

high-bandwidth control loop.

In the AOZ1022, FB pin and COMP pin are the inverting

input and the output of internal error amplifier. A series R

and C compensation network connected to COMP

provides one pole and one zero. The pole is:

where;

GEA is the error amplifier transconductance, which is 200 x 10-6

A/V,

GVEA is the error amplifier voltage; and

C2 is compensation capacitor in Figure 1.

The zero given by the external compensation network,

capacitor C2 and resistor R3, is located at:

To design the compensation circuit, a target crossover

frequency fC for close loop must be se lected. The system

crossover frequency is wher e control loop has unity gain .

The crossover is the also called the con verter bandwid th.

Generally a hig her bandwidth means faster response to

load transient. Howe ver, the bandwid th should not be too

high because of system stability concern. When design-

ing the compensation loop, converter stability under all

line and load condition must be considered.

Usually, it is recommended to set the bandwidth to be

equal or less than 1/10 of switching frequency. The

AOZ1022 operates at a frequency range from 350kHz

to 600kHz. It is recommended to choose a crossover

frequency equal or less than 40kHz.

The strategy for choosing RC and CC is to set the

cross over frequency with RC and set the compensator

zero with CC. Using selected crossover frequency, fC,

to calculate R3:

where;

where fC is desired crossover frequency . For best performance,

fC is set to be about 1/10 of switching frequency,

VFB is 0.8V,

GEA is the error amplifier transconductance, which is 200 x 10-6

A/V, and

GCS is the current sense circuit transconductance, which is 6.86

A/V

The compensation capacitor CC and resistor RC together

make a zero. This zero is put somewhere close to the

dominate pole fp1 but lower than 1/5 of selected

crossover frequency. C2 can is selected by:

The above equation can be simplified to:

fp1

2πCORL

××

-----------------------------------

fZ1

2πCOESRCO

××

------------------------------------------------

fp2

GEA

2πCCGVEA

××

-------------------------------------------

fZ2

2πCCRC

××

-----------------------------------

fC40kHz=

RCfC

VFB

---------- 2πC2

GEA GCS

------------------------------

××=

1.5

2πRCfp1

××

-----------------------------------

CORL

---------------------

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 11 of 17

An easy-to-use application software which helps to

design and simulate the compensation loop can be found

at www.aosmd.com.

Thermal Management and Layout

Consideration

In the AOZ1022 buck regulator circuit, high pulsing

current flows through two circuit loops. The first loop

starts from the input capacitors, to the VIN pin, to the LX

pins, to the filter inductor, to the output capacitor and

load, and then return to the input capacitor through

ground. Current flows in the first loop when the high side

switch is on. The second loop starts from inductor, to the

output cap acitors and load, to the anode of Schottky

diode, to the cathode of Schottky diode. Current flows in

the second loop whe n the low sid e dio de is on.

In PCB layout, minimizing the two loops area redu ces the

noise of this circuit and improves efficiency. A ground

plane is strongly recommended to connect input capaci-

tor, output capacitor, and PGND pin of the AOZ1022.

In the AOZ1022 buck regulato r circuit, the major power

dissipating components are the AOZ1022 and the

output inductor. The total power dissipation of conver ter

circuit can be measured by inpu t power minus output

power.

The power dissipation of inductor can be approximately

calculated by output current and DCR of inductor.

The actual junction temperature can be calculated with

power dissipation in the AOZ 1 02 2 an d therm al

impedance from junction to ambient.

The maximum junction temperature of AOZ1022 is

150°C, which limits the maximum load current capability.

Please see the thermal de-rating curves for maximum

load current of the AOZ1022 under diffe rent ambient

temperature.

The thermal performance of the AOZ1022 is strongly

affected by the PCB layout. Extra care should be taken

by users during design process to ensure that the IC

will operate under the recommended environmental

conditions.

The AOZ1022 comes in an EPAD SO-8 package. L ayout

tips are listed below for the best electric and thermal

performance. Figure 3 illustrates a PCB layout example

of the AOZ1022.

1. The LX pins are connected to internal PFET and

NFET drains. They are low resistance thermal

conduction path and the most noisy switching node.

Connected a large copper pla ne to the LX pi n to help

thermal dissipation.

2. Do not use thermal relief connection to the VIN and

the PGND pin. Pour a maximized copper area to the

PGND pin and the VIN pin to help thermal dissipation.

3. Input capacitor should be connecte d to the VIN pin

and the PGND pin as close as possible.

4. A ground plane is preferr ed. If a ground plane is

not used, separate PGND from AGND and connect

them only at one point to avoid the PGND pin noise

coupling to the AGND pin.

5. Make the curren t trac e from LX pins to L to Co to the

PGND as short as possible .

6. Pour copper plane on all unused board area and

connect it to stable DC nodes, like VIN, GND or VOUT.

7. Keep sensitive signal trace far away form the LX

pins.

Ptotal_loss VIN IIN VOIO

×–×=

Pinductor_loss IO2Rinductor 1.1××=

Tjunction Ptotal_loss Pinductor_loss

–()Θ×JA

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 12 of 17

Notes:

1. Dimensions and tolerancing conform to ASME Y14.5M-1994.

2. All dimensions are in millimeters.

3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.

4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the

optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.

5. Coplanarity applies to the terminals and all other bottom surface metallization.

6. Drawing shown are for illustration only.

7. The dimensions with * are just for reference

8. Pin #3 and Pin #7 are fused to DAP.

Symbols

aaa

bbb

ccc

ddd

eee

Dimensions in millimeters

RECOMMENDED LAND PATTERN

FRONT VIEW

TOP VIEW BOTTOM VIEW

Min.

0.70

0.40

4.90

2.05

1.66

3.90

2.23

0.50

—

Nom.

0.75

0.20 Ref.

0.45

5.00

2.15

1.76

4.00

2.33

0.95 BSC

0.55

0.40

0.285 Ref.

0.835 Ref.

0.15

0.10

0.08

0.05

Max.

0.80

0.50

5.10

2.25

1.86

4.10

2.43

0.60

—

Symbols

aaa

bbb

ccc

ddd

eee

Min.

0.028

0.016

0.190

0.080

0.064

0.154

0.088

0.020

—

Nom.

0.30

0.008 Ref.

0.018

0.200

0.085

0.070

0.157

0.092

0.037 BSC

0.022

0.016

0.011 Ref.

0.033 Ref.

0.006

0.004

0.003

0.002

Max.

0.032

0.020

0.210

0.089

0.074

0.161

0.096

0.024

—

4.51

0.285

2.33

1.65

0.285

1.86

0.40

2.25

0.50 Typ.

0.95 Typ.

0.65

4.20

Dimensions in inches

Seating

Plane

D/2

E/2

L2*

L3*

L2*

D2 Pin #1 IDA

Chamfer 0.30

Index Area

(D/2 x E/2)

Package Dimensions, DFN 5x4

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 13 of 17

R0.40

K0 A0

E2 D0

Package

DFN 5x4

(12 mm)

A0 B0 K0 E E1 E2D0 D1 P0 P1 P2 T

5.30

±0.10 ±0.10

4.30

±0.10

1.20

Min.

1.50 1.50 12.00

±0.10

1.75

±0.10

5.50

±0.10

8.00

±0.20

4.00

±0.10

2.00

±0.05

0.30

UNIT: mm

0.20

Feeding

Direction

Leader/Trailer and Orientation

±0.30

+0.10 / –0

Trailer Tape

300mm Min.

Components Tape

Orientation in Pocket

Leader Tape

500mm Min.

Tape Dimensions, DFN 5x4

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 14 of 17

VIEW: C

0.05 3-1.8

ø960.2

6.450.05

3-ø2.90.05

3-ø1/8"

3-ø1/4"

8.90.1

11.90

14 REF

1.8

5.0

12 REF

41.5 REF

43.00

44.50.1

2.00

6.50

10.0

10.71

3-ø3/16"

R48 REF

ø86.00.1

2.20

6.2

ø13.00

ø21.20

ø17.0

R1.10

R3.10

2.00

3.3

4.0

6.10

0.80

3.00

8.00

+0.050.00

R0.5

1.80

2.5

44.50.1

46.00.1

8.00.1

3-ø3/16"

R3.95

6.50

ø90.00

6.0

1.8

8.00

0.00

-0.05

N=ø1002

R121

R127

R159

R55

II I

6.01

Zoom In

III

Zoom In

Tape Size

12mm

Reel Size

ø330

+0.3

-4.0

12.40

+2.0

-0.0

2.40

0.3

0.5

Reel Dimensions, DFN 5x4

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 15 of 17

Package Dimensions, EPAD SO-8

Notes:

1. Package body sizes exclude mold flash and gate burrs.

2. Dimension L is measured in gauge plane.

3. Tolerance 0.10mm unless otherwise specified.

4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.

5. Die pad exposure size is according to lead frame design.

6. Followed from JEDEC MS-012

Symbols

| L1–L1' |

Dimensions in millimeters

RECOMMENDED LAND PATTERN

Min.

1.40

0.00

1.40

0.31

0.17

4.80

3.20

3.10

5.80

—

3.80

2.21

0.40

—

UNIT: mm

Nom.

1.55

0.05

1.50

0.406

—

4.96

3.40

3.30

6.00

1.27

3.90

2.41

0.40 REF

0.95

—

0.04

1.04 REF

Max.

1.70

0.10

1.60

0.51

0.25

5.00

3.60

3.50

6.20

—

4.00

2.61

1.27

0.10

0.12

Dimensions in inches

E1 E

E3E2

Note 5

L1'

Gauge plane

0.2500 C

7 (4x)

3.70

2.20

2.87

2.71

5.74

1.27 0.80

0.635

eA1

A2 A

Symbols

| L1–L1' |

Min.

0.055

0.000

0.055

0.012

0.007

0.189

0.126

0.122

0.228

—

0.150

0.087

0.016

—

Nom.

0.061

0.002

0.059

0.016

—

0.195

0.134

0.130

0.236

0.050

0.153

0.095

0.016 REF

0.037

—

0.002

0.041 REF

Max.

0.067

0.004

0.063

0.020

0.010

0.197

0.142

0.138

0.244

—

0.157

0.103

0.050

0.004

0.005

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 16 of 17

Tape and Reel Dimensions, EPAD SO-8

Carrier Tape

Reel

Tape Size

12mm

Reel Size

ø330

ø330.00

±0.50

Package

SO-8

(12mm)

6.40

±0.10

5.20

±0.10

2.10

±0.10

1.60

±0.10

1.50

±0.10

12.00

±0.10

1.75

±0.10

5.50

±0.10

8.00

±0.10

4.00

±0.10

2.00

±0.10

0.25

±0.10

ø97.00

±0.10

UNIT: mm

Trailer Tape

300mm min. or

75 empty pockets

Components Tape

Orientation in Pocket

Leader Tape

500mm min. or

125 empty pockets

Feeding Direction

13.00

±0.30

17.40

±1.00

ø13.00

+0.50/-0.20

10.60

2.00

±0.50

—

Leader/Trailer and Orientation

UNIT: mm

AOZ1022

Rev. 1.6 December 2010 www.aosmd.com Page 17 of 17

Part Marking

Z1022

FAY

Part Number Code

Assembly Lot Code

Year & Week Code

WLT

Fab & Assembly Location

Z1022DI

FAYWLT

Part Number Code

Assembly Lot Code

Fab & Assembly Location

Year & Week Code

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body or (b) support or sustain life, and (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of

the user.

2. A critical component in any component of a life

support, device, or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

This data sheet contains preliminary data; supplementary data may be published at a later date.

Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.

LIFE SUPPORT POLICY

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL

COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.