Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter FEATURES 10-bit resolution 2.7 to 5.25 V operation Sampling rate up to 20 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 MHz full-scale input at fo = 20 MHz) In range (IR) CMOS output CMOS/TTL compatible digital inputs and outputs e External reference voltage regulator Power dissipation only 53 mW (typical) Low analog input capacitance, no buffer amplifier required e Standby mode No sampie-and-hoid circuit required. QUICK REFERENCE DATA TDA8766 APPLICATIONS High-speed analog-to-digital conversion for: e Video data digitizing Camera * Camcorder Radio communication. GENERAL DESCRIPTION The TDA8766 is a 10-bit high-speed analog-to-digital converter (ADC) for professional video and other applications. It converts with 2.7 to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows reduction of the device power consumption down to 4 mW. SYMBOL PARAMETER CONDITIONS MIN. TYP. | MAX. | UNIT Vopa analog supply voltage 2.7 3.3 5.25 Vv Voop1 digital supply voltage 1 2.7 3.3 5.25 V Vopp2 digital supply voltage 2 2.7 3.3 5.25 Vv Vppo output stages supply voltage 2.5 3.3 .25 Vv lppa analog supply current - 7.5 10 mA Ippp digital supply current - 7.5 10 mA Ippo output stages supply current =| fo, = 20 MHz; C, = 20 pF; - 1 2 mA ramp input INL integral non-linearity fox = 20 MHz; ramp input - +1 +2 LSB DNL differential non-linearity fol = 20 MHz; ramp input - 40.25 | 40.7 LSB foik(max) maximum clock frequency 20 - - MHz Prot total power dissipation Vopa = Vopp = Vpopo =3.38 Vf = 53 73 mw ORDERING INFORMATION TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION TDA8766G LQFP32 plastic low profile quad flat package; 32 leads; body 5x 5 x 1.4mm SOT401-1 1996 Mar 20 WH 7110826 0101333 455Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter BLOCK DIAGRAM | VDDA CLK | voooe OE | 5 |'8 16 CLOCK DRIVER Le stppy TDA8766 Vat] 15 y y _ifDs . > MSB 31| 08 30} D7 FLAD 29] DG V 28] DS analog i] 14 ANALOG -TO - DIGITAL |_| , GMOS voltage input > CONVERTER 7 > LATCHES ~* ouTPUTS 2? D4 > data outputs y 26] D3 RM | 11 25| 02 23] D1 p22} 00_ J LSB 4 20 Vep| 10 4Vpopo CMOS 2] IR IN RANGE LATCH > ourpuT > curput 4 r Yppp1 9 19 24 3 [Vesa J Ysse Jvsso Jyssot MLG853 analog digital output digital ground ground 2 ground ground 1 Fig.1 Block diagram. 1996 Mar 20 MB 7110626 01013354 751Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V TDA8766 analog-to-digital converter PINNING SYMBOL | PIN DESCRIPTION SYMBOL | PIN DESCRIPTION D9 1 | data output; bit 9 (MSB) Vopp2 18 | digital supply voltage 2 (2.7 to 5.25 V) IR 2 | in range data output Vsspe 19 | digital ground 2 Vssp1 3 | digital ground 1 Vopo 20 | positive supply voltage for output Vppp1 4 | digital supply voltage 1 (2.7 to 5.25 V) stage (2.5 to 5.25 V) CLK 5 | clock input Vsso 21 | digital output ground STDBY | 6 |standby mode input DO 22 | data output; bit 0 (LSB) Vppa 7 | analog supply voltage (2.7 to 5.25 V) D1 23 | data output; bit 1 n.c. 8 |not connected n.c. 24 | not connected Vep 10 | reference voltage BOTTOM input D3 26 | data output; bit 3 Vam 11 |reference voltage MIDDLE D4 27 | data output; bit 4 n.c. 12 | not connected DS 28 | data output; bit S n.c. 13 | not connected D6 29 | data output; bit 6 Vy 14 | analog input voltage Db? 30_| data output; bit 7 Vat 15 | reference voltage TOP input D8 31 | data output; bit 8 OE 16 | output enable input nc. 32 | not connected n.c. 17 | not connected Sew m- 8 HW t+ MO A ec ie) a a ao a a Oo oe \ sills] [a] fs) 151 fs) fe] / DS [1] [24] nc. IR [2] [23] D4 Vsspi [3] [22] Do Vppp1 (4 21| Vsso Ly TDA8766 a ck [5 | [20] Vopo soy [6 | 19] Yssp2 Vppa [7] 118] Yoppe n.c. [3] 7] Ac. HERPES a Gezeer ee Fig.2 Pin configuration. 1996 Mar 20 4 @ 7110826 0101335 bed =Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V . TDA8766 analog-to-digital converter LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VopA analog supply voltage note 1 -0.3 +7.0 Vv Vopp1, Vppp2 digital supply voltages note 1 -0.3 +7.0 Vv Vppo output stages supply voltage note 1 -0.3 +7.0 V AVpp supply voltage difference Vppa Vppp -1.0 +4.0 v Vopp - Vppo -1.0 +4.0 Vv Vopa Vopo -1.0 +4.0 Vv Vi input voltage referenced to Vssa -0.3 +7.0 Vv Vetk(p-p) AC input voltage for switching referenced to Vssp - Vppp Vv (peak-to-peak value} lo output current -~ 10 mA Tstg storage temperature -55 +150 C Tamb operating ambient temperature -20 +75 C Tj junction temperature - +150 C Note 1. The supply voltages Vppa, Vppp and Vppo may have any value between -0.3 V and +7.0 V provided that the supply voltage differences AVpp are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT Rihj-a thermal resistance from junction to ambient in free air 90 K/W 1996 Mar 20 5 mm 7110826 0101336 564Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 CHARACTERISTICS Vopa = V7 to Vg = 3.3 V; Vopp = V4 to V3 = Vig to Vig = 3.3 V; Vpopo = Va to Voi = 3.3 V; Vssa, Vssp and Vsso short-circuited together; Vigp.p) = 1.83 V; CL = 20 pF; Tamp = 0 to +70 C; typical values measured at Tamp = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply Vppa analog supply voltage 2.7 3.3 5.25 Vv Vppp1 digital supply voltage 1 2.7 3.3 5.25 Vv Vpppbe digital supply voltage 2 2.7 3.3 5.25 Vv Vopo output stages supply voltage 2.5 3.3 5.25 Vv AVpp voltage difference Vopa - Vppp -0.2 - +0.2 Vv Vopa - Vppo 0.2 - +3.0 Vv Vppp - Vpopo 0.2 - +3.0 V IppaA analog supply current - 7.5 10 mA lppp digital supply current - 7.5 10 mA Ippo output stages supply current fo = 20 MHz; - 1 2 mA ramp input; C_ = 20 pF Inputs CLOCK INPUT CLK (REFERENCED TO Vggp); see note 1 ViL LOW level input voltage 0 - 0.3Vppp Vv Vin HIGH level input voltage 0.7Vppp - Vopp Vv Vppp $ 3.6 V 0.6Vppp - Vppp v hie LOW level input current Var =0.3Vppp -1 0 +1 pA he HIGH level input current Vow =0.7Vppp ~ - 5 pA Z, input impedance fei = 20 MHz - 4 - kQ C; input capacitance foi = 20 MHz ~ 3 - pF INPUTS OE AND STDBY (REFERENCED TO Vggp); see Table 3 Vit LOW level input voltage 0 - 0.3Vppp Vv Vin HIGH level input voltage 0.7Vppp - Vppp V Vopp $ 3.6 V 0.6Vppp - Vppp Vv liv LOW level input current Vit = 0.3Vppp -1 - - HA liq HIGH level input current Vin = 0.7Vppp - - +1 pA V, (ANALOG INPUT VOLTAGE REFERENCED TO Vgga) hie LOW level input current Vi = Ves - 0 - HA hy HIGH level input current Vi = Vet - 35 - HA Zz input impedance f,= 1 MHz - 5 - kQ C; input capacitance fj = 1 MHz - 8 - pF 1996 Mar 20 6 We 7110826 0101337 4TOPhilips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V TDA8766 analog-to-digital converter SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder; see Table 1 Vap reference voltage BOTTOM 1.1 1.2 - Vv Vat reference voltage TOP Vrop S$ Vopa 2.7 3.3 VppaA Vv Vaitt differential reference voltage 1.5 2.1 2.7 Vv Vat Vrs lret reference current - 7.2 - mA Reap resistor ladder - 290 - Q TCrtap temperature coefficient of the resistor - 1860 |- ppm ladder - 539 | - ma/K VosB offset voltage BOTTOM note 2 - 135 - mV VosT offset voltage TOP note 2 - 135 - mV Vigp-p) analog input voltage note 3 1.4 1.83 [2.4 V (peak-to-peak value) Outputs DIGITAL OUTPUTS D9 TO DO AND IR (REFERENCED TO Vggp) VoL LOW level output voltage lo=1mA 0 - 0.5 Vv Vou HIGH level output voltage lo =-1 mA Vppo 0.5 | - Vppo Vv loz output current in 3-state mode 0.5 V < Vo < Vppo -20 - +20 HA Switching characteristics CLOCK INPUT CLK; see Fig.4; note 1 fom maximum clock frequency 20 - - MHz topy clock pulse width HIGH 15 - - ns top clock pulse width LOW 15 - - ns Analog signal processing LINEARITY INL integral non-linearity fotk = 20 MHz; - +1 +2 LSB ramp input; (see Fig.6) DNL differential non-linearity fo = 20 MHz; - +0.25 |+0.7 LSB ramp input; (see Fig.7) INPUT SET RESPONSE (foi, = 20 MHz; see Fig.8; note 4) tsTLH analog input settling time full-scale square wave | - 4 6 ns LOW-to-HIGH tsTHL analog input settling time full-scale square wave |- 4 6 ns HIGH-to-LOW HARMONICS; (fo, = 20 MHZ; see Fig.9; note 5} THD _| total harmonic distortion | f= 1 MHz - |-63 |~ dB SIGNAL-TO-NOISE RATIO; see Fig.9; note 5 S/N signal-to-noise ratio (full scale) without harmonics; - 60 - dB tok = 20 MHz; f, = 1 MHz 1996 Mar 20 7 M3 71108eb 0101338 337Phil ips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V - TDA8766 analog-to-digital converter SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT EFFECTIVE BITS; see Fig.9; note 5 EB effective bits fo = 20 MHz f, = 300 kHz - 9.5 - bits fi= 1 MHz - 9.3 - bits f, = 3.58 MHz - 8.0 - bits Timing (fo, = 20 MHz; C, = 20 pF); see Fig.4; note 6 tas sampling delay time - - 5 ns th output hold time 5 - - ns ta output delay time Vopo = 4.75 V 8 12 15 ns Vppo =3.15V 8 17 20 ns Vppo = 2.7 V 8 21 24 ns 3-state output delay times; see Fig.5 tgzH enable HIGH - 14 18 ns taze enable LOW - 16 20 ns taHz disable HIGH ~ 16 20 ns taLz disable LOW - 14 18 ns Standby mode output delay times tdsTBLH standby (LOW-to-HIGH transition) - - 200 ns tasTBHL start-up (HIGH-to-LOW transition) - - 500 ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. Analog input voltages producing code 0 up te and including 1023: a) Vosp (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (Vas) at Tamb = 25 C. b) Vost (voltage offset TOP) is the difference between Vpr (reference voltage TOP) and the analog input which produces data outputs equal to 1023 at Tamp = 25 C. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins Vrg and Vprz via offset resistors Rog and Ror as shown in Fig.3. Vat ~ Vip a) The current flowing into the resistor ladder is IL = RoR GRD OB L OT and the full-scale input range at the converter, Ri to cover code 0 to code 1023, is V, = R, xl. = s5- 5 Rog t+ RL +R op TOL "oT X (Var - Vag) = 0.871 X (Va - Vag) b) Since R_, Rog and Rot have similar behaviour with respect to process and temperature variation, the ratio R -__+ ___. will be kept reasonably constant from part to part. Consequently variation of the output codes Rog t+ FR, + Ror at a given input voltage depends mainly on the difference Var Vag andits variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 1996 Mar 20 8 me 71108 2b 0101339 273Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. 6. Output data acquisition: the output data is available after the maximum delay time of ty. code 0 MGD281 Fig.3 Explanation of note 3. 1996 Mar 20 9 MM 71108626 0101340 195Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V . TDA8766 analog-to-digital converter Table 1 Output coding and input voltage (typical values; referenced to Vssa) Vv BINARY OUTPUT BITS STEP KP) IR (Vv) D9 | ps | p7 | be | D5 | D4 | D3 | D2 | D1 | DO Underflow | <1.335 0 0 0 0 0 0 0 0 0 0 0 0 1.335 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1022 . 1 1 1 1 1 1 1 1 1 1 0 1023 3.165 1 1 1 1 1 1 1 1 1 1 1 Overflow >3.165 0 1 1 1 1 1 1 1 1 1 1 Table 2 Mode selection OE D9 TO DO IR 1 high impedance high impedance 0 active; binary active Table 3 Standby selection STDBY D3 TO DO Ippa + Ippp {typ-) 1 last logic state 1.2mA 0 active 15mA TopL p+ > OPH CLK \ \ f C 50% sample N sampleN+1 | sample N+2 Fig.4 Timing diagram. 1996 Mar 20 10 M@ 7110826 0101341 421Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V TDA8766 analog-to-digital converter output data output data TEST $1 Vv DDD | taz Yppp 3.3kQ ; v TDA8766 St dZL DDD 20 pF "dHZ GND T 4 ta7H GND OE MLG855 fOE = 100 kHz. Fig.5 Timing diagram and test conditions of 3-state output delay time. 1996 Mar 20 11 MH 7110826 0101342 666Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 MLDITS 0.6 (LSB) 04 0.2 0 200 400 600 800 1000 ; 1100 f (codes) 1023 Fig.6 Typical integral non-linearity (INL) performance. MLD116 0.25 a | | Buia uN | 0.15 0.05 -0.15 : | ~0.25 ~| -L 0 200 400 600 800 1000 | 1100 f (codes) 1023 Fig.7 Typical differential non-linearity (DNL) performance. 1996 Mar 20 12 mm 71104ceb 0301343 774Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V gh-sp TDA8766 analog-to-digital converter tSTLH 'STHL code 1023 Vi 50% 50% code 0 5ns 5 nsle CLK 50% 50% MBD875 2ns " jae- 2 1S, Fig.8 Analog input settling-time diagram. MLBTI7 (dB) -20 -60 -80 -100 -120 0 1.25 25 3.76 5.01 6.26 7.51 Effective bits: 9.59; THD = -76.60 dB. Harmonic levels (dB): 2nd = -81.85; 3rd = -87.56; 4th = -88.81; 5th = -88.96; 6th = -79.58. Fig.9 Typical Fast Fourier Transform (fon, = 20 MHz; fj = 1 MHz). 8.76 10 { (MHz) 1996 Mar 20 13 MB 7110826 0101344 30Phitips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V TDA8766 analog-to-digital converter INTERNAL PIN CONFIGURATIONS V ppo VDDA a {~ << x D9 to DO 4 Fi Vv _ x Vsso Vesa c-7- MLC8SE MLC857 Fig.10 CMOS data and in Range (IR) outputs. Fig.11 Analog inputs. Vv DDO Vopa 4 a a VAT oe Vem t Rap (STDBY) VaB 7 x j Vsso Vssa MLC8&58 Fig.12 OE (STDBY) input. MLO8&S59 Fig.13 Vas, Vam and Vr. 1996 Mar 20 MH 7110826 0101345 577 14Philips Semiconductors 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter Product specification TDA8766 VpppD + A CLK + VeVppp Vssp __{~ +--+} a MLC85C Fig.14 CLK input. 1996 Mar 20 15 Mi 7110826 0101346 403Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 APPLICATION INFORMATION Additional application information will be supplied upon request (please quote number AN96072). Tye Jo | o7 lo los | ba los | be 32 31 30 2 28 27 26 28 Dg nc) : Si 24 | _R in|, 93 LD! Vv sso1 |, op [2 v Vv ppp1 |, 1 LYsso TDA8&766 Vv CuK] 99 LLppo Vv sTopy | . 19 [8802 V Vv DBAT 7 4@ LxDDo2 (2) 2) yes ls 47 Las: 9 a Vag"! a) he Pale Muce61 3. 100 ) 100 nF VSSA Vgsa 100 ro Vssa The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived trom a weil regulated Vpp, supply through a resistor bridge and a decoupled capacitor. (1) Vas, Vam and Vaz are decoupled to Vgsa. (2) Pins 8, 12, 13, 17,24 and 32 should be connected to the closest ground pin in order to prevent noise influence. (3) When Vey is not used, pin 11 can be left open, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded. (4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to V, input (pin 14). Fig.15 Application diagram. 1996 Mar 20 Me 7310826 0101347 JYT 16Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V TDA8766 analog-to-digital converter PACKAGE OUTLINE LQFP32: plastic low profile quad flat package; 32 leads; body 5x 5x 1.4mm SOT401-1 iT rs =} Lp a | 0 25 5mm scale DIMENSIONS (mm are the orlginal dimensions) A UNIT | ax.| At | Az | As | bp | | DMEM) 6 | Hp | He} L | tp | @ | v | wy oy f2pl ze) 0.15] 15 0.27 | 0.18) 5.1 | 51 7.15 | 7.15 0.75 | 0.70 035 | 095] 7 mm 11-60) 05} 13 | loizioi] 49] 49 | 9 | 6851 685! ' | o4s|o57| 92 112 | 1 |ossloss| o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC ElAJ PROJECTION ISSUE DATE SOT401-1 E36 95-12-19 1996 Mar 20 17 me 71L108eb 0101348 cobPhilips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 SOLDERING Introduction There is no soldering method that is ideal for all 1C packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our iC Package Databook (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all LOFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Mar 20 mm 7110826 0101344 lic = 18 lf wave soldering cannot be avoided, the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The footprint must be at an angle cf 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.