FUJITSU MICROELECTRONICS DATA SHEET DS07-12555-3E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89560A Series MB89567A/567AC/P568/PV560 DESCRIPTION The MB89560A series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as I2C interface, timers, 2 ch 8-bit PWM timers, 8/16-bit timer, 21-bit timebase timer, 8-bit PWC timer, 17-bit Watch prescaler, Watch-dog timer, High speed UART, 8-bit SIO, UART/SIO, LCD controller/driver (optional booster), Two type Programmable Pulse Generators (PPG), an A/D converter, and external interrupt. * : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. FEATURES * F2MC-8L family CPU core * Instruction set optimized for controllers: - Multiplication and division instructions - 16-bit arithmetic operations - Test and branch instructions - Bit manipulation instructions, etc. * Low-voltage operation (when an A/D converter is not used) * Low current consumption (applicable to the dual-clock system) * Minimum execution time: 0.32 s at 12.5 MHz /3.5 V to 5.5 V * Two type of Programmable Pulse Generator (PPG): 6-bit PPG and 12-bit PPG * I2C interface circuit *Three types of Serial Interface: - 8-bit Serial I/O (SIO) - UART/SIO - High Speed UART (Transfer rate from 300 bps to 192000 bps /10 MHz main clock) (Continued) For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ Copyright(c)2002-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.5 MB89560A Series (Continued) * I/O ports: Max 50 channels * 21-bit time-base timer * 8-bit PWM 2 channels timers * 8/16-bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel) * 8-bit PWC timer operation * Watchdog timer * 17-bit Watch prescaler * 10-bit A/D converter: 8 channels * External interrupt 1: 8 channels * External interrupt 2 (wake-up function): 4 channels * LCD controller/driver: 24 segments x 4 commons (Max 96 pixels, duty LCD mode and Static LCD mode) * LCD booster function (option) * Wild register (Max 6 different address locations) * Low-power consumption modes (stop mode, sleep mode, watch mode, and sub clock mode) * LQFP-80 and QFP-80 package * CMOS technology 2 DS07-12555-3E MB89560A Series PRODUCT LINEUP Part number MB89567A MB89567AC MB89P568 MB89PV560 Mass production products (mask ROM products) OTP Piggy-back 32 K x 8-bit (internal mask ROM) 48 K x 8-bit (internal PROM) 56 K x 8-bit (external ROM) Parameter Classification ROM size RAM size 1 K x 8-bit 1 K x 8-bit CPU functions Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time : 136 : 8-bit : 1 to 3 bytes : 1-, 8-, 16-bit : 0.32 s/12.5 MHz : 2.88 s/12.5 MHz Ports General-purpose I/O ports (N-channel open drain): 20 pins (2 shared with I2C inputs, 16 shared with LCD, 2 shared with other resources) General-purpose I/O ports (CMOS) : 30 pins (shared with resources) Total : 50 pins Watchdog timer Reset generate cycle: Min 221/FCH*7 for main clock, Min 214/FCL*7 for sub clock 21-bit time-base timer 21-bit Interrupt cycle: (213, 215, 218 or 222)/FCH*7 8-bit PWM 2 ch timer 8-bit interval timer operation (square wave output capable, operating clock cycle: 1 tinst, 8 tinst, 16 tinst, 64 tinst) 8-bit resolution PWM operation (conversion cycle: 128 x 1 tinst to 256 x 64 tinst) 8/16-bit timer/counter output for counter clock selectability 10-bit A/D converter *2 10-bit resolution x 8 channels A/D conversion function (conversion time: 60 tinst) Continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable. External interrupt 1 (wake-up function) 8 independent channels (interrupt vector, request flag, request output enable) Edge selectability (rising/falling) Used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) External interrupt 2 (wake-up function) 4 channels ("L" level interrupts, independent input enable). Used also for wake-up from stop/sleep mode. (Low-level detection is also permitted in stop mode.) PWC timer 8-bit timer operation (count clock cycle: 1 tinst, 4 tinst, 32 tinst) 8-bit reload timer operation (toggle output possible, operating clock cycle: 1 to 32 tinst) 8-bit pulse width measurement (continuous measurement possible: H-width, L-width, rising edge to rising edge, falling edge to falling edge, and rising edge to falling edge) 8/16-bit timer/ counter Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable (Continued) DS07-12555-3E 3 MB89560A Series (Continued) Part number MB89567A MB89567AC MB89P568 MB89PV560 Parameter Watch prescaler 17-bit Interrupt cycle: 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s/32.768 kHz for subclock 6-bit PPG Internal 6-bit counter Pulse width and cycle are program selectable 12-bit PPG Internal 12-bit counter Pulse width and cycle are program selectable Not Available I2C interface*4 1 channel 8-bit serial I/O 8-bit, LSB first/MSB first selectability Transfer clocks (one external shift clock, three internal shift clocks: 2 tinst, 8 tinst, 32 tinst) *5 UART/SIO Transfer data length: 7-, 8-bit for UART, 8-bit for SIO Transfer rate (1201 bps to 78125 bps / 10 MHz main clock) support sub-clock mode Transfer data length: 4-, 6-, 7-, 8-bit High speed UART Transfer rate (300 bps to 192000 bps /9.216 MHz main clock) support sub-clock mode LCD Common output: 4 (Max) Segment output: 24 (Max) LCD driving power (bias) pins: 4 LCD display RAM size: 12 bytes (24 x 4 bits, Max 96 pixels) Duty LCD mode and Static LCD mode Booster for LCD driving: option*1 Dividing resistor for LCD driving: option Wild register Maximum of 6-byte data can be assigned in 6 different address. Used to replace any data in the ROM when specific address and data are assigned in Wild register. Wild register can be set up by using different communication methods through the device. Standby mode Sub clock mode, sleep mode, stop mode and watch mode Process Operating voltage * CMOS 6 2.2 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V*3 *1 : When booster is used, the bias is reduced by 1/3. It can be selected by mask option. *2 : Voltage varies with product. *3 : When external ROM is used, EPROM: MBM27C512-20 should be used, the operating voltage: 4.5 V to 5.5 V. *4 : I2C is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips I2C specification. *5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock if main clock mode is selected, or 1/2 of the subclock if subclock mode is selected. *6 : Varies with conditions such as the operating frequency. (See " ELECTRICAL CHARACTERISTICS".) *7 : FCH : main clock source oscillation, FCL : sub clock source oscillation 4 DS07-12555-3E MB89560A Series PACKAGE AND CORRESPONDING PRODUCTS Package MB89567A MB89567AC MB89P568-101 MB89P568-102 MB89PV560-101 MB89PV560-102 FPT-80P-M21 FPT-80P-M06 FPT-80P-M22 MQP-80C-P01 : Supported : Not supported Note : For more information, see " PACKAGE DIMENSIONS". DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that will actually be used. Take particular care on the following points: * The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption * For the MB89PV560, add the current consumed by the EPROM mounted in the piggy-back socket. * When operating at low speed, the current consumed by the one-time PROM product is greater than that for the mask ROM product. However, the current consumption is roughly the same in sleep or stop mode. * For more information, see " ELECTRICAL CHARACTERISTICS". 3. Mask Options The functions available as options and the method of specifying options differ between products. Before using options check " MASK OPTIONS". 4. Wild register function The Wild Register can be used in the following address spaces. Device MB89PV560 4000H to FFFFH MB89P568 4000H to FFFFH MB89567A/567AC 8000H to FFFFH Address Space 5. P40, P41 It will take about 64 count clock of external oscillation to initialize P40 and P41 pins in MB89PV560/P568. Therefore, these ports will be unstable for a while during power-on. For MB89567A/567AC, these ports will be in High-Z during power-on. DS07-12555-3E 5 MB89560A Series PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0*2 C1*2 P47/PWC P46/UI/SI1 P45/UO/SO1 (Top view) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P44/UCK/SCK1 P43/PWM2/PPG2 P42/PWM1/EC1 P41/HCK*1/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 RST X0A 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc (FPT-80P-M21) (FPT-80P-M22) *1: Main clock oscillation divided by two output *2: For built-in LCD booster only Note: For mask option of *2, please refer to " MASK OPTIONS". (Continued) 6 DS07-12555-3E MB89560A Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0*2 C1*2 P47/PWC (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P46/UI/SI1 P45/UO/SO1 P44/UCK/SCK1 P43/PWM2/PPG2 P42/PWM1/EC1 P41/HCK*1/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A X0A RST P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG05 SEG06 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc P07/AN7 P06/AN6 (FPT-80P-M06) *1: Main clock divided by two output *2: For built-in LCD booster only Note: For mask option of *2, please refer to " MASK OPTIONS". (Continued) DS07-12555-3E 7 MB89560A Series (Continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0*2 C1*2 P47/PWC (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 100 99 98 97 96 95 94 *3 101 102 103 104 105 106 107 108 109 110 111 112 81 82 83 84 93 92 91 90 89 88 87 86 85 P46/UI/SI1 P45/UO/SO1 P44/UCK/SCK1 P43/PWM2/PPG2 P42/PWM1/EC1 P41/HCK*1/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A X0A RST P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG05 SEG06 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc P07/AN7 P06/AN6 (MQP-80C-P01) *1: Main clock divided by two output *2: For built-in LCD booster only *3: Pin assignment on package top (MB89PV560 only) Pin no. Pin Pin no. Pin Pin no. Pin 81 N.C. 89 AD2 97 N.C. Pin no. 105 Pin OE 82 A15 90 AD1 98 04 106 N.C. 83 A12 91 AD0 99 O5 107 A11 84 AD7 92 N.C. 100 O6 108 A9 85 AD6 93 O1 101 07 109 A8 86 AD5 94 O2 102 O8 110 A13 87 AD4 95 O3 103 CE 111 A14 88 AD3 96 VSS 104 A10 112 VCC N.C.: Internally connected. Do not use. Note: For mask option of *2, please refer to " MASK OPTIONS". 8 DS07-12555-3E MB89560A Series PIN DESCRIPTION Pin no. LQFP*1 LQFP*2 MQFP*3 QFP*4 Pin name 43 45 X0 44 46 X1 42 44 MODA 39 41 RST 49 to 52 51 to 54 P24/INT20 to P27/INT23 38, 36 to 30 40, 38 to 32 P10/INT10 to P17/INT17 I/O circuit type Function A Crystal or other resonator connector pins for the main clock. The external clock can be connected to X0. When this is done, be sure to leave X1 open. C Memory access mode setting pins. Connect directly to VSS. Hysteresis input type. D Reset I/O pin This pin is a CMOS output type with a pull-up resistor, and a hysteresis input type. "L" is output from this pin by an internal reset request (optional). The internal circuit is initialized by the input of "L". E General-purpose CMOS I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. Selectable pull-up resistor. E General-purpose CMOS I/O ports Also serve as input for external interrupt 1 input. External interrupt 1 input is hysteresis input. Selectable pull-up resistor. 60 62 P44/UCK/ SCK1 E General-purpose CMOS I/O ports Also serve as the clock I/O for the High-speed UART and Serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. 61 63 P45/UO/ SO1 F General-purpose CMOS I/O ports Also serves as the data output for the High-speed UART and Serial I/O. 62 64 P46/UI/SI1 G N-ch open drain general-purpose I/O ports Also serves as the data input for the High-speed UART and Serial I/O. The peripheral is a hysteresis input type. 63 65 P47/PWC G N-ch open drain general-purpose I/O port Also serve as the external clock input for PWC. The peripheral is a hysteresis input. 56 58 P40/WTO/ TO11 F General-purpose CMOS I/O port Also serves as an 8/16-bit timer/counter output and PWC output. (Continued) DS07-12555-3E 9 MB89560A Series Pin no. LQFP*1 LQFP*2 57 MQFP*3 QFP*4 59 Pin name P41/HCK/ TO12 I/O circuit type Function F General-purpose CMOS I/O port Also serves as an 8/16-bit timer/counter output. and half of main clock output Selectable pull-up resistor. 45 47 P20/SI E General-purpose CMOS I/O port Also serves as the data input for the serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. 46 48 P21/SO F General-purpose CMOS I/O port Also serves as the data output for the serial I/O. Selectable pull-up resistor. 47 49 P22/SCK E General-purpose CMOS I/O port Also serves as the clock I/O for the serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. 48 50 P23/PPG1 F General-purpose CMOS I/O port Also serves as the 6 bit PPG output pin. Selectable pull-up resistor. 54 56 P30/SCL G N-ch open-drain general-purpose I/O port Clock I/O pin for I2C interface 55 57 P31/SDA G N-ch open-drain general-purpose I/O port Data I/O pin for I2C interface 65 67 C0 64 66 C1 -- Function as capacitor connection pin in the products with a booster. 61 P43/ PWM2/ PPG2 F General-purpose CMOS I/O port Also serves PWM wave output for the 8-bit PWM timer 1 and as 12 bit programmable pulse generator output. Selectable pull-up resistor. 58 60 P42/ PWM1/ EC1 E General-purpose CMOS I/O port Also serves as the PWM wave output and external clock for the 8/16 bit timer counter. Selectable pull-up resistor. 28 to 21 30 to 23 P00/AN0 to P07/AN7 J General-purpose CMOS I/O ports Also serve as the analog input for the A/D converter. Selectable pull-up resistor. 59 (Continued) 10 DS07-12555-3E MB89560A Series (Continued) Pin no. Pin name I/O circuit type 12 to 14, 16 to 20 P60/ SEG16 to P67/ SEG23 H N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. 2 to 9 4 to 11 P50/SEG8 to P57/ SEG15 H N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. 74 to 80, 1 76 to 80, 1 to 3 SEG0 to SEG7 I LCD controller/driver segment output-only pins 70 to 73 72 to 75 COM0 to COM3 I LCD controller/driver common output-only pins 66 to 69 68 to 71 V0 to V3 -- LCD driving power supply pins. 40 42 X0A 41 43 X1A B Crystal or other resonator connector pins for the subclock (Subclock: 32.768 kHz) 53 55 Vcc -- Power supply pin 37 39 C -- Capacitor connection pin *5 13 15 Vss -- Power supply (GND) pin 20 22 AVcc -- A/D converter power supply pin 19 21 AVR -- A/D converter reference voltage input pin 29 31 AVss -- A/D converter power supply pin Use this pin at the same voltage as VSS. LQFP*1 LQFP*2 MQFP*3 QFP*4 10 to 12, 14 to 18 Function *1: FPT-80P-M21 *2: FPT-80P-M22 *3: MQP-80C-P01 *4: FPT-80P-M06 *5: When MB89567A / MB89567AC / MB89PV560-101 / MB89PV560-102 is used, this pin will become NC pin without internal connection. There is no problem to leave pins open, to fix pins at VCC and to fix pins at VSS. When MB89P568-101 or MB89P568-102 is used, this pin must be connected to VSS. DS07-12555-3E 11 MB89560A Series * For External EPROM Socket (MB89PV560 ONLY) Pin no. Pin name I/O 12 Function 82 83 84 85 86 87 88 89 90 91 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 93 94 95 O1 O2 O3 I Data input pins 96 Vss O Power supply (GND) pin 98 99 100 101 102 O4 O5 O6 O7 O8 I Data input pins 103 CE O ROM chip enable pin Outputs "H" during standby. 104 A10 O Address output pin 105 OE/Vpp O ROM output enable pin Outputs "L" at all times. 107 108 109 A11 A9 A8 O 110 A13 O 111 A14 O 112 Vcc O EPROM power supply pin 81 92 97 106 N.C. -- Internally connected pins Be sure to leave them open. Address output pins DS07-12555-3E MB89560A Series I/O CIRCUIT TYPE Type A Circuit Remarks Main clock (main clock crystal oscillator) * At an oscillation feedback resistor of approximately 1 M/5.0 V X1 N-ch P-ch P-ch X0 N-ch Main clock control signal B Subclock (subclock crystal oscillator) * At an oscillation feedback resistor of approximately 4.5 M/5.0 V X1A N-ch P-ch X0A N-ch Sub clock control signal C * Hysteresis input D * CMOS output * Hysteresis input * At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V R P-ch N-ch E R Pull-up control register P-ch P-ch * CMOS output * CMOS input * The peripheral is a hysteresis input type. * Selectable pull-up resistor (P-ch) of approximately 50 k/5.0 V N-ch Port Peripheral (Continued) DS07-12555-3E 13 MB89560A Series (Continued) Type Circuit Remarks F R Pull-up resistor control register P-ch P-ch * CMOS output * CMOS input * Selectable pull-up resistor (P-ch) of approximately 50 k/5.0 V N-ch Port G N-ch Port * N-ch open-drain input/output * CMOS input * The peripheral is a hysteresis input type. (P30,P31 are OR-type input for I2C) Peripheral H * N-ch open-drain output * CMOS input * LCD controller/driver segment output P-ch N-ch P-ch N-ch N-ch Port I * LCD controller/driver common/ segment output P-ch N-ch P-ch N-ch J R Pull-up control register P-ch P-ch * General CMOS I/O * Analog input (A/D converter) * Selectable pull-up resistor (P-ch) of approximately 50 k/5.0 V * Pull-up resistors must be disabled when used as an analog input. N-ch ADEN Port Analog input 14 DS07-12555-3E MB89560A Series HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in " ELECTRICAL CHARACTERISTICS" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DVCC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode. 7. Unused LCD dedicated pins When LCD dedicated pins are not in use, keep it open. 8. Ports shared with SEG pin When using port shared with SEG pin, be sure that the input voltage to port does not exceed the voltage of V3 (SEG driving voltage). This is particularly important to those devices with booster. When power-on or reset, SEG pin will output an initial value of "L". 9. LCD not in use When LCD is not in use, connect the V3 pin to Vcc and keep other LCD dedicated pins open. 10. Wild Register function In MB89PV560, wild register function cannot be evaluated. To evaluate the wild register function, use MB89P568. 11. Programming operation on RAM Program operation debugging at RAM is not possible even when using MB89PV560. 12. Note to Noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) . DS07-12555-3E 15 MB89560A Series PROGRAMMING TO THE EPROM ON THE MB89P568 The MB89P568 is an OTPROM version of the MB89567A and MB89567AC. 1. Features * 48-Kbyte PROM on chip * Equivalency to the MBM27C1001 in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. Normal operation 0000 H EPROM mode (Corresponding addresses on the EPROM programmer) I/O 0080 H RAM 0480 H Not available 4000 H 4000 H Program area (PROM) FFFF H Program area (PROM) FFFF H 3. Programming to the EPROM In EPROM mode, the MB89P568 functions equivalent to the MBM27C1001. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. * Programming procedure (1) Set the EPROM programmer to the MBM27C1001. (2) Load program data into the EPROM programmer at 4000H to FFFFH (3) Program with the EPROM programmer. 16 DS07-12555-3E MB89560A Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure. Program, verify Program, verify +100 C, 48 h Read Assembly 5. Programming Yield All bits cannot be programmed at FUJITSU MICROELECTRONICS shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. DS07-12555-3E 17 MB89560A Series PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C512-20TV 2. Memory Space Normal operation EPROM mode (Corresponding addresses on the EPROM programmer) 0000 H I/O 0080 H RAM 0480 H Not available 2000 H 2000 H Program area (PROM) FFFF H Program area (PROM) FFFF H 3. Programming to EPROM (1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 2000H to FFFFH. (3) Program to 2000H to FFFFH with the EPROM programmer. 18 DS07-12555-3E MB89560A Series BLOCK DIAGRAM Oscillator N-ch open drain I/O port Low-power oscillator (32.768 kHz) Watch prescaler 8 8 External interrupt 1 CMOS I/O port 6 bit PPG P24/INT20 to P27/INT23 P20/SI P21/SO P22/SCK 4 Port 2 P23/PPG1 4 External interrupt 2 (wake-up function) 12 bit PPG P42/PWM1/EC1 P41/HCK*1/TO12 P43/PWM2/PPG2 Port 4 *4 8-bit timer/counter 1 (Timer 1) Internal data bus P10/INT10 to P17/INT17 Port 1 21-bit Time-base timer P40/WTO/TO11 PWC Reset circuit (Watchdog timer) RST High-speed UART P46/UI/SI1 8-bit PWM timer 1 CMOS I/O port (P46 and P47 are N-ch Open-drain I/O Type) P47/PWC 4 N-ch open-drain output port LCD controller/ driver 8 CMOS I/O port 1K Byte RAM P45/UO/SO1 8-bit PWM timer 2 8 UART/SIO P44/UCK/SCK1 *4 8-bit timer/counter 2 (Timer 2) Port 5 & Port 6 Subclock P31/SDA SIO Clock controller X0A X1A P30/SCL Port 3 I2C*2 Main clock X0 X1 4 4 4 8 Display RAM (12 bytes) 4 4 F2MC-8L CPU 10-bit A/D converter Port 0 8 *1: Output of Main clock oscillation/2. *2: I2C is not available in MB89567A. *3: Selected by mask option *4: Can be used as a 16-bit timer/counter by connecting Timer 1 output to Timer 2 input. *5: C pin becomes NC pin in MB89567A/AC/PV560 *6: 48 K byte ROM for MB89P568 DS07-12555-3E COM0 to COM3 V0 to V3 Option CMOS I/O port 32K*6 Byte ROM Other pins MODA, C,*5 VCC, VSS SEG0 to SEG7 C0*3 C1*3 Booster Wild register P60/SEG16 to P63/SEG19 P64/SEG20 to P67/SEG23 P50/SEG8 to P53/SEG11 P54/SEG12 to P57/SEG15 8 P00/AN0 to P07/AN7 AVCC AVSS AVR 19 MB89560A Series CPU CORE 1. Memory Space The microcontrollers of the MB89560A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/ O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89560A series is structured as illustrated below. Memory space MB89567A, MB89567AC 0000 H MB89P568-101,102 0000 H 0000 H 0080 H 0080 H RAM 0100 H 0100 H 0200 H 0200 H 0480 H 0480 H *2 0492 H Register Register Register 0480 H RAM RAM 0100 H 0200 H I/O I/O I/O 0080 H MB89PV560-101,102 *2 0492 H Access prohibited Access prohibited 0492 H *2 Access prohibited 2000 H 4000 H 8000 H ROM FFC0 H FFFF H External*1 ROM External*1 ROM FFC0 H FFFF H FFC0 H FFFF H Vector table (Reset * Interrupt * Vector call instruction) *1 : MB89P568-101,102 has OTP ROM inside. *2 : Wild register setting registers 20 DS07-12555-3E MB89560A Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC) Accumulator (A) : A 16-bit register for indicating specifies instruction storage positions. : A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer for indicating a memory address Stack pointer (SP) : A 16-bit register for indicating a stack area Program status (PS) : A 16-bit register for storing a register pointer, a condition code 16 bits Initial value : Program counter PC FFFDH : Accumulator Undefined : Temporally accumulator Undefined : Indexing register Undefined : Extra pointer Undefined SP : Stuck pointer Undefined PS : Program status I Flag = 0, IL1, 0 = 11 other bits are undefined. A IX EP The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) * Structure of program status 15 PS 14 13 12 10 9 8 Va- VaVacancy cancy cancy RP RP DS07-12555-3E 11 7 6 H I 5 4 IL1 IL0 3 2 1 0 N Z V C CCR 21 MB89560A Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. * Rule for Conversion of Actual Addresses of the General-purpose Register Area Operation Code lower RP Upper Generated address b0 "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A1 A0 A3 A2 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag : Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag : Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level High-low 0 0 0 1 1 0 2 1 1 3 1 High Low = no interrupt N-flag : Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag : Set when an arithmetic operation results in 0. Cleared otherwise. V-flag : Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag : Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. The following general-purpose registers are provided : General-purpose registers : An 8-bit resister for storing data 22 DS07-12555-3E MB89560A Series The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used. The bank currently in use is indicated by the register bank pointer (RP). * Register Bank Configuration This address = 0100H+8x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 bank (MB89567A/567AC) Memory range DS07-12555-3E 23 MB89560A Series I/O MAP Address Register name Register Description 00H PDR0 Port 0 data register 01H DDR0 Port 0 data direction register 02H PDR1 Port 1 data register 03H DDR1 Port 1 data direction register 04H to 06H Read/Write Initial value R/W XXXXXXXXB W 00000000B R/W XXXXXXXXB W 00000000B (Vacancy) 07H SYCC System clock control register R/W XXXMM100B 08H STBC Standby control register R/W 00010XXXB 09H WDTC Watchdog timer control register W 0XXXXXXXB 0AH TBTC Timebase timer control register R/W 00XXX000B 0BH WPCR Watch prescaler control register R/W 00XX0000B 0CH PDR2 Port 2 data register R/W XXXXXXXXB 0DH DDR2 Port 2 data direction register R/W 00000000B 0EH PDR3 Port 3 data register R/W XXXXXX11B 0FH PDR4 Port 4 data register R/W XXXXXXXXB 10H DDR4 Port 4 direction register R/W XX000000B 11H PDR5 Port 5 data register R/W 00000000B R/W 00000000B 12H 13H (Vacancy) PDR6 Port 6 data register 14H to 19H (Vacancy) 1AH T2CR Timer2 control register R/W X00000X0B 1BH T2DR Timer2 data register R/W XXXXXXXXB 1CH T1CR Timer1 control register R/W X00000X0B 1DH T1DR Timer1 data register R/W XXXXXXXXB UART1 mode control register 1 R/W 00000000B 1EH to 21H (Vacancy) 22H SMC11 23H SRC1 UART1 mode data register R/W XX011000B 24H SSD1 UART1 status/data register R/W 00100X1XB 25H SIDR1/SODR1 UART1 data register R/W XXXXXXXXB 26H SMC12 UART1 mode control register 2 R/W XX100001B 27H CNTR1 PWM control register 1 R/W 00000000B 28H CNTR2 PWM control register 2 R/W 000X0000B 29H CNTR3 PWM control register 3 R/W X000XXXXB 2AH COMR1 PWM compare register 1 W XXXXXXXXB 2BH COMR2 PWM compare register 2 W XXXXXXXXB 2CH PCR1 R/W 000XX000B PWC pulse width control register 1 (Continued) 24 DS07-12555-3E MB89560A Series Address Register name 2DH PCR2 2EH RLBR 2FH Register Description Read/Write Initial value PWC pulse width control register 2 R/W 00000000B PWC reload buffer register R/W XXXXXXXXB SMC21 UART2/SIO mode control register R/W 00000000B 30H SMC22 UART2/SIO mode control register 2 R/W 00000000B 31H SSD2 UART2/SIO status/data register R/W 00001XXXB 32H SIDR2/SODR2 UART2/SIO data register R/W XXXXXXXXB 33H SRC2 UART2/SIO rate control register R/W XXXXXXXXB 34H ADC1 A/D control register 1 R/W X00000X0B 35H ADC2 A/D control register 2 R/W X0000001B 36H ADDL A/D data register L R/W XXXXXXXXB 37H ADDH A/D data register H R/W XXXXXXXXB 38H RCR21 PPG control register 1(PPG2) R/W 00000000B 39H RCR23 PPG control register 3(PPG2) R/W 0X000000B 3AH RCR22 PPG control register 2(PPG2) R/W XX000000B 3BH RCR24 PPG control register 4(PPG2) R/W XX000000B 3CH to 3EH (Vacancy) 3FH EIC1 External interrupt 1 control register 1 R/W 00000000B 40H EIC2 External interrupt 1 control register 2 R/W 00000000B 41H EIC3 External interrupt 1 control register 3 R/W 00000000B 42H EIC4 External interrupt 1 control register 4 R/W 00000000B 43H to 50H (Vacancy) 51H IBSR I2C bus status register R 00000000B 52H IBCR I2C bus control register 53H ICCR R/W 00000000B 2 R/W 000XXXXXB 2 I C clock control register 54H IADR I C address register R/W XXXXXXXXB 55H IDAR I2C data register R/W XXXXXXXXB 56H EIE2 External interrupt 2 enable register R/W XXXX0000B 57H EIF2 External interrupt 2 flag register R/W XXXXXXX0B 58H RCR1 PPG control register 1(PPG1) R/W 00000000B 59H RCR2 PPG control register 2(PPG1) R/W 0X000000B 5AH CKR Clock Output control register R/W 00000000B 5BH LCR1 LCD controller/driver control register 1 R/W 00010000B 5CH LCR2 LCD controller/driver control register 2 R/W 00000000B 5DH LCR3 LCD controller/driver control register 3 R/W XX000000B 5EH LDR1 LCD data register 1 R/W XXXXXXXXB (Continued) DS07-12555-3E 25 MB89560A Series (Continued) Address Register name Register Description 5FH 60H to 6BH Read/Write Initial value R/W XXXXXXXXB (Vacancy) VRAM Display RAM 6CH to 6FH (Vacancy) 70H SMR Serial I/O mode register R/W 00000000B 71H SDR Serial I/O data register R/W XXXXXXXXB 72H PURR0 Pull-up resistor register 0 R/W 11111111B 73H PURR1 Pull-up resistor register 1 R/W 11111111B 74H PURR2 Pull-up resistor register 2 R/W 11111111B 75H PURR4 Pull-up resistor register 4 R/W XX111111B 76H (Vacancy) 77H WREN Wild register enable register R/W XX000000B 78H WROR Wild register data test register R/W XX000000B 79H ADEN A/D port input enable register R/W 11111111B 7AH (Vacancy) 7BH ILR1 Interrupt level setting register 1 W 11111111B 7CH ILR2 Interrupt level setting register 2 W 11111111B 7DH ILR3 Interrupt level setting register 3 W 11111111B 7EH ILR4 Interrupt level setting register 4 W 11111111B 7FH ITR Interrupt test register Access Prohibited 11111111B Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. M : The initial value of this bit is determined by mask option. Note : Do not use vacancies. 26 DS07-12555-3E MB89560A Series WILD REGISTER I/O MAP Address Register name 480H WRARH1 481H Register description Read/Write Initial value Wild register high-byte address register1 R/W XXXXXXXXB WRARL1 Wild register low-byte address register1 R/W XXXXXXXXB 482H WRDR1 Wild register data register1 R/W XXXXXXXXB 483H WRARH2 Wild register high-byte address register2 R/W XXXXXXXXB 484H WRARL2 Wild register low-byte address register2 R/W XXXXXXXXB 485H WRDR2 Wild register data register2 R/W XXXXXXXXB 486H WRARH3 Wild register high-byte address register3 R/W XXXXXXXXB 487H WRARL3 Wild register low-byte address register3 R/W XXXXXXXXB 488H WRDR3 Wild register data register3 R/W XXXXXXXXB 489H WRARH4 Wild register high-byte address register4 R/W XXXXXXXXB 48AH WRARL4 Wild register low-byte address register4 R/W XXXXXXXXB 48BH WRDR4 Wild register data register4 R/W XXXXXXXXB 48CH WRARH5 Wild register high-byte address register5 R/W XXXXXXXXB 48DH WRARL5 Wild register low-byte address register5 R/W XXXXXXXXB 48EH WRDR5 Wild register data register5 R/W XXXXXXXXB 48FH WRARH6 Wild register high-byte address register6 R/W XXXXXXXXB 490H WRARL6 Wild register low-byte address register6 R/W XXXXXXXXB 491H WRDR6 Wild register data register6 R/W XXXXXXXXB Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. M : The initial value of this bit is determined by mask option. Note : Do not use vacancies. DS07-12555-3E 27 MB89560A Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Power supply voltage LCD power voltage Program voltage Input voltage Output voltage Symbol Rating Unit Remarks VSS + 6.0 V VSS - 0.3 VSS + 6.0 V MB89567A, MB89567AC, MB89P568 and MB89PV560*1 AVR must not exceed "AVcc + 0.3V". V0 to V3 VSS - 0.3 VSS + 6.0 V V0 to V3 should not exceed Vcc Without booster VPP VSS - 0.6 VSS +13.0 V Only for the MB89P568 VSS - 0.3 VCC + 0.3 V For pins other than P30, P31, P46, P47, P50 to P57 and P60 to P67 VSS - 0.3 VCC + 0.3 V P50 to P57, P60 to P67 Resister Ladder option VSS - 0.3 V3 V P50 to P57, P60 to P67 LCD booster option VSS - 0.3 VSS + 6.0 V For P30, P31, P46, P47 VSS - 0.3 VCC + 0.3 V For pins other than P30, P31, P46, P47, P50 to P57 and P60 to P67 VSS - 0.3 VCC + 0.3 V P50 to P57, P60 to P67 Resister Ladder option VSS - 0.3 V3 V P50 to P57, P60 to P67 LCD booster option VSS - 0.3 VSS + 6.0 V For P30, P31, P46, P47 15 mA For pins other than P20 to P27 30 mA For P20 to P27 only 4 mA For pins other than P20 to P27*2 15 mA For P20 to P27 only*2 Min Max VCC AVCC VSS - 0.3 AVR VI VO "L" level maximum output current IOL "L" level average output current IOLAV "L" level total maximum output current IOL 100 mA IOLAV 60 mA *2 - 15 mA For pins other than P20 to P27, P30, P31, P46, P47, P50 to P57, P60 to P67 - 30 mA For P20 to P27 only "L" level total average output current "H" level maximum output current "H" level average output current IOH IOHAV -4 - 15 mA For pins other than P20 to P27*2 For P20 to P27 only*2 (Continued) 28 DS07-12555-3E MB89560A Series (Continued) (AVSS = VSS = 0.0 V) Parameter Symbol Rating Unit Min Max IOH - 50 mA IOHAV - 30 mA Power consumption PD 300 mW Operating temperature TA - 40 + 85 C Tstg - 55 + 150 C "H" level total maximum output current "H" level total average output current Storage temperature Remarks *2 *1 : Use AVCC and VCC set at the same voltage. Take care so that AVR does not exceed AVCC + 0.3 V, such as when power is turned on. Take care so that AVCC does not exceed VCC, such as when power is turned on. *2 : Average value (operating current x operating rate) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS07-12555-3E 29 MB89560A Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Power supply voltage LCD power voltage A/D converter reference input voltage Operating temperature Symbol VCC AVCC Value Unit Remarks Min Max 2.2* 5.5* V For MB89567A and MB89567AC 1.5 5.5 V Retains the RAM state in stop mode for MB89567A and MB89567AC 2.7* 5.5* V For MB89PV560 and MB89P568 1.5 5.5 V Retains the RAM state in stop mode for MB89PV560 and MB89P568 Liquid crystal power supply range: without booster (The best value is according to the specification of LCD used.) V0 to V3 Vss VCC V AVR 3.5 AVCC V TA - 40 + 85 C * : These values depend on the operating conditions and the analog assurance range. See Figure "Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC) ", "Operating Voltage vs. Main Clock Operating Frequency (MB89P568/MB89PV560) " and "6. A/D Converter Electrical Characteristics". WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 30 DS07-12555-3E MB89560A Series "Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC) and "Operating Voltage vs. Main Clock Operating Frequency (MB89P568/MB89PV560) indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH Operating Voltage (V) A/D Converter accuracy assurance range: Vcc = AVcc =3.5 V to 5.5 V 5.5 5.0 Operation assurance range 4.0 3.5 3.0 2.7 2.2 2.0 Main clock operating Freq. (MHz) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Instruction cycle: 4/Fc 4.0 2.0 0.8 11.0 12.0 12.5 Min execution time (inst. cycle) (s) 0.4 0.32 Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC) DS07-12555-3E 31 MB89560A Series Operating Voltage (V) A/D Converter accuracy assurance range: Vcc = AVcc = 3.5 V to 5.5 V 5.5 5.0 Operation assurance range 4.5 4.0 3.5 3.0 2.7 2.5 2.2 Operation assurance : TA = -10 C to +55 C (Only for MB89P568) 2.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 12.0 Main clock operating Freq. (MHz) 11.0 12.5 Min execution time (inst. cycle) (s) Instruction cycle: 4/Fc 4.0 2.0 0.8 0.4 0.32 Operating Voltage vs. Main Clock Operating Frequency (MB89P568/MB89PV560) Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 32 DS07-12555-3E MB89560A Series 3. DC Characteristics (power supply voltage : 5.0V) Parameter Symbol Pin (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max VIH P00 to P07, P10 to P17, P20 to P27, P30, P31, P40 to P45, P50 to P57, P60 to P67 -- 0.7 VCC -- VCC + 0.3 V CMOS VIHS RST, MODA, INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC -- 0.8 VCC -- VCC + 0.3 V Hysteresis -- VSS +1.4 -- VSS + 5.5 V SMB input buffer selected -- 0.7 VCC -- VSS + 5.5 V I2C input buffer selected VIL P00 to P07, P10 to P17, P20 to P27, P30, P31, P40 to P45, P50 to P57, P60 to P67 -- VSS - 0.3 -- 0.3 VCC V CMOS VILS RST, MODA, INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC -- VSS - 0.3 -- 0.2 VCC V Hysteresis VSS - 0.3 -- VSS + 0.6 V SMB input buffer selected -- VSS - 0.3 -- 0.3 VCC V I2C input buffer selected P60 to P67, P50 to P57 -- VSS - 0.3 -- VCC + 0.3 V Resister Ladder option P60 to P67, P50 to P57 -- VSS - 0.3 -- V3 V LCD booster option P46, P47, P30, P31 -- VSS - 0.3 -- VSS + 5.5 V P00 to P07, P10 to P17, P40 to P45 IOH = -2.0 mA 4.0 -- -- P20 to P27 IOH = -15.0 mA 4.0 -- -- "H" level input voltage VIHSMB SCL, SDA VIHI2C "L" level input voltage VILSMB SCL, SDA VILI2C Open-drain output pin application voltage "H" level output voltage VD VOH V (Continued) DS07-12555-3E 33 MB89560A Series Parameter "L" level output voltage Input leakage current (High-Z output leakage current) Open-drain output leakage current Symbol VOL Pin P00 to P07, P10 to P17, P30, P31, P40 to P47, P50 to P57, P60 to P67, RST IOL = 4.0 mA -- -- 0.4 P20 to P27 IOL = 15.0 mA -- -- 0.4 -5 -- +5 A Without pull-up Resistor -5 -- +5 A Resistor Ladder option P00 to P07, P10 to P17, P20 to P27, P40 to P45 ILI ILIOD P50 to P57, P60 to P67 0.0 V < VI < V3 -5 -- +5 A LCD booster option MODA 0.0 V < VI < VCC - 10 -- +10 A MB89PV560 MB89P568 P50 to P57, P60 to P67 0.0 V < VI < VCC -- -- +5 A Resistor Ladder option P50 to P57, P60 to P67 0.0 V < VI < V3 -- -- +5 A LCD booster option P30, P31, P46, P47 0.0 V < VI < Vss + 5.5 V -- -- +5 A Pull-up resistance RPULL Pull-down resistance RMODA MODA ICC1 ICC2 ICCS1 34 V 0.0 V < VI < VCC P50 to P57, P60 to P67 P00 to P07, P10 to P17, P20 to P27, P40 to P45, RST Power supply current *1 (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max VCC VI = 0.0 V 25 50 100 k When pull-up resistor selected except RST VI = 3.0 V 50 100 200 k MB89567A/ MB89567AC FCH = 10 MHz, tinst*2 = 0.4 s, Main clock run mode -- 15 20 -- 8 13 MB89567A MB89567AC FCH = 10 MHz, tinst*2 = 6.4 s, Main clock run mode -- 5 8.5 MB89PV560 MB89P568 -- 1 3 MB89567A MB89567AC FCH = 10 MHz, tinst*2 = 0.4 s, Main clock sleep mode -- 5 7 MB89PV560 MB89P568 -- 2.5 5 mA mA mA MB89PV560 MB89P568 MB89567A MB89567AC (Continued) DS07-12555-3E MB89560A Series (Continued) Parameter (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin FCH = 10 MHz, tinst*2 = 6.4 s, Sleep mode ICCS2 FCL = 32.768 kHz, Subclock mode, TA = +25 C ICCL Power supply current *1 VCC ICCLS ICCH LCD divided resistance RLCD FCL = 32.768 kHz, Subclock sleep mode, TA = +25 C FCL = 32.768 kHz, TA = +25 C, Watch mode, Main clock stop mode ICCT Power supply current *1 Condition VCC -- TA = +25 C, Subclock stop mode Between VCC and VSS Value Unit Typ Max -- 1.5 3 -- 0.7 2 -- 3 7 mA MB89PV560 MB89P568 -- 50 85 A MB89567A MB89567AC -- 30 50 mA A -- MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC 15 30 5 15 A MB89PV560 MB89P568 1.6 15 A MB89567A MB89567AC 3 10 A MB89PV560 MB89P568 1 10 A MB89567A MB89567AC 300 500 750 k -- -- 5 k -- -- 15 k -- -- COM0 to COM3 output impedance RVCOM SEG0 to SEG23 output impedance RVSEG SEG0 to SEG23 LCD controller/ driver leakage current ILCDL V0 to V3, COM0 to COM3, SEG0 to SEG23 -- -1 -- 1 A Input capacitance CIN Other than AVCC, AVSS, VCC, and f = 1 MHz VSS -- 10 -- pF COM0 to COM3 Remarks Min V1 to V3 = 5.0 V *1 : The power supply current is measured at the external clock *2 : For information on tinst, see "5. AC Characteristics (4) Instruction Cycle". Note : For LCD and port multiplex pin (P50 to P57, P60 to P67), please refer to LCD specification when the port is used, and refer to LCD specification when used as LCD pin. DS07-12555-3E 35 MB89560A Series 4. DC Characteristics (power supply voltage : 3.0 V) Parameter Symbol Pin (AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max VIH P00 to P07, P10 to P17, P20 to P27, P30, P31, P40 to P45, P50 to P57, P60 to P67 -- 0.7 VCC -- VCC + 0.3 V CMOS VIHS RST, MODA, INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC -- 0.8 VCC -- VCC + 0.3 V Hysteresis -- VSS +1.4 -- VSS + 5.5 V SMB input buffer selected -- 0.7 VCC -- VSS + 5.5 V I2C input buffer selected VIL P00 to P07, P10 to P17, P20 to P27, P30, P31, P40 to P45, P50 to P57, P60 to P67 -- VSS - 0.3 -- 0.3 VCC V CMOS VILS RST, MODA, INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC -- VSS - 0.3 -- 0.2 VCC V Hysteresis -- VSS - 0.3 -- VSS + 0.6 V SMB input buffer selected -- VSS - 0.3 -- 0.3 VCC V I2C input buffer selected P60 to P67, P50 to P57 -- VSS - 0.3 -- VCC + 0.3 V Resistor Ladder option P60 to P67, P50 to P57 -- VSS - 0.3 -- V3 V LCD booster option P46, P47, P30, P31 -- VSS - 0.3 -- VSS + 5.5 V P00 to P07, P10 to P17, P40 to P45 IOH = -2.0 mA 2.4 -- -- P20 to P27 IOH = -10 mA 2.4 -- -- "H" level input voltage VIHSMB SCL, SDA VIHI2C "L" level input voltage VILSMB SCL, SDA VILI2C Open-drain output pin application voltage "H" level output voltage VD VOH V (Continued) 36 DS07-12555-3E MB89560A Series Parameter Symbol "L" level output voltage Input leakage current (Hi-z output leakage current) Open-drain output leakage current VOL Pin P00 to P07, P10 to P17, P30, P31, P40 to P47, P50 to P57, P60 to P67, RST IOL = 4.0 mA -- -- 0.4 P20 to P27 IOL = 10 mA -- -- 0.4 -5 -- +5 A Without pull-up Resister -5 -- +5 A Resister Ladder option P00 to P07, P10 to P17, P20 to P27, P40 to P45 ILI ILIOD V 0.0 V < VI < VCC P50 to P57, P60 to P67 P50 to P57, P60 to P67 0.0 V < VI < V3 -5 -- +5 A LCD booster option MODA 0.0 V < VI < VCC -10 -- +10 A MB89PV560 MB89P568 P50 to P57, P60 to P67 0.0 V < VI < VCC -- -- +5 A Resister Ladder option P50 to P57, P60 to P67 0.0 V < VI < V3 -- -- +5 A LCD booster option P30, P31, P46, P47 0.0 V < VI < Vss + 5.5 V -- -- +5 A Pull-up resistance RPULL P00 to P07, P10 to P17, P20 to P27, P40 to P45, RST Pull-down resistance RMODA MODA ICC1 Power supply current *1 (AVCC = VCC = 3.0V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max VI = 0.0 V 50 100 200 k When pull-up resistor selected except RST VI = 5.0 V 25 50 100 k MB89567A MB89567AC FCH = 10 MHz, tinst*2 = 0.4 s, Main clock run mode -- 6 10 4 9 MB89567A MB89567AC FCH = 10 MHz, tinst*2 = 6.4 s, Main clock run mode -- 1.5 3 MB89PV560 MB89P568 -- mA VCC ICC2 -- mA 0.4 2 MB89PV560 MB89P568 MB89567A MB89567AC (Continued) DS07-12555-3E 37 MB89560A Series (Continued) Parameter Symbol Pin ICCS1 ICCS2 VCC ICCT ICCH LCD divided resistance COM0 to COM3 output impedance RLCD RVCOM -- -- 1 3 MB89567A MB89567AC FCH = 10 MHz, tinst*2 = 6.4 s, Main clock sleep mode -- 1 2 MB89PV560 MB89P568 FCL = 32.768 kHz, Subclock sleep mode, TA = +25 C ICCLS -- MB89PV560 MB89P568 FCH = 10 MHz, tinst*2 = 0.4 s, Main clock sleep mode FCL = 32.768 kHz, Subclock mode, TA = +25 C ICCL Power supply current *1 (AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max 2 4 mA mA 0.3 1.5 -- 1 3 mA MB89PV560 MB89P568 -- 25 60 A MB89567A MB89567AC -- 15 30 -- 8 25 5 15 A MB89PV560 MB89P568 1 14 A MB89567A MB89567AC MB89PV560 MB89P568 A FCL = 32.768 kHz, TA = +25 C, Watch mode, Main clock stop mode -- TA = +25 C, Subclock stop mode -- 1 5 A Between VCC and VSS 300 500 750 k -- -- 5 k -- -- 15 k -1 -- 1 A -- 10 -- pF COM0 to COM3 MB89567A MB89567AC -- MB89567A MB89567AC V1 to V3 = 3.0 V SEG0 to 23 output RVSEG impedance SEG0 to SEG23 LCD controller/ driver leakage current ILCDL V0 to V3, COM0 to COM3, SEG0 to SEG23 Input capacitance CIN Other than AVCC, AVSS, VCC, and f = 1 MHz VSS -- *1 : The power supply current is measured at the external clock *2 : For information on tinst, see "5. AC Characteristics (4) Instruction Cycle". Note : For LCD and port multiplex pin (P50 to P57, P60 to P67), please refer to LCD specification when the port is used, and refer to LCD specification when used as LCD pin. 38 DS07-12555-3E MB89560A Series 5. AC Characteristics (1) Reset Timing Parameter (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Max Symbol RST "L" pulse width tZLZH -- 48 tHCYL -- ns Notes : * tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin. * If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) . t ZLZH RST 0.2 V CC 0.2 V CC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition -- Value Unit Min Max 0.5 50 ms 1 -- ms Remarks Due to repeated operations Note : Make sure that power supply rises within the selected oscillation stabilization time. For example, when the main clock is operating at 10 MHz (FCH) and the oscillation stabilization time select option has been set to 218/FCH, the oscillation stabilization delay time is 26.2 ms. Therefore, the maximum value of power supply rising time is about 26.2 ms. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tOFF tR 2.0 V VCC DS07-12555-3E 0.2 V 0.2 V 0.2 V 39 MB89560A Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Unit Remarks Typ Max Symbol Pin FCH X0, X1 1 -- 12.5 FCL X0A, X1A -- 32.768 -- kHz tHCYL X0, X1 80 -- 1000 ns Main clock tLCYL X0A, X1A -- 30.5 -- s Subclock Input clock pulse width PWH PWL X0 20 -- -- ns External clock Input clock rising/falling time tCR tCF X0 -- -- 10 ns External clock Parameter Clock frequency Clock cycle time Min MHz Main clock Subclock X0 and X1 Timing and Conditions tHCYL PWH PWL tCF tCR 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2VCC Main Clock Conditions When using a crystal oscillator or ceramic oscillator X0 When using an external clock X0 X1 X1 Open FCH C1 40 C2 FCH DS07-12555-3E MB89560A Series X0A and X1A Timing tLCYL 0.7 VCC 0.7 VCC X0A 0.3 VCC 0.3 VCC 0.3 VCC When using a crystal oscillator X0A X1A FCL C1 C2 Note : External clock is not available. (4) Instruction Cycle (AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Parameter Instruction cycle (minimum execution time) DS07-12555-3E Symbol Value Unit 4/FCH, 8/FCH, 16/FCH, 64/FCH s tinst = 0.32 s when operating at FCH = 12.5 MHz (4/FCH) 2/FCL s tinst = 61.036 s when operating at FCL = 32.768 kHz tinst Remarks 41 MB89560A Series (5) Serial I/O Timing (Vcc = 5.0V, AVSS = VSS= 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Max Symbol Pin Serial clock cycle time tSCYC SCK, SCK1, UCK SCK SO time tSLOV SCK, SO, SCK1, SO1, UCK, UO Parameter Valid SI SCK tIVSH SI, SCK, SI1, SCK1, UI, UCK SCK valid SI hold time tSHIX SCK, SI, SCK1, SI1, UCK, UI Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH SCK SO time tSLOV SCK, SO, SCK1, SO1, UCK, UO Valid SI SCK tIVSH SI, SCK, SI1, SCK1, UI, UCK SCK valid SI hold time tSHIX SCK, SI, SCK1, SI1, UCK, UI Internal shift clock mode SCK, SCK1, UCK External shift clock mode 2 tinst* -- s -200 +200 ns 200 -- ns 200 -- ns 1 tinst* -- s 1 tinst* -- s 0 200 ns 200 -- ns 200 -- ns * : For information on tinst, see "(4) Instruction Cycle". 42 DS07-12555-3E MB89560A Series Internal Shift Clock Mode tSCYC SCK SCK1 UCK 0.8 VCC 0.2 VCC 0.2 VCC tSLOV 0.8 VCC SO SO1 UO 0.2 VCC tIVSH SI SI1 UI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Shift Clock Mode tSLSH tSHSL SCK SCK1 UCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 0.8VCC SO SO1 UO 0.2 VCC tIVSH SI SI1 UI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC (6) Peripheral Input Timing (Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Max Parameter Symbol Pin Peripheral input "H" pulse width 1 tILIH1 INT10 to INT17, INT20 to INT23, EC, PWC Peripheral input "L" pulse width 1 tIHIL1 -- 2 tinst* -- s 2 tinst* -- s * : For information on tinst, see "(4) Instruction Cycle". tIHIL1 INT10 to INT17, INT20 to INT23, EC, PWC 0.8 VCC 0.2 VCC DS07-12555-3E tILIH1 0.8 VCC 0.2 VCC 43 MB89560A Series (7) I2C timing (Vcc = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Unit Remarks Min Max Parameter Symbol Pin Condition Start condition output tSTA SCL SDA -- Stop condition output tSTO SCL SDA -- Start condition detect tSTA SCL SDA -- 1/4 tinst x 6 + 40 -- ns Stop condition detect tSTO SCL SDA -- 1/4 tinst x 6 + 40 -- ns Re-start condition output tSTASU SCL SDA -- Re-start condition detect tSTASU SCL SDA -- 1/4 tinst x 4 + 40 -- ns SCL output LOW width tLOW SCL -- 1/4 tinst x M*2 x N*3 - 20 1/4 tinst x M*2 x N*3 + 20 ns Master mode SCL output HIGH width tHIGH SCL -- ns Master mode SDA output delay tDO SDA -- 1/4 tinst x 4 - 20 1/4 tinst x 4 + 20 ns SDA output setup time after interrupt tDOSU SDA -- 1/4 tinst x 4 - 20 -- ns SCL input LOW pulse width tLOW SCL -- 1/4 tinst x 6 + 40 -- ns SCL input HIGH pulse width tHIGH SCL -- 1/4 tinst x 2 + 40 -- ns SDA input setup time tSU SDA -- 40 -- ns SDA hold time tHO SDA -- 0 -- ns 1/4 tinst*1 x M*2 x N*3 - 20 1/4 tinst x M*2 x N*3 + 20 1/4 tinst x 1/4 tinst x (M*2 x N*3 + 8) - 20 (M*2 x N*3 + 8) + 20 1/4 tinst x 1/4 tinst x (M*2 x N*3 + 8) - 20 (M*2 x N*3 + 8) + 20 1/4 tinst x 1/4 tinst x (M*2 x N*3 + 8) - 20 (M*2 x N*3 + 8) + 20 ns Master mode ns Master mode ns Master mode *4 *1 : For information in tinst, see " (4) Instruction Cycle". *2 : M is defined in the ICCR CS4 and CS3 (bit 4, bit 3) . For details, please refer to the H/W manual register explanation. *3 : N is defined in the ICCR CS2 to CS0 (bit 2 to bit 0) . *4 : When the interrupt period is greater than SCL "L" width, SDA and SCL output (Standard) value is based on hypothesis when rising time is 0 ns. 44 DS07-12555-3E MB89560A Series Data transmit (master/slave) tDO tDO tHO tSU SDA tDOSU ACK tSTASU tSTA tLOW SCL tHIGH 9 1 Data receive (master/slave) tSU tDO tHO SDA DS07-12555-3E tDOSU ACK tHIGH SCL tDO 6 7 tSTO tLOW 8 9 45 MB89560A Series 6. A/D Converter Electrical Characteristics (1) For MB89567A/AC A/D Converter Parameter Symbol Pin Resolution (AVcc = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max -- Total error Non-linearity error -- Differential linearity error Zero transition voltage VOT Full-scale transition voltage VFST AVR=AVCC -- Interchannel disparity A/D mode conversion time *3 -- 10 bit -- -- 3.0 LSB -- -- 2.5 LSB -- -- 1.9 LSB AVss - 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB V AVR - 3.5 LSB AVR - 1.5 LSB AVR + 1.5 LSB V -- -- 4 LSB -- 60 tinst*1 -- -- inst 1 16 t * -- -- -- 10 A AVss -- AVR V -- 4 6 when A/D mA conversion is activated -- 1 5 A AVss+3.5 -- AVCC V -- 200 -- A -- -- 5 A *2 1LSB = (AVR - AVss) / 1024 -- Analog port input current IAIN Analog input voltage VAIN AN0 to AN7 IA Power supply current -- AVCC IAH Reference voltage supply current -- s A/D Sampling time Reference voltage -- -- IR IRH TA = +25 C -- AVR A/D is Activated A/D is Stopped when A/D conversion is stopped *1 : For information on tinst, see "(4) Instruction Cycle" in "5. AC Characteristics". *2 : When A/D conversion is not in operation, and the CPU is in STOP mode. *3 : Included sampling time 46 DS07-12555-3E MB89560A Series (2) For MB89P568/PV560 A/D Converter Parameter Symbol Pin Resolution (AVcc=3.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min Typ Max -- -- -- 10 bit -- -- 3.0 LSB -- -- 2.5 LSB -- -- 1.9 AVss - 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB LSB 1LSB = (AVR - AVss) / 1024 V AVR - 3.5 LSB AVR - 1.5 LSB AVR + 1.5 LSB V -- -- 4 LSB -- 60 tinst*1 -- -- inst 1 16 t * -- -- -- 10 A AVss -- AVR V -- 4 6 when A/D mA conversion is activated -- 1 5 when A/D A conversion is stopped AVss + 3.5 -- AVCC V A/D is Activated -- 400 -- A A/D is Stopped -- -- 5 A *2 Total error -- Non-linearity error Differential linearity error Zero transition voltage VOT Full-scale transition voltage VFST AVR=AVCC -- Interchannel disparity A/D mode conversion time *3 -- A/D Sampling time -- Analog port input current IAIN Analog input voltage VAIN AN0 to AN7 -- IA AVCC Power supply current TA = +25 C IAH Reference voltage Reference voltage supply current -- IR IRH -- AVR s *1 : For information on tinst, see "(4) Instruction Cycle" in "5. AC Characteristics". *2 : When A/D conversion is not in operation, and the CPU is in STOP mode. *3 : Included sampling time DS07-12555-3E 47 MB89560A Series (3) A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter. * Linearity error The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics * Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit: LSB) The difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise Theoretical I/O characteristics 3FF Total error 3FF VFST 3FE 3FD 3FD 1.5 LSB Digital Output Digital Output Actual Conversion Characteristic 3FE 004 003 VOT 002 {1 LSB x N + 0.5 LSB} 004 VNT 003 Actual Conversion Characteristic Theoretical Conversion Characteristic 002 1 LSB 001 001 0.5 LSB AVR AVSS Analog Input 1 LSB = VFST - VOT 1022 AVR AVSS Analog Input (V) VNT - {1 LSB x N + 0.5 LSB} 1 LSB Total error for digital output N = (Continued) 48 DS07-12555-3E MB89560A Series (Continued) Zero transition error Theoretical Characteristic Actual Conversion Characteristic Actual Conversion Characteristics 3FF Digital Output Digital Output 004 Full-scale transition error 003 002 3FE VFST (actual measured value) Actual Conversion Characteristic 3FD Actual Conversion Characteristic 001 VOT 3FC (actual measured value) AVSS AVR AVSS AVR Linearity error Differential linearity error Theoretical Characteristic Actual Conversion Characteristic 3FF N+1 {1 LSB x N + VOT} 3FD VFST VNT (actual measured value) 004 003 Actual Conversion Characteristic 002 Theoretical Characteristic 001 VOT AVSS Digital Output Digital Output 3FE Actual Conversion Characteristic V(N + 1)T N N-1 VNT (actual measured value) Actual Conversion Characteristic N-2 (actual measured value) AVR AVR AVSS Analog Input Analog Input Linearity error in digital output N = VNT - {1 LSB x N + 0.5 LSB} 1 LSB Differential linearity error in digital output N = DS07-12555-3E V(N + 1)T - VNT -1 1 LSB 49 MB89560A Series (4) Precautions * The smaller the | AVR-AVSS | is, the greater the error would become relatively. * The output impedance of the external circuit for the analog input must satisfy the following conditions : Output impedance of the external circuit < Approx. 10 k * If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient. Analog Input equivalent circuit Sample hold circuit * . C =. 45 pF Analog input pin Comparator If the analog input impedance is higher than 10 k, it is recommended to connect an external capacitor of approx. 0.1 F. . R =. 2.2 k Close for 8 instruction cycles after starting A/D conversion. Analog channel selector * : The value of R and C at the sample hold circuit depends on the following. MB89567A/MB89567AC : R =: 2.2 k, C =: 45 pF MB89P568/MB89PV560 : R =: 1.4 k, C =: 64 pF 50 DS07-12555-3E MB89560A Series EXAMPLE CHARACTERISTICS (1) "L" Level Output Voltage VOL1 vs. IOL VCC = 2.5 V 1.0 VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 3.5 V VCC = 4.5 V VCC = 5.5 V VCC = 6.0 V VCC = 6.5 V 0.9 0.8 VOL1 (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) (2) "H" Level Output Voltage VCC - VOH1 (V) VCC - VOH1 vs. IOH 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V VCC = 6.5 V 0 -2 -4 -6 -8 -10 IOH (mA) DS07-12555-3E 51 MB89560A Series (3) "H" Level Input Voltage / "L" Level Input Voltage CMOS input Hysteresis input 5.0 5.0 4.5 4.5 TA = + 25 C 4.0 3.5 VIHS 3.5 3.0 VIN (V) VIN (V) TA = + 25 C 4.0 2.5 2.0 3.0 2.5 1.5 2.0 1.0 1.5 0.5 1.0 0.0 1 2 3 4 VCC (V) 5 6 7 VILS 0.5 0.0 1 2 3 4 VCC (V) 5 6 7 VIHS : Threshold when input voltage in hysteresis characteristics is set to "H" level. VILS : Threshold when input voltage in hysteresis characteristics is set to "L" level. 52 DS07-12555-3E MB89560A Series (4) Power Supply Current (External Clock) ICC1 vs. VCC ICC2 vs. VCC (Mask ROM products) (Mask ROM products) 1.2 15 TA = + 25 C TA = + 25 C FCH = 12.5 MHz 12 FCH = 10.0 MHz 0.8 ICC2 (mA) ICC1 (mA) FCH = 12.5 MHz 1.0 9 FCH = 10.0 MHz 6 FCH = 4.2 MHz 3 0.6 FCH = 4.2 MHz 0.4 FCH = 3.0 MHz FCH = 3.0 MHz 0.2 FCH = 1.0 MHz FCH = 1.0 MHz 0 0.0 0 1 4.0 2 3 4 5 6 7 VCC (V) 0 4 VCC (V) ICCS1 vs. VCC (Mask ROM products) ICCS2 vs. VCC (Mask ROM products) 2 0.7 TA = + 25 C 3.5 1 5 6 7 TA = + 25 C 0.6 FCH = 12.5 MHz 3 FCH = 12.5 MHz FCH = 10.0 MHz 2.5 2.0 1.5 FCH = 4.2 MHz 1.0 0.5 ICCS2 (mA) ICCS1 (mA) 3.0 FCH = 10.0 MHz 0.4 0.3 FCH = 4.2 MHz 0.2 FCH = 3.0 MHz FCH = 3.0 MHz 0.1 0.5 FCH = 1.0 MHz FCH = 1.0 MHz 0.0 0.0 0 1 2 3 4 5 6 0 7 VCC (V) 1 2 3 4 VCC (V) 6 7 ICCT vs. VCC ICCL vs. VCC (Mask ROM products) (Mask ROM products) 4.0 100 TA = + 25 C 3.6 TA = + 25 C 3.2 80 60 FCL = 32.768 kHz 40 ICCT (A) 2.8 ICCL (A) 5 FCL = 32.768 kHz 2.4 2.0 1.6 1.2 20 0.8 0 0.4 0.0 0 1 2 3 4 VCC (V) 5 6 7 0 1 2 3 4 VCC (V) 5 6 7 (Continued) DS07-12555-3E 53 MB89560A Series (Continued) ICCLS (A) ICCLS vs. VCC (Mask ROM products) 22 20 18 16 14 12 10 8 6 4 2 0 TA = + 25 C 0 1 2 3 4 VCC (V) 5 6 7 IR vs. AVR IA VS. AVCC 4.0 3.5 3.0 200 180 TA = + 25 C 160 140 FCH = 10.0 MHz IR (A) IA (mA) 2.5 2.0 TA = + 25 C 120 100 80 1.5 60 1.0 40 0.5 20 0.0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 AVCC (V) AVR (V) (5) Pull-up Resistance Rpull vs.VCC 210 190 Rpull (k) 170 150 130 110 90 70 TA = + 93 C 50 TA = + 25 C 30 TA = - 40 C 10 2 54 3 4 5 VCC (V) 6 7 8 DS07-12555-3E MB89560A Series MASK OPTIONS Model MB89567A MB89567AC MB89P568 MB89PV560 Specification method Specify when ordering mask. Setting unavailable. Setting unavailable. No. 1 Main clock oscillation stabilization delay time initial value* selection (FCH = 10 MHz) * 01: 214/FCH (Approx. 1.6 ms) Selectable * 10: 217/FCH (Approx. 13.1 ms) * 11: 218/FCH (Approx. 26.2 ms) 218/FCH (Approx. 26.2 ms) 218/FCH (approx. 26.2 ms) 2 LCD driving power supply * On-chip voltage booster * Internal voltage divider (external divider resistors can be used) -101 Internal voltage divider -102 On-chip voltage booster -101 Internal voltage divider -102 On-chip voltage booster Selectable ORDERING INFORMATION Part number MB89567APMC MB89567ACPMC MB89P568-101PMC MB89567APMC MB89567ACPMC MB89P568-102PMC MB89567APF MB89567ACPF MB89P568-101PF MB89567APF MB89567ACPF MB89P568-102PF MB89567APMC1 MB89567ACPMC1 MB89P568-101PMC1 MB89567APMC1 MB89567ACPMC1 MB89P568-102PMC1 MB89PV560-101CF MB89PV560-102CF DS07-12555-3E Package 80-pin Plastic LQFP (FPT-80P-M21) Remarks Without Booster Resistor divider With Booster 80-pin Plastic QFP (FPT-80P-M06) Without Booster Resistor divider With Booster 80-pin Plastic LQFP (FPT-80P-M22) Without Booster Resistor divider With Booster 80-pin Ceramic MQFP (MQP-80C-P01) Without Booster Resistor divider With Booster 55 MB89560A Series PACKAGE DIMENSIONS 80-pin plastic LQFP Lead pitch 0.50 mm Package width x package length 12 mm x 12 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.47 g Code (Reference) P-LFQFP80-12x12-0.50 (FPT-80P-M21) 80-pin plastic LQFP (FPT-80P-M21) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.000.20(.551.008)SQ * 12.000.10(.472.004)SQ 60 0.1450.055 (.006.002) 41 40 61 0.08(.003) Details of "A" part +0.20 1.50 -0.10 +.008 .059 -.004 INDEX 0~8 80 (Mounting height) 0.100.05 (.004.002) (Stand off) 21 "A" LEAD No. 1 20 0.50(.020) 0.200.05 (.008.002) 0.08(.003) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) M (c)2006-2008 FUJITSU MICROELECTRONICS LIMITED F80035S-c-2-3 C 2006 FUJITSU LIMITED F80035S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 56 DS07-12555-3E MB89560A Series 80-pin plastic QFP Lead pitch 0.80 mm Package width x package length 14.00 x 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP80-14x20-0.80 (FPT-80P-M06) 80-pin plastic QFP (FPT-80P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.900.40(.941.016) * 20.000.20(.787.008) 64 41 40 65 0.10(.004) 17.900.40 (.705.016) * 14.000.20 (.551.008) INDEX Details of "A" part 25 80 0.25(.010) +0.30 3.05 -0.20 +.012 .120 -.008 (Mounting height) 1 24 0.80(.031) 0.370.05 (.015.002) 0.16(.006) 0~8 M "A" C 2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) +0.10 0.30 -0.25 +.004 .012 -.010 (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07-12555-3E 57 MB89560A Series 80-pin plastic LQFP (FPT-80P-M22) 80-pin plastic LQFP (FPT-80P-M22) Lead pitch 0.65 mm Package width x package length 14.00 mm x 14.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.62 g Code (Reference) P-LFQFP80-14x14-0.65 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.000.20(.630.008)SQ * 14.000.10(.551.004)SQ 60 0.1450.055 (.006.002) 41 61 40 0.10(.004) Details of "A" part +0.20 +.008 1.50 -0.10 .059 -.004 (Mounting height) 0.25(.010) INDEX 0~8 80 21 1 "A" 20 0.65(.026) 0.320.05 (.013.002) 0.13(.005) 0.100.10 (.004.004) (Stand off) M (c)2007-2008 FUJITSU MICROELECTRONICS LIMITED F80036S-c-1-2 C 0.500.20 (.020.008) 0.600.15 (.024.006) 2007 FUJITSU LIMITED F80036S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 58 DS07-12555-3E MB89560A Series (Continued) 80-pin ceramic MQFP Lead pitch 0.8 mm Lead shape Straight Motherboard material Ceramic Mounted package material Plastic (MQP-80C-P01) 80-pin ceramic MQFP (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP INDEX AREA 16.300.33 (.642.013) 15.580.20 (.613.008) 1.50(.059)TYP +0.40 1.20 -0.20 +.016 .047 -.008 1.270.13 (.050.005) INDEX AREA 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP 22.300.33 (.878.013) 24.70(.972) TYP 0.800.25 (.0315.010) 0.800.25 (.0315.010) 1.00(.040)TYP 4.50(.177) TYP 0.30(.012) TYP 18.40(.724) REF INDEX 1.270.13 (.050.005) 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.400.10 (.016.004) 1.50(.059) TYP 1.00(.040) TYP 0.400.10 (.016.004) +0.40 1.20 -0.20 +.016 .047 -.008 0.150.05 8.70(.343) (.006.002) MAX C 1994-2008 FUJITSU MICROELECTRONICS LIMITED M80001SC-4-3 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ DS07-12555-3E 59 MB89560A Series MAIN CHANGES IN THIS EDITION Page 6 Section PIN ASSIGNMENT BLOCK DIAGRAM 19 41 45 Change Results Changed the package code. (*1: Main clock divided by two output *1: Main clock oscillation divided by two output) Changed the package code. (*1: Output of Main clock/2. *1: Output of Main clock oscillation/2.) ELECTRICAL CHARACTERISTICS 5. AC Characteristics (3) Clock Timing Changed the position of FCL of "When using a crystal oscillator". ELECTRICAL CHARACTERISTICS 5. AC Characteristics (4) Instruction Cycle Changed Instruction cycle (minimum execution time). ELECTRICAL CHARACTERISTICS 5. AC Characteristics (7) I2C Timing Changed the Data transmit (master/slave). (tHO tHIGH) The vertical lines marked in the left side of the page show the changes. 60 DS07-12555-3E MB89560A Series MEMO DS07-12555-3E 61 MB89560A Series MEMO 62 DS07-12555-3E MB89560A Series MEMO DS07-12555-3E 63 MB89560A Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. 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