MB89567ACPMC1 - Fujitsu Limited - Datasheet.Directory

FUJITSU MICROELECTRONICS

DATA SHEET

2009.5

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89560A Series

MB89567A/567AC/P568/PV560

■DESCRIPTION

The MB89560A series has been developed as a general-purpose version of the F2MC*-8L family consisting of

proprietary 8-bit, single-chip microcontrollers.

In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as I2C

interface, timers, 2 ch 8-bit PWM timers, 8/16-bit timer, 21-bit timebase timer, 8-bit PWC timer, 17-bit Watch

prescaler, Watch-dog timer, High speed UART, 8-bit SIO, UART/SIO, LCD controller/driver (optional booster),

Two type Programmable Pulse Generators (PPG), an A/D converter, and external interrupt.

* : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURES

•F

2MC-8L family CPU core

• Instruction set optimized for controllers:

- Multiplication and division instructions

- 16-bit arithmetic operations

- Test and branch instructions

- Bit manipulation instructions, etc.

• Low-voltage operation (when an A/D converter is not used)

• Low current consumption (applicable to the dual-clock system)

• Minimum execution time: 0.32 μs at 12.5 MHz /3.5 V to 5.5 V

• Two type of Programmable Pulse Generator (PPG): 6-bit PPG and 12-bit PPG

•I

2C interface circuit

•Three types of Serial Interface:

- 8-bit Serial I/O (SIO)

- UART/SIO

- High Speed UART (Transfer rate from 300 bps to 192000 bps /10 MHz main clock) (Continued)

DS07-12555-3E

MB89560A Series

2DS07-12555-3E

(Continued)

• I/O ports: Max 50 channels

• 21-bit time-base timer

• 8-bit PWM 2 channels timers

• 8/16-bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel)

• 8-bit PWC timer operation

• Watchdog timer

• 17-bit Watch prescaler

• 10-bit A/D converter: 8 channels

• External interrupt 1: 8 channels

• External interrupt 2 (wake-up function): 4 channels

• LCD controller/driver: 24 segments x 4 commons (Max 96 pixels, duty LCD mode and Static LCD mode)

• LCD booster function (option)

• Wild register (Max 6 different address locations)

• Low-power consumption modes (stop mode, sleep mode, watch mode, and sub clock mode)

• LQFP-80 and QFP-80 package

•CMOS technology

MB89560A Series

DS07-12555-3E 3

■PRODUCT LINEUP

(Continued)

Part number

Parameter MB89567A MB89567AC MB89P568 MB89PV560

Classification Mass production products

(mask ROM products) OTP Piggy-back

ROM size 32 K × 8-bit

(internal mask ROM) 48 K × 8-bit

(internal PROM) 56 K × 8-bit

(external ROM)

RAM size 1 K × 8-bit 1 K × 8-bit

CPU functions

Number of instructions : 136

Instruction bit length : 8-bit

Instruction length : 1 to 3 bytes

Data bit length : 1-, 8-, 16-bit

Minimum execution time : 0.32 μs/12.5 MHz

Minimum interrupt processing time : 2.88 μs/12.5 MHz

Ports

General-purpose I/O ports (N-channel open drain): 20 pins (2 shared with I2C inputs,

16 shared with LCD, 2 shared with other

resources)

General-purpose I/O ports (CMOS) : 30 pins (shared with resources)

Total : 50 pins

Watchdog timer Reset generate cycle: Min 221/FCH*7 for main clock, Min 214/FCL*7 for sub clock

21-bit time-base

timer 21-bit Interrupt cycle: (213, 215, 218 or 222)/FCH*7

8-bit PWM 2 ch

timer

8-bit interval timer operation (square wave output capable, operating clock cycle: 1 tinst, 8 tinst,

16 tinst, 64 tinst)

8-bit resolution PWM operation (conversion cycle: 128 × 1 tinst to 256 × 64 tinst)

8/16-bit timer/counter output for counter clock selectability

10-bit A/D

converter *2

10-bit resolution × 8 channels

A/D conversion function (conversion time: 60 tinst)

Continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable.

External interrupt

1 (wake-up

function)

8 independent channels (interrupt vector, request flag, request output enable)

Edge selectability (rising/falling)

Used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.)

External interrupt

2 (wake-up

function)

4 channels (“L” level interrupts, independent input enable).

Used also for wake-up from stop/sleep mode. (Low-level detection is also permitted in stop

mode.)

PWC timer

8-bit timer operation (count clock cycle: 1 tinst, 4 tinst, 32 tinst)

8-bit reload timer operation (toggle output possible, operating clock cycle: 1 to 32 tinst)

8-bit pulse width measurement (continuous measurement possible: H-width, L-width, rising

edge to rising edge, falling edge to falling edge, and rising edge to falling edge)

8/16-bit timer/

counter

Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its

own independent operating clock cycle), or as one 16-bit timer/counter

In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered)

and square wave output capable

MB89560A Series

4DS07-12555-3E

(Continued)

*1 : When booster is used, the bias is reduced by 1/3. It can be selected by mask option.

*2 : Voltage varies with product.

*3 : When external ROM is used, EPR OM: MBM27C512-20 should be used, the operating voltage: 4.5 V to 5.5 V.

*4 : I2C is complied to Intel Corp. System Management Bus Rev . 1.0 specification and to the Philips I2C specification.

*5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock

if main clock mode is selected, or 1/2 of the subclock if subclock mode is selected.

*6 : Varies with conditions such as the operating frequency. (See “■ ELECTRICAL CHARACTERISTICS”.)

*7 : FCH : main clock source oscillation, FCL : sub clock source oscillation

Part number

Parameter MB89567A MB89567AC MB89P568 MB89PV560

Watch prescaler 17-bit

Interrupt cycle: 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s/32.768 kHz for subclock

6-bit PPG Internal 6-bit counter

Pulse width and cycle are program selectable

12-bit PPG Internal 12-bit counter

Pulse width and cycle are program selectable

I2C interface*4Not

Available 1 channel

8-bit serial I/O 8-bit, LSB first/MSB first selectability

Transfer clocks (one external shift clock, three internal shift clocks: 2 tinst, 8 tinst, 32 tinst) *5

UART/SIO Transfer data length: 7-, 8-bit for UART, 8-bit for SIO

Transfer rate (1201 bps to 78125 bps / 10 MHz main clock)

support sub-clock mode

High speed UART Transfer data length: 4-, 6-, 7-, 8-bit

Transfer rate (300 bps to 192000 bps /9.216 MHz main clock)

support sub-clock mode

LCD

Common output: 4 (Max)

Segment output: 24 (Max)

LCD driving power (bias) pins: 4

LCD display RAM size: 12 bytes (24 × 4 bits, Max 96 pixels)

Duty LCD mode and Static LCD mode

Booster for LCD driving: option*1

Dividing resistor for LCD driving: option

Wild register

Maximum of 6-byte data can be assigned in 6 different address.

Used to replace any data in the ROM when specific address and data are assigned in Wild

Wild register can be set up by using different communication methods through the device.

Standby mode Sub clock mode, sleep mode, stop mode and watch mode

Process CMOS

Operating voltage *6 2.2 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V*3

MB89560A Series

DS07-12555-3E 5

■PACKAGE AND CORRESPONDING PRODUCTS

: Supported : Not supported

Note : For more information, see “■ PACKAGE DIMENSIONS”.

■DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that

will actually be used. Take particular care on the following points:

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

• For the MB89PV560, add the current consumed by the EPROM mounted in the piggy-back socket.

• When operating at low speed, the current consumed by the one-time PROM product is greater than that for

the mask ROM product. However, the current consumption is roughly the same in sleep or stop mode.

• For more information, see “■ ELECTRICAL CHARACTERISTICS”.

3. Mask Options

The functions available as options and the method of specifying options differ between products.

Before using options check “■ MASK OPTIONS”.

4. Wild register function

The Wild Register can be used in the following address spaces.

5. P40, P41

It will take about 64 count clock of external oscillation to initialize P40 and P41 pins in MB89PV560/P568.

Therefore, these ports will be unstable for a while during power-on. For MB89567A/567AC, these por ts will be

in High-Z during power-on.

Package MB89567A

MB89567AC MB89P568-101

MB89P568-102 MB89PV560-101

MB89PV560-102

FPT-80P-M21

FPT-80P-M06

FPT-80P-M22

MQP-80C-P01

Device Address Space

MB89PV560 4000H to FFFFH

MB89P568 4000H to FFFFH

MB89567A/567AC 8000H to FFFFH

MB89560A Series

6DS07-12555-3E

■PIN ASSIGNMENT

(Continued)

SEG07

P50/SEG08

P51/SEG09

P52/SEG10

P53/SEG11

P54/SEG12

P55/SEG13

P56/SEG14

P57/SEG15

P60/SEG16

P61/SEG17

P62/SEG18

Vss

P63/SEG19

P64/SEG20

P65/SEG21

P66/SEG22

P67/SEG23

AVR

AVcc

P44/UCK/SCK1

P43/PWM2/PPG2

P42/PWM1/EC1

P41/HCK*1/TO12

P40/WTO/TO11

P31/SDA

P30/SCL

Vcc

P27/INT23

P26/INT22

P25/INT21

P24/INT20

P23/PPG1

P22/SCK

P21/SO

P20/SI

MODA

X1A

SEG06

SEG05

SEG04

SEG03

SEG02

SEG01

SEG00

COM3

COM2

COM1

COM0

C0*2

C1*2

P47/PWC

P46/UI/SI1

P45/UO/SO1

P07/AN7

P06/AN6

P05/AN5

P04/AN4

P03/AN3

P02/AN2

P01/AN1

P00/AN0

AVss

P17/INT17

P16/INT16

P15/INT15

P14/INT14

P13/INT13

P12/INT12

P11/INT11

P10/INT10

RST

X0A

(Top view)

(FPT-80P-M21)

(FPT-80P-M22)

*1: Main clock oscillation divided by two output

*2: For built-in LCD booster only

Note: For mask option of *2, please refer to “■ MASK OPTIONS”.

MB89560A Series

DS07-12555-3E 7

(Continued)

SEG05

SEG06

SEG07

P50/SEG08

P51/SEG09

P52/SEG10

P53/SEG11

P54/SEG12

P55/SEG13

P56/SEG14

P57/SEG15

P60/SEG16

P61/SEG17

P62/SEG18

Vss

P63/SEG19

P64/SEG20

P65/SEG21

P66/SEG22

P67/SEG23

AVR

AVcc

P07/AN7

P06/AN6

P46/UI/SI1

P45/UO/SO1

P44/UCK/SCK1

P43/PWM2/PPG2

P42/PWM1/EC1

P41/HCK*1/TO12

P40/WTO/TO11

P31/SDA

P30/SCL

Vcc

P27/INT23

P26/INT22

P25/INT21

P24/INT20

P23/PPG1

P22/SCK

P21/SO

P20/SI

MODA

X1A

X0A

RST

SEG04

SEG03

SEG02

SEG01

SEG00

COM3

COM2

COM1

COM0

C0*2

C1*2

P47/PWC

P05/AN5

P04/AN4

P03/AN3

P02/AN2

P01/AN1

P00/AN0

AVss

P17/INT17

P16/INT16

P15/INT15

P14/INT14

P13/INT13

P12/INT12

P11/INT11

P10/INT10

(Top view)

(FPT-80P-M06)

*1: Main clock divided by two output

*2: For built-in LCD booster only

Note: For mask option of *2, please refer to “■ MASK OPTIONS”.

MB89560A Series

8DS07-12555-3E

(Continued)

SEG05

SEG06

SEG07

P50/SEG08

P51/SEG09

P52/SEG10

P53/SEG11

P54/SEG12

P55/SEG13

P56/SEG14

P57/SEG15

P60/SEG16

P61/SEG17

P62/SEG18

Vss

P63/SEG19

P64/SEG20

P65/SEG21

P66/SEG22

P67/SEG23

AVR

AVcc

P07/AN7

P06/AN6

P46/UI/SI1

P45/UO/SO1

P44/UCK/SCK1

P43/PWM2/PPG2

P42/PWM1/EC1

P41/HCK*

/TO12

P40/WTO/TO11

P31/SDA

P30/SCL

Vcc

P27/INT23

P26/INT22

P25/INT21

P24/INT20

P23/PPG1

P22/SCK

P21/SO

P20/SI

MODA

X1A

X0A

RST

SEG04

SEG03

SEG02

SEG01

SEG00

COM3

COM2

COM1

COM0

C0*

C1*

P47/PWC

P05/AN5

P04/AN4

P03/AN3

P02/AN2

P01/AN1

P00/AN0

AVss

P17/INT17

P16/INT16

P15/INT15

P14/INT14

P13/INT13

P12/INT12

P11/INT11

P10/INT10

(Top view)

101

102

103

104

105

106

107

108

109

100

110

111

112

(MQP-80C-P01)

*1: Main clock divided by two output

*2: For built-in LCD booster only

*3: Pin assignment on package top (MB89PV560 only)

N.C.: Internally connected. Do not use.

Note: For mask option of *2, please refer to “■ MASK OPTIONS”.

Pin no. Pin Pin no. Pin Pin no. Pin Pin no. Pin

81 N.C. 89 AD2 97 N.C. 105 OE

82 A15 90 AD1 98 04 106 N.C.

83 A12 91 AD0 99 O5 107 A11

84 AD7 92 N.C. 100 O6 108 A9

85 AD6 93 O1 101 07 109 A8

86 AD5 94 O2 102 O8 110 A13

87 AD4 95 O3 103 CE 111 A14

88 AD3 96 VSS 104 A10 112 VCC

MB89560A Series

DS07-12555-3E 9

■PIN DESCRIPTION

(Continued)

Pin no. Pin name I/O circuit

type Function

LQFP*1

LQFP*2MQFP*3

QFP*4

43 45 X0 ACrystal or other resonator connector pins for the main clock.

The external clock can be connected to X0. When this is done,

be sure to leave X1 open.

44 46 X1

42 44 MODA C Memory access mode setting pins.

Connect directly to VSS.

Hysteresis input type.

39 41 RST D

Reset I/O pin

This pin is a CMOS output type with a pull-up resistor, and a

hysteresis input type.

“L” is output from this pin by an internal reset request (optional).

The internal circuit is initialized by the input of “L”.

49 to 52 51 to 54 P24/INT20

P27/INT23 E

General-purpose CMOS I/O ports

Also serve as an external interrupt 2 input (wake-up function).

External interrupt 2 input is hysteresis input.

Selectable pull-up resistor.

38,

36 to 30 40,

38 to 32

P10/INT10

P17/INT17 E

General-purpose CMOS I/O ports

Also serve as input for external interrupt 1 input.

External interrupt 1 input is hysteresis input.

Selectable pull-up resistor.

60 62 P44/UCK/

SCK1 E

General-purpose CMOS I/O ports

Also serve as the clock I/O for the High-speed UART and Serial

I/O.

The peripheral is a hysteresis input type.

Selectable pull-up resistor.

61 63 P45/UO/

SO1 FGeneral-purpose CMOS I/O ports

Also serves as the data output for the High-speed UART and

Serial I/O.

62 64 P46/UI/SI1 G N-ch open drain general-purpose I/O ports

Also serves as the data input for the High-speed UART and Serial I/O.

The peripheral is a hysteresis input type.

63 65 P47/PWC G N-ch open drain general-purpose I/O port

Also serve as the external clock input for PWC.

The peripheral is a hysteresis input.

56 58 P40/WTO/

TO11 FGeneral-purpose CMOS I/O port

Also serves as an 8/16-bit timer/counter output and PWC output.

MB89560A Series

10 DS07-12555-3E

(Continued)

Pin no. Pin name I/O circuit

type Function

LQFP*1

LQFP*2MQFP*3

QFP*4

57 59 P41/HCK/

TO12 F

General-purpose CMOS I/O port

Also serves as an 8/16-bit timer/counter output.

and half of main clock output

Selectable pull-up resistor.

45 47 P20/SI E

General-purpose CMOS I/O port

Also serves as the data input for the serial I/O.

The peripheral is a hysteresis input type.

Selectable pull-up resistor.

46 48 P21/SO F General-purpose CMOS I/O port

Also serves as the data output for the serial I/O.

Selectable pull-up resistor.

47 49 P22/SCK E

General-purpose CMOS I/O port

Also serves as the clock I/O for the serial I/O.

The peripheral is a hysteresis input type.

Selectable pull-up resistor.

48 50 P23/PPG1 F General-purpose CMOS I/O port

Also serves as the 6 bit PPG output pin.

Selectable pull-up resistor.

54 56 P30/SCL G N-ch open-drain general-purpose I/O port

Clock I/O pin for I2C interface

55 57 P31/SDA G N-ch open-drain general-purpose I/O port

Data I/O pin for I2C interface

65 67 C0 —Function as capacitor connection pin in the products with a

booster.

64 66 C1

59 61 P43/

PWM2/

PPG2 F

General-purpose CMOS I/O port

Also serves PWM wave output for the 8-bit PWM timer 1 and

as 12 bit programmable pulse generator output.

Selectable pull-up resistor.

58 60 P42/

PWM1/

EC1 E

General-purpose CMOS I/O port

Also serves as the PWM wave output and external clock for

the 8/16 bit timer counter.

Selectable pull-up resistor.

28 to 21 30 to 23 P00/AN0

P07/AN7 JGeneral-purpose CMOS I/O ports

Also serve as the analog input for the A/D converter.

Selectable pull-up resistor.

MB89560A Series

DS07-12555-3E 11

(Continued)

*1: FPT-80P-M21

*2: FPT-80P-M22

*3: MQP-80C-P01

*4: FPT-80P-M06

*5: When MB89567A / MB89567AC / MB89PV560-101 / MB89PV560-102 is used, this pin will become NC pin

without internal connection. There is no problem to leave pins open, to fix pins at VCC and to fix pins at VSS.

When MB89P568-101 or MB89P568-102 is used, this pin must be connected to VSS.

Pin no. Pin name I/O circuit

type Function

LQFP*1

LQFP*2MQFP*3

QFP*4

10 to 12,

14 to 18 12 to 14,

16 to 20

P60/

SEG16 to

P67/

SEG23

HN-ch open-drain general-purpose output ports

Also serve as an LCD controller/driver segment output.

2 to 9 4 to 11

P50/SEG8

P57/

SEG15

HN-ch open-drain general-purpose output ports

Also serve as an LCD controller/driver segment output.

74 to 80, 1 76 to 80,

1 to 3 SEG0 to

SEG7 I LCD controller/driver segment output-only pins

70 to 73 72 to 75 COM0

COM3 I LCD controller/driver common output-only pins

66 to 69 68 to 71 V0 to V3 — LCD driving power supply pins.

40 42 X0A BCrystal or other resonator connector pins for the subclock

(Subclock: 32.768 kHz)

41 43 X1A

53 55 Vcc — Power supply pin

37 39 C — Capacitor connection pin *5

13 15 Vss — Power supply (GND) pin

20 22 AVcc — A/D converter power supply pin

19 21 AVR — A/D converter reference voltage input pin

29 31 AVss — A/D converter power supply pin

Use this pin at the same voltage as VSS.

MB89560A Series

12 DS07-12555-3E

• For External EPROM Socket (MB89PV560 ONLY)

Pin no. Pin name I/O Function

A15

A12

O Address output pins

O3 I Data input pins

96 Vss O Power supply (GND) pin

100

101

102

I Data input pins

103 CE OROM chip enable pin

Outputs “H” during standby.

104 A10 O Address output pin

105 OE/Vpp OROM output enable pin

Outputs “L” at all times.

107

108

109

A11

A8 O

Address output pins

110 A13 O

111 A14 O

112 Vcc O EPROM power supply pin

106

N.C. — Internally connected pins

Be sure to leave them open.

MB89560A Series

DS07-12555-3E 13

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

A Main clock (main clock crystal oscillator)

• At an oscillation feedback resistor of

approximately 1 MΩ/5.0 V

B Subclock (subclock crystal oscillator)

• At an oscillation feedback resistor of

approximately 4.5 MΩ/5.0 V

C • Hysteresis input

D • CMOS output

• Hysteresis input

• At an output pull-up resistor (P-ch)

of approximately 50 kΩ/5.0 V

E • CMOS output

•CMOS input

• The peripheral is a hysteresis input

type.

• Selectable pull-up resistor (P-ch) of

approximately 50 kΩ/5.0 V

N-ch

X0 P-ch

P-ch

Main clock control signal

N-ch

X1A

X0A

P-ch

Sub clock control signal

P-ch

N-ch

P-ch

N-ch

Pull-up control

Port

Peripheral

MB89560A Series

14 DS07-12555-3E

(Continued)

Type Circuit Remarks

F • CMOS output

• CMOS input

• Selectable pull-up resistor (P-ch) of

approximately 50 kΩ/5.0 V

G • N-ch open-drain input/output

• CMOS input

• The peripheral is a hysteresis input

type.

(P30,P31 are OR-type input for I2C)

H • N-ch open-drain output

• CMOS input

• LCD controller/driver segment

output

I • LCD controller/driver common/

segment output

J • General CMOS I/O

• Analog input (A/D converter)

• Selectable pull-up resistor (P-ch) of

approximately 50 kΩ/5.0 V

• Pull-up resistors must be disabled

when used as an analog input.

P-ch

N-ch

Pull-up resistor

control register

Port

N-ch

Port

Peripheral

N-ch

P-ch

N-ch

Port

N-ch

P-ch

N-ch

P-ch

N-ch

ADEN

Pull-up control

Port

Analog input

MB89560A Series

DS07-12555-3E 15

■HANDLING DEVICES

1. Preventing Latchup

Latchup ma y occur on CMOS ICs if voltage higher than V CC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving un used input pins open could cause malfunctions . The y should be connected to a pull-up or pull-do wn

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DVCC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated r ange, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore

important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P

value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

6. Precautions when Using an External Clock

Even when an exter nal clock is used, oscillation stabilization time is required for power-on reset and wake-up

from stop mode.

7. Unused LCD dedicated pins

When LCD dedicated pins are not in use, keep it open.

8. Ports shared with SEG pin

When using port shared with SEG pin, be sure that the input voltage to port does not exceed the voltage of V3

(SEG driving voltage). This is particularly important to those devices with booster . When power-on or reset, SEG

pin will output an initial value of “L”.

9. LCD not in use

When LCD is not in use, connect the V3 pin to Vcc and keep other LCD dedicated pins open.

10. Wild Register function

In MB89PV560, wild register function cannot be evaluated. To evaluate the wild register function, use MB89P568.

11. Programming operation on RAM

Program operation debugging at RAM is not possible even when using MB89PV560.

12. Note to Noise in the External Reset Pin (RST)

If the reset pulse applied to the e xternal reset pin (RST) does not meet the specifications, it ma y cause malfunc-

tions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) .

MB89560A Series

16 DS07-12555-3E

■PROGRAMMING TO THE EPROM ON THE MB89P568

The MB89P568 is an OTPROM version of the MB89567A and MB89567AC.

1. Features

• 48-Kbyte PROM on chip

• Equivalency to the MBM27C1001 in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

3. Programming to the EPROM

In EPROM mode, the MB89P568 functions equivalent to the MBM27C1001. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C1001.

(2) Load program data into the EPROM programmer at 4000H to FFFFH

(3) Program with the EPROM programmer.

0000 H

0080 H

0480 H

FFFF H

I/O

RAM

4000 H

FFFF H

4000 H

EPROM mode

(Corresponding addresses on

the EPROM programmer)

Not available

Program

area

(PROM)

Normal operation

Program

area

(PROM)

MB89560A Series

DS07-12555-3E 17

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure.

5. Programming Yield

All bits cannot be programmed at FUJITSU MICR OELECTRONICS shipping test to a b lanked OTPROM micro-

computer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.

Program, verify

+100 °C, 48 h

Read

Assembly

MB89560A Series

18 DS07-12555-3E

■PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C512-20TV

2. Memory Space

3. Programming to EPROM

(1) Set the EPROM programmer to the MBM27C512.

(2) Load program data into the EPROM programmer at 2000H to FFFFH.

(3) Program to 2000H to FFFFH with the EPROM programmer.

0000 H

0080 H

0480 H

FFFF H

I/O

RAM

2000 H

FFFF H

2000 H

Normal operation EPROM mode

(Corresponding addresses on

the EPROM programmer)

Not available

Program area

(PROM)

Program area

(PROM)

MB89560A Series

DS07-12555-3E 19

■BLOCK DIAGRAM

Oscillator

Clock controller

Low-power oscillator

(32.768 kHz)

1K Byte RAM

F2MC-8L

CPU

32K*6 Byte ROM

Other pins

MODA, C,*5 VCC, VSS

Internal data bus

21-bit Time-base

UART/SIO

Port 2

CMOS I/O port

Port 5 & Port 6

*1: Output of Main clock oscillation/2.

*2: I2C is not available in MB89567A.

*3: Selected by mask option

*4: Can be used as a 16-bit timer/counter by connecting Timer 1 output to Timer 2 input.

*5: C pin becomes NC pin in MB89567A/AC/PV560

*6: 48 K byte ROM for MB89P568

P10/INT10

to P17/INT17

P23/PPG1

P20/SI

P21/SO

P22/SCK

timer

Main clock

Watch prescaler

Reset circuit

(Watchdog timer)

RST

X0A

X1A

Port 1

CMOS I/O port

External interrupt 2

(wake-up function)

Port 4

P24/INT20

to P27/INT23 4

Port 0

CMOS I/O port

10-bit A/D converter

P00/AN0

to P07/AN7

AVCC

AVSS

N-ch open-drain

output port

LCD controller/

driver

Display RAM

(12 bytes)

8-bit PWM timer 1

P60/SEG16 to

P63/SEG19

P64/SEG20 to

P67/SEG23

P50/SEG8 to

P53/SEG11

P54/SEG12 to

P57/SEG15

SEG0 to SEG7

COM0 to COM3

V0 to V3

Subclock

8-bit PWM timer 2

AVR

Port 3

N-ch open drain I/O port

I2C*2P30/SCL

P31/SDA

C0*3

C1*3

8-bit

timer/counter 1

(Timer 1)

8-bit

timer/counter 2

(Timer 2)

PWC

SIO

P40/WTO/TO11

P41/HCK*1/TO12

P42/PWM1/EC1

P43/PWM2/PPG2

P44/UCK/SCK1

P45/UO/SO1

P46/UI/SI1

P47/PWC

Wild register

High-speed

External interrupt 1

Booster Option

12 bit PPG

6 bit PPG

UART

CMOS I/O port

(P46 and P47 are N-ch

Open-drain I/O Type)

MB89560A Series

20 DS07-12555-3E

■CPU CORE

1. Memory Space

The microcontrollers of the MB89560A series offer a memory space of 64 Kbytes f or storing all of I/O, data, and

program areas . The I/O area is located the lowest address. The data area is pro vided immediately abo ve the I/

O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89560A series is structured as illustrated below.

0000 H

0080 H

0100 H

4000 H

MB89P568-101,102

I/O

RAM

0000 H

0080 H

0100 H

0200 H

8000 H

FFFF H

MB89567A, MB89567AC

I/O

RAM

FFFF H

0200 H

FFC0

HFFC0

0480 H

0000 H

0080 H

0100 H

2000 H

MB89PV560-101,102

I/O

RAM

ROM

FFFF H

0200 H

FFC0

0480 H

*2 *2 *2

0480 H

0492 H0492 H

0492 H

*1 : MB89P568-101,102 has OTP ROM inside.

*2 : Wild register setting registers

Memory space

Access

prohibited

Access

prohibited

Access

prohibited

External*1

ROM

External*1

ROM

Vector table

(Reset • Interrupt • Vector call instruction)

MB89560A Series

DS07-12555-3E 21

2. Registers

The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following registers are provided:

Program counter (PC) : A 16-bit register for indicating specifies instruction storage positions.

Accumulator (A) : A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which perf orms arithmetic operations with the accumulator when

the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX) : A 16-bit register for index modification

Extra pointer (EP) : A 16-bit pointer for indicating a memory address

Stack pointer (SP) : A 16-bit register for indicating a stack area

Program status (PS) : A 16-bit register for storing a register pointer, a condition code

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

P C

I X

E P

S P

P S

FFFDH

Initial value

16 bits

: Program counter

: Accumulator

: Temporally accumulator

: Indexing register

: Extra pointer

: Stuck pointer

: Program status

Undefined

I Flag = 0, IL1, 0 = 11

other bits are undefined.

15 14 13 12 11 10 9 8

H I IL1 IL0 N Z V C

CCR

76543210

Va-

cancy Va-

cancy

• Structure of program status

MB89560A Series

22 DS07-12555-3E

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag : Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag : Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

N-flag : Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag : Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag : Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag : Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

The following general-purpose registers are provided :

General-purpose registers : An 8-bit resister for storing data

IL1 IL0 Interrupt level High-low

00 1High

Low = no interrupt

10 2

11 3

"0" "0" "0" "1""0" "0" "0" "0" R0 b2 b1 b0

R4 R3 R2 R1

A11 A10

A9 A8

A15 A14 A13 A12

A3 A2 A1A7 A6 A5 A4 A0

RP Upper Operation Code

lower

• Rule for Conversion of Actual Addresses of the General-purpose Register Area

Generated address

MB89560A Series

DS07-12555-3E 23

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers. Up to a total of 32 banks can be used. The bank currently in use is indicated b y the register bank

pointer (RP).

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

• Register Bank Configuration

This address = 0100H+8× (RP)

32 bank (MB89567A/567AC)

Memory range

MB89560A Series

24 DS07-12555-3E

■ I/O MAP

(Continued)

Address Register name Register Description Read/Write Initial value

00HPDR0 Port 0 data register R/W XXXXXXXXB

01HDDR0 Port 0 data direction register W 00000000B

02HPDR1 Port 1 data register R/W XXXXXXXXB

03HDDR1 Port 1 data direction register W 00000000B

04H to 06H(Vacancy)

07HSYCC System clock control register R/W XXXMM100B

08HSTBC Standby control register R/W 00010XXXB

09HWDTC Watchdog timer control register W 0XXXXXXXB

0AHTBTC Timebase timer control register R/W 00XXX000B

0BHWPCR Watch prescaler control register R/W 00XX0000B

0CHPDR2 Port 2 data register R/W XXXXXXXXB

0DHDDR2 Port 2 data direction register R/W 00000000B

0EHPDR3 Port 3 data register R/W XXXXXX11B

0FHPDR4 Port 4 data register R/W XXXXXXXXB

10HDDR4 Port 4 direction register R/W XX000000B

11HPDR5 Port 5 data register R/W 00000000B

12H(Vacancy)

13HPDR6 Port 6 data register R/W 00000000B

14H to 19H(Vacancy)

1AHT2CR Timer2 control register R/W X00000X0B

1BHT2DR Timer2 data register R/W XXXXXXXXB

1CHT1CR Timer1 control register R/W X00000X0B

1DHT1DR Timer1 data register R/W XXXXXXXXB

1EH to 21H(Vacancy)

22HSMC11 UART1 mode control register 1 R/W 00000000B

23HSRC1 UART1 mode data register R/W XX011000B

24HSSD1 UART1 status/data register R/W 00100X1XB

25HSIDR1/SODR1 UART1 data register R/W XXXXXXXXB

26HSMC12 UART1 mode control register 2 R/W XX100001B

27HCNTR1 PWM control register 1 R/W 00000000B

28HCNTR2 PWM control register 2 R/W 000X0000B

29HCNTR3 PWM control register 3 R/W X000XXXXB

2AHCOMR1 PWM compare register 1 W XXXXXXXXB

2BHCOMR2 PWM compare register 2 W XXXXXXXXB

2CHPCR1 PWC pulse width control register 1 R/W 000XX000B

MB89560A Series

DS07-12555-3E 25

(Continued)

Address Register name Register Description Read/Write Initial value

2DHPCR2 PWC pulse width control register 2 R/W 00000000B

2EHRLBR PWC reload buffer register R/W XXXXXXXXB

2FHSMC21 UART2/SIO mode control register R/W 00000000B

30HSMC22 UART2/SIO mode control register 2 R/W 00000000B

31HSSD2 UART2/SIO status/data register R/W 00001XXXB

32HSIDR2/SODR2 UART2/SIO data register R/W XXXXXXXXB

33HSRC2 UART2/SIO rate control register R/W XXXXXXXXB

34HADC1 A/D control register 1 R/W X00000X0B

35HADC2 A/D control register 2 R/W X0000001B

36HADDL A/D data register L R/W XXXXXXXXB

37HADDH A/D data register H R/W XXXXXXXXB

38HRCR21 PPG control register 1(PPG2) R/W 00000000B

39HRCR23 PPG control register 3(PPG2) R/W 0X000000B

3AHRCR22 PPG control register 2(PPG2) R/W XX000000B

3BHRCR24 PPG control register 4(PPG2) R/W XX000000B

3CH to 3EH(Vacancy)

3FHEIC1 External interrupt 1 control register 1 R/W 00000000B

40HEIC2 External interrupt 1 control register 2 R/W 00000000B

41HEIC3 External interrupt 1 control register 3 R/W 00000000B

42HEIC4 External interrupt 1 control register 4 R/W 00000000B

43H to 50H(Vacancy)

51HIBSR I2C bus status register R 00000000B

52HIBCR I2C bus control register R/W 00000000B

53HICCR I2C clock control register R/W 000XXXXXB

54HIADR I2C address register R/W XXXXXXXXB

55HIDAR I2C data register R/W XXXXXXXXB

56HEIE2 External interrupt 2 enable register R/W XXXX0000B

57HEIF2 External interrupt 2 flag register R/W XXXXXXX0B

58HRCR1 PPG control register 1(PPG1) R/W 00000000B

59HRCR2 PPG control register 2(PPG1) R/W 0X000000B

5AHCKR Clock Output control register R/W 00000000B

5BHLCR1 LCD controller/driver control register 1 R/W 00010000B

5CHLCR2 LCD controller/driver control register 2 R/W 00000000B

5DHLCR3 LCD controller/driver control register 3 R/W XX000000B

5EHLDR1 LCD data register 1 R/W XXXXXXXXB

MB89560A Series

26 DS07-12555-3E

(Continued)

Read/write access symbols

R/W : Readable and writable

R : Read-only

W : Write-only

Initial value symbols

0 : The initial value of this bit is “0”.

1 : The initial value of this bit is “1”.

X : The initial value of this bit is undefined.

M : The initial value of this bit is determined by mask option.

Note : Do not use vacancies.

Address Register name Register Description Read/Write Initial value

5FH(Vacancy)

60H to 6BHVRAM Display RAM R/W XXXXXXXXB

6CH to 6FH(Vacancy)

70HSMR Serial I/O mode register R/W 00000000B

71HSDR Serial I/O data register R/W XXXXXXXXB

72HPURR0 Pull-up resistor register 0 R/W 11111111B

73HPURR1 Pull-up resistor register 1 R/W 11111111B

74HPURR2 Pull-up resistor register 2 R/W 11111111B

75HPURR4 Pull-up resistor register 4 R/W XX111111B

76H(Vacancy)

77HWREN Wild register enable register R/W XX000000B

78HWROR Wild register data test register R/W XX000000B

79HADEN A/D port input enable register R/W 11111111B

7AH(Vacancy)

7BHILR1 Interrupt level setting register 1 W 11111111B

7CHILR2 Interrupt level setting register 2 W 11111111B

7DHILR3 Interrupt level setting register 3 W 11111111B

7EHILR4 Interrupt level setting register 4 W 11111111B

7FHITR Interrupt test register Access

Prohibited 11111111B

MB89560A Series

DS07-12555-3E 27

■WILD REGISTER I/O MAP

Read/write access symbols

R/W : Readable and writable

R : Read-only

W : Write-only

Initial value symbols

0 : The initial value of this bit is “0”.

1 : The initial value of this bit is “1”.

X : The initial value of this bit is undefined.

M : The initial value of this bit is determined by mask option.

Note : Do not use vacancies.

Address Register name Register description Read/Write Initial value

480HWRARH1 Wild register high-byte address register1 R/W XXXXXXXXB

481HWRARL1 Wild register low-byte address register1 R/W XXXXXXXXB

482HWRDR1 Wild register data register1 R/W XXXXXXXXB

483HWRARH2 Wild register high-byte address register2 R/W XXXXXXXXB

484HWRARL2 Wild register low-byte address register2 R/W XXXXXXXXB

485HWRDR2 Wild register data register2 R/W XXXXXXXXB

486HWRARH3 Wild register high-byte address register3 R/W XXXXXXXXB

487HWRARL3 Wild register low-byte address register3 R/W XXXXXXXXB

488HWRDR3 Wild register data register3 R/W XXXXXXXXB

489HWRARH4 Wild register high-byte address register4 R/W XXXXXXXXB

48AHWRARL4 Wild register low-byte address register4 R/W XXXXXXXXB

48BHWRDR4 Wild register data register4 R/W XXXXXXXXB

48CHWRARH5 Wild register high-byte address register5 R/W XXXXXXXXB

48DHWRARL5 Wild register low-byte address register5 R/W XXXXXXXXB

48EHWRDR5 Wild register data register5 R/W XXXXXXXXB

48FHWRARH6 Wild register high-byte address register6 R/W XXXXXXXXB

490HWRARL6 Wild register low-byte address register6 R/W XXXXXXXXB

491HWRDR6 Wild register data register6 R/W XXXXXXXXB

MB89560A Series

28 DS07-12555-3E

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V)

(Continued)

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage VCC

AVCC VSS – 0.3 VSS + 6.0 V MB89567A, MB89567AC,

MB89P568 and MB89PV560*1

AVR must not exceed “AVcc + 0.3V”.

AVR VSS – 0.3 VSS + 6.0 V

LCD power voltage V0 to V3 VSS – 0.3 VSS + 6.0 V V0 to V3 should not exceed Vcc

Without booster

Program voltage VPP VSS – 0.6 VSS +13.0 V Only for the MB89P568

Input voltage VI

VSS – 0.3 VCC + 0.3 V For pins other than P30, P31, P46,

P47, P50 to P57 and P60 to P67

VSS – 0.3 VCC + 0.3 V P50 to P57, P60 to P67

Resister Ladder option

VSS – 0.3 V3 V P50 to P57, P60 to P67

LCD booster option

VSS – 0.3 VSS + 6.0 V For P30, P31, P46, P47

Output voltage VO

VSS – 0.3 VCC + 0.3 V For pins other than P30, P31, P46,

P47, P50 to P57 and P60 to P67

VSS – 0.3 VCC + 0.3 V P50 to P57, P60 to P67

Resister Ladder option

VSS – 0.3 V3 V P50 to P57, P60 to P67

LCD booster option

VSS – 0.3 VSS + 6.0 V For P30, P31, P46, P47

“L” level maximum output current IOL ⎯15 mA For pins other than P20 to P27

30 mA For P20 to P27 only

“L” level average output current IOLAV ⎯4 mA For pins other than P20 to P27*2

15 mA For P20 to P27 only*2

“L” level total maximum output

current ΣIOL ⎯100 mA

“L” level total average output

current ΣIOLAV ⎯60 mA *2

“H” level maximum output current IOH ⎯– 15 mA For pins other than P20 to P27, P30,

P31, P46, P47, P50 to P57, P60 to

P67

– 30 mA For P20 to P27 only

“H” level average output current IOHAV ⎯– 4 mA For pins other than P20 to P27*2

– 15 For P20 to P27 only*2

MB89560A Series

DS07-12555-3E 29

(Continued) (AVSS = VSS = 0.0 V)

*1 : Use AVCC and VCC set at the same voltage.

Take care so that AVR does not exceed AVCC + 0.3 V, such as when power is turned on.

Take care so that AVCC does not exceed VCC, such as when power is turned on.

*2 : Average value (operating current × operating rate)

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Rating Unit Remarks

Min Max

“H” level total maximum output

current ΣIOH ⎯– 50 mA

“H” level total average output

current ΣIOHAV ⎯– 30 mA *2

Power consumption PD⎯300 mW

Operating temperature TA– 40 + 85 °C

Storage temperature Tstg – 55 + 150 °C

MB89560A Series

30 DS07-12555-3E

2. Recommended Operating Conditions (AVSS = VSS = 0.0 V)

* : These values depend on the operating conditions and the analog assurance range. See Figure “Operating Voltage

vs. Main Cloc k Operating Frequency (MB89567A, MB89567AC) ”, “Operating V oltage vs. Main Clock Operating

Frequency (MB89P568/MB89PV560) ” and “6. A/D Converter Electrical Characteristics”.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Max

Power supply voltage VCC

AVCC

2.2* 5.5* V For MB89567A and MB89567AC

1.5 5.5 V Retains the RAM state in stop mode

for MB89567A and MB89567AC

2.7* 5.5* V For MB89PV560 and MB89P568

1.5 5.5 V Retains the RAM state in stop mode

for MB89PV560 and MB89P568

LCD power voltage V0 to V3 Vss VCC V

Liquid crystal power supply range:

without booster

(The best value is according to the

specification of LCD used.)

A/D converter reference input

voltage AVR 3.5 AVCC V

Operating temperature TA– 40 + 85 °C

MB89560A Series

DS07-12555-3E 31

“Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC) and “Operating Voltage vs.

Main Clock Oper ating F requency (MB89P568/MB89PV560) indicate the operating frequency of the e xternal oscil-

lator at an instruction cycle of 4/FCH

2.0

4.0

5.0

3.0

1.0

4.0 2.0 0.40.8

2.7

3.5

0.32

5.5

2.2

1.0 3.0 4.02.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5

Operating

Voltage (V) A/D Converter accuracy assurance range: Vcc = AVcc =3.5 V to 5.5 V

Main clock

operating Freq. (MHz)

Operation assurance range

Min execution time

(inst. cycle) (μs)

Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC)

Instruction cycle: 4/Fc

MB89560A Series

32 DS07-12555-3E

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

2.0

3.0

2.5

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

4.0 2.0 0.40.8

3.5

12.0 11.0 12.5

0.32

2.7

2.2

4.0

4.5

5.0

5.5

Operating

Voltage (V) A/D Converter accuracy assurance range: Vcc = AVcc = 3.5 V to 5.5 V

Main clock

operating Freq. (MHz)

Operation assurance range

Min execution time

(inst. cycle) (μs)

Operation assurance : TA = −10 °C to +55 °C (Only for MB89P568)

Operating Voltage vs. Main Clock Operating Frequency (MB89P568/MB89PV560)

Instruction cycle: 4/Fc

MB89560A Series

DS07-12555-3E 33

3. DC Characteristics (power supply voltage : 5.0V)

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

“H” level

input voltage

VIH

P00 to P07,

P10 to P17,

P20 to P27,

P30, P31,

P40 to P45,

P50 to P57,

P60 to P67

—0.7 V

CC —VCC + 0.3 V CMOS

VIHS

RST, MODA,

INT10 to INT17,

INT20 to INT23,

SI,SCK,EC1,UCK,

SCK1,UI,SI1,PWC

—0.8 VCC —VCC + 0.3 V Hysteresis

VIHSMB SCL, SDA —V

SS +1.4 — VSS + 5.5 V SMB input

buffer selected

VIHI2C —0.7 VCC —VSS + 5.5 V I2C input buffer

selected

“L” level

input voltage

VIL

P00 to P07,

P10 to P17,

P20 to P27,

P30, P31,

P40 to P45,

P50 to P57,

P60 to P67

—V

SS − 0.3 — 0.3 VCC VCMOS

VILS

RST, MODA,

INT10 to INT17,

INT20 to INT23,

SI,SCK,EC1,UCK,

SCK1,UI,SI1,PWC

—VSS − 0.3 — 0.2 VCC V Hysteresis

VILSMB SCL, SDA ⎯VSS − 0.3 — VSS + 0.6 V SMB input

buffer selected

VILI2C —VSS − 0.3 — 0.3 VCC VI2C input buffer

selected

Open-drain

output pin

application

voltage

P60 to P67,

P50 to P57 —V

SS − 0.3 — VCC + 0.3 V Resister

Ladder option

P60 to P67,

P50 to P57 —V

SS − 0.3 — V3 V LCD booster

option

P46, P47, P30,

P31 —V

SS − 0.3 — VSS + 5.5 V

“H” level

output

voltage VOH

P00 to P07,

P10 to P17,

P40 to P45 IOH = –2.0 mA 4.0 — — V

P20 to P27 IOH = –15.0 mA 4.0 — —

MB89560A Series

34 DS07-12555-3E

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

“L” level

output

voltage VOL

P00 to P07,

P10 to P17,

P30, P31,

P40 to P47,

P50 to P57,

P60 to P67,

RST

IOL = 4.0 mA — — 0.4 V

P20 to P27 IOL = 15.0 mA — — 0.4

Input leakage

current

(High-Z

output

leakage

current)

ILI

P00 to P07,

P10 to P17,

P20 to P27,

P40 to P45 0.0 V < VI < VCC

− 5—+5μAWithout

pull-up

Resistor

P50 to P57,

P60 to P67 − 5— +5μAResistor

Ladder

option

P50 to P57,

P60 to P67 0.0 V < VI < V3 − 5—+5μALCD booster

option

MODA 0.0 V < V I < VCC − 10 — +10 μAMB89PV560

MB89P568

Open-drain

output

leakage

current

ILIOD

P50 to P57,

P60 to P67 0.0 V < VI < VCC ——+5μAResistor

Ladder

option

P50 to P57,

P60 to P67 0.0 V < VI < V3 — — +5 μALCD booster

option

P30, P31,

P46, P47 0.0 V < VI < Vss

+ 5.5 V ——+5μA

Pull-up

resistance RPULL

P00 to P07,

P10 to P17,

P20 to P27,

P40 to P45,

RST

VI = 0.0 V 25 50 100 kΩ

When pull-up

resistor

selected

except RST

Pull-down

resistance RMODA MODA VI = 3.0 V 50 100 200 kΩMB89567A/

MB89567AC

Power supply

current *1

ICC1

VCC

FCH = 10 MHz,

tinst*2 = 0.4 μs,

Main clock run

mode

—1520

MB89PV560

MB89P568

—813 MB89567A

MB89567AC

ICC2

FCH = 10 MHz,

tinst*2 = 6.4 μs,

Main clock run

mode

—58.5

MB89PV560

MB89P568

—1 3 MB89567A

MB89567AC

ICCS1

FCH = 10 MHz,

tinst*2 = 0.4 μs,

Main clock sleep

mode

—5 7

MB89PV560

MB89P568

—2.5 5 MB89567A

MB89567AC

MB89560A Series

DS07-12555-3E 35

(Continued) (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

*1 : The power supply current is measured at the external clock

*2 : For information on tinst, see “5. AC Characteristics (4) Instruction Cycle”.

Note : F or LCD and port multiple x pin (P50 to P57, P60 to P67), please ref er to LCD specification when the port is

used, and refer to LCD specification when used as LCD pin.

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

Power supply

current *1

ICCS2

VCC

FCH = 10 MHz,

tinst*2 = 6.4 μs,

Sleep mode

—1.5 3

MB89PV560

MB89P568

—0.7 2 MB89567A

MB89567AC

ICCL

FCL = 32.768

kHz,

Subclock mode,

TA = +25 °C

—3 7mA

MB89PV560

MB89P568

—5085μAMB89567A

MB89567AC

ICCLS

FCL = 32.768

kHz,

Subclock sleep

mode,

TA = +25 °C

—3050

μA

MB89PV560

MB89P568

—1530 MB89567A

MB89567AC

ICCT

FCL = 32.768

kHz,

TA = +25 °C,

Watch mode,

Main clock stop

mode

—

515μAMB89PV560

MB89P568

1.6 15 μAMB89567A

MB89567AC

Power supply

current *1ICCH VCC TA = +25 °C,

Subclock stop

mode —310μAMB89PV560

MB89P568

110μAMB89567A

MB89567AC

LCD divided

resistance RLCD —Between

VCC and VSS 300 500 750 kΩ

COM0 to COM3

output

impedance RVCOM COM0 to COM3

V1 to V3 = 5.0 V

—— 5kΩ

SEG0 to SEG23

output

impedance RVSEG SEG0 to SEG23 — — 15 kΩ

LCD controller/

driver leakage

current ILCDL V0 to V3,

COM0 to COM3,

SEG0 to SEG23 — − 1— 1μA

Input

capacitance CIN Other than AVCC,

AVSS, VCC, and

VSS f = 1 MHz — 10 — pF

MB89560A Series

36 DS07-12555-3E

4. DC Characteristics (power supply voltage : 3.0 V)

(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

“H” level

input voltage

VIH

P00 to P07,

P10 to P17,

P20 to P27,

P30, P31,

P40 to P45,

P50 to P57,

P60 to P67

— 0.7 VCC —VCC + 0.3 V CMOS

VIHS

RST, MODA,

INT10 to INT17,

INT20 to INT23,

SI,SCK,EC1,UCK,

SCK1,UI,SI1,PWC

— 0.8 VCC —VCC + 0.3 V Hysteresis

VIHSMB SCL, SDA —V

SS +1.4 — VSS + 5.5 V SMB input

buffer selected

VIHI2C — 0.7 VCC —VSS + 5.5 V I2C input buffer

selected

“L” level

input voltage

VIL

P00 to P07,

P10 to P17,

P20 to P27,

P30, P31,

P40 to P45,

P50 to P57,

P60 to P67

—V

SS − 0.3 — 0.3 VCC VCMOS

VILS

RST, MODA,

INT10 to INT17,

INT20 to INT23,

SI,SCK,EC1,UCK,

SCK1,UI,SI1,PWC

—VSS − 0.3 — 0.2 VCC VHysteresis

VILSMB SCL, SDA —V

SS - 0.3 — VSS + 0.6 V SMB input

buffer selected

VILI2C —VSS − 0.3 — 0.3 VCC VI2C input buffer

selected

Open-drain

output pin

application

voltage

P60 to P67,

P50 to P57 —V

SS − 0.3 — VCC + 0.3 V Resistor

Ladder option

P60 to P67,

P50 to P57 —V

SS − 0.3 — V3 V LCD booster

option

P46, P47, P30,

P31 —V

SS − 0.3 — VSS + 5.5 V

“H” level

output

voltage VOH

P00 to P07,

P10 to P17,

P40 to P45 IOH = –2.0 mA 2.4 — — V

P20 to P27 IOH = –10 mA 2.4 — —

MB89560A Series

DS07-12555-3E 37

(AVCC = VCC = 3.0V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

“L” level

output

voltage VOL

P00 to P07,

P10 to P17,

P30, P31,

P40 to P47,

P50 to P57,

P60 to P67,

RST

IOL = 4.0 mA — — 0.4 V

P20 to P27 IOL = 10 mA — — 0.4

Input leakage

current

(Hi-z output

leakage

current)

ILI

P00 to P07,

P10 to P17,

P20 to P27,

P40 to P45 0.0 V < VI < VCC

–5 — +5μAWithout

pull-up

Resister

P50 to P57,

P60 to P67 –5 — +5μAResister

Ladder

option

P50 to P57,

P60 to P67 0.0 V < VI < V3 –5 — +5μALCD booster

option

MODA 0.0 V < VI < VCC –10 — +10 μAMB89PV560

MB89P568

Open-drain

output

leakage

current

ILIOD

P50 to P57,

P60 to P67 0.0 V < VI < VCC ——+5μAResister

Ladder

option

P50 to P57,

P60 to P67 0.0 V < VI < V3 — — +5 μALCD booster

option

P30, P31,

P46, P47 0.0 V < VI < Vss

+ 5.5 V ——+5μA

Pull-up

resistance RPULL

P00 to P07,

P10 to P17,

P20 to P27,

P40 to P45,

RST

VI = 0.0 V 50 100 200 kΩ

When pull-up

resistor

selected

except RST

Pull-down

resistance RMODA MODA VI = 5.0 V 25 50 100 kΩMB89567A

MB89567AC

Power supply

current *1

ICC1

VCC

FCH = 10 MHz,

tinst*2 = 0.4 μs,

Main clock run

mode

—610

MB89PV560

MB89P568

—49 MB89567A

MB89567AC

ICC2

FCH = 10 MHz,

tinst*2 = 6.4 μs,

Main clock run

mode

—1.5 3

MB89PV560

MB89P568

—0.4 2 MB89567A

MB89567AC

MB89560A Series

38 DS07-12555-3E

(Continued) (AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

*1 : The power supply current is measured at the external clock

*2 : For information on tinst, see “5. AC Characteristics (4) Instruction Cycle”.

Note : F or LCD and port multiple x pin (P50 to P57, P60 to P67), please ref er to LCD specification when the port is

used, and refer to LCD specification when used as LCD pin.

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

Power supply

current *1

ICCS1

VCC

FCH = 10 MHz,

tinst*2 = 0.4 μs,

Main clock

sleep mode

—2 4

MB89PV560

MB89P568

—1 3 MB89567A

MB89567AC

ICCS2

FCH = 10 MHz,

tinst*2 = 6.4 μs,

Main clock

sleep mode

—1 2

MB89PV560

MB89P568

—0.31.5 MB89567A

MB89567AC

ICCL

FCL = 32.768

kHz,

Subclock

mode,

TA = +25 °C

—1 3mA

MB89PV560

MB89P568

—2560μAMB89567A

MB89567AC

ICCLS

FCL = 32.768

kHz,

Subclock sleep

mode,

TA = +25 °C

—1530

μA

MB89PV560

MB89P568

—825 MB89567A

MB89567AC

ICCT

FCL = 32.768

kHz,

TA = +25 °C,

Watch mode,

Main clock stop

mode

—

515μAMB89PV560

MB89P568

114μAMB89567A

MB89567AC

ICCH TA = +25 °C,

Subclock stop

mode —1 5μA

LCD divided

resistance RLCD —Between VCC

and VSS 300 500 750 kΩ

COM0 to COM3

output impedance RVCOM COM0 to COM3 V1 to V3 = 3.0 V —— 5kΩ

SEG0 to 23 output

impedance RVSEG SEG0 to SEG23 — — 15 kΩ

LCD controller/

driver leakage

current ILCDL

V0 to V3,

COM0 to COM3,

SEG0 to SEG23 —–1—1μA

Input

capacitance CIN

Other than AVCC,

AVSS, VCC, and

VSS f = 1 MHz — 10 — pF

MB89560A Series

DS07-12555-3E 39

5. AC Characteristics

(1) Reset Timing (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Notes : • tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin.

• If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause

malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external

reset pin (RST) .

(2) Power-on Reset (AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Note : Make sure that power supply rises within the selected oscillation stabilization time.

F or example, when the main clock is operating at 10 MHz (FCH) and the oscillation stabilization time select

option has been set to 218/FCH, the oscillation stabilization delay time is 26.2 ms. Therefore, the maximum

value of power supply rising time is about 26.2 ms.

Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be

varied in the course of operation, a smooth voltage rise is recommended.

Parameter Symbol Condition Value Unit Remarks

Min Max

RST “L” pulse width tZLZH — 48 tHCYL —ns

Parameter Symbol Condition Value Unit Remarks

Min Max

Power supply rising time tR—0.5 50 ms

Power supply cut-off time tOFF 1 — ms Due to repeated operations

0.2 V CC 0.2 V CC

RST

t ZLZH

0.2

V 0.2

2.0 V

0.2

OFF

MB89560A Series

40 DS07-12555-3E

(3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Clock frequency FCH X0, X1 1 — 12.5 MHz Main clock

FCL X0A, X1A — 32.768 — kHz Subclock

Clock cycle time tHCYL X0, X1 80 — 1000 ns Main clock

tLCYL X0A, X1A — 30.5 — μs Subclock

Input clock pulse width PWH

PWL X0 20 — — ns External clock

Input clock rising/falling time tCR

tCF X0 — — 10 ns External clock

PWH

0.2 VCC

X0 0.2VCC

X0 X1 X0 X1

0.2 VCC

0.8 VCC 0.8 VCC

tCR tCF

tHCYL

PWL

FCH

C1 C2

Open

X0 and X1 Timing and Conditions

Main Clock Conditions

When using a crystal oscillator

or ceramic oscillator When using an external clock

MB89560A Series

DS07-12555-3E 41

(4) Instruction Cycle (AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

Parameter Symbol Value Unit Remarks

Instruction cycle

(minimum execution time) tinst

4/FCH, 8/FCH, 16/FCH, 64/FCH μstinst = 0.32 μs when operating

at FCH = 12.5 MHz (4/FCH)

2/FCL μstinst = 61.036 μs when

operating at FCL = 32.768 kHz

0.3 V

X0A 0.3 V

0.3 V

0.7 V

LCYL

X0A X1A

X0A and X1A Timing

When using a crystal oscillator

Note : External clock is not available.

MB89560A Series

42 DS07-12555-3E

(5) Serial I/O Timing (Vcc = 5.0V, AVSS = VSS= 0.0 V, TA = –40 °C to +85 °C)

* : For information on tinst, see “(4) Instruction Cycle”.

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK, SCK1, UCK

Internal shift

clock mode

2 tinst*— μs

SCK ↓ → SO time tSLOV SCK, SO, SCK1,

SO1, UCK, UO –200 +200 ns

Valid SI → SCK ↑tIVSH SI, SCK, SI1,

SCK1, UI, UCK 200 — ns

SCK ↑ → valid SI hold time tSHIX SCK, SI, SCK1,

SI1, UCK, UI 200 — ns

Serial clock “H” pulse width tSHSL SCK, SCK1, UCK

External shift

clock mode

1 tinst*— μs

Serial clock “L” pulse width tSLSH 1 tinst*— μs

SCK ↓ → SO time tSLOV SCK, SO, SCK1,

SO1, UCK, UO 0 200 ns

Valid SI → SCK ↑tIVSH SI, SCK, SI1,

SCK1, UI, UCK 200 — ns

SCK ↑ → valid SI hold time tSHIX SCK, SI, SCK1,

SI1, UCK, UI 200 — ns

MB89560A Series

DS07-12555-3E 43

(6) Peripheral Input Timing (Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

* : For information on tinst, see “(4) Instruction Cycle”.

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Peripheral input “H” pulse width 1 tILIH1 INT10 to INT17,

INT20 to INT23,

EC, PWC —2 tinst*— μs

Peripheral input “L” pulse width 1 tIHIL1 2 tinst*— μs

tSCYC

tSLOV

tSHIXtIVSH

SCK

SCK1

UCK 0.8 VCC

0.2 VCC 0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SO1

SI1

tSLSH

tSLOV

tSHIXtIVSH

SCK

SCK1

UCK 0.8 VCC

0.2 VCC

0.8VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SO1

SI1

0.2 VCC

tSHSL

0.8 VCC

Internal Shift Clock Mode

External Shift Clock Mode

0.2 VCC

0.8 VCC

tIHIL1

0.8 VCC

0.2 VCC

tILIH1

INT10 to INT17,

INT20 to INT23,

EC, PWC

MB89560A Series

44 DS07-12555-3E

(7) I2C timing (Vcc = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

*1 : For information in tinst, see “ (4) Instruction Cycle”.

*2 : M is defined in the ICCR CS4 and CS3 (bit 4, bit 3) . For details, please refer to the H/W manual register

explanation.

*3 : N is defined in the ICCR CS2 to CS0 (bit 2 to bit 0) .

*4 : When the interrupt period is greater than SCL “L” width, SDA and SCL output (Standard) value is based on

hypothesis when rising time is 0 ns.

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Start condition output tSTA SCL

SDA —1/4 tinst*1 ×

M*2 x N*3 - 20 1/4 tinst ×

M*2 x N*3 + 20 ns Master

mode

Stop condition output tSTO SCL

SDA — 1/4 tinst ×

(M*2 × N*3 + 8) - 20 1/4 tinst ×

(M*2 × N*3 + 8) + 20 ns Master

mode

Start condition detect tSTA SCL

SDA — 1/4 tinst × 6 + 40 — ns

Stop condition detect tSTO SCL

SDA — 1/4 tinst × 6 + 40 — ns

Re-start condition

output tSTASU SCL

SDA —1/4 tinst ×

(M*2 × N*3 + 8) - 20 1/4 tinst ×

(M*2 × N*3 + 8) + 20 ns Master

mode

Re-start condition

detect tSTASU SCL

SDA — 1/4 tinst × 4 + 40 — ns

SCL output LOW

width tLOW SCL — 1/4 tinst ×

M*2 × N*3 - 20 1/4 tinst ×

M*2 × N*3 + 20 ns Master

mode

SCL output HIGH

width tHIGH SCL — 1/4 tinst ×

(M*2 × N*3 + 8) - 20 1/4 tinst ×

(M*2 × N*3 + 8) + 20 ns Master

mode

SDA output delay tDO SDA — 1/4 tinst × 4 - 20 1/4 tinst × 4 + 20 ns

SDA output setup

time after interrupt tDOSU SDA — 1/4 tinst × 4 - 20 — ns *4

SCL input LOW

pulse width tLOW SCL — 1/4 tinst × 6 + 40 — ns

SCL input HIGH

pulse width tHIGH SCL — 1/4 tinst × 2 + 40 — ns

SDA input setup time tSU SDA — 40 — ns

SDA hold time tHO SDA — 0 — ns

MB89560A Series

DS07-12555-3E 45

ACK

DOSU

HIGH

STO

STA

STASU

HIGH

LOW

876

SDA

SCL

Data transmit (master/slave)

Data receive (master/slave)

MB89560A Series

46 DS07-12555-3E

6. A/D Converter Electrical Characteristics

(1) For MB89567A/AC A/D Converter (AVcc = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

*1 : For information on tinst, see “(4) Instruction Cycle” in “5. AC Characteristics”.

*2 : When A/D conversion is not in operation, and the CPU is in STOP mode.

*3 : Included sampling time

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

Resolution

—

———10bit

1LSB =

(AVR – AVss) /

1024

Total error

AVR=AVCC

——±3.0 LSB

Non-linearity error — — ±2.5 LSB

Differential

linearity error ——±1.9 LSB

Zero transition

voltage VOT AVss −

1.5 LSB AVss +

0.5 LSB AVss +

2.5 LSB V

Full-scale

transition voltage VFST AVR −

3.5 LSB AVR −

1.5 LSB AVR +

1.5 LSB V

Interchannel

disparity

—

——4LSB

A/D mode

conversion time *3

—

—60 t

inst*1—

μs

A/D Sampling

time —16 t

inst*1—

Analog port input

current IAIN AN0

AN7

——10μA

Analog input

voltage VAIN AVss — AVR V

Power supply

current

AVCC

——46mA

when A/D

conversion is

activated

IAH TA = +25 °C—1 5μAwhen A/D

conversion is

stopped

Reference

voltage —

AVR

—AVss+3.5—AV

CC V

Reference

voltage supply

current

IRA/D is Activated — 200 — μA

IRH A/D is Stopped — — 5 μA*2

MB89560A Series

DS07-12555-3E 47

(2) For MB89P568/PV560 A/D Converter (AVcc=3.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)

*1 : For information on tinst, see “(4) Instruction Cycle” in “5. AC Characteristics”.

*2 : When A/D conversion is not in operation, and the CPU is in STOP mode.

*3 : Included sampling time

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

Resolution

—

———10bit

1LSB =

(AVR – AVss) /

1024

Total error

AVR=AVCC

——±3.0LSB

Non-linearity error — — ±2.5 LSB

Differential linearity

error ——±1.9 LSB

Zero transition voltage VOT AVss –

1.5 LSB AVss +

0.5 LSB AVss +

2.5 LSB V

Full-scale transition

voltage VFST AVR –

3.5 LSB AVR –

1.5 LSB AVR +

1.5 LSB V

Interchannel disparity

—

——4LSB

A/D mode conversion

time *3

—

— 60 tinst*1—μs

A/D Sampling time — 16 tinst*1—

Analog port input cur-

rent IAIN AN0 to

AN7 ——10μA

Analog input voltage VAIN AVss — AVR V

Power supply current

AVCC

——46mA

when A/D

conversion is

activated

IAH TA = +25 °C— 1 5μAwhen A/D

conversion is

stopped

Reference voltage —

AVR

— AVss + 3.5 — AVCC V

Reference voltage

supply current

IRA/D is

Activated — 400 — μA

IRH A/D is

Stopped ——5μA*2

MB89560A Series

48 DS07-12555-3E

(3) A/D Converter Glossary

• Resolution

Analog changes that are identifiable with the A/D converter.

• Linearity error

The de viation of the straight line connecting the z ero transition point (“00 0000 0000” ↔ “00 0000 0001”) with

the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics

• Differential linearity error

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values caused by the zero transition error, full-scale

transition error, linearity error, quantization error, and noise

(Continued)

0.5 LSB

1 LSB

1.5 LSB

3FF

3FE

3FD

004

003

002

001

AVR AV

3FF

3FE

3FD

004

003

002

001

AVR

{1 LSB × N + 0.5 LSB}

FST

− {1 LSB × N + 0.5 LSB}

1 LSB

1 LSB = V

FST

− V

1022 (V)

Theoretical I/O characteristics Total error

Digital Output

Analog Input Analog Input

Total error for digital output N =

Actual Conversion

Characteristic

Theoretical Conversion

Characteristic

Actual Conversion

Characteristic

MB89560A Series

DS07-12555-3E 49

(Continued)

3FF

3FE

3FD

004

003

002

001

AVR AV

(N + 1)T

N + 1

N − 1

N − 2

AVR

{1 LSB × N + V

}

FST

004

003

002

001

AVR

FST

3FF

3FE

3FD

3FC

VNT − {1 LSB × N + 0.5 LSB}

1 LSB

(N + 1)T

− VNT

1 LSB− 1

AVR AV

Zero transition error Full-scale transition error

Digital Output

Actual Conversion

Characteristic Actual Conversion

Characteristics

Actual Conversion

Characteristic

Theoretical

Characteristic

Linearity error Differential linearity error

Digital Output

Analog Input Analog Input

(actual measured value)

Actual Conversion

Characteristic Actual Conversion

Characteristic

Actual Conversion

Characteristic

Linearity error in digital output N =

Differential linearity error in digital output N =

Actual Conversion

Characteristic

(actual measured value)

(actual measured

value)

(actual measured

value)

(actual measured

value)

Actual Conversion

Characteristic

Theoretical Characteristic

Theoretical

Characteristic

MB89560A Series

50 DS07-12555-3E

(4) Precautions

• The smaller the | AVR–AVSS | is, the greater the error would become relatively.

• The output impedance of the external circuit for the analog input must satisfy the following conditions :

Output impedance of the external circuit < Approx. 10 kΩ

• If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient.

* : The value of R and C at the sample hold circuit depends on the following.

MB89567A/MB89567AC : R := 2.2 kΩ, C := 45 pF

MB89P568/MB89PV560 : R := 1.4 kΩ, C := 64 pF

Sample hold circuit *

C = 45 pF

Analog channel selector

Close for 8 instruction cycles

after starting A/D conversion.

If the analog input impedance

is higher than 10 kΩ, it is

recommended to connect an

external capacitor of approx.

0.1 μF.

Analog input pin Comparator

R = 2.2 kΩ

Analog Input equivalent circuit

MB89560A Series

DS07-12555-3E 51

■EXAMPLE CHARACTERISTICS

(1) “L” Level Output Voltage

(2) “H” Level Output Voltage

OL1

vs. I

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0246810 12 14 16 1820

IOL (mA)

VOL1 (V)

= 2.5 V V

= 3.0 V V

= 4.5 V

= 4.0 V

= 3.5 V V

= 5.0 V

= 5.5 V

= 6.0 V

= 6.5 V

- V

OH1

vs. I

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-10-8-6-4-20I

(mA)

- V

OH1

(V)

= 4.0 V

= 4.5 V

= 5.0 V

= 5.5 V

= 6.0 V

= 6.5 V

= 3.5 V

MB89560A Series

52 DS07-12555-3E

(3) “H” Level Input Voltage / “L” Level Input Voltage

1234567

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

(V)

= + 25 °C

CMOS input

1234567

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

IHS

ILS

(V)

= + 25 °C

Hysteresis input

VIHS : Threshold when input voltage in hysteresis

characteristics is set to “H” level.

VILS : Threshold when input voltage in hysteresis

characteristics is set to “L” level.

MB89560A Series

DS07-12555-3E 53

(4) Power Supply Current (External Clock)

(Continued)

CCT

vs. V

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

01234567

(V)

CCT

(μA)

FCL = 32.768 kHz

= + 25 °C

ICCL vs. VCC

100

01234567

VCC (V)

ICCL (μA)

= 32.768 kHz

= + 25 °C

ICCS2 vs. VCC

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

01234567

VCC (V)

ICCS2 (mA)

FCH = 12.5 MHz

FCH = 10.0 MHz

FCH = 4.2 MHz

FCH = 3.0 MHz

FCH = 1.0 MHz

TA = + 25 °C

CC2

vs. V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

01234567

VCC (V)

ICC2 (mA)

= 12.5 MHz

= 10.0 MHz

= 4.2 MHz

= 3.0 MHz

= 1.0 MHz

TA = + 25 °C

ICCS1 vs. VCC

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

01234567

VCC (V)

ICCS1 (mA)

FCH = 12.5 MHz

FCH = 10.0 MHz

FCH = 4.2 MHz

FCH = 3.0 MHz

FCH = 1.0 MHz

TA = + 25 °C

ICC1 vs. VCC

01234567

CC (V)

CC1

(mA)

FCH = 12.5 MHz

FCH = 10.0 MHz

FCH = 4.2 MHz

FCH = 3.0 MHz

FCH = 1.0 MHz

TA = + 25 °C

(Mask ROM products) (Mask ROM products)

MB89560A Series

54 DS07-12555-3E

(Continued)

(5) Pull-up Resistance

IR vs. AVR

100

120

140

160

180

200

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

AVR (V)

IR (μA)

= + 25 °C

ICCLS vs. VCC

01234567

VCC (V)

ICCLS (μA)

TA = + 25 °C

IA VS. AVCC

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

AVCC (V)

IA (mA)

= 10.0 MHz

= + 25 °C

(Mask ROM products)

Rpull vs.VCC

110

130

150

170

190

210

2345678

VCC (V)

Rpull (kΩ)

TA = + 93 °C

TA = + 25 °C

TA = − 40 °C

MB89560A Series

DS07-12555-3E 55

■MASK OPTIONS

■ORDERING INFORMATION

No. Model MB89567A

MB89567AC MB89P568 MB89PV560

Specification method Specify when

ordering mask. Setting

unavailable. Setting

unavailable.

Main clock oscillation stabilization delay

time initial value* selection (FCH = 10 MHz)

• 01: 214/FCH (Approx. 1.6 ms)

• 10: 217/FCH (Approx. 13.1 ms)

• 11: 218/FCH (Approx. 26.2 ms)

Selectable 218/FCH (Approx.

26.2 ms) 218/FCH (approx.

26.2 ms)

LCD driving power supply

• On-chip voltage booster

• Internal voltage divider (external divider

resistors can be used)

Selectable

-101

Internal voltage

divider

-102

On-chip voltage

booster

-101

Internal voltage

divider

-102

On-chip voltage

booster

Part number Package Remarks

MB89567APMC

MB89567ACPMC

MB89P568-101PMC 80-pin Plastic LQFP

(FPT-80P-M21)

Without Booster

Resistor divider

MB89567APMC

MB89567ACPMC

MB89P568-102PMC With Booster

MB89567APF

MB89567ACPF

MB89P568-101PF 80-pin Plastic QFP

(FPT-80P-M06)

Without Booster

Resistor divider

MB89567APF

MB89567ACPF

MB89P568-102PF With Booster

MB89567APMC1

MB89567ACPMC1

MB89P568-101PMC1 80-pin Plastic LQFP

(FPT-80P-M22)

Without Booster

Resistor divider

MB89567APMC1

MB89567ACPMC1

MB89P568-102PMC1 With Booster

MB89PV560-101CF 80-pin Ceramic MQFP

(MQP-80C-P01)

Without Booster

Resistor divider

MB89PV560-102CF With Booster

MB89560A Series

56 DS07-12555-3E

■PACKAGE DIMENSIONS

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

80-pin plastic LQFP Lead pitch 0.50 mm

Package width ×

package length 12 mm × 12 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm Max

Weig ht 0.47 g

Code

(Reference) P-LFQFP80-12×12-0.50

80-pin plastic LQFP

(FPT-80P-M21)

2006 FUJITSU LIMITED F80035S-c-2-2

120

60 41

INDEX

12.00±0.10(.472±.004)SQ

14.00±0.20(.551±.008)SQ

0.50(.020) 0.20±0.05

(.008±.002) M

0.08(.003)

0.145±0.055

(.006±.002)

0.08(.003)

"A"

0˚~8˚

.059 –.004

+.008

–0.10

+0.20

1.50

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.10±0.05

(.004±.002)

(Stand off)

0.25(.010)

Details of "A" part

LEAD No.

(Mounting height)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

MB89560A Series

DS07-12555-3E 57

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

80-pin plastic QFP Lead pitch 0.80 mm

Package width ×

package length 14.00 × 20.00 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

3.35 mm MAX

Code

(Reference) P-QFP80-14×20-0.80

80-pin plastic QFP

(FPT-80P-M06)

(

FPT-80P-M06

)

2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6

1 24

4164

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

14.00±0.20

(.551±.008)

17.90±0.40

(.705±.016)

INDEX

0.80(.031) 0.37±0.05

(.015±.002)

0.16(.006)

"A"

0.17±0.06

(.007±.002)

0.10(.004)

0.80±0.20

(.031±.008)

0.88±0.15

(.035±.006)

0~8

.120

–.008

+.012

–0.20

+0.30

3.05 0.25(.010)

0.30

+0.10

–0.25

+.004

–.010

.012

(Stand off)

Details of "A" part

(Mounting height)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB89560A Series

58 DS07-12555-3E

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

80-pin plastic LQFP Lead pitch 0.65 mm

Package width ×

package length 14.00 mm × 14.00 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm Max

Weig ht 0.6 2 g

Code

(Reference) P-LFQFP80-14×14-0.65

80-pin plastic LQFP

(FPT-80P-M22)

2007 FUJITSU LIMITED F80036S-c-1-1

120

4160

14.00±0.10(.551±.004)SQ

16.00±0.20(.630±.008)SQ

INDEX

0.65(.026) 0.32±0.05

(.013±.002)

0.13(.005)

"A"

(.006±.002)

0.145±0.055

0.10(.004)

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0~8˚

.059 –.004

+.008

–0.10

+0.20

1.50

(Mounting height)

0.25(.010)

0.10±0.10

(.004±.004)

(Stand off)

Details of "A" part

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB89560A Series

DS07-12555-3E 59

(Continued)

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

80-pin ceramic MQFP Lead pitch 0.8 mm

Lead shape Straight

Motherboard

materialCeramic

Mounted package

materialPlastic

80-pin ceramic MQFP

(MQP-80C-P01)

1994-2008 FUJITSU MICROELECTRONICS LIMITED M80001SC-4-3

15.58±0.20

(.613±.008)

16.30±0.33

(.642±.013)

18.70(.736)TYP

INDEX AREA

0.30(.012)

TYP

1.27±0.13

(.050±.005)

22.30±0.33

(.878±.013)

24.70(.972)

TYP

10.16(.400)

TYP

12.02(.473)

TYP14.22(.560)

TYP

18.12±0.20

(.713±.008)

1.27±0.13

(.050±.005) 0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

0.15±0.05

(.006±.002) 8.70(.343)

MAX

0.40±0.10

(.016±.004) .047 –.008

+.016

–0.20

+0.40

1.20

0.40±0.10

(.016±.004)

18.40(.724)

REF

0.80±0.25

(.0315±.010)

12.00(.472)TYP

.047 –.008

+.016

–0.20

+0.40

1.20 0.80±0.25

(.0315±.010)

1.50(.059)

TYP

1.00(.040)

TYP

1.00(.040)TYP

1.50(.059)TYP

INDEX AREA

6.00(.236)

TYP

4.50(.177)

TYP

INDEX

Dimensions in mm (inches).

Note: The values in parentheses are reference values

MB89560A Series

60 DS07-12555-3E

■MAIN CHANGES IN THIS EDITION

The vertical lines marked in the left side of the page show the changes.

Page Section Change Results

6■ PIN ASSIGNMENT Changed the package code.

(*1: Main clock divided by two output →

*1: Main clock oscillation divided by two output)

19 ■ BLOCK DIAGRAM Changed the package code.

(*1: Output of Main clock/2. →

*1: Output of Main clock oscillation/2.)

■ ELECTRICAL CHARACTERISTICS

5. AC Characteristics

(3) Clock Timing

Changed the position of FCL of “When using a crystal

oscillator”.

■ ELECTRICAL CHARACTERISTICS

5. AC Characteristics

(4) Instruction Cycle Changed Instruction cycle (minimum execution time).

45 ■ ELECTRICAL CHARACTERISTICS

5. AC Characteristics

(7) I2C Timing

Changed the Data transmit (master/slave).

(tHO → tHIGH)

MB89560A Series

DS07-12555-3E 61

MEMO

MB89560A Series

62 DS07-12555-3E

MEMO

MB89560A Series

DS07-12555-3E 63

MEMO

MB89560A Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3329

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department